[deliverable/linux.git] / drivers / ata / pata_via.c

/*
 * pata_via.c 	- VIA PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 *  Documentation
 *	Most chipset documentation available under NDA only
 *
 *  VIA version guide
 *	VIA VT82C561	-	early design, uses ata_generic currently
 *	VIA VT82C576	-	MWDMA, 33Mhz
 *	VIA VT82C586	-	MWDMA, 33Mhz
 *	VIA VT82C586a	-	Added UDMA to 33Mhz
 *	VIA VT82C586b	-	UDMA33
 *	VIA VT82C596a	-	Nonfunctional UDMA66
 *	VIA VT82C596b	-	Working UDMA66
 *	VIA VT82C686	-	Nonfunctional UDMA66
 *	VIA VT82C686a	-	Working UDMA66
 *	VIA VT82C686b	-	Updated to UDMA100
 *	VIA VT8231	-	UDMA100
 *	VIA VT8233	-	UDMA100
 *	VIA VT8233a	-	UDMA133
 *	VIA VT8233c	-	UDMA100
 *	VIA VT8235	-	UDMA133
 *	VIA VT8237	-	UDMA133
 *
 *	Most registers remain compatible across chips. Others start reserved
 *	and acquire sensible semantics if set to 1 (eg cable detect). A few
 *	exceptions exist, notably around the FIFO settings.
 *
 *	One additional quirk of the VIA design is that like ALi they use few
 *	PCI IDs for a lot of chips.
 *
 *	Based heavily on:
 *
 * Version 3.38
 *
 * VIA IDE driver for Linux. Supported southbridges:
 *
 *   vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
 *   vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
 *   vt8235, vt8237
 *
 * Copyright (c) 2000-2002 Vojtech Pavlik
 *
 * Based on the work of:
 *	Michel Aubry
 *	Jeff Garzik
 *	Andre Hedrick

 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_via"
#define DRV_VERSION "0.2.0"

/*
 *	The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
 *	driver.
 */

enum {
	VIA_UDMA	= 0x007,
	VIA_UDMA_NONE	= 0x000,
	VIA_UDMA_33	= 0x001,
	VIA_UDMA_66	= 0x002,
	VIA_UDMA_100	= 0x003,
	VIA_UDMA_133	= 0x004,
	VIA_BAD_PREQ	= 0x010, /* Crashes if PREQ# till DDACK# set */
	VIA_BAD_CLK66	= 0x020, /* 66 MHz clock doesn't work correctly */
	VIA_SET_FIFO	= 0x040, /* Needs to have FIFO split set */
	VIA_NO_UNMASK	= 0x080, /* Doesn't work with IRQ unmasking on */
	VIA_BAD_ID	= 0x100, /* Has wrong vendor ID (0x1107) */
	VIA_BAD_AST	= 0x200, /* Don't touch Address Setup Timing */
	VIA_NO_ENABLES	= 0x400, /* Has no enablebits */
};

/*
 * VIA SouthBridge chips.
 */

static const struct via_isa_bridge {
	const char *name;
	u16 id;
	u8 rev_min;
	u8 rev_max;
	u16 flags;
} via_isa_bridges[] = {
	{ "cx700",	PCI_DEVICE_ID_VIA_CX700,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt6410",	PCI_DEVICE_ID_VIA_6410,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
	{ "vt8237a",	PCI_DEVICE_ID_VIA_8237A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8237",	PCI_DEVICE_ID_VIA_8237,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8235",	PCI_DEVICE_ID_VIA_8235,     0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233a",	PCI_DEVICE_ID_VIA_8233A,    0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
	{ "vt8233c",	PCI_DEVICE_ID_VIA_8233C_0,  0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8233",	PCI_DEVICE_ID_VIA_8233_0,   0x00, 0x2f, VIA_UDMA_100 },
	{ "vt8231",	PCI_DEVICE_ID_VIA_8231,     0x00, 0x2f, VIA_UDMA_100 },
	{ "vt82c686b",	PCI_DEVICE_ID_VIA_82C686,   0x40, 0x4f, VIA_UDMA_100 },
	{ "vt82c686a",	PCI_DEVICE_ID_VIA_82C686,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c686",	PCI_DEVICE_ID_VIA_82C686,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c596b",	PCI_DEVICE_ID_VIA_82C596,   0x10, 0x2f, VIA_UDMA_66 },
	{ "vt82c596a",	PCI_DEVICE_ID_VIA_82C596,   0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
	{ "vt82c586b",	PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586a",	PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
	{ "vt82c586",	PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
	{ "vt82c576",	PCI_DEVICE_ID_VIA_82C576,   0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
	{ NULL }
};

/**
 *	via_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection. Actually for the VIA case the BIOS
 *	already did this for us. We read the values provided by the
 *	BIOS. If you are using an 8235 in a non-PC configuration you
 *	may need to update this code.
 *
 *	Hotplug also impacts on this.
 */

static int via_cable_detect(struct ata_port *ap) {
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 ata66;

	pci_read_config_dword(pdev, 0x50, &ata66);
	/* Check both the drive cable reporting bits, we might not have
	   two drives */
	if (ata66 & (0x10100000 >> (16 * ap->port_no)))
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

static int via_pre_reset(struct ata_port *ap)
{
	const struct via_isa_bridge *config = ap->host->private_data;

	if (!(config->flags & VIA_NO_ENABLES)) {
		static const struct pci_bits via_enable_bits[] = {
			{ 0x40, 1, 0x02, 0x02 },
			{ 0x40, 1, 0x01, 0x01 }
		};

		struct pci_dev *pdev = to_pci_dev(ap->host->dev);

		if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
			return -ENOENT;
	}

	if ((config->flags & VIA_UDMA) >= VIA_UDMA_66)
		ap->cbl = via_cable_detect(ap);
	else
		ap->cbl = ATA_CBL_PATA40;
	return ata_std_prereset(ap);
}


/**
 *	via_error_handler		-	reset for VIA chips
 *	@ap: ATA port
 *
 *	Handle the reset callback for the later chips with cable detect
 */

static void via_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	via_do_set_mode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: ATA mode being programmed
 *	@tdiv: Clocks per PCI clock
 *	@set_ast: Set to program address setup
 *	@udma_type: UDMA mode/format of registers
 *
 *	Program the VIA registers for DMA and PIO modes. Uses the ata timing
 *	support in order to compute modes.
 *
 *	FIXME: Hotplug will require we serialize multiple mode changes
 *	on the two channels.
 */

static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_device *peer = ata_dev_pair(adev);
	struct ata_timing t, p;
	static int via_clock = 33333;	/* Bus clock in kHZ - ought to be tunable one day */
	unsigned long T =  1000000000 / via_clock;
	unsigned long UT = T/tdiv;
	int ut;
	int offset = 3 - (2*ap->port_no) - adev->devno;


	/* Calculate the timing values we require */
	ata_timing_compute(adev, mode, &t, T, UT);

	/* We share 8bit timing so we must merge the constraints */
	if (peer) {
		if (peer->pio_mode) {
			ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
			ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
		}
	}

	/* Address setup is programmable but breaks on UDMA133 setups */
	if (set_ast) {
		u8 setup;	/* 2 bits per drive */
		int shift = 2 * offset;

		pci_read_config_byte(pdev, 0x4C, &setup);
		setup &= ~(3 << shift);
		setup |= FIT(t.setup, 1, 4) << shift;	/* 1,4 or 1,4 - 1  FIXME */
		pci_write_config_byte(pdev, 0x4C, setup);
	}

	/* Load the PIO mode bits */
	pci_write_config_byte(pdev, 0x4F - ap->port_no,
		((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
	pci_write_config_byte(pdev, 0x48 + offset,
		((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));

	/* Load the UDMA bits according to type */
	switch(udma_type) {
		default:
			/* BUG() ? */
			/* fall through */
		case 33:
			ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
			break;
		case 66:
			ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
			break;
		case 100:
			ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
			break;
		case 133:
			ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
			break;
	}
	/* Set UDMA unless device is not UDMA capable */
	if (udma_type)
		pci_write_config_byte(pdev, 0x50 + offset, ut);
}

static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	const struct via_isa_bridge *config = ap->host->private_data;
	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
	int mode = config->flags & VIA_UDMA;
	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
	static u8 udma[5] = { 0, 33, 66, 100, 133 };

	via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
}

static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	const struct via_isa_bridge *config = ap->host->private_data;
	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
	int mode = config->flags & VIA_UDMA;
	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
	static u8 udma[5] = { 0, 33, 66, 100, 133 };

	via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
}

static struct scsi_host_template via_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
	.resume			= ata_scsi_device_resume,
	.suspend		= ata_scsi_device_suspend,
};

static struct ata_port_operations via_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= via_set_piomode,
	.set_dmamode	= via_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= via_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
	.port_stop	= ata_port_stop,
	.host_stop	= ata_host_stop
};

static struct ata_port_operations via_port_ops_noirq = {
	.port_disable	= ata_port_disable,
	.set_piomode	= via_set_piomode,
	.set_dmamode	= via_set_dmamode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= via_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_pio_data_xfer_noirq,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
	.port_stop	= ata_port_stop,
	.host_stop	= ata_host_stop
};

/**
 *	via_config_fifo		-	set up the FIFO
 *	@pdev: PCI device
 *	@flags: configuration flags
 *
 *	Set the FIFO properties for this device if neccessary. Used both on
 *	set up and on and the resume path
 */

static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
{
	u8 enable;
	
	/* 0x40 low bits indicate enabled channels */
	pci_read_config_byte(pdev, 0x40 , &enable);
	enable &= 3;
	
	if (flags & VIA_SET_FIFO) {
		u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
		u8 fifo;

		pci_read_config_byte(pdev, 0x43, &fifo);

		/* Clear PREQ# until DDACK# for errata */
		if (flags & VIA_BAD_PREQ)
			fifo &= 0x7F;
		else
			fifo &= 0x9f;
		/* Turn on FIFO for enabled channels */
		fifo |= fifo_setting[enable];
		pci_write_config_byte(pdev, 0x43, fifo);
	}
}

/**
 *	via_init_one		-	discovery callback
 *	@pdev: PCI device
 *	@id: PCI table info
 *
 *	A VIA IDE interface has been discovered. Figure out what revision
 *	and perform configuration work before handing it to the ATA layer
 */

static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	/* Early VIA without UDMA support */
	static struct ata_port_info via_mwdma_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &via_port_ops
	};
	/* Ditto with IRQ masking required */
	static struct ata_port_info via_mwdma_info_borked = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.port_ops = &via_port_ops_noirq,
	};
	/* VIA UDMA 33 devices (and borked 66) */
	static struct ata_port_info via_udma33_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x7,
		.port_ops = &via_port_ops
	};
	/* VIA UDMA 66 devices */
	static struct ata_port_info via_udma66_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x1f,
		.port_ops = &via_port_ops
	};
	/* VIA UDMA 100 devices */
	static struct ata_port_info via_udma100_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x3f,
		.port_ops = &via_port_ops
	};
	/* UDMA133 with bad AST (All current 133) */
	static struct ata_port_info via_udma133_info = {
		.sht = &via_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x7f,	/* FIXME: should check north bridge */
		.port_ops = &via_port_ops
	};
	struct ata_port_info *port_info[2], *type;
	struct pci_dev *isa = NULL;
	const struct via_isa_bridge *config;
	static int printed_version;
	u8 t;
	u8 enable;
	u32 timing;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/* To find out how the IDE will behave and what features we
	   actually have to look at the bridge not the IDE controller */
	for (config = via_isa_bridges; config->id; config++)
		if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
			!!(config->flags & VIA_BAD_ID),
			config->id, NULL))) {

			pci_read_config_byte(isa, PCI_REVISION_ID, &t);
			if (t >= config->rev_min &&
			    t <= config->rev_max)
				break;
			pci_dev_put(isa);
		}

	if (!config->id) {
		printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
		return -ENODEV;
	}
	pci_dev_put(isa);

	/* 0x40 low bits indicate enabled channels */
	pci_read_config_byte(pdev, 0x40 , &enable);
	enable &= 3;
	if (enable == 0) {
		return -ENODEV;
	}

	/* Initialise the FIFO for the enabled channels. */
	via_config_fifo(pdev, config->flags);
	
	/* Clock set up */
	switch(config->flags & VIA_UDMA) {
		case VIA_UDMA_NONE:
			if (config->flags & VIA_NO_UNMASK)
				type = &via_mwdma_info_borked;
			else
				type = &via_mwdma_info;
			break;
		case VIA_UDMA_33:
			type = &via_udma33_info;
			break;
		case VIA_UDMA_66:
			type = &via_udma66_info;
			/* The 66 MHz devices require we enable the clock */
			pci_read_config_dword(pdev, 0x50, &timing);
			timing |= 0x80008;
			pci_write_config_dword(pdev, 0x50, timing);
			break;
		case VIA_UDMA_100:
			type = &via_udma100_info;
			break;
		case VIA_UDMA_133:
			type = &via_udma133_info;
			break;
		default:
			WARN_ON(1);
			return -ENODEV;
	}

	if (config->flags & VIA_BAD_CLK66) {
		/* Disable the 66MHz clock on problem devices */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing &= ~0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}

	/* We have established the device type, now fire it up */
	type->private_data = (void *)config;

	port_info[0] = port_info[1] = type;
	return ata_pci_init_one(pdev, port_info, 2);
}

/**
 *	via_reinit_one		-	reinit after resume
 *	@pdev; PCI device
 *
 *	Called when the VIA PATA device is resumed. We must then
 *	reconfigure the fifo and other setup we may have altered. In
 *	addition the kernel needs to have the resume methods on PCI
 *	quirk supported.
 */

static int via_reinit_one(struct pci_dev *pdev)
{
	u32 timing;
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	const struct via_isa_bridge *config = host->private_data;
	
	via_config_fifo(pdev, config->flags);

	if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
		/* The 66 MHz devices require we enable the clock */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing |= 0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}
	if (config->flags & VIA_BAD_CLK66) {
		/* Disable the 66MHz clock on problem devices */
		pci_read_config_dword(pdev, 0x50, &timing);
		timing &= ~0x80008;
		pci_write_config_dword(pdev, 0x50, timing);
	}
	return ata_pci_device_resume(pdev);	
}

static const struct pci_device_id via[] = {
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },

	{ },
};

static struct pci_driver via_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= via,
	.probe 		= via_init_one,
	.remove		= ata_pci_remove_one,
	.suspend	= ata_pci_device_suspend,
	.resume		= via_reinit_one,
};

static int __init via_init(void)
{
	return pci_register_driver(&via_pci_driver);
}

static void __exit via_exit(void)
{
	pci_unregister_driver(&via_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for VIA PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, via);
MODULE_VERSION(DRV_VERSION);

module_init(via_init);
module_exit(via_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_via.c - VIA PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Documentation
	7	* Most chipset documentation available under NDA only
	8	*
	9	* VIA version guide
	10	* VIA VT82C561 - early design, uses ata_generic currently
	11	* VIA VT82C576 - MWDMA, 33Mhz
	12	* VIA VT82C586 - MWDMA, 33Mhz
	13	* VIA VT82C586a - Added UDMA to 33Mhz
	14	* VIA VT82C586b - UDMA33
	15	* VIA VT82C596a - Nonfunctional UDMA66
	16	* VIA VT82C596b - Working UDMA66
	17	* VIA VT82C686 - Nonfunctional UDMA66
	18	* VIA VT82C686a - Working UDMA66
	19	* VIA VT82C686b - Updated to UDMA100
	20	* VIA VT8231 - UDMA100
	21	* VIA VT8233 - UDMA100
	22	* VIA VT8233a - UDMA133
	23	* VIA VT8233c - UDMA100
	24	* VIA VT8235 - UDMA133
	25	* VIA VT8237 - UDMA133
	26	*
	27	* Most registers remain compatible across chips. Others start reserved
	28	* and acquire sensible semantics if set to 1 (eg cable detect). A few
	29	* exceptions exist, notably around the FIFO settings.
	30	*
	31	* One additional quirk of the VIA design is that like ALi they use few
	32	* PCI IDs for a lot of chips.
	33	*
	34	* Based heavily on:
	35	*
	36	* Version 3.38
	37	*
	38	* VIA IDE driver for Linux. Supported southbridges:
	39	*
	40	* vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
	41	* vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
	42	* vt8235, vt8237
	43	*
	44	* Copyright (c) 2000-2002 Vojtech Pavlik
	45	*
	46	* Based on the work of:
	47	* Michel Aubry
	48	* Jeff Garzik
	49	* Andre Hedrick
	50
	51	*/
	52
	53	#include <linux/kernel.h>
	54	#include <linux/module.h>
	55	#include <linux/pci.h>
	56	#include <linux/init.h>
	57	#include <linux/blkdev.h>
	58	#include <linux/delay.h>
	59	#include <scsi/scsi_host.h>
	60	#include <linux/libata.h>
	61
	62	#define DRV_NAME "pata_via"
627d2d32	63	#define DRV_VERSION "0.2.0"
669a5db4 JG	64
	65	/*
	66	* The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
	67	* driver.
	68	*/
	69
	70	enum {
	71	VIA_UDMA = 0x007,
	72	VIA_UDMA_NONE = 0x000,
	73	VIA_UDMA_33 = 0x001,
	74	VIA_UDMA_66 = 0x002,
	75	VIA_UDMA_100 = 0x003,
	76	VIA_UDMA_133 = 0x004,
	77	VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
	78	VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
	79	VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
	80	VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
	81	VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
	82	VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
	83	VIA_NO_ENABLES = 0x400, /* Has no enablebits */
	84	};
	85
	86	/*
	87	* VIA SouthBridge chips.
	88	*/
	89
	90	static const struct via_isa_bridge {
	91	const char *name;
	92	u16 id;
	93	u8 rev_min;
	94	u8 rev_max;
	95	u16 flags;
	96	} via_isa_bridges[] = {
	97	{ "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	98	{ "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST \| VIA_NO_ENABLES},
	99	{ "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	100	{ "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	101	{ "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	102	{ "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 \| VIA_BAD_AST },
	103	{ "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
	104	{ "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
	105	{ "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
	106	{ "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
	107	{ "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
	108	{ "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	109	{ "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
	110	{ "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 \| VIA_BAD_CLK66 },
	111	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 \| VIA_SET_FIFO },
	112	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 \| VIA_SET_FIFO \| VIA_BAD_PREQ },
	113	{ "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 \| VIA_SET_FIFO },
	114	{ "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 \| VIA_SET_FIFO },
	115	{ "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE \| VIA_SET_FIFO },
	116	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK },
	117	{ "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE \| VIA_SET_FIFO \| VIA_NO_UNMASK \| VIA_BAD_ID },
	118	{ NULL }
	119	};
	120
	121	/**
	122	* via_cable_detect - cable detection
	123	* @ap: ATA port
	124	*
	125	* Perform cable detection. Actually for the VIA case the BIOS
	126	* already did this for us. We read the values provided by the
	127	* BIOS. If you are using an 8235 in a non-PC configuration you
128	* may need to update this code.
129	*
130	* Hotplug also impacts on this.
131	*/
132
133	static int via_cable_detect(struct ata_port *ap) {
134	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
135	u32 ata66;
136
137	pci_read_config_dword(pdev, 0x50, &ata66);
138	/* Check both the drive cable reporting bits, we might not have
139	two drives */
140	if (ata66 & (0x10100000 >> (16 * ap->port_no)))
141	return ATA_CBL_PATA80;
142	else
143	return ATA_CBL_PATA40;
144	}
145
146	static int via_pre_reset(struct ata_port *ap)
147	{
148	const struct via_isa_bridge *config = ap->host->private_data;
149
150	if (!(config->flags & VIA_NO_ENABLES)) {
151	static const struct pci_bits via_enable_bits[] = {
152	{ 0x40, 1, 0x02, 0x02 },
153	{ 0x40, 1, 0x01, 0x01 }
154	};
155
156	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251	157
c961922b AC	158	if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
c961922b AC	159	return -ENOENT;
669a5db4 JG	160	}
	161
	162	if ((config->flags & VIA_UDMA) >= VIA_UDMA_66)
	163	ap->cbl = via_cable_detect(ap);
	164	else
	165	ap->cbl = ATA_CBL_PATA40;
	166	return ata_std_prereset(ap);
	167	}
	168
	169
	170	/**
	171	* via_error_handler - reset for VIA chips
	172	* @ap: ATA port
	173	*
	174	* Handle the reset callback for the later chips with cable detect
	175	*/
	176
	177	static void via_error_handler(struct ata_port *ap)
	178	{
	179	ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
	180	}
	181
	182	/**
	183	* via_do_set_mode - set initial PIO mode data
	184	* @ap: ATA interface
	185	* @adev: ATA device
	186	* @mode: ATA mode being programmed
	187	* @tdiv: Clocks per PCI clock
	188	* @set_ast: Set to program address setup
	189	* @udma_type: UDMA mode/format of registers
	190	*
	191	* Program the VIA registers for DMA and PIO modes. Uses the ata timing
	192	* support in order to compute modes.
	193	*
	194	* FIXME: Hotplug will require we serialize multiple mode changes
	195	* on the two channels.
	196	*/
	197
	198	static void via_do_set_mode(struct ata_port ap, struct ata_device adev, int mode, int tdiv, int set_ast, int udma_type)
	199	{
	200	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	201	struct ata_device *peer = ata_dev_pair(adev);
	202	struct ata_timing t, p;
	203	static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
	204	unsigned long T = 1000000000 / via_clock;
	205	unsigned long UT = T/tdiv;
	206	int ut;
	207	int offset = 3 - (2*ap->port_no) - adev->devno;
	208
	209
	210	/* Calculate the timing values we require */
	211	ata_timing_compute(adev, mode, &t, T, UT);
	212
	213	/* We share 8bit timing so we must merge the constraints */
	214	if (peer) {
	215	if (peer->pio_mode) {
	216	ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
	217	ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
	218	}
	219	}
	220
	221	/* Address setup is programmable but breaks on UDMA133 setups */
	222	if (set_ast) {
	223	u8 setup; /* 2 bits per drive */
224	int shift = 2 * offset;
225
226	pci_read_config_byte(pdev, 0x4C, &setup);
227	setup &= ~(3 << shift);
228	setup \|= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
229	pci_write_config_byte(pdev, 0x4C, setup);
230	}
231
232	/* Load the PIO mode bits */
233	pci_write_config_byte(pdev, 0x4F - ap->port_no,
234	((FIT(t.act8b, 1, 16) - 1) << 4) \| (FIT(t.rec8b, 1, 16) - 1));
235	pci_write_config_byte(pdev, 0x48 + offset,
236	((FIT(t.active, 1, 16) - 1) << 4) \| (FIT(t.recover, 1, 16) - 1));
237
238	/* Load the UDMA bits according to type */
239	switch(udma_type) {
240	default:
241	/* BUG() ? */
242	/* fall through */
243	case 33:
244	ut = t.udma ? (0xe0 \| (FIT(t.udma, 2, 5) - 2)) : 0x03;
245	break;
246	case 66:
247	ut = t.udma ? (0xe8 \| (FIT(t.udma, 2, 9) - 2)) : 0x0f;
248	break;
249	case 100:
250	ut = t.udma ? (0xe0 \| (FIT(t.udma, 2, 9) - 2)) : 0x07;
251	break;
252	case 133:
253	ut = t.udma ? (0xe0 \| (FIT(t.udma, 2, 9) - 2)) : 0x07;
254	break;
255	}
256	/* Set UDMA unless device is not UDMA capable */
257	if (udma_type)
258	pci_write_config_byte(pdev, 0x50 + offset, ut);
259	}
260
261	static void via_set_piomode(struct ata_port ap, struct ata_device adev)
262	{
263	const struct via_isa_bridge *config = ap->host->private_data;
264	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
265	int mode = config->flags & VIA_UDMA;
266	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
267	static u8 udma[5] = { 0, 33, 66, 100, 133 };
268
269	via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
270	}
271
272	static void via_set_dmamode(struct ata_port ap, struct ata_device adev)
273	{
274	const struct via_isa_bridge *config = ap->host->private_data;
275	int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
276	int mode = config->flags & VIA_UDMA;
277	static u8 tclock[5] = { 1, 1, 2, 3, 4 };
278	static u8 udma[5] = { 0, 33, 66, 100, 133 };
279
280	via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
281	}
282
283	static struct scsi_host_template via_sht = {
284	.module = THIS_MODULE,
285	.name = DRV_NAME,
286	.ioctl = ata_scsi_ioctl,
287	.queuecommand = ata_scsi_queuecmd,
288	.can_queue = ATA_DEF_QUEUE,
289	.this_id = ATA_SHT_THIS_ID,
290	.sg_tablesize = LIBATA_MAX_PRD,
291	.max_sectors = ATA_MAX_SECTORS,
292	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
293	.emulated = ATA_SHT_EMULATED,
294	.use_clustering = ATA_SHT_USE_CLUSTERING,
295	.proc_name = DRV_NAME,
296	.dma_boundary = ATA_DMA_BOUNDARY,
297	.slave_configure = ata_scsi_slave_config,
afdfe899	298	.slave_destroy = ata_scsi_slave_destroy,
669a5db4	299	.bios_param = ata_std_bios_param,
627d2d32 A	300	.resume = ata_scsi_device_resume,
627d2d32 A	301	.suspend = ata_scsi_device_suspend,
669a5db4 JG	302	};
	303
	304	static struct ata_port_operations via_port_ops = {
	305	.port_disable = ata_port_disable,
	306	.set_piomode = via_set_piomode,
	307	.set_dmamode = via_set_dmamode,
	308	.mode_filter = ata_pci_default_filter,
	309
	310	.tf_load = ata_tf_load,
	311	.tf_read = ata_tf_read,
	312	.check_status = ata_check_status,
	313	.exec_command = ata_exec_command,
	314	.dev_select = ata_std_dev_select,
	315
	316	.freeze = ata_bmdma_freeze,
	317	.thaw = ata_bmdma_thaw,
	318	.error_handler = via_error_handler,
	319	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	320
	321	.bmdma_setup = ata_bmdma_setup,
	322	.bmdma_start = ata_bmdma_start,
	323	.bmdma_stop = ata_bmdma_stop,
	324	.bmdma_status = ata_bmdma_status,
	325
	326	.qc_prep = ata_qc_prep,
	327	.qc_issue = ata_qc_issue_prot,
bda30288	328
669a5db4 JG	329	.data_xfer = ata_pio_data_xfer,
	330
	331	.irq_handler = ata_interrupt,
	332	.irq_clear = ata_bmdma_irq_clear,
	333
	334	.port_start = ata_port_start,
	335	.port_stop = ata_port_stop,
	336	.host_stop = ata_host_stop
	337	};
	338
	339	static struct ata_port_operations via_port_ops_noirq = {
	340	.port_disable = ata_port_disable,
	341	.set_piomode = via_set_piomode,
	342	.set_dmamode = via_set_dmamode,
	343	.mode_filter = ata_pci_default_filter,
	344
	345	.tf_load = ata_tf_load,
	346	.tf_read = ata_tf_read,
	347	.check_status = ata_check_status,
	348	.exec_command = ata_exec_command,
	349	.dev_select = ata_std_dev_select,
	350
	351	.freeze = ata_bmdma_freeze,
	352	.thaw = ata_bmdma_thaw,
	353	.error_handler = via_error_handler,
	354	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	355
	356	.bmdma_setup = ata_bmdma_setup,
	357	.bmdma_start = ata_bmdma_start,
	358	.bmdma_stop = ata_bmdma_stop,
	359	.bmdma_status = ata_bmdma_status,
	360
	361	.qc_prep = ata_qc_prep,
	362	.qc_issue = ata_qc_issue_prot,
bda30288	363
669a5db4 JG	364	.data_xfer = ata_pio_data_xfer_noirq,
	365
	366	.irq_handler = ata_interrupt,
	367	.irq_clear = ata_bmdma_irq_clear,
	368
	369	.port_start = ata_port_start,
	370	.port_stop = ata_port_stop,
	371	.host_stop = ata_host_stop
	372	};
	373
627d2d32 A	374	/**
	375	* via_config_fifo - set up the FIFO
	376	* @pdev: PCI device
	377	* @flags: configuration flags
	378	*
	379	* Set the FIFO properties for this device if neccessary. Used both on
	380	* set up and on and the resume path
	381	*/
	382
	383	static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
	384	{
	385	u8 enable;
	386
	387	/* 0x40 low bits indicate enabled channels */
	388	pci_read_config_byte(pdev, 0x40 , &enable);
	389	enable &= 3;
	390
	391	if (flags & VIA_SET_FIFO) {
	392	u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
	393	u8 fifo;
	394
	395	pci_read_config_byte(pdev, 0x43, &fifo);
	396
	397	/* Clear PREQ# until DDACK# for errata */
	398	if (flags & VIA_BAD_PREQ)
	399	fifo &= 0x7F;
	400	else
	401	fifo &= 0x9f;
	402	/* Turn on FIFO for enabled channels */
	403	fifo \|= fifo_setting[enable];
	404	pci_write_config_byte(pdev, 0x43, fifo);
	405	}
	406	}
	407
669a5db4 JG	408	/**
669a5db4 JG	409	* via_init_one - discovery callback
627d2d32	410	* @pdev: PCI device
669a5db4 JG	411	* @id: PCI table info
	412	*
	413	* A VIA IDE interface has been discovered. Figure out what revision
	414	* and perform configuration work before handing it to the ATA layer
	415	*/
	416
	417	static int via_init_one(struct pci_dev pdev, const struct pci_device_id id)
	418	{
	419	/* Early VIA without UDMA support */
	420	static struct ata_port_info via_mwdma_info = {
	421	.sht = &via_sht,
	422	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	423	.pio_mask = 0x1f,
	424	.mwdma_mask = 0x07,
	425	.port_ops = &via_port_ops
	426	};
	427	/* Ditto with IRQ masking required */
	428	static struct ata_port_info via_mwdma_info_borked = {
	429	.sht = &via_sht,
	430	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	431	.pio_mask = 0x1f,
	432	.mwdma_mask = 0x07,
	433	.port_ops = &via_port_ops_noirq,
	434	};
	435	/* VIA UDMA 33 devices (and borked 66) */
	436	static struct ata_port_info via_udma33_info = {
	437	.sht = &via_sht,
	438	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	439	.pio_mask = 0x1f,
	440	.mwdma_mask = 0x07,
	441	.udma_mask = 0x7,
	442	.port_ops = &via_port_ops
	443	};
	444	/* VIA UDMA 66 devices */
	445	static struct ata_port_info via_udma66_info = {
	446	.sht = &via_sht,
	447	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	448	.pio_mask = 0x1f,
	449	.mwdma_mask = 0x07,
	450	.udma_mask = 0x1f,
	451	.port_ops = &via_port_ops
	452	};
	453	/* VIA UDMA 100 devices */
	454	static struct ata_port_info via_udma100_info = {
	455	.sht = &via_sht,
	456	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	457	.pio_mask = 0x1f,
	458	.mwdma_mask = 0x07,
	459	.udma_mask = 0x3f,
	460	.port_ops = &via_port_ops
	461	};
	462	/* UDMA133 with bad AST (All current 133) */
	463	static struct ata_port_info via_udma133_info = {
	464	.sht = &via_sht,
	465	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	466	.pio_mask = 0x1f,
	467	.mwdma_mask = 0x07,
	468	.udma_mask = 0x7f, /* FIXME: should check north bridge */
	469	.port_ops = &via_port_ops
	470	};
	471	struct ata_port_info port_info[2], type;
	472	struct pci_dev *isa = NULL;
	473	const struct via_isa_bridge *config;
	474	static int printed_version;
475	u8 t;
476	u8 enable;
477	u32 timing;
478
479	if (!printed_version++)
480	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
481
482	/* To find out how the IDE will behave and what features we
483	actually have to look at the bridge not the IDE controller */
484	for (config = via_isa_bridges; config->id; config++)
485	if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
486	!!(config->flags & VIA_BAD_ID),
487	config->id, NULL))) {
488
489	pci_read_config_byte(isa, PCI_REVISION_ID, &t);
490	if (t >= config->rev_min &&
491	t <= config->rev_max)
492	break;
493	pci_dev_put(isa);
494	}
495
496	if (!config->id) {
497	printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
498	return -ENODEV;
499	}
500	pci_dev_put(isa);
501
502	/* 0x40 low bits indicate enabled channels */
503	pci_read_config_byte(pdev, 0x40 , &enable);
504	enable &= 3;
505	if (enable == 0) {
506	return -ENODEV;
507	}
508
509	/* Initialise the FIFO for the enabled channels. */
627d2d32 A	510	via_config_fifo(pdev, config->flags);
627d2d32 A	511
669a5db4 JG	512	/* Clock set up */
	513	switch(config->flags & VIA_UDMA) {
	514	case VIA_UDMA_NONE:
	515	if (config->flags & VIA_NO_UNMASK)
	516	type = &via_mwdma_info_borked;
	517	else
	518	type = &via_mwdma_info;
	519	break;
	520	case VIA_UDMA_33:
	521	type = &via_udma33_info;
	522	break;
	523	case VIA_UDMA_66:
	524	type = &via_udma66_info;
	525	/* The 66 MHz devices require we enable the clock */
	526	pci_read_config_dword(pdev, 0x50, &timing);
	527	timing \|= 0x80008;
	528	pci_write_config_dword(pdev, 0x50, timing);
	529	break;
	530	case VIA_UDMA_100:
	531	type = &via_udma100_info;
	532	break;
	533	case VIA_UDMA_133:
	534	type = &via_udma133_info;
	535	break;
	536	default:
	537	WARN_ON(1);
	538	return -ENODEV;
	539	}
	540
	541	if (config->flags & VIA_BAD_CLK66) {
	542	/* Disable the 66MHz clock on problem devices */
	543	pci_read_config_dword(pdev, 0x50, &timing);
	544	timing &= ~0x80008;
	545	pci_write_config_dword(pdev, 0x50, timing);
	546	}
	547
	548	/* We have established the device type, now fire it up */
	549	type->private_data = (void *)config;
	550
	551	port_info[0] = port_info[1] = type;
	552	return ata_pci_init_one(pdev, port_info, 2);
	553	}
	554
627d2d32 A	555	/**
	556	* via_reinit_one - reinit after resume
	557	* @pdev; PCI device
	558	*
	559	* Called when the VIA PATA device is resumed. We must then
	560	* reconfigure the fifo and other setup we may have altered. In
	561	* addition the kernel needs to have the resume methods on PCI
	562	* quirk supported.
	563	*/
	564
	565	static int via_reinit_one(struct pci_dev *pdev)
	566	{
	567	u32 timing;
	568	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	569	const struct via_isa_bridge *config = host->private_data;
	570
	571	via_config_fifo(pdev, config->flags);
	572
	573	if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
	574	/* The 66 MHz devices require we enable the clock */
	575	pci_read_config_dword(pdev, 0x50, &timing);
	576	timing \|= 0x80008;
	577	pci_write_config_dword(pdev, 0x50, timing);
	578	}
	579	if (config->flags & VIA_BAD_CLK66) {
	580	/* Disable the 66MHz clock on problem devices */
	581	pci_read_config_dword(pdev, 0x50, &timing);
	582	timing &= ~0x80008;
	583	pci_write_config_dword(pdev, 0x50, timing);
	584	}
	585	return ata_pci_device_resume(pdev);
	586	}
	587
669a5db4	588	static const struct pci_device_id via[] = {
2d2744fc JG	589	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
	590	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
	591	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
	592	{ PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
	593
	594	{ },
669a5db4 JG	595	};
	596
	597	static struct pci_driver via_pci_driver = {
2d2744fc	598	.name = DRV_NAME,
669a5db4 JG	599	.id_table = via,
669a5db4 JG	600	.probe = via_init_one,
627d2d32 A	601	.remove = ata_pci_remove_one,
	602	.suspend = ata_pci_device_suspend,
	603	.resume = via_reinit_one,
669a5db4 JG	604	};
	605
	606	static int __init via_init(void)
	607	{
	608	return pci_register_driver(&via_pci_driver);
	609	}
	610
669a5db4 JG	611	static void __exit via_exit(void)
	612	{
	613	pci_unregister_driver(&via_pci_driver);
	614	}
	615
669a5db4 JG	616	MODULE_AUTHOR("Alan Cox");
	617	MODULE_DESCRIPTION("low-level driver for VIA PATA");
	618	MODULE_LICENSE("GPL");
	619	MODULE_DEVICE_TABLE(pci, via);
	620	MODULE_VERSION(DRV_VERSION);
	621
	622	module_init(via_init);
	623	module_exit(via_exit);