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edea3ab5 ML |
1 | /* |
2 | * pdc_adma.c - Pacific Digital Corporation ADMA | |
3 | * | |
4 | * Maintained by: Mark Lord <mlord@pobox.com> | |
5 | * | |
6 | * Copyright 2005 Mark Lord | |
7 | * | |
68399bb5 JG |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; see the file COPYING. If not, write to | |
20 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * | |
23 | * libata documentation is available via 'make {ps|pdf}docs', | |
24 | * as Documentation/DocBook/libata.* | |
edea3ab5 | 25 | * |
edea3ab5 ML |
26 | * |
27 | * Supports ATA disks in single-packet ADMA mode. | |
28 | * Uses PIO for everything else. | |
29 | * | |
30 | * TODO: Use ADMA transfers for ATAPI devices, when possible. | |
31 | * This requires careful attention to a number of quirks of the chip. | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/sched.h> | |
a9524a76 | 43 | #include <linux/device.h> |
edea3ab5 | 44 | #include <scsi/scsi_host.h> |
edea3ab5 ML |
45 | #include <linux/libata.h> |
46 | ||
47 | #define DRV_NAME "pdc_adma" | |
af64371a | 48 | #define DRV_VERSION "0.04" |
edea3ab5 ML |
49 | |
50 | /* macro to calculate base address for ATA regs */ | |
51 | #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40)) | |
52 | ||
53 | /* macro to calculate base address for ADMA regs */ | |
54 | #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20)) | |
55 | ||
56 | enum { | |
57 | ADMA_PORTS = 2, | |
58 | ADMA_CPB_BYTES = 40, | |
59 | ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, | |
60 | ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, | |
61 | ||
62 | ADMA_DMA_BOUNDARY = 0xffffffff, | |
63 | ||
64 | /* global register offsets */ | |
65 | ADMA_MODE_LOCK = 0x00c7, | |
66 | ||
67 | /* per-channel register offsets */ | |
68 | ADMA_CONTROL = 0x0000, /* ADMA control */ | |
69 | ADMA_STATUS = 0x0002, /* ADMA status */ | |
70 | ADMA_CPB_COUNT = 0x0004, /* CPB count */ | |
71 | ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ | |
72 | ADMA_CPB_NEXT = 0x000c, /* next CPB address */ | |
73 | ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ | |
74 | ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ | |
75 | ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ | |
76 | ||
77 | /* ADMA_CONTROL register bits */ | |
78 | aNIEN = (1 << 8), /* irq mask: 1==masked */ | |
79 | aGO = (1 << 7), /* packet trigger ("Go!") */ | |
80 | aRSTADM = (1 << 5), /* ADMA logic reset */ | |
edea3ab5 ML |
81 | aPIOMD4 = 0x0003, /* PIO mode 4 */ |
82 | ||
83 | /* ADMA_STATUS register bits */ | |
84 | aPSD = (1 << 6), | |
85 | aUIRQ = (1 << 4), | |
86 | aPERR = (1 << 0), | |
87 | ||
88 | /* CPB bits */ | |
89 | cDONE = (1 << 0), | |
90 | cVLD = (1 << 0), | |
91 | cDAT = (1 << 2), | |
92 | cIEN = (1 << 3), | |
93 | ||
94 | /* PRD bits */ | |
95 | pORD = (1 << 4), | |
96 | pDIRO = (1 << 5), | |
97 | pEND = (1 << 7), | |
98 | ||
99 | /* ATA register flags */ | |
100 | rIGN = (1 << 5), | |
101 | rEND = (1 << 7), | |
102 | ||
103 | /* ATA register addresses */ | |
104 | ADMA_REGS_CONTROL = 0x0e, | |
105 | ADMA_REGS_SECTOR_COUNT = 0x12, | |
106 | ADMA_REGS_LBA_LOW = 0x13, | |
107 | ADMA_REGS_LBA_MID = 0x14, | |
108 | ADMA_REGS_LBA_HIGH = 0x15, | |
109 | ADMA_REGS_DEVICE = 0x16, | |
110 | ADMA_REGS_COMMAND = 0x17, | |
111 | ||
112 | /* PCI device IDs */ | |
113 | board_1841_idx = 0, /* ADMA 2-port controller */ | |
114 | }; | |
115 | ||
116 | typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; | |
117 | ||
118 | struct adma_port_priv { | |
119 | u8 *pkt; | |
120 | dma_addr_t pkt_dma; | |
121 | adma_state_t state; | |
122 | }; | |
123 | ||
124 | static int adma_ata_init_one (struct pci_dev *pdev, | |
125 | const struct pci_device_id *ent); | |
7d12e780 | 126 | static irqreturn_t adma_intr (int irq, void *dev_instance); |
edea3ab5 | 127 | static int adma_port_start(struct ata_port *ap); |
cca3974e | 128 | static void adma_host_stop(struct ata_host *host); |
edea3ab5 ML |
129 | static void adma_port_stop(struct ata_port *ap); |
130 | static void adma_phy_reset(struct ata_port *ap); | |
131 | static void adma_qc_prep(struct ata_queued_cmd *qc); | |
9a3d9eb0 | 132 | static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); |
edea3ab5 ML |
133 | static int adma_check_atapi_dma(struct ata_queued_cmd *qc); |
134 | static void adma_bmdma_stop(struct ata_queued_cmd *qc); | |
135 | static u8 adma_bmdma_status(struct ata_port *ap); | |
136 | static void adma_irq_clear(struct ata_port *ap); | |
137 | static void adma_eng_timeout(struct ata_port *ap); | |
138 | ||
193515d5 | 139 | static struct scsi_host_template adma_ata_sht = { |
edea3ab5 ML |
140 | .module = THIS_MODULE, |
141 | .name = DRV_NAME, | |
142 | .ioctl = ata_scsi_ioctl, | |
143 | .queuecommand = ata_scsi_queuecmd, | |
edea3ab5 ML |
144 | .can_queue = ATA_DEF_QUEUE, |
145 | .this_id = ATA_SHT_THIS_ID, | |
146 | .sg_tablesize = LIBATA_MAX_PRD, | |
edea3ab5 ML |
147 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
148 | .emulated = ATA_SHT_EMULATED, | |
149 | .use_clustering = ENABLE_CLUSTERING, | |
150 | .proc_name = DRV_NAME, | |
151 | .dma_boundary = ADMA_DMA_BOUNDARY, | |
152 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 153 | .slave_destroy = ata_scsi_slave_destroy, |
edea3ab5 ML |
154 | .bios_param = ata_std_bios_param, |
155 | }; | |
156 | ||
057ace5e | 157 | static const struct ata_port_operations adma_ata_ops = { |
edea3ab5 ML |
158 | .port_disable = ata_port_disable, |
159 | .tf_load = ata_tf_load, | |
160 | .tf_read = ata_tf_read, | |
161 | .check_status = ata_check_status, | |
162 | .check_atapi_dma = adma_check_atapi_dma, | |
163 | .exec_command = ata_exec_command, | |
164 | .dev_select = ata_std_dev_select, | |
165 | .phy_reset = adma_phy_reset, | |
166 | .qc_prep = adma_qc_prep, | |
167 | .qc_issue = adma_qc_issue, | |
168 | .eng_timeout = adma_eng_timeout, | |
1049cb47 | 169 | .data_xfer = ata_mmio_data_xfer, |
edea3ab5 ML |
170 | .irq_handler = adma_intr, |
171 | .irq_clear = adma_irq_clear, | |
172 | .port_start = adma_port_start, | |
173 | .port_stop = adma_port_stop, | |
174 | .host_stop = adma_host_stop, | |
175 | .bmdma_stop = adma_bmdma_stop, | |
176 | .bmdma_status = adma_bmdma_status, | |
177 | }; | |
178 | ||
179 | static struct ata_port_info adma_port_info[] = { | |
180 | /* board_1841_idx */ | |
181 | { | |
182 | .sht = &adma_ata_sht, | |
cca3974e | 183 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | |
51704c60 AL |
184 | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | |
185 | ATA_FLAG_PIO_POLLING, | |
edea3ab5 ML |
186 | .pio_mask = 0x10, /* pio4 */ |
187 | .udma_mask = 0x1f, /* udma0-4 */ | |
188 | .port_ops = &adma_ata_ops, | |
189 | }, | |
190 | }; | |
191 | ||
3b7d697d | 192 | static const struct pci_device_id adma_ata_pci_tbl[] = { |
54bb3a94 | 193 | { PCI_VDEVICE(PDC, 0x1841), board_1841_idx }, |
edea3ab5 ML |
194 | |
195 | { } /* terminate list */ | |
196 | }; | |
197 | ||
198 | static struct pci_driver adma_ata_pci_driver = { | |
199 | .name = DRV_NAME, | |
200 | .id_table = adma_ata_pci_tbl, | |
201 | .probe = adma_ata_init_one, | |
202 | .remove = ata_pci_remove_one, | |
203 | }; | |
204 | ||
205 | static int adma_check_atapi_dma(struct ata_queued_cmd *qc) | |
206 | { | |
207 | return 1; /* ATAPI DMA not yet supported */ | |
208 | } | |
209 | ||
210 | static void adma_bmdma_stop(struct ata_queued_cmd *qc) | |
211 | { | |
212 | /* nothing */ | |
213 | } | |
214 | ||
215 | static u8 adma_bmdma_status(struct ata_port *ap) | |
216 | { | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static void adma_irq_clear(struct ata_port *ap) | |
221 | { | |
222 | /* nothing */ | |
223 | } | |
224 | ||
225 | static void adma_reset_engine(void __iomem *chan) | |
226 | { | |
227 | /* reset ADMA to idle state */ | |
228 | writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); | |
229 | udelay(2); | |
230 | writew(aPIOMD4, chan + ADMA_CONTROL); | |
231 | udelay(2); | |
232 | } | |
233 | ||
234 | static void adma_reinit_engine(struct ata_port *ap) | |
235 | { | |
236 | struct adma_port_priv *pp = ap->private_data; | |
cca3974e | 237 | void __iomem *mmio_base = ap->host->mmio_base; |
edea3ab5 ML |
238 | void __iomem *chan = ADMA_REGS(mmio_base, ap->port_no); |
239 | ||
240 | /* mask/clear ATA interrupts */ | |
241 | writeb(ATA_NIEN, (void __iomem *)ap->ioaddr.ctl_addr); | |
242 | ata_check_status(ap); | |
243 | ||
244 | /* reset the ADMA engine */ | |
245 | adma_reset_engine(chan); | |
246 | ||
247 | /* set in-FIFO threshold to 0x100 */ | |
248 | writew(0x100, chan + ADMA_FIFO_IN); | |
249 | ||
250 | /* set CPB pointer */ | |
251 | writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); | |
252 | ||
253 | /* set out-FIFO threshold to 0x100 */ | |
254 | writew(0x100, chan + ADMA_FIFO_OUT); | |
255 | ||
256 | /* set CPB count */ | |
257 | writew(1, chan + ADMA_CPB_COUNT); | |
258 | ||
259 | /* read/discard ADMA status */ | |
260 | readb(chan + ADMA_STATUS); | |
261 | } | |
262 | ||
263 | static inline void adma_enter_reg_mode(struct ata_port *ap) | |
264 | { | |
cca3974e | 265 | void __iomem *chan = ADMA_REGS(ap->host->mmio_base, ap->port_no); |
edea3ab5 ML |
266 | |
267 | writew(aPIOMD4, chan + ADMA_CONTROL); | |
268 | readb(chan + ADMA_STATUS); /* flush */ | |
269 | } | |
270 | ||
271 | static void adma_phy_reset(struct ata_port *ap) | |
272 | { | |
273 | struct adma_port_priv *pp = ap->private_data; | |
274 | ||
275 | pp->state = adma_state_idle; | |
276 | adma_reinit_engine(ap); | |
277 | ata_port_probe(ap); | |
278 | ata_bus_reset(ap); | |
279 | } | |
280 | ||
281 | static void adma_eng_timeout(struct ata_port *ap) | |
282 | { | |
283 | struct adma_port_priv *pp = ap->private_data; | |
284 | ||
285 | if (pp->state != adma_state_idle) /* healthy paranoia */ | |
286 | pp->state = adma_state_mmio; | |
287 | adma_reinit_engine(ap); | |
288 | ata_eng_timeout(ap); | |
289 | } | |
290 | ||
291 | static int adma_fill_sg(struct ata_queued_cmd *qc) | |
292 | { | |
972c26bd | 293 | struct scatterlist *sg; |
edea3ab5 ML |
294 | struct ata_port *ap = qc->ap; |
295 | struct adma_port_priv *pp = ap->private_data; | |
296 | u8 *buf = pp->pkt; | |
972c26bd | 297 | int i = (2 + buf[3]) * 8; |
edea3ab5 ML |
298 | u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); |
299 | ||
972c26bd | 300 | ata_for_each_sg(sg, qc) { |
edea3ab5 ML |
301 | u32 addr; |
302 | u32 len; | |
303 | ||
304 | addr = (u32)sg_dma_address(sg); | |
305 | *(__le32 *)(buf + i) = cpu_to_le32(addr); | |
306 | i += 4; | |
307 | ||
308 | len = sg_dma_len(sg) >> 3; | |
309 | *(__le32 *)(buf + i) = cpu_to_le32(len); | |
310 | i += 4; | |
311 | ||
972c26bd | 312 | if (ata_sg_is_last(sg, qc)) |
edea3ab5 ML |
313 | pFLAGS |= pEND; |
314 | buf[i++] = pFLAGS; | |
315 | buf[i++] = qc->dev->dma_mode & 0xf; | |
316 | buf[i++] = 0; /* pPKLW */ | |
317 | buf[i++] = 0; /* reserved */ | |
318 | ||
319 | *(__le32 *)(buf + i) | |
320 | = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); | |
321 | i += 4; | |
322 | ||
db7f44d9 | 323 | VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, |
edea3ab5 ML |
324 | (unsigned long)addr, len); |
325 | } | |
326 | return i; | |
327 | } | |
328 | ||
329 | static void adma_qc_prep(struct ata_queued_cmd *qc) | |
330 | { | |
331 | struct adma_port_priv *pp = qc->ap->private_data; | |
332 | u8 *buf = pp->pkt; | |
333 | u32 pkt_dma = (u32)pp->pkt_dma; | |
334 | int i = 0; | |
335 | ||
336 | VPRINTK("ENTER\n"); | |
337 | ||
338 | adma_enter_reg_mode(qc->ap); | |
339 | if (qc->tf.protocol != ATA_PROT_DMA) { | |
340 | ata_qc_prep(qc); | |
341 | return; | |
342 | } | |
343 | ||
344 | buf[i++] = 0; /* Response flags */ | |
345 | buf[i++] = 0; /* reserved */ | |
346 | buf[i++] = cVLD | cDAT | cIEN; | |
347 | i++; /* cLEN, gets filled in below */ | |
348 | ||
349 | *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ | |
350 | i += 4; /* cNCPB */ | |
351 | i += 4; /* cPRD, gets filled in below */ | |
352 | ||
353 | buf[i++] = 0; /* reserved */ | |
354 | buf[i++] = 0; /* reserved */ | |
355 | buf[i++] = 0; /* reserved */ | |
356 | buf[i++] = 0; /* reserved */ | |
357 | ||
358 | /* ATA registers; must be a multiple of 4 */ | |
359 | buf[i++] = qc->tf.device; | |
360 | buf[i++] = ADMA_REGS_DEVICE; | |
361 | if ((qc->tf.flags & ATA_TFLAG_LBA48)) { | |
362 | buf[i++] = qc->tf.hob_nsect; | |
363 | buf[i++] = ADMA_REGS_SECTOR_COUNT; | |
364 | buf[i++] = qc->tf.hob_lbal; | |
365 | buf[i++] = ADMA_REGS_LBA_LOW; | |
366 | buf[i++] = qc->tf.hob_lbam; | |
367 | buf[i++] = ADMA_REGS_LBA_MID; | |
368 | buf[i++] = qc->tf.hob_lbah; | |
369 | buf[i++] = ADMA_REGS_LBA_HIGH; | |
370 | } | |
371 | buf[i++] = qc->tf.nsect; | |
372 | buf[i++] = ADMA_REGS_SECTOR_COUNT; | |
373 | buf[i++] = qc->tf.lbal; | |
374 | buf[i++] = ADMA_REGS_LBA_LOW; | |
375 | buf[i++] = qc->tf.lbam; | |
376 | buf[i++] = ADMA_REGS_LBA_MID; | |
377 | buf[i++] = qc->tf.lbah; | |
378 | buf[i++] = ADMA_REGS_LBA_HIGH; | |
379 | buf[i++] = 0; | |
380 | buf[i++] = ADMA_REGS_CONTROL; | |
381 | buf[i++] = rIGN; | |
382 | buf[i++] = 0; | |
383 | buf[i++] = qc->tf.command; | |
384 | buf[i++] = ADMA_REGS_COMMAND | rEND; | |
385 | ||
386 | buf[3] = (i >> 3) - 2; /* cLEN */ | |
387 | *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ | |
388 | ||
389 | i = adma_fill_sg(qc); | |
390 | wmb(); /* flush PRDs and pkt to memory */ | |
391 | #if 0 | |
392 | /* dump out CPB + PRDs for debug */ | |
393 | { | |
394 | int j, len = 0; | |
395 | static char obuf[2048]; | |
396 | for (j = 0; j < i; ++j) { | |
397 | len += sprintf(obuf+len, "%02x ", buf[j]); | |
398 | if ((j & 7) == 7) { | |
399 | printk("%s\n", obuf); | |
400 | len = 0; | |
401 | } | |
402 | } | |
403 | if (len) | |
404 | printk("%s\n", obuf); | |
405 | } | |
406 | #endif | |
407 | } | |
408 | ||
409 | static inline void adma_packet_start(struct ata_queued_cmd *qc) | |
410 | { | |
411 | struct ata_port *ap = qc->ap; | |
cca3974e | 412 | void __iomem *chan = ADMA_REGS(ap->host->mmio_base, ap->port_no); |
edea3ab5 ML |
413 | |
414 | VPRINTK("ENTER, ap %p\n", ap); | |
415 | ||
416 | /* fire up the ADMA engine */ | |
68399bb5 | 417 | writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); |
edea3ab5 ML |
418 | } |
419 | ||
9a3d9eb0 | 420 | static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) |
edea3ab5 ML |
421 | { |
422 | struct adma_port_priv *pp = qc->ap->private_data; | |
423 | ||
424 | switch (qc->tf.protocol) { | |
425 | case ATA_PROT_DMA: | |
426 | pp->state = adma_state_pkt; | |
427 | adma_packet_start(qc); | |
428 | return 0; | |
429 | ||
430 | case ATA_PROT_ATAPI_DMA: | |
431 | BUG(); | |
432 | break; | |
433 | ||
434 | default: | |
435 | break; | |
436 | } | |
437 | ||
438 | pp->state = adma_state_mmio; | |
439 | return ata_qc_issue_prot(qc); | |
440 | } | |
441 | ||
cca3974e | 442 | static inline unsigned int adma_intr_pkt(struct ata_host *host) |
edea3ab5 ML |
443 | { |
444 | unsigned int handled = 0, port_no; | |
cca3974e | 445 | u8 __iomem *mmio_base = host->mmio_base; |
edea3ab5 | 446 | |
cca3974e JG |
447 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
448 | struct ata_port *ap = host->ports[port_no]; | |
edea3ab5 ML |
449 | struct adma_port_priv *pp; |
450 | struct ata_queued_cmd *qc; | |
451 | void __iomem *chan = ADMA_REGS(mmio_base, port_no); | |
a7dac447 | 452 | u8 status = readb(chan + ADMA_STATUS); |
edea3ab5 ML |
453 | |
454 | if (status == 0) | |
455 | continue; | |
456 | handled = 1; | |
457 | adma_enter_reg_mode(ap); | |
029f5468 | 458 | if (ap->flags & ATA_FLAG_DISABLED) |
edea3ab5 ML |
459 | continue; |
460 | pp = ap->private_data; | |
461 | if (!pp || pp->state != adma_state_pkt) | |
462 | continue; | |
463 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
94ec1ef1 | 464 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
a21a84a3 | 465 | if ((status & (aPERR | aPSD | aUIRQ))) |
a22e2eb0 | 466 | qc->err_mask |= AC_ERR_OTHER; |
a21a84a3 | 467 | else if (pp->pkt[0] != cDONE) |
a22e2eb0 | 468 | qc->err_mask |= AC_ERR_OTHER; |
a7dac447 | 469 | |
a22e2eb0 | 470 | ata_qc_complete(qc); |
a21a84a3 | 471 | } |
edea3ab5 ML |
472 | } |
473 | return handled; | |
474 | } | |
475 | ||
cca3974e | 476 | static inline unsigned int adma_intr_mmio(struct ata_host *host) |
edea3ab5 ML |
477 | { |
478 | unsigned int handled = 0, port_no; | |
479 | ||
cca3974e | 480 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
edea3ab5 | 481 | struct ata_port *ap; |
cca3974e | 482 | ap = host->ports[port_no]; |
029f5468 | 483 | if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) { |
edea3ab5 ML |
484 | struct ata_queued_cmd *qc; |
485 | struct adma_port_priv *pp = ap->private_data; | |
486 | if (!pp || pp->state != adma_state_mmio) | |
487 | continue; | |
488 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
be697c3f | 489 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
edea3ab5 ML |
490 | |
491 | /* check main status, clearing INTRQ */ | |
ac19bff2 | 492 | u8 status = ata_check_status(ap); |
edea3ab5 ML |
493 | if ((status & ATA_BUSY)) |
494 | continue; | |
495 | DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", | |
496 | ap->id, qc->tf.protocol, status); | |
9bec2e38 | 497 | |
edea3ab5 ML |
498 | /* complete taskfile transaction */ |
499 | pp->state = adma_state_idle; | |
a22e2eb0 AL |
500 | qc->err_mask |= ac_err_mask(status); |
501 | ata_qc_complete(qc); | |
edea3ab5 ML |
502 | handled = 1; |
503 | } | |
504 | } | |
505 | } | |
506 | return handled; | |
507 | } | |
508 | ||
7d12e780 | 509 | static irqreturn_t adma_intr(int irq, void *dev_instance) |
edea3ab5 | 510 | { |
cca3974e | 511 | struct ata_host *host = dev_instance; |
edea3ab5 ML |
512 | unsigned int handled = 0; |
513 | ||
514 | VPRINTK("ENTER\n"); | |
515 | ||
cca3974e JG |
516 | spin_lock(&host->lock); |
517 | handled = adma_intr_pkt(host) | adma_intr_mmio(host); | |
518 | spin_unlock(&host->lock); | |
edea3ab5 ML |
519 | |
520 | VPRINTK("EXIT\n"); | |
521 | ||
522 | return IRQ_RETVAL(handled); | |
523 | } | |
524 | ||
525 | static void adma_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
526 | { | |
527 | port->cmd_addr = | |
528 | port->data_addr = base + 0x000; | |
529 | port->error_addr = | |
530 | port->feature_addr = base + 0x004; | |
531 | port->nsect_addr = base + 0x008; | |
532 | port->lbal_addr = base + 0x00c; | |
533 | port->lbam_addr = base + 0x010; | |
534 | port->lbah_addr = base + 0x014; | |
535 | port->device_addr = base + 0x018; | |
536 | port->status_addr = | |
537 | port->command_addr = base + 0x01c; | |
538 | port->altstatus_addr = | |
539 | port->ctl_addr = base + 0x038; | |
540 | } | |
541 | ||
542 | static int adma_port_start(struct ata_port *ap) | |
543 | { | |
cca3974e | 544 | struct device *dev = ap->host->dev; |
edea3ab5 ML |
545 | struct adma_port_priv *pp; |
546 | int rc; | |
547 | ||
548 | rc = ata_port_start(ap); | |
549 | if (rc) | |
550 | return rc; | |
551 | adma_enter_reg_mode(ap); | |
24dc5f33 | 552 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
edea3ab5 | 553 | if (!pp) |
24dc5f33 TH |
554 | return -ENOMEM; |
555 | pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, | |
556 | GFP_KERNEL); | |
edea3ab5 | 557 | if (!pp->pkt) |
24dc5f33 | 558 | return -ENOMEM; |
edea3ab5 ML |
559 | /* paranoia? */ |
560 | if ((pp->pkt_dma & 7) != 0) { | |
561 | printk("bad alignment for pp->pkt_dma: %08x\n", | |
562 | (u32)pp->pkt_dma); | |
24dc5f33 | 563 | return -ENOMEM; |
edea3ab5 ML |
564 | } |
565 | memset(pp->pkt, 0, ADMA_PKT_BYTES); | |
566 | ap->private_data = pp; | |
567 | adma_reinit_engine(ap); | |
568 | return 0; | |
edea3ab5 ML |
569 | } |
570 | ||
571 | static void adma_port_stop(struct ata_port *ap) | |
572 | { | |
cca3974e | 573 | adma_reset_engine(ADMA_REGS(ap->host->mmio_base, ap->port_no)); |
edea3ab5 ML |
574 | } |
575 | ||
cca3974e | 576 | static void adma_host_stop(struct ata_host *host) |
edea3ab5 ML |
577 | { |
578 | unsigned int port_no; | |
579 | ||
580 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) | |
cca3974e | 581 | adma_reset_engine(ADMA_REGS(host->mmio_base, port_no)); |
edea3ab5 ML |
582 | } |
583 | ||
584 | static void adma_host_init(unsigned int chip_id, | |
585 | struct ata_probe_ent *probe_ent) | |
586 | { | |
587 | unsigned int port_no; | |
588 | void __iomem *mmio_base = probe_ent->mmio_base; | |
589 | ||
590 | /* enable/lock aGO operation */ | |
591 | writeb(7, mmio_base + ADMA_MODE_LOCK); | |
592 | ||
593 | /* reset the ADMA logic */ | |
594 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) | |
595 | adma_reset_engine(ADMA_REGS(mmio_base, port_no)); | |
596 | } | |
597 | ||
598 | static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) | |
599 | { | |
600 | int rc; | |
601 | ||
602 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
603 | if (rc) { | |
a9524a76 JG |
604 | dev_printk(KERN_ERR, &pdev->dev, |
605 | "32-bit DMA enable failed\n"); | |
edea3ab5 ML |
606 | return rc; |
607 | } | |
608 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
609 | if (rc) { | |
a9524a76 JG |
610 | dev_printk(KERN_ERR, &pdev->dev, |
611 | "32-bit consistent DMA enable failed\n"); | |
edea3ab5 ML |
612 | return rc; |
613 | } | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static int adma_ata_init_one(struct pci_dev *pdev, | |
618 | const struct pci_device_id *ent) | |
619 | { | |
620 | static int printed_version; | |
621 | struct ata_probe_ent *probe_ent = NULL; | |
622 | void __iomem *mmio_base; | |
623 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
624 | int rc, port_no; | |
625 | ||
626 | if (!printed_version++) | |
a9524a76 | 627 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edea3ab5 | 628 | |
24dc5f33 | 629 | rc = pcim_enable_device(pdev); |
edea3ab5 ML |
630 | if (rc) |
631 | return rc; | |
632 | ||
633 | rc = pci_request_regions(pdev, DRV_NAME); | |
634 | if (rc) | |
24dc5f33 | 635 | return rc; |
edea3ab5 | 636 | |
24dc5f33 TH |
637 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) |
638 | return -ENODEV; | |
edea3ab5 | 639 | |
24dc5f33 TH |
640 | mmio_base = pcim_iomap(pdev, 4, 0); |
641 | if (mmio_base == NULL) | |
642 | return -ENOMEM; | |
edea3ab5 ML |
643 | |
644 | rc = adma_set_dma_masks(pdev, mmio_base); | |
645 | if (rc) | |
24dc5f33 | 646 | return rc; |
edea3ab5 | 647 | |
24dc5f33 TH |
648 | probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); |
649 | if (probe_ent == NULL) | |
650 | return -ENOMEM; | |
edea3ab5 ML |
651 | |
652 | probe_ent->dev = pci_dev_to_dev(pdev); | |
653 | INIT_LIST_HEAD(&probe_ent->node); | |
654 | ||
655 | probe_ent->sht = adma_port_info[board_idx].sht; | |
cca3974e | 656 | probe_ent->port_flags = adma_port_info[board_idx].flags; |
edea3ab5 ML |
657 | probe_ent->pio_mask = adma_port_info[board_idx].pio_mask; |
658 | probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask; | |
659 | probe_ent->udma_mask = adma_port_info[board_idx].udma_mask; | |
660 | probe_ent->port_ops = adma_port_info[board_idx].port_ops; | |
661 | ||
662 | probe_ent->irq = pdev->irq; | |
1d6f359a | 663 | probe_ent->irq_flags = IRQF_SHARED; |
edea3ab5 ML |
664 | probe_ent->mmio_base = mmio_base; |
665 | probe_ent->n_ports = ADMA_PORTS; | |
666 | ||
667 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { | |
668 | adma_ata_setup_port(&probe_ent->port[port_no], | |
669 | ADMA_ATA_REGS((unsigned long)mmio_base, port_no)); | |
670 | } | |
671 | ||
672 | pci_set_master(pdev); | |
673 | ||
674 | /* initialize adapter */ | |
675 | adma_host_init(board_idx, probe_ent); | |
676 | ||
24dc5f33 TH |
677 | if (!ata_device_add(probe_ent)) |
678 | return -ENODEV; | |
edea3ab5 | 679 | |
24dc5f33 TH |
680 | devm_kfree(&pdev->dev, probe_ent); |
681 | return 0; | |
edea3ab5 ML |
682 | } |
683 | ||
684 | static int __init adma_ata_init(void) | |
685 | { | |
b7887196 | 686 | return pci_register_driver(&adma_ata_pci_driver); |
edea3ab5 ML |
687 | } |
688 | ||
689 | static void __exit adma_ata_exit(void) | |
690 | { | |
691 | pci_unregister_driver(&adma_ata_pci_driver); | |
692 | } | |
693 | ||
694 | MODULE_AUTHOR("Mark Lord"); | |
695 | MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); | |
696 | MODULE_LICENSE("GPL"); | |
697 | MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); | |
698 | MODULE_VERSION(DRV_VERSION); | |
699 | ||
700 | module_init(adma_ata_init); | |
701 | module_exit(adma_ata_exit); |