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edea3ab5 ML |
1 | /* |
2 | * pdc_adma.c - Pacific Digital Corporation ADMA | |
3 | * | |
4 | * Maintained by: Mark Lord <mlord@pobox.com> | |
5 | * | |
6 | * Copyright 2005 Mark Lord | |
7 | * | |
68399bb5 JG |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; see the file COPYING. If not, write to | |
20 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * | |
23 | * libata documentation is available via 'make {ps|pdf}docs', | |
24 | * as Documentation/DocBook/libata.* | |
edea3ab5 | 25 | * |
edea3ab5 ML |
26 | * |
27 | * Supports ATA disks in single-packet ADMA mode. | |
28 | * Uses PIO for everything else. | |
29 | * | |
30 | * TODO: Use ADMA transfers for ATAPI devices, when possible. | |
31 | * This requires careful attention to a number of quirks of the chip. | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/sched.h> | |
a9524a76 | 43 | #include <linux/device.h> |
edea3ab5 ML |
44 | #include <scsi/scsi_host.h> |
45 | #include <asm/io.h> | |
46 | #include <linux/libata.h> | |
47 | ||
48 | #define DRV_NAME "pdc_adma" | |
af64371a | 49 | #define DRV_VERSION "0.04" |
edea3ab5 ML |
50 | |
51 | /* macro to calculate base address for ATA regs */ | |
52 | #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40)) | |
53 | ||
54 | /* macro to calculate base address for ADMA regs */ | |
55 | #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20)) | |
56 | ||
57 | enum { | |
58 | ADMA_PORTS = 2, | |
59 | ADMA_CPB_BYTES = 40, | |
60 | ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, | |
61 | ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, | |
62 | ||
63 | ADMA_DMA_BOUNDARY = 0xffffffff, | |
64 | ||
65 | /* global register offsets */ | |
66 | ADMA_MODE_LOCK = 0x00c7, | |
67 | ||
68 | /* per-channel register offsets */ | |
69 | ADMA_CONTROL = 0x0000, /* ADMA control */ | |
70 | ADMA_STATUS = 0x0002, /* ADMA status */ | |
71 | ADMA_CPB_COUNT = 0x0004, /* CPB count */ | |
72 | ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ | |
73 | ADMA_CPB_NEXT = 0x000c, /* next CPB address */ | |
74 | ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ | |
75 | ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ | |
76 | ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ | |
77 | ||
78 | /* ADMA_CONTROL register bits */ | |
79 | aNIEN = (1 << 8), /* irq mask: 1==masked */ | |
80 | aGO = (1 << 7), /* packet trigger ("Go!") */ | |
81 | aRSTADM = (1 << 5), /* ADMA logic reset */ | |
edea3ab5 ML |
82 | aPIOMD4 = 0x0003, /* PIO mode 4 */ |
83 | ||
84 | /* ADMA_STATUS register bits */ | |
85 | aPSD = (1 << 6), | |
86 | aUIRQ = (1 << 4), | |
87 | aPERR = (1 << 0), | |
88 | ||
89 | /* CPB bits */ | |
90 | cDONE = (1 << 0), | |
91 | cVLD = (1 << 0), | |
92 | cDAT = (1 << 2), | |
93 | cIEN = (1 << 3), | |
94 | ||
95 | /* PRD bits */ | |
96 | pORD = (1 << 4), | |
97 | pDIRO = (1 << 5), | |
98 | pEND = (1 << 7), | |
99 | ||
100 | /* ATA register flags */ | |
101 | rIGN = (1 << 5), | |
102 | rEND = (1 << 7), | |
103 | ||
104 | /* ATA register addresses */ | |
105 | ADMA_REGS_CONTROL = 0x0e, | |
106 | ADMA_REGS_SECTOR_COUNT = 0x12, | |
107 | ADMA_REGS_LBA_LOW = 0x13, | |
108 | ADMA_REGS_LBA_MID = 0x14, | |
109 | ADMA_REGS_LBA_HIGH = 0x15, | |
110 | ADMA_REGS_DEVICE = 0x16, | |
111 | ADMA_REGS_COMMAND = 0x17, | |
112 | ||
113 | /* PCI device IDs */ | |
114 | board_1841_idx = 0, /* ADMA 2-port controller */ | |
115 | }; | |
116 | ||
117 | typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; | |
118 | ||
119 | struct adma_port_priv { | |
120 | u8 *pkt; | |
121 | dma_addr_t pkt_dma; | |
122 | adma_state_t state; | |
123 | }; | |
124 | ||
125 | static int adma_ata_init_one (struct pci_dev *pdev, | |
126 | const struct pci_device_id *ent); | |
127 | static irqreturn_t adma_intr (int irq, void *dev_instance, | |
128 | struct pt_regs *regs); | |
129 | static int adma_port_start(struct ata_port *ap); | |
cca3974e | 130 | static void adma_host_stop(struct ata_host *host); |
edea3ab5 ML |
131 | static void adma_port_stop(struct ata_port *ap); |
132 | static void adma_phy_reset(struct ata_port *ap); | |
133 | static void adma_qc_prep(struct ata_queued_cmd *qc); | |
9a3d9eb0 | 134 | static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); |
edea3ab5 ML |
135 | static int adma_check_atapi_dma(struct ata_queued_cmd *qc); |
136 | static void adma_bmdma_stop(struct ata_queued_cmd *qc); | |
137 | static u8 adma_bmdma_status(struct ata_port *ap); | |
138 | static void adma_irq_clear(struct ata_port *ap); | |
139 | static void adma_eng_timeout(struct ata_port *ap); | |
140 | ||
193515d5 | 141 | static struct scsi_host_template adma_ata_sht = { |
edea3ab5 ML |
142 | .module = THIS_MODULE, |
143 | .name = DRV_NAME, | |
144 | .ioctl = ata_scsi_ioctl, | |
145 | .queuecommand = ata_scsi_queuecmd, | |
edea3ab5 ML |
146 | .can_queue = ATA_DEF_QUEUE, |
147 | .this_id = ATA_SHT_THIS_ID, | |
148 | .sg_tablesize = LIBATA_MAX_PRD, | |
edea3ab5 ML |
149 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
150 | .emulated = ATA_SHT_EMULATED, | |
151 | .use_clustering = ENABLE_CLUSTERING, | |
152 | .proc_name = DRV_NAME, | |
153 | .dma_boundary = ADMA_DMA_BOUNDARY, | |
154 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 155 | .slave_destroy = ata_scsi_slave_destroy, |
edea3ab5 ML |
156 | .bios_param = ata_std_bios_param, |
157 | }; | |
158 | ||
057ace5e | 159 | static const struct ata_port_operations adma_ata_ops = { |
edea3ab5 ML |
160 | .port_disable = ata_port_disable, |
161 | .tf_load = ata_tf_load, | |
162 | .tf_read = ata_tf_read, | |
163 | .check_status = ata_check_status, | |
164 | .check_atapi_dma = adma_check_atapi_dma, | |
165 | .exec_command = ata_exec_command, | |
166 | .dev_select = ata_std_dev_select, | |
167 | .phy_reset = adma_phy_reset, | |
168 | .qc_prep = adma_qc_prep, | |
169 | .qc_issue = adma_qc_issue, | |
170 | .eng_timeout = adma_eng_timeout, | |
1049cb47 | 171 | .data_xfer = ata_mmio_data_xfer, |
edea3ab5 ML |
172 | .irq_handler = adma_intr, |
173 | .irq_clear = adma_irq_clear, | |
174 | .port_start = adma_port_start, | |
175 | .port_stop = adma_port_stop, | |
176 | .host_stop = adma_host_stop, | |
177 | .bmdma_stop = adma_bmdma_stop, | |
178 | .bmdma_status = adma_bmdma_status, | |
179 | }; | |
180 | ||
181 | static struct ata_port_info adma_port_info[] = { | |
182 | /* board_1841_idx */ | |
183 | { | |
184 | .sht = &adma_ata_sht, | |
cca3974e | 185 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | |
51704c60 AL |
186 | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | |
187 | ATA_FLAG_PIO_POLLING, | |
edea3ab5 ML |
188 | .pio_mask = 0x10, /* pio4 */ |
189 | .udma_mask = 0x1f, /* udma0-4 */ | |
190 | .port_ops = &adma_ata_ops, | |
191 | }, | |
192 | }; | |
193 | ||
3b7d697d | 194 | static const struct pci_device_id adma_ata_pci_tbl[] = { |
edea3ab5 ML |
195 | { PCI_VENDOR_ID_PDC, 0x1841, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
196 | board_1841_idx }, | |
197 | ||
198 | { } /* terminate list */ | |
199 | }; | |
200 | ||
201 | static struct pci_driver adma_ata_pci_driver = { | |
202 | .name = DRV_NAME, | |
203 | .id_table = adma_ata_pci_tbl, | |
204 | .probe = adma_ata_init_one, | |
205 | .remove = ata_pci_remove_one, | |
206 | }; | |
207 | ||
208 | static int adma_check_atapi_dma(struct ata_queued_cmd *qc) | |
209 | { | |
210 | return 1; /* ATAPI DMA not yet supported */ | |
211 | } | |
212 | ||
213 | static void adma_bmdma_stop(struct ata_queued_cmd *qc) | |
214 | { | |
215 | /* nothing */ | |
216 | } | |
217 | ||
218 | static u8 adma_bmdma_status(struct ata_port *ap) | |
219 | { | |
220 | return 0; | |
221 | } | |
222 | ||
223 | static void adma_irq_clear(struct ata_port *ap) | |
224 | { | |
225 | /* nothing */ | |
226 | } | |
227 | ||
228 | static void adma_reset_engine(void __iomem *chan) | |
229 | { | |
230 | /* reset ADMA to idle state */ | |
231 | writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); | |
232 | udelay(2); | |
233 | writew(aPIOMD4, chan + ADMA_CONTROL); | |
234 | udelay(2); | |
235 | } | |
236 | ||
237 | static void adma_reinit_engine(struct ata_port *ap) | |
238 | { | |
239 | struct adma_port_priv *pp = ap->private_data; | |
cca3974e | 240 | void __iomem *mmio_base = ap->host->mmio_base; |
edea3ab5 ML |
241 | void __iomem *chan = ADMA_REGS(mmio_base, ap->port_no); |
242 | ||
243 | /* mask/clear ATA interrupts */ | |
244 | writeb(ATA_NIEN, (void __iomem *)ap->ioaddr.ctl_addr); | |
245 | ata_check_status(ap); | |
246 | ||
247 | /* reset the ADMA engine */ | |
248 | adma_reset_engine(chan); | |
249 | ||
250 | /* set in-FIFO threshold to 0x100 */ | |
251 | writew(0x100, chan + ADMA_FIFO_IN); | |
252 | ||
253 | /* set CPB pointer */ | |
254 | writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); | |
255 | ||
256 | /* set out-FIFO threshold to 0x100 */ | |
257 | writew(0x100, chan + ADMA_FIFO_OUT); | |
258 | ||
259 | /* set CPB count */ | |
260 | writew(1, chan + ADMA_CPB_COUNT); | |
261 | ||
262 | /* read/discard ADMA status */ | |
263 | readb(chan + ADMA_STATUS); | |
264 | } | |
265 | ||
266 | static inline void adma_enter_reg_mode(struct ata_port *ap) | |
267 | { | |
cca3974e | 268 | void __iomem *chan = ADMA_REGS(ap->host->mmio_base, ap->port_no); |
edea3ab5 ML |
269 | |
270 | writew(aPIOMD4, chan + ADMA_CONTROL); | |
271 | readb(chan + ADMA_STATUS); /* flush */ | |
272 | } | |
273 | ||
274 | static void adma_phy_reset(struct ata_port *ap) | |
275 | { | |
276 | struct adma_port_priv *pp = ap->private_data; | |
277 | ||
278 | pp->state = adma_state_idle; | |
279 | adma_reinit_engine(ap); | |
280 | ata_port_probe(ap); | |
281 | ata_bus_reset(ap); | |
282 | } | |
283 | ||
284 | static void adma_eng_timeout(struct ata_port *ap) | |
285 | { | |
286 | struct adma_port_priv *pp = ap->private_data; | |
287 | ||
288 | if (pp->state != adma_state_idle) /* healthy paranoia */ | |
289 | pp->state = adma_state_mmio; | |
290 | adma_reinit_engine(ap); | |
291 | ata_eng_timeout(ap); | |
292 | } | |
293 | ||
294 | static int adma_fill_sg(struct ata_queued_cmd *qc) | |
295 | { | |
972c26bd | 296 | struct scatterlist *sg; |
edea3ab5 ML |
297 | struct ata_port *ap = qc->ap; |
298 | struct adma_port_priv *pp = ap->private_data; | |
299 | u8 *buf = pp->pkt; | |
972c26bd | 300 | int i = (2 + buf[3]) * 8; |
edea3ab5 ML |
301 | u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); |
302 | ||
972c26bd | 303 | ata_for_each_sg(sg, qc) { |
edea3ab5 ML |
304 | u32 addr; |
305 | u32 len; | |
306 | ||
307 | addr = (u32)sg_dma_address(sg); | |
308 | *(__le32 *)(buf + i) = cpu_to_le32(addr); | |
309 | i += 4; | |
310 | ||
311 | len = sg_dma_len(sg) >> 3; | |
312 | *(__le32 *)(buf + i) = cpu_to_le32(len); | |
313 | i += 4; | |
314 | ||
972c26bd | 315 | if (ata_sg_is_last(sg, qc)) |
edea3ab5 ML |
316 | pFLAGS |= pEND; |
317 | buf[i++] = pFLAGS; | |
318 | buf[i++] = qc->dev->dma_mode & 0xf; | |
319 | buf[i++] = 0; /* pPKLW */ | |
320 | buf[i++] = 0; /* reserved */ | |
321 | ||
322 | *(__le32 *)(buf + i) | |
323 | = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); | |
324 | i += 4; | |
325 | ||
db7f44d9 | 326 | VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, |
edea3ab5 ML |
327 | (unsigned long)addr, len); |
328 | } | |
329 | return i; | |
330 | } | |
331 | ||
332 | static void adma_qc_prep(struct ata_queued_cmd *qc) | |
333 | { | |
334 | struct adma_port_priv *pp = qc->ap->private_data; | |
335 | u8 *buf = pp->pkt; | |
336 | u32 pkt_dma = (u32)pp->pkt_dma; | |
337 | int i = 0; | |
338 | ||
339 | VPRINTK("ENTER\n"); | |
340 | ||
341 | adma_enter_reg_mode(qc->ap); | |
342 | if (qc->tf.protocol != ATA_PROT_DMA) { | |
343 | ata_qc_prep(qc); | |
344 | return; | |
345 | } | |
346 | ||
347 | buf[i++] = 0; /* Response flags */ | |
348 | buf[i++] = 0; /* reserved */ | |
349 | buf[i++] = cVLD | cDAT | cIEN; | |
350 | i++; /* cLEN, gets filled in below */ | |
351 | ||
352 | *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ | |
353 | i += 4; /* cNCPB */ | |
354 | i += 4; /* cPRD, gets filled in below */ | |
355 | ||
356 | buf[i++] = 0; /* reserved */ | |
357 | buf[i++] = 0; /* reserved */ | |
358 | buf[i++] = 0; /* reserved */ | |
359 | buf[i++] = 0; /* reserved */ | |
360 | ||
361 | /* ATA registers; must be a multiple of 4 */ | |
362 | buf[i++] = qc->tf.device; | |
363 | buf[i++] = ADMA_REGS_DEVICE; | |
364 | if ((qc->tf.flags & ATA_TFLAG_LBA48)) { | |
365 | buf[i++] = qc->tf.hob_nsect; | |
366 | buf[i++] = ADMA_REGS_SECTOR_COUNT; | |
367 | buf[i++] = qc->tf.hob_lbal; | |
368 | buf[i++] = ADMA_REGS_LBA_LOW; | |
369 | buf[i++] = qc->tf.hob_lbam; | |
370 | buf[i++] = ADMA_REGS_LBA_MID; | |
371 | buf[i++] = qc->tf.hob_lbah; | |
372 | buf[i++] = ADMA_REGS_LBA_HIGH; | |
373 | } | |
374 | buf[i++] = qc->tf.nsect; | |
375 | buf[i++] = ADMA_REGS_SECTOR_COUNT; | |
376 | buf[i++] = qc->tf.lbal; | |
377 | buf[i++] = ADMA_REGS_LBA_LOW; | |
378 | buf[i++] = qc->tf.lbam; | |
379 | buf[i++] = ADMA_REGS_LBA_MID; | |
380 | buf[i++] = qc->tf.lbah; | |
381 | buf[i++] = ADMA_REGS_LBA_HIGH; | |
382 | buf[i++] = 0; | |
383 | buf[i++] = ADMA_REGS_CONTROL; | |
384 | buf[i++] = rIGN; | |
385 | buf[i++] = 0; | |
386 | buf[i++] = qc->tf.command; | |
387 | buf[i++] = ADMA_REGS_COMMAND | rEND; | |
388 | ||
389 | buf[3] = (i >> 3) - 2; /* cLEN */ | |
390 | *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ | |
391 | ||
392 | i = adma_fill_sg(qc); | |
393 | wmb(); /* flush PRDs and pkt to memory */ | |
394 | #if 0 | |
395 | /* dump out CPB + PRDs for debug */ | |
396 | { | |
397 | int j, len = 0; | |
398 | static char obuf[2048]; | |
399 | for (j = 0; j < i; ++j) { | |
400 | len += sprintf(obuf+len, "%02x ", buf[j]); | |
401 | if ((j & 7) == 7) { | |
402 | printk("%s\n", obuf); | |
403 | len = 0; | |
404 | } | |
405 | } | |
406 | if (len) | |
407 | printk("%s\n", obuf); | |
408 | } | |
409 | #endif | |
410 | } | |
411 | ||
412 | static inline void adma_packet_start(struct ata_queued_cmd *qc) | |
413 | { | |
414 | struct ata_port *ap = qc->ap; | |
cca3974e | 415 | void __iomem *chan = ADMA_REGS(ap->host->mmio_base, ap->port_no); |
edea3ab5 ML |
416 | |
417 | VPRINTK("ENTER, ap %p\n", ap); | |
418 | ||
419 | /* fire up the ADMA engine */ | |
68399bb5 | 420 | writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); |
edea3ab5 ML |
421 | } |
422 | ||
9a3d9eb0 | 423 | static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) |
edea3ab5 ML |
424 | { |
425 | struct adma_port_priv *pp = qc->ap->private_data; | |
426 | ||
427 | switch (qc->tf.protocol) { | |
428 | case ATA_PROT_DMA: | |
429 | pp->state = adma_state_pkt; | |
430 | adma_packet_start(qc); | |
431 | return 0; | |
432 | ||
433 | case ATA_PROT_ATAPI_DMA: | |
434 | BUG(); | |
435 | break; | |
436 | ||
437 | default: | |
438 | break; | |
439 | } | |
440 | ||
441 | pp->state = adma_state_mmio; | |
442 | return ata_qc_issue_prot(qc); | |
443 | } | |
444 | ||
cca3974e | 445 | static inline unsigned int adma_intr_pkt(struct ata_host *host) |
edea3ab5 ML |
446 | { |
447 | unsigned int handled = 0, port_no; | |
cca3974e | 448 | u8 __iomem *mmio_base = host->mmio_base; |
edea3ab5 | 449 | |
cca3974e JG |
450 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
451 | struct ata_port *ap = host->ports[port_no]; | |
edea3ab5 ML |
452 | struct adma_port_priv *pp; |
453 | struct ata_queued_cmd *qc; | |
454 | void __iomem *chan = ADMA_REGS(mmio_base, port_no); | |
a7dac447 | 455 | u8 status = readb(chan + ADMA_STATUS); |
edea3ab5 ML |
456 | |
457 | if (status == 0) | |
458 | continue; | |
459 | handled = 1; | |
460 | adma_enter_reg_mode(ap); | |
029f5468 | 461 | if (ap->flags & ATA_FLAG_DISABLED) |
edea3ab5 ML |
462 | continue; |
463 | pp = ap->private_data; | |
464 | if (!pp || pp->state != adma_state_pkt) | |
465 | continue; | |
466 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
94ec1ef1 | 467 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
a21a84a3 | 468 | if ((status & (aPERR | aPSD | aUIRQ))) |
a22e2eb0 | 469 | qc->err_mask |= AC_ERR_OTHER; |
a21a84a3 | 470 | else if (pp->pkt[0] != cDONE) |
a22e2eb0 | 471 | qc->err_mask |= AC_ERR_OTHER; |
a7dac447 | 472 | |
a22e2eb0 | 473 | ata_qc_complete(qc); |
a21a84a3 | 474 | } |
edea3ab5 ML |
475 | } |
476 | return handled; | |
477 | } | |
478 | ||
cca3974e | 479 | static inline unsigned int adma_intr_mmio(struct ata_host *host) |
edea3ab5 ML |
480 | { |
481 | unsigned int handled = 0, port_no; | |
482 | ||
cca3974e | 483 | for (port_no = 0; port_no < host->n_ports; ++port_no) { |
edea3ab5 | 484 | struct ata_port *ap; |
cca3974e | 485 | ap = host->ports[port_no]; |
029f5468 | 486 | if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) { |
edea3ab5 ML |
487 | struct ata_queued_cmd *qc; |
488 | struct adma_port_priv *pp = ap->private_data; | |
489 | if (!pp || pp->state != adma_state_mmio) | |
490 | continue; | |
491 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
be697c3f | 492 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { |
edea3ab5 ML |
493 | |
494 | /* check main status, clearing INTRQ */ | |
ac19bff2 | 495 | u8 status = ata_check_status(ap); |
edea3ab5 ML |
496 | if ((status & ATA_BUSY)) |
497 | continue; | |
498 | DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", | |
499 | ap->id, qc->tf.protocol, status); | |
500 | ||
501 | /* complete taskfile transaction */ | |
502 | pp->state = adma_state_idle; | |
a22e2eb0 AL |
503 | qc->err_mask |= ac_err_mask(status); |
504 | ata_qc_complete(qc); | |
edea3ab5 ML |
505 | handled = 1; |
506 | } | |
507 | } | |
508 | } | |
509 | return handled; | |
510 | } | |
511 | ||
512 | static irqreturn_t adma_intr(int irq, void *dev_instance, struct pt_regs *regs) | |
513 | { | |
cca3974e | 514 | struct ata_host *host = dev_instance; |
edea3ab5 ML |
515 | unsigned int handled = 0; |
516 | ||
517 | VPRINTK("ENTER\n"); | |
518 | ||
cca3974e JG |
519 | spin_lock(&host->lock); |
520 | handled = adma_intr_pkt(host) | adma_intr_mmio(host); | |
521 | spin_unlock(&host->lock); | |
edea3ab5 ML |
522 | |
523 | VPRINTK("EXIT\n"); | |
524 | ||
525 | return IRQ_RETVAL(handled); | |
526 | } | |
527 | ||
528 | static void adma_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
529 | { | |
530 | port->cmd_addr = | |
531 | port->data_addr = base + 0x000; | |
532 | port->error_addr = | |
533 | port->feature_addr = base + 0x004; | |
534 | port->nsect_addr = base + 0x008; | |
535 | port->lbal_addr = base + 0x00c; | |
536 | port->lbam_addr = base + 0x010; | |
537 | port->lbah_addr = base + 0x014; | |
538 | port->device_addr = base + 0x018; | |
539 | port->status_addr = | |
540 | port->command_addr = base + 0x01c; | |
541 | port->altstatus_addr = | |
542 | port->ctl_addr = base + 0x038; | |
543 | } | |
544 | ||
545 | static int adma_port_start(struct ata_port *ap) | |
546 | { | |
cca3974e | 547 | struct device *dev = ap->host->dev; |
edea3ab5 ML |
548 | struct adma_port_priv *pp; |
549 | int rc; | |
550 | ||
551 | rc = ata_port_start(ap); | |
552 | if (rc) | |
553 | return rc; | |
554 | adma_enter_reg_mode(ap); | |
555 | rc = -ENOMEM; | |
556 | pp = kcalloc(1, sizeof(*pp), GFP_KERNEL); | |
557 | if (!pp) | |
558 | goto err_out; | |
559 | pp->pkt = dma_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, | |
560 | GFP_KERNEL); | |
561 | if (!pp->pkt) | |
562 | goto err_out_kfree; | |
563 | /* paranoia? */ | |
564 | if ((pp->pkt_dma & 7) != 0) { | |
565 | printk("bad alignment for pp->pkt_dma: %08x\n", | |
566 | (u32)pp->pkt_dma); | |
a21a84a3 JG |
567 | dma_free_coherent(dev, ADMA_PKT_BYTES, |
568 | pp->pkt, pp->pkt_dma); | |
569 | goto err_out_kfree; | |
edea3ab5 ML |
570 | } |
571 | memset(pp->pkt, 0, ADMA_PKT_BYTES); | |
572 | ap->private_data = pp; | |
573 | adma_reinit_engine(ap); | |
574 | return 0; | |
575 | ||
edea3ab5 ML |
576 | err_out_kfree: |
577 | kfree(pp); | |
578 | err_out: | |
579 | ata_port_stop(ap); | |
580 | return rc; | |
581 | } | |
582 | ||
583 | static void adma_port_stop(struct ata_port *ap) | |
584 | { | |
cca3974e | 585 | struct device *dev = ap->host->dev; |
edea3ab5 ML |
586 | struct adma_port_priv *pp = ap->private_data; |
587 | ||
cca3974e | 588 | adma_reset_engine(ADMA_REGS(ap->host->mmio_base, ap->port_no)); |
edea3ab5 ML |
589 | if (pp != NULL) { |
590 | ap->private_data = NULL; | |
591 | if (pp->pkt != NULL) | |
592 | dma_free_coherent(dev, ADMA_PKT_BYTES, | |
593 | pp->pkt, pp->pkt_dma); | |
594 | kfree(pp); | |
595 | } | |
596 | ata_port_stop(ap); | |
597 | } | |
598 | ||
cca3974e | 599 | static void adma_host_stop(struct ata_host *host) |
edea3ab5 ML |
600 | { |
601 | unsigned int port_no; | |
602 | ||
603 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) | |
cca3974e | 604 | adma_reset_engine(ADMA_REGS(host->mmio_base, port_no)); |
edea3ab5 | 605 | |
cca3974e | 606 | ata_pci_host_stop(host); |
edea3ab5 ML |
607 | } |
608 | ||
609 | static void adma_host_init(unsigned int chip_id, | |
610 | struct ata_probe_ent *probe_ent) | |
611 | { | |
612 | unsigned int port_no; | |
613 | void __iomem *mmio_base = probe_ent->mmio_base; | |
614 | ||
615 | /* enable/lock aGO operation */ | |
616 | writeb(7, mmio_base + ADMA_MODE_LOCK); | |
617 | ||
618 | /* reset the ADMA logic */ | |
619 | for (port_no = 0; port_no < ADMA_PORTS; ++port_no) | |
620 | adma_reset_engine(ADMA_REGS(mmio_base, port_no)); | |
621 | } | |
622 | ||
623 | static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) | |
624 | { | |
625 | int rc; | |
626 | ||
627 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
628 | if (rc) { | |
a9524a76 JG |
629 | dev_printk(KERN_ERR, &pdev->dev, |
630 | "32-bit DMA enable failed\n"); | |
edea3ab5 ML |
631 | return rc; |
632 | } | |
633 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
634 | if (rc) { | |
a9524a76 JG |
635 | dev_printk(KERN_ERR, &pdev->dev, |
636 | "32-bit consistent DMA enable failed\n"); | |
edea3ab5 ML |
637 | return rc; |
638 | } | |
639 | return 0; | |
640 | } | |
641 | ||
642 | static int adma_ata_init_one(struct pci_dev *pdev, | |
643 | const struct pci_device_id *ent) | |
644 | { | |
645 | static int printed_version; | |
646 | struct ata_probe_ent *probe_ent = NULL; | |
647 | void __iomem *mmio_base; | |
648 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
649 | int rc, port_no; | |
650 | ||
651 | if (!printed_version++) | |
a9524a76 | 652 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edea3ab5 ML |
653 | |
654 | rc = pci_enable_device(pdev); | |
655 | if (rc) | |
656 | return rc; | |
657 | ||
658 | rc = pci_request_regions(pdev, DRV_NAME); | |
659 | if (rc) | |
660 | goto err_out; | |
661 | ||
662 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) { | |
663 | rc = -ENODEV; | |
664 | goto err_out_regions; | |
665 | } | |
666 | ||
667 | mmio_base = pci_iomap(pdev, 4, 0); | |
668 | if (mmio_base == NULL) { | |
669 | rc = -ENOMEM; | |
670 | goto err_out_regions; | |
671 | } | |
672 | ||
673 | rc = adma_set_dma_masks(pdev, mmio_base); | |
674 | if (rc) | |
675 | goto err_out_iounmap; | |
676 | ||
677 | probe_ent = kcalloc(1, sizeof(*probe_ent), GFP_KERNEL); | |
678 | if (probe_ent == NULL) { | |
679 | rc = -ENOMEM; | |
680 | goto err_out_iounmap; | |
681 | } | |
682 | ||
683 | probe_ent->dev = pci_dev_to_dev(pdev); | |
684 | INIT_LIST_HEAD(&probe_ent->node); | |
685 | ||
686 | probe_ent->sht = adma_port_info[board_idx].sht; | |
cca3974e | 687 | probe_ent->port_flags = adma_port_info[board_idx].flags; |
edea3ab5 ML |
688 | probe_ent->pio_mask = adma_port_info[board_idx].pio_mask; |
689 | probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask; | |
690 | probe_ent->udma_mask = adma_port_info[board_idx].udma_mask; | |
691 | probe_ent->port_ops = adma_port_info[board_idx].port_ops; | |
692 | ||
693 | probe_ent->irq = pdev->irq; | |
1d6f359a | 694 | probe_ent->irq_flags = IRQF_SHARED; |
edea3ab5 ML |
695 | probe_ent->mmio_base = mmio_base; |
696 | probe_ent->n_ports = ADMA_PORTS; | |
697 | ||
698 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { | |
699 | adma_ata_setup_port(&probe_ent->port[port_no], | |
700 | ADMA_ATA_REGS((unsigned long)mmio_base, port_no)); | |
701 | } | |
702 | ||
703 | pci_set_master(pdev); | |
704 | ||
705 | /* initialize adapter */ | |
706 | adma_host_init(board_idx, probe_ent); | |
707 | ||
708 | rc = ata_device_add(probe_ent); | |
709 | kfree(probe_ent); | |
710 | if (rc != ADMA_PORTS) | |
711 | goto err_out_iounmap; | |
712 | return 0; | |
713 | ||
714 | err_out_iounmap: | |
715 | pci_iounmap(pdev, mmio_base); | |
716 | err_out_regions: | |
717 | pci_release_regions(pdev); | |
718 | err_out: | |
719 | pci_disable_device(pdev); | |
720 | return rc; | |
721 | } | |
722 | ||
723 | static int __init adma_ata_init(void) | |
724 | { | |
b7887196 | 725 | return pci_register_driver(&adma_ata_pci_driver); |
edea3ab5 ML |
726 | } |
727 | ||
728 | static void __exit adma_ata_exit(void) | |
729 | { | |
730 | pci_unregister_driver(&adma_ata_pci_driver); | |
731 | } | |
732 | ||
733 | MODULE_AUTHOR("Mark Lord"); | |
734 | MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); | |
735 | MODULE_LICENSE("GPL"); | |
736 | MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); | |
737 | MODULE_VERSION(DRV_VERSION); | |
738 | ||
739 | module_init(adma_ata_init); | |
740 | module_exit(adma_ata_exit); |