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[libata] sata_mv: clean up DMA boundary issues, turn on 64-bit DMA
[deliverable/linux.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
8b260248 4 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 5 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include <linux/interrupt.h>
20f733e7 31#include <linux/dma-mapping.h>
a9524a76 32#include <linux/device.h>
20f733e7 33#include <scsi/scsi_host.h>
193515d5 34#include <scsi/scsi_cmnd.h>
20f733e7 35#include <linux/libata.h>
20f733e7
BR		 36
37#define DRV_NAME "sata_mv"
cb48cab7 38#define DRV_VERSION "0.8"
20f733e7
BR		 39
40enum {
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
45
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
48
49 MV_PCI_REG_BASE = 0,
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 51 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
52 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
53 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
54 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
55 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
56
20f733e7 57 MV_SATAHC0_REG_BASE = 0x20000,
522479fb 58 MV_FLASH_CTL = 0x1046c,
bca1c4eb
JG		 59 MV_GPIO_PORT_CTL = 0x104f0,
60 MV_RESET_CFG = 0x180d8,
20f733e7
BR		 61
62 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
63 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
65 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
66
31961943 67 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
20f733e7 68
31961943
BR		 69 MV_MAX_Q_DEPTH = 32,
70 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
71
72 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
73 * CRPB needs alignment on a 256B boundary. Size == 256B
74 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
75 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
76 */
77 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
78 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
79 MV_MAX_SG_CT = 176,
80 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
81 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
82
20f733e7
BR		 83 MV_PORTS_PER_HC = 4,
84 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
85 MV_PORT_HC_SHIFT = 2,
31961943 86 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
20f733e7
BR		 87 MV_PORT_MASK = 3,
88
89 /* Host Flags */
90 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
91 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
31961943 92 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
50630195 93 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
1f3461a7 94 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
47c2b677 95 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 96
31961943
BR		 97 CRQB_FLAG_READ = (1 << 0),
98 CRQB_TAG_SHIFT = 1,
99 CRQB_CMD_ADDR_SHIFT = 8,
100 CRQB_CMD_CS = (0x2 << 11),
101 CRQB_CMD_LAST = (1 << 15),
102
103 CRPB_FLAG_STATUS_SHIFT = 8,
104
105 EPRD_FLAG_END_OF_TBL = (1 << 31),
106
20f733e7
BR		 107 /* PCI interface registers */
108
31961943
BR		 109 PCI_COMMAND_OFS = 0xc00,
110
20f733e7
BR		 111 PCI_MAIN_CMD_STS_OFS = 0xd30,
112 STOP_PCI_MASTER = (1 << 2),
113 PCI_MASTER_EMPTY = (1 << 3),
114 GLOB_SFT_RST = (1 << 4),
115
522479fb
JG		 116 MV_PCI_MODE = 0xd00,
117 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
118 MV_PCI_DISC_TIMER = 0xd04,
119 MV_PCI_MSI_TRIGGER = 0xc38,
120 MV_PCI_SERR_MASK = 0xc28,
121 MV_PCI_XBAR_TMOUT = 0x1d04,
122 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
123 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
124 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
125 MV_PCI_ERR_COMMAND = 0x1d50,
126
127 PCI_IRQ_CAUSE_OFS = 0x1d58,
128 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 129 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
130
131 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
132 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
133 PORT0_ERR = (1 << 0), /* shift by port # */
134 PORT0_DONE = (1 << 1), /* shift by port # */
135 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
136 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
137 PCI_ERR = (1 << 18),
138 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
139 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 140 PORTS_0_3_COAL_DONE = (1 << 8),
141 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 147 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
8b260248 148 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
20f733e7
BR		 149 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
150 HC_MAIN_RSVD),
fb621e2f
JG		 151 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
152 HC_MAIN_RSVD_5),
20f733e7
BR		 153
154 /* SATAHC registers */
155 HC_CFG_OFS = 0,
156
157 HC_IRQ_CAUSE_OFS = 0x14,
31961943 158 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
20f733e7
BR		 159 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
160 DEV_IRQ = (1 << 8), /* shift by port # */
161
162 /* Shadow block registers */
31961943
BR		 163 SHD_BLK_OFS = 0x100,
164 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 165
166 /* SATA registers */
167 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
168 SATA_ACTIVE_OFS = 0x350,
47c2b677 169 PHY_MODE3 = 0x310,
bca1c4eb
JG		 170 PHY_MODE4 = 0x314,
171 PHY_MODE2 = 0x330,
c9d39130
JG		 172 MV5_PHY_MODE = 0x74,
173 MV5_LT_MODE = 0x30,
174 MV5_PHY_CTL = 0x0C,
bca1c4eb
JG		 175 SATA_INTERFACE_CTL = 0x050,
176
177 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 178
179 /* Port registers */
180 EDMA_CFG_OFS = 0,
31961943
BR		 181 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
182 EDMA_CFG_NCQ = (1 << 5),
183 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
184 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
185 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
20f733e7
BR		 186
187 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
188 EDMA_ERR_IRQ_MASK_OFS = 0xc,
189 EDMA_ERR_D_PAR = (1 << 0),
190 EDMA_ERR_PRD_PAR = (1 << 1),
191 EDMA_ERR_DEV = (1 << 2),
192 EDMA_ERR_DEV_DCON = (1 << 3),
193 EDMA_ERR_DEV_CON = (1 << 4),
194 EDMA_ERR_SERR = (1 << 5),
195 EDMA_ERR_SELF_DIS = (1 << 7),
196 EDMA_ERR_BIST_ASYNC = (1 << 8),
197 EDMA_ERR_CRBQ_PAR = (1 << 9),
198 EDMA_ERR_CRPB_PAR = (1 << 10),
199 EDMA_ERR_INTRL_PAR = (1 << 11),
200 EDMA_ERR_IORDY = (1 << 12),
201 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
202 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
203 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
204 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
205 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
206 EDMA_ERR_TRANS_PROTO = (1 << 31),
8b260248 207 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
20f733e7
BR		 208 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
209 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
8b260248 210 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
20f733e7 211 EDMA_ERR_LNK_DATA_RX |
8b260248 212 EDMA_ERR_LNK_DATA_TX |
20f733e7
BR		 213 EDMA_ERR_TRANS_PROTO),
214
31961943
BR		 215 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
216 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 217
218 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
219 EDMA_REQ_Q_PTR_SHIFT = 5,
220
221 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
222 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
223 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 224 EDMA_RSP_Q_PTR_SHIFT = 3,
225
20f733e7
BR		 226 EDMA_CMD_OFS = 0x28,
227 EDMA_EN = (1 << 0),
228 EDMA_DS = (1 << 1),
229 ATA_RST = (1 << 2),
230
c9d39130 231 EDMA_IORDY_TMOUT = 0x34,
bca1c4eb 232 EDMA_ARB_CFG = 0x38,
bca1c4eb 233
31961943
BR		 234 /* Host private flags (hp_flags) */
235 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 236 MV_HP_ERRATA_50XXB0 = (1 << 1),
237 MV_HP_ERRATA_50XXB2 = (1 << 2),
238 MV_HP_ERRATA_60X1B2 = (1 << 3),
239 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892
JG		 240 MV_HP_ERRATA_XX42A0 = (1 << 5),
241 MV_HP_50XX = (1 << 6),
242 MV_HP_GEN_IIE = (1 << 7),
20f733e7 243
31961943
BR		 244 /* Port private flags (pp_flags) */
245 MV_PP_FLAG_EDMA_EN = (1 << 0),
246 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
20f733e7
BR		 247};
248
c9d39130 249#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
bca1c4eb 250#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
e4e7b892
JG		 251#define IS_GEN_I(hpriv) IS_50XX(hpriv)
252#define IS_GEN_II(hpriv) IS_60XX(hpriv)
253#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
bca1c4eb 254
095fec88 255enum {
d88184fb 256 MV_DMA_BOUNDARY = 0xffffffffU,
095fec88
JG		 257
258 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
259
260 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
261};
262
522479fb
JG		 263enum chip_type {
264 chip_504x,
265 chip_508x,
266 chip_5080,
267 chip_604x,
268 chip_608x,
e4e7b892
JG		 269 chip_6042,
270 chip_7042,
522479fb
JG		 271};
272
31961943
BR		 273/* Command ReQuest Block: 32B */
274struct mv_crqb {
e1469874
ML		 275 __le32 sg_addr;
276 __le32 sg_addr_hi;
277 __le16 ctrl_flags;
278 __le16 ata_cmd[11];
31961943 279};
20f733e7 280
e4e7b892 281struct mv_crqb_iie {
e1469874
ML		 282 __le32 addr;
283 __le32 addr_hi;
284 __le32 flags;
285 __le32 len;
286 __le32 ata_cmd[4];
e4e7b892
JG		 287};
288
31961943
BR		 289/* Command ResPonse Block: 8B */
290struct mv_crpb {
e1469874
ML		 291 __le16 id;
292 __le16 flags;
293 __le32 tmstmp;
20f733e7
BR		 294};
295
31961943
BR		 296/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
297struct mv_sg {
e1469874
ML		 298 __le32 addr;
299 __le32 flags_size;
300 __le32 addr_hi;
301 __le32 reserved;
31961943 302};
20f733e7 303
31961943
BR		 304struct mv_port_priv {
305 struct mv_crqb *crqb;
306 dma_addr_t crqb_dma;
307 struct mv_crpb *crpb;
308 dma_addr_t crpb_dma;
309 struct mv_sg *sg_tbl;
310 dma_addr_t sg_tbl_dma;
31961943
BR		 311 u32 pp_flags;
312};
313
bca1c4eb
JG		 314struct mv_port_signal {
315 u32 amps;
316 u32 pre;
317};
318
47c2b677
JG		 319struct mv_host_priv;
320struct mv_hw_ops {
2a47ce06
JG		 321 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
322 unsigned int port);
47c2b677
JG		 323 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
324 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
325 void __iomem *mmio);
c9d39130
JG		 326 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
327 unsigned int n_hc);
522479fb
JG		 328 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
329 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
47c2b677
JG		 330};
331
31961943
BR		 332struct mv_host_priv {
333 u32 hp_flags;
bca1c4eb 334 struct mv_port_signal signal[8];
47c2b677 335 const struct mv_hw_ops *ops;
20f733e7
BR		 336};
337
338static void mv_irq_clear(struct ata_port *ap);
339static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
340static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
c9d39130
JG		 341static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
342static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
20f733e7 343static void mv_phy_reset(struct ata_port *ap);
22374677 344static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
31961943
BR		 345static int mv_port_start(struct ata_port *ap);
346static void mv_port_stop(struct ata_port *ap);
347static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 348static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 349static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
7d12e780 350static irqreturn_t mv_interrupt(int irq, void *dev_instance);
31961943 351static void mv_eng_timeout(struct ata_port *ap);
20f733e7
BR		 352static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
353
2a47ce06
JG		 354static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
355 unsigned int port);
47c2b677
JG		 356static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
357static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
358 void __iomem *mmio);
c9d39130
JG		 359static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
360 unsigned int n_hc);
522479fb
JG		 361static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
362static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
47c2b677 363
2a47ce06
JG		 364static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
365 unsigned int port);
47c2b677
JG		 366static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
367static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
368 void __iomem *mmio);
c9d39130
JG		 369static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
370 unsigned int n_hc);
522479fb
JG		 371static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
372static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
c9d39130
JG		 373static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
374 unsigned int port_no);
375static void mv_stop_and_reset(struct ata_port *ap);
47c2b677 376
193515d5 377static struct scsi_host_template mv_sht = {
20f733e7
BR		 378 .module = THIS_MODULE,
379 .name = DRV_NAME,
380 .ioctl = ata_scsi_ioctl,
381 .queuecommand = ata_scsi_queuecmd,
31961943 382 .can_queue = MV_USE_Q_DEPTH,
20f733e7 383 .this_id = ATA_SHT_THIS_ID,
d88184fb 384 .sg_tablesize = MV_MAX_SG_CT,
20f733e7
BR		 385 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
386 .emulated = ATA_SHT_EMULATED,
d88184fb 387 .use_clustering = 1,
20f733e7
BR		 388 .proc_name = DRV_NAME,
389 .dma_boundary = MV_DMA_BOUNDARY,
390 .slave_configure = ata_scsi_slave_config,
ccf68c34 391 .slave_destroy = ata_scsi_slave_destroy,
20f733e7 392 .bios_param = ata_std_bios_param,
20f733e7
BR		 393};
394
c9d39130
JG		 395static const struct ata_port_operations mv5_ops = {
396 .port_disable = ata_port_disable,
397
398 .tf_load = ata_tf_load,
399 .tf_read = ata_tf_read,
400 .check_status = ata_check_status,
401 .exec_command = ata_exec_command,
402 .dev_select = ata_std_dev_select,
403
404 .phy_reset = mv_phy_reset,
405
406 .qc_prep = mv_qc_prep,
407 .qc_issue = mv_qc_issue,
0d5ff566 408 .data_xfer = ata_data_xfer,
c9d39130
JG		 409
410 .eng_timeout = mv_eng_timeout,
411
412 .irq_handler = mv_interrupt,
413 .irq_clear = mv_irq_clear,
246ce3b6
AI		 414 .irq_on = ata_irq_on,
415 .irq_ack = ata_irq_ack,
c9d39130
JG		 416
417 .scr_read = mv5_scr_read,
418 .scr_write = mv5_scr_write,
419
420 .port_start = mv_port_start,
421 .port_stop = mv_port_stop,
c9d39130
JG		 422};
423
424static const struct ata_port_operations mv6_ops = {
20f733e7
BR		 425 .port_disable = ata_port_disable,
426
427 .tf_load = ata_tf_load,
428 .tf_read = ata_tf_read,
429 .check_status = ata_check_status,
430 .exec_command = ata_exec_command,
431 .dev_select = ata_std_dev_select,
432
433 .phy_reset = mv_phy_reset,
434
31961943
BR		 435 .qc_prep = mv_qc_prep,
436 .qc_issue = mv_qc_issue,
0d5ff566 437 .data_xfer = ata_data_xfer,
20f733e7 438
31961943 439 .eng_timeout = mv_eng_timeout,
20f733e7
BR		 440
441 .irq_handler = mv_interrupt,
442 .irq_clear = mv_irq_clear,
246ce3b6
AI		 443 .irq_on = ata_irq_on,
444 .irq_ack = ata_irq_ack,
20f733e7
BR		 445
446 .scr_read = mv_scr_read,
447 .scr_write = mv_scr_write,
448
31961943
BR		 449 .port_start = mv_port_start,
450 .port_stop = mv_port_stop,
20f733e7
BR		 451};
452
e4e7b892
JG		 453static const struct ata_port_operations mv_iie_ops = {
454 .port_disable = ata_port_disable,
455
456 .tf_load = ata_tf_load,
457 .tf_read = ata_tf_read,
458 .check_status = ata_check_status,
459 .exec_command = ata_exec_command,
460 .dev_select = ata_std_dev_select,
461
462 .phy_reset = mv_phy_reset,
463
464 .qc_prep = mv_qc_prep_iie,
465 .qc_issue = mv_qc_issue,
0d5ff566 466 .data_xfer = ata_data_xfer,
e4e7b892
JG		 467
468 .eng_timeout = mv_eng_timeout,
469
470 .irq_handler = mv_interrupt,
471 .irq_clear = mv_irq_clear,
246ce3b6
AI		 472 .irq_on = ata_irq_on,
473 .irq_ack = ata_irq_ack,
e4e7b892
JG		 474
475 .scr_read = mv_scr_read,
476 .scr_write = mv_scr_write,
477
478 .port_start = mv_port_start,
479 .port_stop = mv_port_stop,
e4e7b892
JG		 480};
481
98ac62de 482static const struct ata_port_info mv_port_info[] = {
20f733e7
BR		 483 { /* chip_504x */
484 .sht = &mv_sht,
cca3974e 485 .flags = MV_COMMON_FLAGS,
31961943 486 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 487 .udma_mask = 0x7f, /* udma0-6 */
488 .port_ops = &mv5_ops,
20f733e7
BR		 489 },
490 { /* chip_508x */
491 .sht = &mv_sht,
cca3974e 492 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
31961943 493 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 494 .udma_mask = 0x7f, /* udma0-6 */
495 .port_ops = &mv5_ops,
20f733e7 496 },
47c2b677
JG		 497 { /* chip_5080 */
498 .sht = &mv_sht,
cca3974e 499 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
47c2b677 500 .pio_mask = 0x1f, /* pio0-4 */
c9d39130
JG		 501 .udma_mask = 0x7f, /* udma0-6 */
502 .port_ops = &mv5_ops,
47c2b677 503 },
20f733e7
BR		 504 { /* chip_604x */
505 .sht = &mv_sht,
cca3974e 506 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
31961943
BR		 507 .pio_mask = 0x1f, /* pio0-4 */
508 .udma_mask = 0x7f, /* udma0-6 */
c9d39130 509 .port_ops = &mv6_ops,
20f733e7
BR		 510 },
511 { /* chip_608x */
512 .sht = &mv_sht,
cca3974e 513 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
31961943
BR		 514 MV_FLAG_DUAL_HC),
515 .pio_mask = 0x1f, /* pio0-4 */
516 .udma_mask = 0x7f, /* udma0-6 */
c9d39130 517 .port_ops = &mv6_ops,
20f733e7 518 },
e4e7b892
JG		 519 { /* chip_6042 */
520 .sht = &mv_sht,
cca3974e 521 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
e4e7b892
JG		 522 .pio_mask = 0x1f, /* pio0-4 */
523 .udma_mask = 0x7f, /* udma0-6 */
524 .port_ops = &mv_iie_ops,
525 },
526 { /* chip_7042 */
527 .sht = &mv_sht,
e93f09dc 528 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
e4e7b892
JG		 529 .pio_mask = 0x1f, /* pio0-4 */
530 .udma_mask = 0x7f, /* udma0-6 */
531 .port_ops = &mv_iie_ops,
532 },
20f733e7
BR		 533};
534
3b7d697d 535static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 536 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
537 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
538 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
539 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
540
541 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
542 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
543 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
544 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
545 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
546
547 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
548
e93f09dc
OJ		 549 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
550
2d2744fc 551 { } /* terminate list */
20f733e7
BR		 552};
553
554static struct pci_driver mv_pci_driver = {
555 .name = DRV_NAME,
556 .id_table = mv_pci_tbl,
557 .probe = mv_init_one,
558 .remove = ata_pci_remove_one,
559};
560
47c2b677
JG		 561static const struct mv_hw_ops mv5xxx_ops = {
562 .phy_errata = mv5_phy_errata,
563 .enable_leds = mv5_enable_leds,
564 .read_preamp = mv5_read_preamp,
565 .reset_hc = mv5_reset_hc,
522479fb
JG		 566 .reset_flash = mv5_reset_flash,
567 .reset_bus = mv5_reset_bus,
47c2b677
JG		 568};
569
570static const struct mv_hw_ops mv6xxx_ops = {
571 .phy_errata = mv6_phy_errata,
572 .enable_leds = mv6_enable_leds,
573 .read_preamp = mv6_read_preamp,
574 .reset_hc = mv6_reset_hc,
522479fb
JG		 575 .reset_flash = mv6_reset_flash,
576 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 577};
578
ddef9bb3
JG		 579/*
580 * module options
581 */
582static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
583
584
d88184fb
JG		 585/* move to PCI layer or libata core? */
586static int pci_go_64(struct pci_dev *pdev)
587{
588 int rc;
589
590 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
591 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
592 if (rc) {
593 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
594 if (rc) {
595 dev_printk(KERN_ERR, &pdev->dev,
596 "64-bit DMA enable failed\n");
597 return rc;
598 }
599 }
600 } else {
601 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
602 if (rc) {
603 dev_printk(KERN_ERR, &pdev->dev,
604 "32-bit DMA enable failed\n");
605 return rc;
606 }
607 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
608 if (rc) {
609 dev_printk(KERN_ERR, &pdev->dev,
610 "32-bit consistent DMA enable failed\n");
611 return rc;
612 }
613 }
614
615 return rc;
616}
617
20f733e7
BR		 618/*
619 * Functions
620 */
621
622static inline void writelfl(unsigned long data, void __iomem *addr)
623{
624 writel(data, addr);
625 (void) readl(addr); /* flush to avoid PCI posted write */
626}
627
20f733e7
BR		 628static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
629{
630 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
631}
632
c9d39130
JG		 633static inline unsigned int mv_hc_from_port(unsigned int port)
634{
635 return port >> MV_PORT_HC_SHIFT;
636}
637
638static inline unsigned int mv_hardport_from_port(unsigned int port)
639{
640 return port & MV_PORT_MASK;
641}
642
643static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
644 unsigned int port)
645{
646 return mv_hc_base(base, mv_hc_from_port(port));
647}
648
20f733e7
BR		 649static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
650{
c9d39130 651 return mv_hc_base_from_port(base, port) +
8b260248 652 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 653 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 654}
655
656static inline void __iomem *mv_ap_base(struct ata_port *ap)
657{
0d5ff566 658 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
20f733e7
BR		 659}
660
cca3974e 661static inline int mv_get_hc_count(unsigned long port_flags)
31961943 662{
cca3974e 663 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 664}
665
666static void mv_irq_clear(struct ata_port *ap)
20f733e7 667{
20f733e7
BR		 668}
669
05b308e1
BR		 670/**
671 * mv_start_dma - Enable eDMA engine
672 * @base: port base address
673 * @pp: port private data
674 *
beec7dbc
TH		 675 * Verify the local cache of the eDMA state is accurate with a
676 * WARN_ON.
05b308e1
BR		 677 *
678 * LOCKING:
679 * Inherited from caller.
680 */
afb0edd9 681static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
20f733e7 682{
afb0edd9
BR		 683 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
684 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
685 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
686 }
beec7dbc 687 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
20f733e7
BR		 688}
689
05b308e1
BR		 690/**
691 * mv_stop_dma - Disable eDMA engine
692 * @ap: ATA channel to manipulate
693 *
beec7dbc
TH		 694 * Verify the local cache of the eDMA state is accurate with a
695 * WARN_ON.
05b308e1
BR		 696 *
697 * LOCKING:
698 * Inherited from caller.
699 */
31961943 700static void mv_stop_dma(struct ata_port *ap)
20f733e7 701{
31961943
BR		 702 void __iomem *port_mmio = mv_ap_base(ap);
703 struct mv_port_priv *pp = ap->private_data;
31961943
BR		 704 u32 reg;
705 int i;
706
afb0edd9
BR		 707 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
708 /* Disable EDMA if active. The disable bit auto clears.
31961943 709 */
31961943
BR		 710 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
711 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
afb0edd9 712 } else {
beec7dbc 713 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
afb0edd9 714 }
8b260248 715
31961943
BR		 716 /* now properly wait for the eDMA to stop */
717 for (i = 1000; i > 0; i--) {
718 reg = readl(port_mmio + EDMA_CMD_OFS);
719 if (!(EDMA_EN & reg)) {
720 break;
721 }
722 udelay(100);
723 }
724
31961943 725 if (EDMA_EN & reg) {
f15a1daf 726 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
afb0edd9 727 /* FIXME: Consider doing a reset here to recover */
31961943 728 }
20f733e7
BR		 729}
730
8a70f8dc 731#ifdef ATA_DEBUG
31961943 732static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 733{
31961943
BR		 734 int b, w;
735 for (b = 0; b < bytes; ) {
736 DPRINTK("%p: ", start + b);
737 for (w = 0; b < bytes && w < 4; w++) {
738 printk("%08x ",readl(start + b));
739 b += sizeof(u32);
740 }
741 printk("\n");
742 }
31961943 743}
8a70f8dc
JG		 744#endif
745
31961943
BR		 746static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
747{
748#ifdef ATA_DEBUG
749 int b, w;
750 u32 dw;
751 for (b = 0; b < bytes; ) {
752 DPRINTK("%02x: ", b);
753 for (w = 0; b < bytes && w < 4; w++) {
754 (void) pci_read_config_dword(pdev,b,&dw);
755 printk("%08x ",dw);
756 b += sizeof(u32);
757 }
758 printk("\n");
759 }
760#endif
761}
762static void mv_dump_all_regs(void __iomem *mmio_base, int port,
763 struct pci_dev *pdev)
764{
765#ifdef ATA_DEBUG
8b260248 766 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 767 port >> MV_PORT_HC_SHIFT);
768 void __iomem *port_base;
769 int start_port, num_ports, p, start_hc, num_hcs, hc;
770
771 if (0 > port) {
772 start_hc = start_port = 0;
773 num_ports = 8; /* shld be benign for 4 port devs */
774 num_hcs = 2;
775 } else {
776 start_hc = port >> MV_PORT_HC_SHIFT;
777 start_port = port;
778 num_ports = num_hcs = 1;
779 }
8b260248 780 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 781 num_ports > 1 ? num_ports - 1 : start_port);
782
783 if (NULL != pdev) {
784 DPRINTK("PCI config space regs:\n");
785 mv_dump_pci_cfg(pdev, 0x68);
786 }
787 DPRINTK("PCI regs:\n");
788 mv_dump_mem(mmio_base+0xc00, 0x3c);
789 mv_dump_mem(mmio_base+0xd00, 0x34);
790 mv_dump_mem(mmio_base+0xf00, 0x4);
791 mv_dump_mem(mmio_base+0x1d00, 0x6c);
792 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 793 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 794 DPRINTK("HC regs (HC %i):\n", hc);
795 mv_dump_mem(hc_base, 0x1c);
796 }
797 for (p = start_port; p < start_port + num_ports; p++) {
798 port_base = mv_port_base(mmio_base, p);
799 DPRINTK("EDMA regs (port %i):\n",p);
800 mv_dump_mem(port_base, 0x54);
801 DPRINTK("SATA regs (port %i):\n",p);
802 mv_dump_mem(port_base+0x300, 0x60);
803 }
804#endif
20f733e7
BR		 805}
806
807static unsigned int mv_scr_offset(unsigned int sc_reg_in)
808{
809 unsigned int ofs;
810
811 switch (sc_reg_in) {
812 case SCR_STATUS:
813 case SCR_CONTROL:
814 case SCR_ERROR:
815 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
816 break;
817 case SCR_ACTIVE:
818 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
819 break;
820 default:
821 ofs = 0xffffffffU;
822 break;
823 }
824 return ofs;
825}
826
827static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
828{
829 unsigned int ofs = mv_scr_offset(sc_reg_in);
830
35177265 831 if (0xffffffffU != ofs)
20f733e7 832 return readl(mv_ap_base(ap) + ofs);
35177265 833 else
20f733e7 834 return (u32) ofs;
20f733e7
BR		 835}
836
837static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
838{
839 unsigned int ofs = mv_scr_offset(sc_reg_in);
840
35177265 841 if (0xffffffffU != ofs)
20f733e7 842 writelfl(val, mv_ap_base(ap) + ofs);
20f733e7
BR		 843}
844
e4e7b892
JG		 845static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
846{
847 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
848
849 /* set up non-NCQ EDMA configuration */
e4e7b892
JG		 850 cfg &= ~(1 << 9); /* disable equeue */
851
e728eabe
JG		 852 if (IS_GEN_I(hpriv)) {
853 cfg &= ~0x1f; /* clear queue depth */
e4e7b892 854 cfg |= (1 << 8); /* enab config burst size mask */
e728eabe 855 }
e4e7b892 856
e728eabe
JG		 857 else if (IS_GEN_II(hpriv)) {
858 cfg &= ~0x1f; /* clear queue depth */
e4e7b892 859 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
e728eabe
JG		 860 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
861 }
e4e7b892
JG		 862
863 else if (IS_GEN_IIE(hpriv)) {
e728eabe
JG		 864 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
865 cfg |= (1 << 22); /* enab 4-entry host queue cache */
e4e7b892
JG		 866 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
867 cfg |= (1 << 18); /* enab early completion */
e728eabe
JG		 868 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
869 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
870 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
e4e7b892
JG		 871 }
872
873 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
874}
875
05b308e1
BR		 876/**
877 * mv_port_start - Port specific init/start routine.
878 * @ap: ATA channel to manipulate
879 *
880 * Allocate and point to DMA memory, init port private memory,
881 * zero indices.
882 *
883 * LOCKING:
884 * Inherited from caller.
885 */
31961943
BR		 886static int mv_port_start(struct ata_port *ap)
887{
cca3974e
JG		 888 struct device *dev = ap->host->dev;
889 struct mv_host_priv *hpriv = ap->host->private_data;
31961943
BR		 890 struct mv_port_priv *pp;
891 void __iomem *port_mmio = mv_ap_base(ap);
892 void *mem;
893 dma_addr_t mem_dma;
24dc5f33 894 int rc;
31961943 895
24dc5f33 896 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 897 if (!pp)
24dc5f33 898 return -ENOMEM;
31961943 899
24dc5f33
TH		 900 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
901 GFP_KERNEL);
6037d6bb 902 if (!mem)
24dc5f33 903 return -ENOMEM;
31961943
BR		 904 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
905
6037d6bb
JG		 906 rc = ata_pad_alloc(ap, dev);
907 if (rc)
24dc5f33 908 return rc;
6037d6bb 909
8b260248 910 /* First item in chunk of DMA memory:
31961943
BR		 911 * 32-slot command request table (CRQB), 32 bytes each in size
912 */
913 pp->crqb = mem;
914 pp->crqb_dma = mem_dma;
915 mem += MV_CRQB_Q_SZ;
916 mem_dma += MV_CRQB_Q_SZ;
917
8b260248 918 /* Second item:
31961943
BR		 919 * 32-slot command response table (CRPB), 8 bytes each in size
920 */
921 pp->crpb = mem;
922 pp->crpb_dma = mem_dma;
923 mem += MV_CRPB_Q_SZ;
924 mem_dma += MV_CRPB_Q_SZ;
925
926 /* Third item:
927 * Table of scatter-gather descriptors (ePRD), 16 bytes each
928 */
929 pp->sg_tbl = mem;
930 pp->sg_tbl_dma = mem_dma;
931
e4e7b892 932 mv_edma_cfg(hpriv, port_mmio);
31961943
BR		 933
934 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
8b260248 935 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
31961943
BR		 936 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
937
e4e7b892
JG		 938 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
939 writelfl(pp->crqb_dma & 0xffffffff,
940 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
941 else
942 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
31961943
BR		 943
944 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
e4e7b892
JG		 945
946 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
947 writelfl(pp->crpb_dma & 0xffffffff,
948 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
949 else
950 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
951
8b260248 952 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
31961943
BR		 953 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
954
31961943
BR		 955 /* Don't turn on EDMA here...do it before DMA commands only. Else
956 * we'll be unable to send non-data, PIO, etc due to restricted access
957 * to shadow regs.
958 */
959 ap->private_data = pp;
960 return 0;
961}
962
05b308e1
BR		 963/**
964 * mv_port_stop - Port specific cleanup/stop routine.
965 * @ap: ATA channel to manipulate
966 *
967 * Stop DMA, cleanup port memory.
968 *
969 * LOCKING:
cca3974e 970 * This routine uses the host lock to protect the DMA stop.
05b308e1 971 */
31961943
BR		 972static void mv_port_stop(struct ata_port *ap)
973{
afb0edd9 974 unsigned long flags;
31961943 975
cca3974e 976 spin_lock_irqsave(&ap->host->lock, flags);
31961943 977 mv_stop_dma(ap);
cca3974e 978 spin_unlock_irqrestore(&ap->host->lock, flags);
31961943
BR		 979}
980
05b308e1
BR		 981/**
982 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
983 * @qc: queued command whose SG list to source from
984 *
985 * Populate the SG list and mark the last entry.
986 *
987 * LOCKING:
988 * Inherited from caller.
989 */
d88184fb 990static unsigned int mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 991{
992 struct mv_port_priv *pp = qc->ap->private_data;
d88184fb 993 unsigned int n_sg = 0;
972c26bd 994 struct scatterlist *sg;
d88184fb 995 struct mv_sg *mv_sg;
31961943 996
d88184fb 997 mv_sg = pp->sg_tbl;
972c26bd 998 ata_for_each_sg(sg, qc) {
d88184fb
JG		 999 dma_addr_t addr = sg_dma_address(sg);
1000 u32 sg_len = sg_dma_len(sg);
22374677 1001
d88184fb
JG		 1002 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1003 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1004 mv_sg->flags_size = cpu_to_le32(sg_len & 0xffff);
22374677 1005
d88184fb
JG		 1006 if (ata_sg_is_last(sg, qc))
1007 mv_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
22374677 1008
d88184fb
JG		 1009 mv_sg++;
1010 n_sg++;
31961943 1011 }
d88184fb
JG		 1012
1013 return n_sg;
31961943
BR		 1014}
1015
a6432436 1016static inline unsigned mv_inc_q_index(unsigned index)
31961943 1017{
a6432436 1018 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
31961943
BR		 1019}
1020
e1469874 1021static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1022{
559eedad 1023 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1024 (last ? CRQB_CMD_LAST : 0);
559eedad 1025 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1026}
1027
05b308e1
BR		 1028/**
1029 * mv_qc_prep - Host specific command preparation.
1030 * @qc: queued command to prepare
1031 *
1032 * This routine simply redirects to the general purpose routine
1033 * if command is not DMA. Else, it handles prep of the CRQB
1034 * (command request block), does some sanity checking, and calls
1035 * the SG load routine.
1036 *
1037 * LOCKING:
1038 * Inherited from caller.
1039 */
31961943
BR		 1040static void mv_qc_prep(struct ata_queued_cmd *qc)
1041{
1042 struct ata_port *ap = qc->ap;
1043 struct mv_port_priv *pp = ap->private_data;
e1469874 1044 __le16 *cw;
31961943
BR		 1045 struct ata_taskfile *tf;
1046 u16 flags = 0;
a6432436 1047 unsigned in_index;
31961943 1048
e4e7b892 1049 if (ATA_PROT_DMA != qc->tf.protocol)
31961943 1050 return;
20f733e7 1051
31961943
BR		 1052 /* Fill in command request block
1053 */
e4e7b892 1054 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1055 flags |= CRQB_FLAG_READ;
beec7dbc 1056 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943
BR		 1057 flags |= qc->tag << CRQB_TAG_SHIFT;
1058
a6432436
ML		 1059 /* get current queue index from hardware */
1060 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1061 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1062
1063 pp->crqb[in_index].sg_addr =
31961943 1064 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
a6432436 1065 pp->crqb[in_index].sg_addr_hi =
31961943 1066 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
a6432436 1067 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1068
a6432436 1069 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1070 tf = &qc->tf;
1071
1072 /* Sadly, the CRQB cannot accomodate all registers--there are
1073 * only 11 bytes...so we must pick and choose required
1074 * registers based on the command. So, we drop feature and
1075 * hob_feature for [RW] DMA commands, but they are needed for
1076 * NCQ. NCQ will drop hob_nsect.
20f733e7 1077 */
31961943
BR		 1078 switch (tf->command) {
1079 case ATA_CMD_READ:
1080 case ATA_CMD_READ_EXT:
1081 case ATA_CMD_WRITE:
1082 case ATA_CMD_WRITE_EXT:
c15d85c8 1083 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1084 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1085 break;
1086#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1087 case ATA_CMD_FPDMA_READ:
1088 case ATA_CMD_FPDMA_WRITE:
8b260248 1089 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1090 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1091 break;
1092#endif /* FIXME: remove this line when NCQ added */
1093 default:
1094 /* The only other commands EDMA supports in non-queued and
1095 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1096 * of which are defined/used by Linux. If we get here, this
1097 * driver needs work.
1098 *
1099 * FIXME: modify libata to give qc_prep a return value and
1100 * return error here.
1101 */
1102 BUG_ON(tf->command);
1103 break;
1104 }
1105 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1106 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1107 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1108 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1109 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1110 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1111 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1112 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1113 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1114
e4e7b892
JG		 1115 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1116 return;
1117 mv_fill_sg(qc);
1118}
1119
1120/**
1121 * mv_qc_prep_iie - Host specific command preparation.
1122 * @qc: queued command to prepare
1123 *
1124 * This routine simply redirects to the general purpose routine
1125 * if command is not DMA. Else, it handles prep of the CRQB
1126 * (command request block), does some sanity checking, and calls
1127 * the SG load routine.
1128 *
1129 * LOCKING:
1130 * Inherited from caller.
1131 */
1132static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1133{
1134 struct ata_port *ap = qc->ap;
1135 struct mv_port_priv *pp = ap->private_data;
1136 struct mv_crqb_iie *crqb;
1137 struct ata_taskfile *tf;
a6432436 1138 unsigned in_index;
e4e7b892
JG		 1139 u32 flags = 0;
1140
1141 if (ATA_PROT_DMA != qc->tf.protocol)
1142 return;
1143
e4e7b892
JG		 1144 /* Fill in Gen IIE command request block
1145 */
1146 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1147 flags |= CRQB_FLAG_READ;
1148
beec7dbc 1149 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892
JG		 1150 flags |= qc->tag << CRQB_TAG_SHIFT;
1151
a6432436
ML		 1152 /* get current queue index from hardware */
1153 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1154 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1155
1156 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
e4e7b892
JG		 1157 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1158 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1159 crqb->flags = cpu_to_le32(flags);
1160
1161 tf = &qc->tf;
1162 crqb->ata_cmd[0] = cpu_to_le32(
1163 (tf->command << 16) |
1164 (tf->feature << 24)
1165 );
1166 crqb->ata_cmd[1] = cpu_to_le32(
1167 (tf->lbal << 0) |
1168 (tf->lbam << 8) |
1169 (tf->lbah << 16) |
1170 (tf->device << 24)
1171 );
1172 crqb->ata_cmd[2] = cpu_to_le32(
1173 (tf->hob_lbal << 0) |
1174 (tf->hob_lbam << 8) |
1175 (tf->hob_lbah << 16) |
1176 (tf->hob_feature << 24)
1177 );
1178 crqb->ata_cmd[3] = cpu_to_le32(
1179 (tf->nsect << 0) |
1180 (tf->hob_nsect << 8)
1181 );
1182
1183 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1184 return;
31961943
BR		 1185 mv_fill_sg(qc);
1186}
1187
05b308e1
BR		 1188/**
1189 * mv_qc_issue - Initiate a command to the host
1190 * @qc: queued command to start
1191 *
1192 * This routine simply redirects to the general purpose routine
1193 * if command is not DMA. Else, it sanity checks our local
1194 * caches of the request producer/consumer indices then enables
1195 * DMA and bumps the request producer index.
1196 *
1197 * LOCKING:
1198 * Inherited from caller.
1199 */
9a3d9eb0 1200static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943
BR		 1201{
1202 void __iomem *port_mmio = mv_ap_base(qc->ap);
1203 struct mv_port_priv *pp = qc->ap->private_data;
a6432436 1204 unsigned in_index;
31961943
BR		 1205 u32 in_ptr;
1206
1207 if (ATA_PROT_DMA != qc->tf.protocol) {
1208 /* We're about to send a non-EDMA capable command to the
1209 * port. Turn off EDMA so there won't be problems accessing
1210 * shadow block, etc registers.
1211 */
1212 mv_stop_dma(qc->ap);
1213 return ata_qc_issue_prot(qc);
1214 }
1215
a6432436
ML		 1216 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1217 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
31961943 1218
31961943 1219 /* until we do queuing, the queue should be empty at this point */
a6432436
ML		 1220 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1221 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943 1222
a6432436 1223 in_index = mv_inc_q_index(in_index); /* now incr producer index */
31961943 1224
afb0edd9 1225 mv_start_dma(port_mmio, pp);
31961943
BR		 1226
1227 /* and write the request in pointer to kick the EDMA to life */
1228 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
a6432436 1229 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1230 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1231
1232 return 0;
1233}
1234
05b308e1
BR		 1235/**
1236 * mv_get_crpb_status - get status from most recently completed cmd
1237 * @ap: ATA channel to manipulate
1238 *
1239 * This routine is for use when the port is in DMA mode, when it
1240 * will be using the CRPB (command response block) method of
beec7dbc 1241 * returning command completion information. We check indices
05b308e1
BR		 1242 * are good, grab status, and bump the response consumer index to
1243 * prove that we're up to date.
1244 *
1245 * LOCKING:
1246 * Inherited from caller.
1247 */
31961943
BR		 1248static u8 mv_get_crpb_status(struct ata_port *ap)
1249{
1250 void __iomem *port_mmio = mv_ap_base(ap);
1251 struct mv_port_priv *pp = ap->private_data;
a6432436 1252 unsigned out_index;
31961943 1253 u32 out_ptr;
806a6e7a 1254 u8 ata_status;
31961943 1255
a6432436
ML		 1256 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1257 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
31961943 1258
a6432436
ML		 1259 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1260 >> CRPB_FLAG_STATUS_SHIFT;
806a6e7a 1261
31961943 1262 /* increment our consumer index... */
a6432436 1263 out_index = mv_inc_q_index(out_index);
8b260248 1264
31961943 1265 /* and, until we do NCQ, there should only be 1 CRPB waiting */
a6432436
ML		 1266 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1267 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
31961943
BR		 1268
1269 /* write out our inc'd consumer index so EDMA knows we're caught up */
1270 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
a6432436 1271 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
31961943
BR		 1272 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1273
1274 /* Return ATA status register for completed CRPB */
806a6e7a 1275 return ata_status;
31961943
BR		 1276}
1277
05b308e1
BR		 1278/**
1279 * mv_err_intr - Handle error interrupts on the port
1280 * @ap: ATA channel to manipulate
9b358e30 1281 * @reset_allowed: bool: 0 == don't trigger from reset here
05b308e1
BR		 1282 *
1283 * In most cases, just clear the interrupt and move on. However,
1284 * some cases require an eDMA reset, which is done right before
1285 * the COMRESET in mv_phy_reset(). The SERR case requires a
1286 * clear of pending errors in the SATA SERROR register. Finally,
1287 * if the port disabled DMA, update our cached copy to match.
1288 *
1289 * LOCKING:
1290 * Inherited from caller.
1291 */
9b358e30 1292static void mv_err_intr(struct ata_port *ap, int reset_allowed)
31961943
BR		 1293{
1294 void __iomem *port_mmio = mv_ap_base(ap);
1295 u32 edma_err_cause, serr = 0;
20f733e7
BR		 1296
1297 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1298
1299 if (EDMA_ERR_SERR & edma_err_cause) {
81952c54
TH		 1300 sata_scr_read(ap, SCR_ERROR, &serr);
1301 sata_scr_write_flush(ap, SCR_ERROR, serr);
20f733e7 1302 }
afb0edd9
BR		 1303 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1304 struct mv_port_priv *pp = ap->private_data;
1305 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1306 }
1307 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
44877b4e 1308 "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr);
20f733e7
BR		 1309
1310 /* Clear EDMA now that SERR cleanup done */
1311 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1312
1313 /* check for fatal here and recover if needed */
9b358e30 1314 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
c9d39130 1315 mv_stop_and_reset(ap);
20f733e7
BR		 1316}
1317
05b308e1
BR		 1318/**
1319 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 1320 * @host: host specific structure
05b308e1
BR		 1321 * @relevant: port error bits relevant to this host controller
1322 * @hc: which host controller we're to look at
1323 *
1324 * Read then write clear the HC interrupt status then walk each
1325 * port connected to the HC and see if it needs servicing. Port
1326 * success ints are reported in the HC interrupt status reg, the
1327 * port error ints are reported in the higher level main
1328 * interrupt status register and thus are passed in via the
1329 * 'relevant' argument.
1330 *
1331 * LOCKING:
1332 * Inherited from caller.
1333 */
cca3974e 1334static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
20f733e7 1335{
0d5ff566 1336 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
20f733e7 1337 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
20f733e7
BR		 1338 struct ata_queued_cmd *qc;
1339 u32 hc_irq_cause;
31961943 1340 int shift, port, port0, hard_port, handled;
a7dac447 1341 unsigned int err_mask;
20f733e7 1342
35177265 1343 if (hc == 0)
20f733e7 1344 port0 = 0;
35177265 1345 else
20f733e7 1346 port0 = MV_PORTS_PER_HC;
20f733e7
BR		 1347
1348 /* we'll need the HC success int register in most cases */
1349 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
35177265 1350 if (hc_irq_cause)
31961943 1351 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 1352
1353 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1354 hc,relevant,hc_irq_cause);
1355
1356 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
cd85f6e2 1357 u8 ata_status = 0;
cca3974e 1358 struct ata_port *ap = host->ports[port];
63af2a5c 1359 struct mv_port_priv *pp = ap->private_data;
55d8ca4f 1360
e857f141 1361 hard_port = mv_hardport_from_port(port); /* range 0..3 */
31961943 1362 handled = 0; /* ensure ata_status is set if handled++ */
20f733e7 1363
63af2a5c 1364 /* Note that DEV_IRQ might happen spuriously during EDMA,
e857f141
ML		 1365 * and should be ignored in such cases.
1366 * The cause of this is still under investigation.
8190bdb9 1367 */
63af2a5c
ML		 1368 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1369 /* EDMA: check for response queue interrupt */
1370 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1371 ata_status = mv_get_crpb_status(ap);
1372 handled = 1;
1373 }
1374 } else {
1375 /* PIO: check for device (drive) interrupt */
1376 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
0d5ff566 1377 ata_status = readb(ap->ioaddr.status_addr);
63af2a5c 1378 handled = 1;
e857f141
ML		 1379 /* ignore spurious intr if drive still BUSY */
1380 if (ata_status & ATA_BUSY) {
1381 ata_status = 0;
1382 handled = 0;
1383 }
63af2a5c 1384 }
20f733e7
BR		 1385 }
1386
029f5468 1387 if (ap && (ap->flags & ATA_FLAG_DISABLED))
a2c91a88
JG		 1388 continue;
1389
a7dac447
JG		 1390 err_mask = ac_err_mask(ata_status);
1391
31961943 1392 shift = port << 1; /* (port * 2) */
20f733e7
BR		 1393 if (port >= MV_PORTS_PER_HC) {
1394 shift++; /* skip bit 8 in the HC Main IRQ reg */
1395 }
1396 if ((PORT0_ERR << shift) & relevant) {
9b358e30 1397 mv_err_intr(ap, 1);
a7dac447 1398 err_mask |= AC_ERR_OTHER;
63af2a5c 1399 handled = 1;
20f733e7 1400 }
8b260248 1401
63af2a5c 1402 if (handled) {
20f733e7 1403 qc = ata_qc_from_tag(ap, ap->active_tag);
63af2a5c 1404 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
20f733e7
BR		 1405 VPRINTK("port %u IRQ found for qc, "
1406 "ata_status 0x%x\n", port,ata_status);
20f733e7 1407 /* mark qc status appropriately */
701db69d 1408 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
a22e2eb0
AL		 1409 qc->err_mask |= err_mask;
1410 ata_qc_complete(qc);
1411 }
20f733e7
BR		 1412 }
1413 }
1414 }
1415 VPRINTK("EXIT\n");
1416}
1417
05b308e1 1418/**
8b260248 1419 * mv_interrupt -
05b308e1
BR		 1420 * @irq: unused
1421 * @dev_instance: private data; in this case the host structure
1422 * @regs: unused
1423 *
1424 * Read the read only register to determine if any host
1425 * controllers have pending interrupts. If so, call lower level
1426 * routine to handle. Also check for PCI errors which are only
1427 * reported here.
1428 *
8b260248 1429 * LOCKING:
cca3974e 1430 * This routine holds the host lock while processing pending
05b308e1
BR		 1431 * interrupts.
1432 */
7d12e780 1433static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 1434{
cca3974e 1435 struct ata_host *host = dev_instance;
20f733e7 1436 unsigned int hc, handled = 0, n_hcs;
0d5ff566 1437 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
615ab953 1438 struct mv_host_priv *hpriv;
20f733e7
BR		 1439 u32 irq_stat;
1440
20f733e7 1441 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
20f733e7
BR		 1442
1443 /* check the cases where we either have nothing pending or have read
1444 * a bogus register value which can indicate HW removal or PCI fault
1445 */
35177265 1446 if (!irq_stat || (0xffffffffU == irq_stat))
20f733e7 1447 return IRQ_NONE;
20f733e7 1448
cca3974e
JG		 1449 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1450 spin_lock(&host->lock);
20f733e7
BR		 1451
1452 for (hc = 0; hc < n_hcs; hc++) {
1453 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1454 if (relevant) {
cca3974e 1455 mv_host_intr(host, relevant, hc);
31961943 1456 handled++;
20f733e7
BR		 1457 }
1458 }
615ab953 1459
cca3974e 1460 hpriv = host->private_data;
615ab953
ML		 1461 if (IS_60XX(hpriv)) {
1462 /* deal with the interrupt coalescing bits */
1463 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1464 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1465 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1466 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1467 }
1468 }
1469
20f733e7 1470 if (PCI_ERR & irq_stat) {
31961943
BR		 1471 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1472 readl(mmio + PCI_IRQ_CAUSE_OFS));
1473
afb0edd9 1474 DPRINTK("All regs @ PCI error\n");
cca3974e 1475 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
20f733e7 1476
31961943
BR		 1477 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1478 handled++;
1479 }
cca3974e 1480 spin_unlock(&host->lock);
20f733e7
BR		 1481
1482 return IRQ_RETVAL(handled);
1483}
1484
c9d39130
JG		 1485static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1486{
1487 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1488 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1489
1490 return hc_mmio + ofs;
1491}
1492
1493static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1494{
1495 unsigned int ofs;
1496
1497 switch (sc_reg_in) {
1498 case SCR_STATUS:
1499 case SCR_ERROR:
1500 case SCR_CONTROL:
1501 ofs = sc_reg_in * sizeof(u32);
1502 break;
1503 default:
1504 ofs = 0xffffffffU;
1505 break;
1506 }
1507 return ofs;
1508}
1509
1510static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1511{
0d5ff566
TH		 1512 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1513 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1514 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1515
1516 if (ofs != 0xffffffffU)
0d5ff566 1517 return readl(addr + ofs);
c9d39130
JG		 1518 else
1519 return (u32) ofs;
1520}
1521
1522static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1523{
0d5ff566
TH		 1524 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1525 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1526 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1527
1528 if (ofs != 0xffffffffU)
0d5ff566 1529 writelfl(val, addr + ofs);
c9d39130
JG		 1530}
1531
522479fb
JG		 1532static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1533{
1534 u8 rev_id;
1535 int early_5080;
1536
1537 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1538
1539 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1540
1541 if (!early_5080) {
1542 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1543 tmp |= (1 << 0);
1544 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1545 }
1546
1547 mv_reset_pci_bus(pdev, mmio);
1548}
1549
1550static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1551{
1552 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1553}
1554
47c2b677 1555static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1556 void __iomem *mmio)
1557{
c9d39130
JG		 1558 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1559 u32 tmp;
1560
1561 tmp = readl(phy_mmio + MV5_PHY_MODE);
1562
1563 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1564 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 1565}
1566
47c2b677 1567static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1568{
522479fb
JG		 1569 u32 tmp;
1570
1571 writel(0, mmio + MV_GPIO_PORT_CTL);
1572
1573 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1574
1575 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1576 tmp |= ~(1 << 0);
1577 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 1578}
1579
2a47ce06
JG		 1580static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1581 unsigned int port)
bca1c4eb 1582{
c9d39130
JG		 1583 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1584 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1585 u32 tmp;
1586 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1587
1588 if (fix_apm_sq) {
1589 tmp = readl(phy_mmio + MV5_LT_MODE);
1590 tmp |= (1 << 19);
1591 writel(tmp, phy_mmio + MV5_LT_MODE);
1592
1593 tmp = readl(phy_mmio + MV5_PHY_CTL);
1594 tmp &= ~0x3;
1595 tmp |= 0x1;
1596 writel(tmp, phy_mmio + MV5_PHY_CTL);
1597 }
1598
1599 tmp = readl(phy_mmio + MV5_PHY_MODE);
1600 tmp &= ~mask;
1601 tmp |= hpriv->signal[port].pre;
1602 tmp |= hpriv->signal[port].amps;
1603 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 1604}
1605
c9d39130
JG		 1606
1607#undef ZERO
1608#define ZERO(reg) writel(0, port_mmio + (reg))
1609static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1610 unsigned int port)
1611{
1612 void __iomem *port_mmio = mv_port_base(mmio, port);
1613
1614 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1615
1616 mv_channel_reset(hpriv, mmio, port);
1617
1618 ZERO(0x028); /* command */
1619 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1620 ZERO(0x004); /* timer */
1621 ZERO(0x008); /* irq err cause */
1622 ZERO(0x00c); /* irq err mask */
1623 ZERO(0x010); /* rq bah */
1624 ZERO(0x014); /* rq inp */
1625 ZERO(0x018); /* rq outp */
1626 ZERO(0x01c); /* respq bah */
1627 ZERO(0x024); /* respq outp */
1628 ZERO(0x020); /* respq inp */
1629 ZERO(0x02c); /* test control */
1630 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1631}
1632#undef ZERO
1633
1634#define ZERO(reg) writel(0, hc_mmio + (reg))
1635static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1636 unsigned int hc)
47c2b677 1637{
c9d39130
JG		 1638 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1639 u32 tmp;
1640
1641 ZERO(0x00c);
1642 ZERO(0x010);
1643 ZERO(0x014);
1644 ZERO(0x018);
1645
1646 tmp = readl(hc_mmio + 0x20);
1647 tmp &= 0x1c1c1c1c;
1648 tmp |= 0x03030303;
1649 writel(tmp, hc_mmio + 0x20);
1650}
1651#undef ZERO
1652
1653static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1654 unsigned int n_hc)
1655{
1656 unsigned int hc, port;
1657
1658 for (hc = 0; hc < n_hc; hc++) {
1659 for (port = 0; port < MV_PORTS_PER_HC; port++)
1660 mv5_reset_hc_port(hpriv, mmio,
1661 (hc * MV_PORTS_PER_HC) + port);
1662
1663 mv5_reset_one_hc(hpriv, mmio, hc);
1664 }
1665
1666 return 0;
47c2b677
JG		 1667}
1668
101ffae2
JG		 1669#undef ZERO
1670#define ZERO(reg) writel(0, mmio + (reg))
1671static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1672{
1673 u32 tmp;
1674
1675 tmp = readl(mmio + MV_PCI_MODE);
1676 tmp &= 0xff00ffff;
1677 writel(tmp, mmio + MV_PCI_MODE);
1678
1679 ZERO(MV_PCI_DISC_TIMER);
1680 ZERO(MV_PCI_MSI_TRIGGER);
1681 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1682 ZERO(HC_MAIN_IRQ_MASK_OFS);
1683 ZERO(MV_PCI_SERR_MASK);
1684 ZERO(PCI_IRQ_CAUSE_OFS);
1685 ZERO(PCI_IRQ_MASK_OFS);
1686 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1687 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1688 ZERO(MV_PCI_ERR_ATTRIBUTE);
1689 ZERO(MV_PCI_ERR_COMMAND);
1690}
1691#undef ZERO
1692
1693static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1694{
1695 u32 tmp;
1696
1697 mv5_reset_flash(hpriv, mmio);
1698
1699 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1700 tmp &= 0x3;
1701 tmp |= (1 << 5) | (1 << 6);
1702 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1703}
1704
1705/**
1706 * mv6_reset_hc - Perform the 6xxx global soft reset
1707 * @mmio: base address of the HBA
1708 *
1709 * This routine only applies to 6xxx parts.
1710 *
1711 * LOCKING:
1712 * Inherited from caller.
1713 */
c9d39130
JG		 1714static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1715 unsigned int n_hc)
101ffae2
JG		 1716{
1717 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1718 int i, rc = 0;
1719 u32 t;
1720
1721 /* Following procedure defined in PCI "main command and status
1722 * register" table.
1723 */
1724 t = readl(reg);
1725 writel(t | STOP_PCI_MASTER, reg);
1726
1727 for (i = 0; i < 1000; i++) {
1728 udelay(1);
1729 t = readl(reg);
1730 if (PCI_MASTER_EMPTY & t) {
1731 break;
1732 }
1733 }
1734 if (!(PCI_MASTER_EMPTY & t)) {
1735 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1736 rc = 1;
1737 goto done;
1738 }
1739
1740 /* set reset */
1741 i = 5;
1742 do {
1743 writel(t | GLOB_SFT_RST, reg);
1744 t = readl(reg);
1745 udelay(1);
1746 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1747
1748 if (!(GLOB_SFT_RST & t)) {
1749 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1750 rc = 1;
1751 goto done;
1752 }
1753
1754 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1755 i = 5;
1756 do {
1757 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1758 t = readl(reg);
1759 udelay(1);
1760 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1761
1762 if (GLOB_SFT_RST & t) {
1763 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1764 rc = 1;
1765 }
1766done:
1767 return rc;
1768}
1769
47c2b677 1770static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1771 void __iomem *mmio)
1772{
1773 void __iomem *port_mmio;
1774 u32 tmp;
1775
ba3fe8fb
JG		 1776 tmp = readl(mmio + MV_RESET_CFG);
1777 if ((tmp & (1 << 0)) == 0) {
47c2b677 1778 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 1779 hpriv->signal[idx].pre = 0x1 << 5;
1780 return;
1781 }
1782
1783 port_mmio = mv_port_base(mmio, idx);
1784 tmp = readl(port_mmio + PHY_MODE2);
1785
1786 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1787 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1788}
1789
47c2b677 1790static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1791{
47c2b677 1792 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
ba3fe8fb
JG		 1793}
1794
c9d39130 1795static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 1796 unsigned int port)
bca1c4eb 1797{
c9d39130
JG		 1798 void __iomem *port_mmio = mv_port_base(mmio, port);
1799
bca1c4eb 1800 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 1801 int fix_phy_mode2 =
1802 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 1803 int fix_phy_mode4 =
47c2b677
JG		 1804 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1805 u32 m2, tmp;
1806
1807 if (fix_phy_mode2) {
1808 m2 = readl(port_mmio + PHY_MODE2);
1809 m2 &= ~(1 << 16);
1810 m2 |= (1 << 31);
1811 writel(m2, port_mmio + PHY_MODE2);
1812
1813 udelay(200);
1814
1815 m2 = readl(port_mmio + PHY_MODE2);
1816 m2 &= ~((1 << 16) | (1 << 31));
1817 writel(m2, port_mmio + PHY_MODE2);
1818
1819 udelay(200);
1820 }
1821
1822 /* who knows what this magic does */
1823 tmp = readl(port_mmio + PHY_MODE3);
1824 tmp &= ~0x7F800000;
1825 tmp |= 0x2A800000;
1826 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 1827
1828 if (fix_phy_mode4) {
47c2b677 1829 u32 m4;
bca1c4eb
JG		 1830
1831 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 1832
1833 if (hp_flags & MV_HP_ERRATA_60X1B2)
1834 tmp = readl(port_mmio + 0x310);
bca1c4eb
JG		 1835
1836 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1837
1838 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 1839
1840 if (hp_flags & MV_HP_ERRATA_60X1B2)
1841 writel(tmp, port_mmio + 0x310);
bca1c4eb
JG		 1842 }
1843
1844 /* Revert values of pre-emphasis and signal amps to the saved ones */
1845 m2 = readl(port_mmio + PHY_MODE2);
1846
1847 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 1848 m2 |= hpriv->signal[port].amps;
1849 m2 |= hpriv->signal[port].pre;
47c2b677 1850 m2 &= ~(1 << 16);
bca1c4eb 1851
e4e7b892
JG		 1852 /* according to mvSata 3.6.1, some IIE values are fixed */
1853 if (IS_GEN_IIE(hpriv)) {
1854 m2 &= ~0xC30FF01F;
1855 m2 |= 0x0000900F;
1856 }
1857
bca1c4eb
JG		 1858 writel(m2, port_mmio + PHY_MODE2);
1859}
1860
c9d39130
JG		 1861static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1862 unsigned int port_no)
1863{
1864 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1865
1866 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1867
1868 if (IS_60XX(hpriv)) {
1869 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 1870 ifctl |= (1 << 7); /* enable gen2i speed */
1871 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
c9d39130
JG		 1872 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1873 }
1874
1875 udelay(25); /* allow reset propagation */
1876
1877 /* Spec never mentions clearing the bit. Marvell's driver does
1878 * clear the bit, however.
1879 */
1880 writelfl(0, port_mmio + EDMA_CMD_OFS);
1881
1882 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1883
1884 if (IS_50XX(hpriv))
1885 mdelay(1);
1886}
1887
1888static void mv_stop_and_reset(struct ata_port *ap)
1889{
cca3974e 1890 struct mv_host_priv *hpriv = ap->host->private_data;
0d5ff566 1891 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
c9d39130
JG		 1892
1893 mv_stop_dma(ap);
1894
1895 mv_channel_reset(hpriv, mmio, ap->port_no);
1896
22374677
JG		 1897 __mv_phy_reset(ap, 0);
1898}
1899
1900static inline void __msleep(unsigned int msec, int can_sleep)
1901{
1902 if (can_sleep)
1903 msleep(msec);
1904 else
1905 mdelay(msec);
c9d39130
JG		 1906}
1907
05b308e1 1908/**
22374677 1909 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
05b308e1
BR		 1910 * @ap: ATA channel to manipulate
1911 *
1912 * Part of this is taken from __sata_phy_reset and modified to
1913 * not sleep since this routine gets called from interrupt level.
1914 *
1915 * LOCKING:
1916 * Inherited from caller. This is coded to safe to call at
1917 * interrupt level, i.e. it does not sleep.
31961943 1918 */
22374677 1919static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
20f733e7 1920{
095fec88 1921 struct mv_port_priv *pp = ap->private_data;
cca3974e 1922 struct mv_host_priv *hpriv = ap->host->private_data;
20f733e7
BR		 1923 void __iomem *port_mmio = mv_ap_base(ap);
1924 struct ata_taskfile tf;
1925 struct ata_device *dev = &ap->device[0];
31961943 1926 unsigned long timeout;
22374677
JG		 1927 int retry = 5;
1928 u32 sstatus;
20f733e7
BR		 1929
1930 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1931
095fec88 1932 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
31961943
BR		 1933 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1934 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
20f733e7 1935
22374677
JG		 1936 /* Issue COMRESET via SControl */
1937comreset_retry:
81952c54 1938 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
22374677
JG		 1939 __msleep(1, can_sleep);
1940
81952c54 1941 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
22374677
JG		 1942 __msleep(20, can_sleep);
1943
1944 timeout = jiffies + msecs_to_jiffies(200);
31961943 1945 do {
81952c54 1946 sata_scr_read(ap, SCR_STATUS, &sstatus);
62f1d0e6 1947 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
31961943 1948 break;
22374677
JG		 1949
1950 __msleep(1, can_sleep);
31961943 1951 } while (time_before(jiffies, timeout));
20f733e7 1952
22374677
JG		 1953 /* work around errata */
1954 if (IS_60XX(hpriv) &&
1955 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1956 (retry-- > 0))
1957 goto comreset_retry;
095fec88
JG		 1958
1959 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
31961943
BR		 1960 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1961 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1962
81952c54 1963 if (ata_port_online(ap)) {
31961943
BR		 1964 ata_port_probe(ap);
1965 } else {
81952c54 1966 sata_scr_read(ap, SCR_STATUS, &sstatus);
f15a1daf
TH		 1967 ata_port_printk(ap, KERN_INFO,
1968 "no device found (phy stat %08x)\n", sstatus);
31961943 1969 ata_port_disable(ap);
20f733e7
BR		 1970 return;
1971 }
31961943 1972 ap->cbl = ATA_CBL_SATA;
20f733e7 1973
22374677
JG		 1974 /* even after SStatus reflects that device is ready,
1975 * it seems to take a while for link to be fully
1976 * established (and thus Status no longer 0x80/0x7F),
1977 * so we poll a bit for that, here.
1978 */
1979 retry = 20;
1980 while (1) {
1981 u8 drv_stat = ata_check_status(ap);
1982 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1983 break;
1984 __msleep(500, can_sleep);
1985 if (retry-- <= 0)
1986 break;
1987 }
1988
0d5ff566
TH		 1989 tf.lbah = readb(ap->ioaddr.lbah_addr);
1990 tf.lbam = readb(ap->ioaddr.lbam_addr);
1991 tf.lbal = readb(ap->ioaddr.lbal_addr);
1992 tf.nsect = readb(ap->ioaddr.nsect_addr);
20f733e7
BR		 1993
1994 dev->class = ata_dev_classify(&tf);
e1211e3f 1995 if (!ata_dev_enabled(dev)) {
20f733e7
BR		 1996 VPRINTK("Port disabled post-sig: No device present.\n");
1997 ata_port_disable(ap);
1998 }
095fec88
JG		 1999
2000 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2001
2002 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2003
bca1c4eb 2004 VPRINTK("EXIT\n");
20f733e7
BR		 2005}
2006
22374677
JG		 2007static void mv_phy_reset(struct ata_port *ap)
2008{
2009 __mv_phy_reset(ap, 1);
2010}
2011
05b308e1
BR		 2012/**
2013 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2014 * @ap: ATA channel to manipulate
2015 *
2016 * Intent is to clear all pending error conditions, reset the
2017 * chip/bus, fail the command, and move on.
2018 *
2019 * LOCKING:
cca3974e 2020 * This routine holds the host lock while failing the command.
05b308e1 2021 */
31961943
BR		 2022static void mv_eng_timeout(struct ata_port *ap)
2023{
0d5ff566 2024 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
31961943 2025 struct ata_queued_cmd *qc;
2f9719b6 2026 unsigned long flags;
31961943 2027
f15a1daf 2028 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
31961943 2029 DPRINTK("All regs @ start of eng_timeout\n");
0d5ff566 2030 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
31961943
BR		 2031
2032 qc = ata_qc_from_tag(ap, ap->active_tag);
2033 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
0d5ff566 2034 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
31961943 2035
cca3974e 2036 spin_lock_irqsave(&ap->host->lock, flags);
9b358e30 2037 mv_err_intr(ap, 0);
c9d39130 2038 mv_stop_and_reset(ap);
cca3974e 2039 spin_unlock_irqrestore(&ap->host->lock, flags);
31961943 2040
9b358e30
ML		 2041 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2042 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2043 qc->err_mask |= AC_ERR_TIMEOUT;
2044 ata_eh_qc_complete(qc);
2045 }
31961943
BR		 2046}
2047
05b308e1
BR		 2048/**
2049 * mv_port_init - Perform some early initialization on a single port.
2050 * @port: libata data structure storing shadow register addresses
2051 * @port_mmio: base address of the port
2052 *
2053 * Initialize shadow register mmio addresses, clear outstanding
2054 * interrupts on the port, and unmask interrupts for the future
2055 * start of the port.
2056 *
2057 * LOCKING:
2058 * Inherited from caller.
2059 */
31961943 2060static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2061{
0d5ff566 2062 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2063 unsigned serr_ofs;
2064
8b260248 2065 /* PIO related setup
31961943
BR		 2066 */
2067 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2068 port->error_addr =
31961943
BR		 2069 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2070 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2071 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2072 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2073 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2074 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2075 port->status_addr =
31961943
BR		 2076 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2077 /* special case: control/altstatus doesn't have ATA_REG_ address */
2078 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2079
2080 /* unused: */
8d9db2d2 2081 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2082
31961943
BR		 2083 /* Clear any currently outstanding port interrupt conditions */
2084 serr_ofs = mv_scr_offset(SCR_ERROR);
2085 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2086 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2087
20f733e7 2088 /* unmask all EDMA error interrupts */
31961943 2089 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2090
8b260248 2091 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2092 readl(port_mmio + EDMA_CFG_OFS),
2093 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2094 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2095}
2096
47c2b677 2097static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
522479fb 2098 unsigned int board_idx)
bca1c4eb
JG		 2099{
2100 u8 rev_id;
2101 u32 hp_flags = hpriv->hp_flags;
2102
2103 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2104
2105 switch(board_idx) {
47c2b677
JG		 2106 case chip_5080:
2107 hpriv->ops = &mv5xxx_ops;
2108 hp_flags |= MV_HP_50XX;
2109
2110 switch (rev_id) {
2111 case 0x1:
2112 hp_flags |= MV_HP_ERRATA_50XXB0;
2113 break;
2114 case 0x3:
2115 hp_flags |= MV_HP_ERRATA_50XXB2;
2116 break;
2117 default:
2118 dev_printk(KERN_WARNING, &pdev->dev,
2119 "Applying 50XXB2 workarounds to unknown rev\n");
2120 hp_flags |= MV_HP_ERRATA_50XXB2;
2121 break;
2122 }
2123 break;
2124
bca1c4eb
JG		 2125 case chip_504x:
2126 case chip_508x:
47c2b677 2127 hpriv->ops = &mv5xxx_ops;
bca1c4eb
JG		 2128 hp_flags |= MV_HP_50XX;
2129
47c2b677
JG		 2130 switch (rev_id) {
2131 case 0x0:
2132 hp_flags |= MV_HP_ERRATA_50XXB0;
2133 break;
2134 case 0x3:
2135 hp_flags |= MV_HP_ERRATA_50XXB2;
2136 break;
2137 default:
2138 dev_printk(KERN_WARNING, &pdev->dev,
2139 "Applying B2 workarounds to unknown rev\n");
2140 hp_flags |= MV_HP_ERRATA_50XXB2;
2141 break;
bca1c4eb
JG		 2142 }
2143 break;
2144
2145 case chip_604x:
2146 case chip_608x:
47c2b677
JG		 2147 hpriv->ops = &mv6xxx_ops;
2148
bca1c4eb 2149 switch (rev_id) {
47c2b677
JG		 2150 case 0x7:
2151 hp_flags |= MV_HP_ERRATA_60X1B2;
2152 break;
2153 case 0x9:
2154 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2155 break;
2156 default:
2157 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2158 "Applying B2 workarounds to unknown rev\n");
2159 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2160 break;
2161 }
2162 break;
2163
e4e7b892
JG		 2164 case chip_7042:
2165 case chip_6042:
2166 hpriv->ops = &mv6xxx_ops;
2167
2168 hp_flags |= MV_HP_GEN_IIE;
2169
2170 switch (rev_id) {
2171 case 0x0:
2172 hp_flags |= MV_HP_ERRATA_XX42A0;
2173 break;
2174 case 0x1:
2175 hp_flags |= MV_HP_ERRATA_60X1C0;
2176 break;
2177 default:
2178 dev_printk(KERN_WARNING, &pdev->dev,
2179 "Applying 60X1C0 workarounds to unknown rev\n");
2180 hp_flags |= MV_HP_ERRATA_60X1C0;
2181 break;
2182 }
2183 break;
2184
bca1c4eb
JG		 2185 default:
2186 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2187 return 1;
2188 }
2189
2190 hpriv->hp_flags = hp_flags;
2191
2192 return 0;
2193}
2194
05b308e1 2195/**
47c2b677 2196 * mv_init_host - Perform some early initialization of the host.
bca1c4eb 2197 * @pdev: host PCI device
05b308e1
BR		 2198 * @probe_ent: early data struct representing the host
2199 *
2200 * If possible, do an early global reset of the host. Then do
2201 * our port init and clear/unmask all/relevant host interrupts.
2202 *
2203 * LOCKING:
2204 * Inherited from caller.
2205 */
47c2b677 2206static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
bca1c4eb 2207 unsigned int board_idx)
20f733e7
BR		 2208{
2209 int rc = 0, n_hc, port, hc;
0d5ff566 2210 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
bca1c4eb
JG		 2211 struct mv_host_priv *hpriv = probe_ent->private_data;
2212
47c2b677
JG		 2213 /* global interrupt mask */
2214 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2215
2216 rc = mv_chip_id(pdev, hpriv, board_idx);
bca1c4eb
JG		 2217 if (rc)
2218 goto done;
2219
cca3974e 2220 n_hc = mv_get_hc_count(probe_ent->port_flags);
bca1c4eb
JG		 2221 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2222
47c2b677
JG		 2223 for (port = 0; port < probe_ent->n_ports; port++)
2224 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2225
c9d39130 2226 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2227 if (rc)
20f733e7 2228 goto done;
20f733e7 2229
522479fb
JG		 2230 hpriv->ops->reset_flash(hpriv, mmio);
2231 hpriv->ops->reset_bus(pdev, mmio);
47c2b677 2232 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7
BR		 2233
2234 for (port = 0; port < probe_ent->n_ports; port++) {
2a47ce06 2235 if (IS_60XX(hpriv)) {
c9d39130
JG		 2236 void __iomem *port_mmio = mv_port_base(mmio, port);
2237
2a47ce06 2238 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
eb46d684
ML		 2239 ifctl |= (1 << 7); /* enable gen2i speed */
2240 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2a47ce06
JG		 2241 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2242 }
2243
c9d39130 2244 hpriv->ops->phy_errata(hpriv, mmio, port);
2a47ce06
JG		 2245 }
2246
2247 for (port = 0; port < probe_ent->n_ports; port++) {
2248 void __iomem *port_mmio = mv_port_base(mmio, port);
31961943 2249 mv_port_init(&probe_ent->port[port], port_mmio);
20f733e7
BR		 2250 }
2251
2252 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2253 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2254
2255 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2256 "(before clear)=0x%08x\n", hc,
2257 readl(hc_mmio + HC_CFG_OFS),
2258 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2259
2260 /* Clear any currently outstanding hc interrupt conditions */
2261 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2262 }
2263
31961943
BR		 2264 /* Clear any currently outstanding host interrupt conditions */
2265 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2266
2267 /* and unmask interrupt generation for host regs */
2268 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
fb621e2f
JG		 2269
2270 if (IS_50XX(hpriv))
2271 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
2272 else
2273 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
20f733e7
BR		 2274
2275 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
8b260248 2276 "PCI int cause/mask=0x%08x/0x%08x\n",
20f733e7
BR		 2277 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2278 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2279 readl(mmio + PCI_IRQ_CAUSE_OFS),
2280 readl(mmio + PCI_IRQ_MASK_OFS));
bca1c4eb 2281
31961943 2282done:
20f733e7
BR		 2283 return rc;
2284}
2285
05b308e1
BR		 2286/**
2287 * mv_print_info - Dump key info to kernel log for perusal.
2288 * @probe_ent: early data struct representing the host
2289 *
2290 * FIXME: complete this.
2291 *
2292 * LOCKING:
2293 * Inherited from caller.
2294 */
31961943
BR		 2295static void mv_print_info(struct ata_probe_ent *probe_ent)
2296{
2297 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2298 struct mv_host_priv *hpriv = probe_ent->private_data;
2299 u8 rev_id, scc;
2300 const char *scc_s;
2301
2302 /* Use this to determine the HW stepping of the chip so we know
2303 * what errata to workaround
2304 */
2305 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2306
2307 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2308 if (scc == 0)
2309 scc_s = "SCSI";
2310 else if (scc == 0x01)
2311 scc_s = "RAID";
2312 else
2313 scc_s = "unknown";
2314
a9524a76
JG		 2315 dev_printk(KERN_INFO, &pdev->dev,
2316 "%u slots %u ports %s mode IRQ via %s\n",
8b260248 2317 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
31961943
BR		 2318 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2319}
2320
05b308e1
BR		 2321/**
2322 * mv_init_one - handle a positive probe of a Marvell host
2323 * @pdev: PCI device found
2324 * @ent: PCI device ID entry for the matched host
2325 *
2326 * LOCKING:
2327 * Inherited from caller.
2328 */
20f733e7
BR		 2329static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2330{
2331 static int printed_version = 0;
24dc5f33
TH		 2332 struct device *dev = &pdev->dev;
2333 struct ata_probe_ent *probe_ent;
20f733e7
BR		 2334 struct mv_host_priv *hpriv;
2335 unsigned int board_idx = (unsigned int)ent->driver_data;
24dc5f33 2336 int rc;
20f733e7 2337
a9524a76
JG		 2338 if (!printed_version++)
2339 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 2340
24dc5f33
TH		 2341 rc = pcim_enable_device(pdev);
2342 if (rc)
20f733e7 2343 return rc;
eb46d684 2344 pci_set_master(pdev);
20f733e7 2345
0d5ff566
TH		 2346 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2347 if (rc == -EBUSY)
24dc5f33 2348 pcim_pin_device(pdev);
0d5ff566 2349 if (rc)
24dc5f33 2350 return rc;
20f733e7 2351
d88184fb
JG		 2352 rc = pci_go_64(pdev);
2353 if (rc)
2354 return rc;
2355
24dc5f33
TH		 2356 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2357 if (probe_ent == NULL)
2358 return -ENOMEM;
20f733e7 2359
20f733e7
BR		 2360 probe_ent->dev = pci_dev_to_dev(pdev);
2361 INIT_LIST_HEAD(&probe_ent->node);
2362
24dc5f33
TH		 2363 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2364 if (!hpriv)
2365 return -ENOMEM;
20f733e7
BR		 2366
2367 probe_ent->sht = mv_port_info[board_idx].sht;
cca3974e 2368 probe_ent->port_flags = mv_port_info[board_idx].flags;
20f733e7
BR		 2369 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2370 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2371 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2372
2373 probe_ent->irq = pdev->irq;
1d6f359a 2374 probe_ent->irq_flags = IRQF_SHARED;
0d5ff566 2375 probe_ent->iomap = pcim_iomap_table(pdev);
20f733e7
BR		 2376 probe_ent->private_data = hpriv;
2377
2378 /* initialize adapter */
47c2b677 2379 rc = mv_init_host(pdev, probe_ent, board_idx);
24dc5f33
TH		 2380 if (rc)
2381 return rc;
20f733e7 2382
31961943 2383 /* Enable interrupts */
6a59dcf8 2384 if (msi && pci_enable_msi(pdev))
31961943 2385 pci_intx(pdev, 1);
20f733e7 2386
31961943
BR		 2387 mv_dump_pci_cfg(pdev, 0x68);
2388 mv_print_info(probe_ent);
2389
24dc5f33
TH		 2390 if (ata_device_add(probe_ent) == 0)
2391 return -ENODEV;
20f733e7 2392
24dc5f33 2393 devm_kfree(dev, probe_ent);
20f733e7 2394 return 0;
20f733e7
BR		 2395}
2396
2397static int __init mv_init(void)
2398{
b7887196 2399 return pci_register_driver(&mv_pci_driver);
20f733e7
BR		 2400}
2401
2402static void __exit mv_exit(void)
2403{
2404 pci_unregister_driver(&mv_pci_driver);
2405}
2406
2407MODULE_AUTHOR("Brett Russ");
2408MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2409MODULE_LICENSE("GPL");
2410MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2411MODULE_VERSION(DRV_VERSION);
2412
ddef9bb3
JG		 2413module_param(msi, int, 0444);
2414MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2415
20f733e7
BR		 2416module_init(mv_init);
2417module_exit(mv_exit);
Linux kernel - Deliverables
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