Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
95006188 | 42 | #include <scsi/scsi.h> |
1da177e4 | 43 | #include <scsi/scsi_host.h> |
193515d5 | 44 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
45 | #include <linux/libata.h> |
46 | #include <asm/io.h> | |
47 | #include "sata_promise.h" | |
48 | ||
49 | #define DRV_NAME "sata_promise" | |
46b027cc | 50 | #define DRV_VERSION "1.05" |
1da177e4 LT |
51 | |
52 | ||
53 | enum { | |
95006188 MP |
54 | /* register offsets */ |
55 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | |
56 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
57 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
58 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
59 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
60 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
61 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
1da177e4 LT |
62 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
63 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 64 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
65 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
66 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
67 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 68 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
69 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
70 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 LT |
71 | |
72 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
73 | (1<<8) | (1<<9) | (1<<10), | |
74 | ||
75 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
76 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 77 | board_20619 = 2, /* FastTrak TX4000 */ |
d324d462 MP |
78 | board_2057x = 3, /* SATAII150 Tx2plus */ |
79 | board_40518 = 4, /* SATAII150 Tx4 */ | |
1da177e4 | 80 | |
6340f019 | 81 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 82 | |
95006188 MP |
83 | /* Sequence counter control registers bit definitions */ |
84 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
85 | ||
86 | /* Feature register values */ | |
87 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
88 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
89 | ||
90 | /* Device/Head register values */ | |
91 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
92 | ||
25b93d81 MP |
93 | /* PDC_CTLSTAT bit definitions */ |
94 | PDC_DMA_ENABLE = (1 << 7), | |
95 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 96 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 97 | |
25b93d81 | 98 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 99 | ATA_FLAG_MMIO | |
3d0a59c0 | 100 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 MP |
101 | |
102 | /* hp->flags bits */ | |
103 | PDC_FLAG_GEN_II = (1 << 0), | |
1da177e4 LT |
104 | }; |
105 | ||
106 | ||
107 | struct pdc_port_priv { | |
108 | u8 *pkt; | |
109 | dma_addr_t pkt_dma; | |
110 | }; | |
111 | ||
6340f019 | 112 | struct pdc_host_priv { |
b2d1eee1 | 113 | unsigned long flags; |
870ae337 | 114 | unsigned long port_flags[ATA_MAX_PORTS]; |
6340f019 LK |
115 | }; |
116 | ||
1da177e4 LT |
117 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
118 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
119 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
7d12e780 | 120 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance); |
1da177e4 LT |
121 | static void pdc_eng_timeout(struct ata_port *ap); |
122 | static int pdc_port_start(struct ata_port *ap); | |
123 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a | 124 | static void pdc_pata_phy_reset(struct ata_port *ap); |
1da177e4 | 125 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
126 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
127 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 MP |
128 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
129 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc); | |
1da177e4 | 130 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 131 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
cca3974e | 132 | static void pdc_host_stop(struct ata_host *host); |
25b93d81 MP |
133 | static void pdc_freeze(struct ata_port *ap); |
134 | static void pdc_thaw(struct ata_port *ap); | |
135 | static void pdc_error_handler(struct ata_port *ap); | |
136 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); | |
1da177e4 | 137 | |
374b1873 | 138 | |
193515d5 | 139 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
140 | .module = THIS_MODULE, |
141 | .name = DRV_NAME, | |
142 | .ioctl = ata_scsi_ioctl, | |
143 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
144 | .can_queue = ATA_DEF_QUEUE, |
145 | .this_id = ATA_SHT_THIS_ID, | |
146 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
147 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
148 | .emulated = ATA_SHT_EMULATED, | |
149 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
150 | .proc_name = DRV_NAME, | |
151 | .dma_boundary = ATA_DMA_BOUNDARY, | |
152 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 153 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 154 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
155 | }; |
156 | ||
057ace5e | 157 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
158 | .port_disable = ata_port_disable, |
159 | .tf_load = pdc_tf_load_mmio, | |
160 | .tf_read = ata_tf_read, | |
161 | .check_status = ata_check_status, | |
162 | .exec_command = pdc_exec_command_mmio, | |
163 | .dev_select = ata_std_dev_select, | |
95006188 MP |
164 | .check_atapi_dma = pdc_check_atapi_dma, |
165 | ||
166 | .qc_prep = pdc_qc_prep, | |
167 | .qc_issue = pdc_qc_issue_prot, | |
168 | .freeze = pdc_freeze, | |
169 | .thaw = pdc_thaw, | |
170 | .error_handler = pdc_error_handler, | |
171 | .post_internal_cmd = pdc_post_internal_cmd, | |
172 | .data_xfer = ata_mmio_data_xfer, | |
173 | .irq_handler = pdc_interrupt, | |
174 | .irq_clear = pdc_irq_clear, | |
175 | ||
176 | .scr_read = pdc_sata_scr_read, | |
177 | .scr_write = pdc_sata_scr_write, | |
178 | .port_start = pdc_port_start, | |
179 | .port_stop = pdc_port_stop, | |
180 | .host_stop = pdc_host_stop, | |
181 | }; | |
182 | ||
183 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ | |
184 | static const struct ata_port_operations pdc_old_sata_ops = { | |
185 | .port_disable = ata_port_disable, | |
186 | .tf_load = pdc_tf_load_mmio, | |
187 | .tf_read = ata_tf_read, | |
188 | .check_status = ata_check_status, | |
189 | .exec_command = pdc_exec_command_mmio, | |
190 | .dev_select = ata_std_dev_select, | |
191 | .check_atapi_dma = pdc_old_check_atapi_dma, | |
2cba582a | 192 | |
1da177e4 LT |
193 | .qc_prep = pdc_qc_prep, |
194 | .qc_issue = pdc_qc_issue_prot, | |
25b93d81 MP |
195 | .freeze = pdc_freeze, |
196 | .thaw = pdc_thaw, | |
197 | .error_handler = pdc_error_handler, | |
198 | .post_internal_cmd = pdc_post_internal_cmd, | |
a6b2c5d4 | 199 | .data_xfer = ata_mmio_data_xfer, |
1da177e4 LT |
200 | .irq_handler = pdc_interrupt, |
201 | .irq_clear = pdc_irq_clear, | |
2cba582a | 202 | |
1da177e4 LT |
203 | .scr_read = pdc_sata_scr_read, |
204 | .scr_write = pdc_sata_scr_write, | |
205 | .port_start = pdc_port_start, | |
206 | .port_stop = pdc_port_stop, | |
6340f019 | 207 | .host_stop = pdc_host_stop, |
1da177e4 LT |
208 | }; |
209 | ||
057ace5e | 210 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
211 | .port_disable = ata_port_disable, |
212 | .tf_load = pdc_tf_load_mmio, | |
213 | .tf_read = ata_tf_read, | |
214 | .check_status = ata_check_status, | |
215 | .exec_command = pdc_exec_command_mmio, | |
216 | .dev_select = ata_std_dev_select, | |
95006188 | 217 | .check_atapi_dma = pdc_check_atapi_dma, |
2cba582a JG |
218 | |
219 | .phy_reset = pdc_pata_phy_reset, | |
220 | ||
221 | .qc_prep = pdc_qc_prep, | |
222 | .qc_issue = pdc_qc_issue_prot, | |
a6b2c5d4 | 223 | .data_xfer = ata_mmio_data_xfer, |
2cba582a JG |
224 | .eng_timeout = pdc_eng_timeout, |
225 | .irq_handler = pdc_interrupt, | |
226 | .irq_clear = pdc_irq_clear, | |
227 | ||
228 | .port_start = pdc_port_start, | |
229 | .port_stop = pdc_port_stop, | |
6340f019 | 230 | .host_stop = pdc_host_stop, |
2cba582a JG |
231 | }; |
232 | ||
98ac62de | 233 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
234 | /* board_2037x */ |
235 | { | |
236 | .sht = &pdc_ata_sht, | |
870ae337 | 237 | .flags = PDC_COMMON_FLAGS, |
1da177e4 LT |
238 | .pio_mask = 0x1f, /* pio0-4 */ |
239 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
240 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 241 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
242 | }, |
243 | ||
244 | /* board_20319 */ | |
245 | { | |
246 | .sht = &pdc_ata_sht, | |
cca3974e | 247 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
248 | .pio_mask = 0x1f, /* pio0-4 */ |
249 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
250 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 251 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 252 | }, |
f497ba73 TL |
253 | |
254 | /* board_20619 */ | |
255 | { | |
256 | .sht = &pdc_ata_sht, | |
25b93d81 | 257 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
258 | .pio_mask = 0x1f, /* pio0-4 */ |
259 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
260 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 261 | .port_ops = &pdc_pata_ops, |
f497ba73 | 262 | }, |
5a46fe89 | 263 | |
6340f019 LK |
264 | /* board_2057x */ |
265 | { | |
266 | .sht = &pdc_ata_sht, | |
870ae337 | 267 | .flags = PDC_COMMON_FLAGS, |
6340f019 LK |
268 | .pio_mask = 0x1f, /* pio0-4 */ |
269 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
270 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
271 | .port_ops = &pdc_sata_ops, | |
272 | }, | |
273 | ||
274 | /* board_40518 */ | |
275 | { | |
276 | .sht = &pdc_ata_sht, | |
cca3974e | 277 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
278 | .pio_mask = 0x1f, /* pio0-4 */ |
279 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
280 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
281 | .port_ops = &pdc_sata_ops, | |
282 | }, | |
1da177e4 LT |
283 | }; |
284 | ||
3b7d697d | 285 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 286 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
287 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
288 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
289 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
290 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
291 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 292 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 293 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 294 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 295 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
296 | |
297 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
298 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
299 | { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, | |
300 | { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, | |
b2d1eee1 | 301 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
302 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
303 | ||
304 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 305 | |
1da177e4 LT |
306 | { } /* terminate list */ |
307 | }; | |
308 | ||
309 | ||
310 | static struct pci_driver pdc_ata_pci_driver = { | |
311 | .name = DRV_NAME, | |
312 | .id_table = pdc_ata_pci_tbl, | |
313 | .probe = pdc_ata_init_one, | |
314 | .remove = ata_pci_remove_one, | |
315 | }; | |
316 | ||
317 | ||
318 | static int pdc_port_start(struct ata_port *ap) | |
319 | { | |
cca3974e | 320 | struct device *dev = ap->host->dev; |
599b7202 | 321 | struct pdc_host_priv *hp = ap->host->private_data; |
1da177e4 LT |
322 | struct pdc_port_priv *pp; |
323 | int rc; | |
324 | ||
870ae337 MP |
325 | /* fix up port flags and cable type for SATA+PATA chips */ |
326 | ap->flags |= hp->port_flags[ap->port_no]; | |
327 | if (ap->flags & ATA_FLAG_SATA) | |
328 | ap->cbl = ATA_CBL_SATA; | |
329 | ||
1da177e4 LT |
330 | rc = ata_port_start(ap); |
331 | if (rc) | |
332 | return rc; | |
333 | ||
6340f019 | 334 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
1da177e4 LT |
335 | if (!pp) { |
336 | rc = -ENOMEM; | |
337 | goto err_out; | |
338 | } | |
1da177e4 LT |
339 | |
340 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
341 | if (!pp->pkt) { | |
342 | rc = -ENOMEM; | |
343 | goto err_out_kfree; | |
344 | } | |
345 | ||
346 | ap->private_data = pp; | |
347 | ||
599b7202 MP |
348 | /* fix up PHYMODE4 align timing */ |
349 | if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) { | |
350 | void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr; | |
351 | unsigned int tmp; | |
352 | ||
353 | tmp = readl(mmio + 0x014); | |
354 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | |
355 | writel(tmp, mmio + 0x014); | |
356 | } | |
357 | ||
1da177e4 LT |
358 | return 0; |
359 | ||
360 | err_out_kfree: | |
361 | kfree(pp); | |
362 | err_out: | |
363 | ata_port_stop(ap); | |
364 | return rc; | |
365 | } | |
366 | ||
367 | ||
368 | static void pdc_port_stop(struct ata_port *ap) | |
369 | { | |
cca3974e | 370 | struct device *dev = ap->host->dev; |
1da177e4 LT |
371 | struct pdc_port_priv *pp = ap->private_data; |
372 | ||
373 | ap->private_data = NULL; | |
374 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
375 | kfree(pp); | |
376 | ata_port_stop(ap); | |
377 | } | |
378 | ||
379 | ||
cca3974e | 380 | static void pdc_host_stop(struct ata_host *host) |
6340f019 | 381 | { |
cca3974e | 382 | struct pdc_host_priv *hp = host->private_data; |
6340f019 | 383 | |
cca3974e | 384 | ata_pci_host_stop(host); |
6340f019 LK |
385 | |
386 | kfree(hp); | |
387 | } | |
388 | ||
389 | ||
1da177e4 LT |
390 | static void pdc_reset_port(struct ata_port *ap) |
391 | { | |
ea6ba10b | 392 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
393 | unsigned int i; |
394 | u32 tmp; | |
395 | ||
396 | for (i = 11; i > 0; i--) { | |
397 | tmp = readl(mmio); | |
398 | if (tmp & PDC_RESET) | |
399 | break; | |
400 | ||
401 | udelay(100); | |
402 | ||
403 | tmp |= PDC_RESET; | |
404 | writel(tmp, mmio); | |
405 | } | |
406 | ||
407 | tmp &= ~PDC_RESET; | |
408 | writel(tmp, mmio); | |
409 | readl(mmio); /* flush */ | |
410 | } | |
411 | ||
d3fb4e8d | 412 | static void pdc_pata_cbl_detect(struct ata_port *ap) |
2cba582a | 413 | { |
d3fb4e8d | 414 | u8 tmp; |
03dc5506 | 415 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d JG |
416 | |
417 | tmp = readb(mmio); | |
418 | ||
419 | if (tmp & 0x01) { | |
420 | ap->cbl = ATA_CBL_PATA40; | |
421 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
422 | } else | |
423 | ap->cbl = ATA_CBL_PATA80; | |
424 | } | |
2cba582a | 425 | |
d3fb4e8d JG |
426 | static void pdc_pata_phy_reset(struct ata_port *ap) |
427 | { | |
428 | pdc_pata_cbl_detect(ap); | |
2cba582a JG |
429 | pdc_reset_port(ap); |
430 | ata_port_probe(ap); | |
431 | ata_bus_reset(ap); | |
432 | } | |
433 | ||
1da177e4 LT |
434 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
435 | { | |
870ae337 | 436 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 437 | return 0xffffffffU; |
b181d3b0 | 438 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
439 | } |
440 | ||
441 | ||
442 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
443 | u32 val) | |
444 | { | |
870ae337 | 445 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 446 | return; |
b181d3b0 | 447 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
448 | } |
449 | ||
95006188 MP |
450 | static void pdc_atapi_dma_pkt(struct ata_taskfile *tf, |
451 | dma_addr_t sg_table, | |
452 | unsigned int cdb_len, u8 *cdb, | |
453 | u8 *buf) | |
454 | { | |
455 | u32 *buf32 = (u32 *) buf; | |
456 | ||
457 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
458 | * and seq id (byte 2) | |
459 | */ | |
460 | if (!(tf->flags & ATA_TFLAG_WRITE)) | |
461 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
462 | else | |
463 | buf32[0] = 0; | |
464 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ | |
465 | buf32[2] = 0; /* no next-packet */ | |
466 | ||
467 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ | |
468 | BUG_ON(cdb_len & ~0x1E); | |
469 | ||
470 | buf[12] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
471 | memcpy(buf+13, cdb, cdb_len); | |
472 | } | |
473 | ||
1da177e4 LT |
474 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
475 | { | |
476 | struct pdc_port_priv *pp = qc->ap->private_data; | |
477 | unsigned int i; | |
478 | ||
479 | VPRINTK("ENTER\n"); | |
480 | ||
481 | switch (qc->tf.protocol) { | |
482 | case ATA_PROT_DMA: | |
483 | ata_qc_prep(qc); | |
484 | /* fall through */ | |
485 | ||
486 | case ATA_PROT_NODATA: | |
487 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
488 | qc->dev->devno, pp->pkt); | |
489 | ||
490 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
491 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
492 | else | |
493 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
494 | ||
495 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
496 | break; | |
497 | ||
95006188 MP |
498 | case ATA_PROT_ATAPI: |
499 | case ATA_PROT_ATAPI_NODATA: | |
500 | ata_qc_prep(qc); | |
501 | break; | |
502 | ||
503 | case ATA_PROT_ATAPI_DMA: | |
504 | ata_qc_prep(qc); | |
505 | pdc_atapi_dma_pkt(&qc->tf, qc->ap->prd_dma, qc->dev->cdb_len, qc->cdb, pp->pkt); | |
506 | break; | |
507 | ||
1da177e4 LT |
508 | default: |
509 | break; | |
510 | } | |
511 | } | |
512 | ||
25b93d81 MP |
513 | static void pdc_freeze(struct ata_port *ap) |
514 | { | |
515 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
516 | u32 tmp; | |
517 | ||
518 | tmp = readl(mmio + PDC_CTLSTAT); | |
519 | tmp |= PDC_IRQ_DISABLE; | |
520 | tmp &= ~PDC_DMA_ENABLE; | |
521 | writel(tmp, mmio + PDC_CTLSTAT); | |
522 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
523 | } | |
524 | ||
525 | static void pdc_thaw(struct ata_port *ap) | |
526 | { | |
527 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
528 | u32 tmp; | |
529 | ||
530 | /* clear IRQ */ | |
531 | readl(mmio + PDC_INT_SEQMASK); | |
532 | ||
533 | /* turn IRQ back on */ | |
534 | tmp = readl(mmio + PDC_CTLSTAT); | |
535 | tmp &= ~PDC_IRQ_DISABLE; | |
536 | writel(tmp, mmio + PDC_CTLSTAT); | |
537 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
538 | } | |
539 | ||
540 | static void pdc_error_handler(struct ata_port *ap) | |
541 | { | |
542 | ata_reset_fn_t hardreset; | |
543 | ||
544 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) | |
545 | pdc_reset_port(ap); | |
546 | ||
547 | hardreset = NULL; | |
548 | if (sata_scr_valid(ap)) | |
549 | hardreset = sata_std_hardreset; | |
550 | ||
551 | /* perform recovery */ | |
552 | ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, | |
553 | ata_std_postreset); | |
554 | } | |
555 | ||
556 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) | |
557 | { | |
558 | struct ata_port *ap = qc->ap; | |
559 | ||
560 | if (qc->flags & ATA_QCFLAG_FAILED) | |
561 | qc->err_mask |= AC_ERR_OTHER; | |
562 | ||
563 | /* make DMA engine forget about the failed command */ | |
564 | if (qc->err_mask) | |
565 | pdc_reset_port(ap); | |
566 | } | |
567 | ||
1da177e4 LT |
568 | static void pdc_eng_timeout(struct ata_port *ap) |
569 | { | |
cca3974e | 570 | struct ata_host *host = ap->host; |
1da177e4 LT |
571 | u8 drv_stat; |
572 | struct ata_queued_cmd *qc; | |
b8f6153e | 573 | unsigned long flags; |
1da177e4 LT |
574 | |
575 | DPRINTK("ENTER\n"); | |
576 | ||
cca3974e | 577 | spin_lock_irqsave(&host->lock, flags); |
b8f6153e | 578 | |
1da177e4 | 579 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1da177e4 | 580 | |
1da177e4 LT |
581 | switch (qc->tf.protocol) { |
582 | case ATA_PROT_DMA: | |
583 | case ATA_PROT_NODATA: | |
f15a1daf | 584 | ata_port_printk(ap, KERN_ERR, "command timeout\n"); |
a7dac447 | 585 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 | 586 | qc->err_mask |= __ac_err_mask(drv_stat); |
1da177e4 LT |
587 | break; |
588 | ||
589 | default: | |
590 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
591 | ||
f15a1daf TH |
592 | ata_port_printk(ap, KERN_ERR, |
593 | "unknown timeout, cmd 0x%x stat 0x%x\n", | |
594 | qc->tf.command, drv_stat); | |
1da177e4 | 595 | |
a22e2eb0 | 596 | qc->err_mask |= ac_err_mask(drv_stat); |
1da177e4 LT |
597 | break; |
598 | } | |
599 | ||
cca3974e | 600 | spin_unlock_irqrestore(&host->lock, flags); |
f6379020 | 601 | ata_eh_qc_complete(qc); |
1da177e4 LT |
602 | DPRINTK("EXIT\n"); |
603 | } | |
604 | ||
605 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
606 | struct ata_queued_cmd *qc) | |
607 | { | |
a22e2eb0 | 608 | unsigned int handled = 0; |
1da177e4 | 609 | u32 tmp; |
ea6ba10b | 610 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
611 | |
612 | tmp = readl(mmio); | |
613 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 614 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
615 | pdc_reset_port(ap); |
616 | } | |
617 | ||
618 | switch (qc->tf.protocol) { | |
619 | case ATA_PROT_DMA: | |
620 | case ATA_PROT_NODATA: | |
95006188 | 621 | case ATA_PROT_ATAPI_DMA: |
a22e2eb0 AL |
622 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
623 | ata_qc_complete(qc); | |
1da177e4 LT |
624 | handled = 1; |
625 | break; | |
626 | ||
627 | default: | |
ee500aab AL |
628 | ap->stats.idle_irq++; |
629 | break; | |
1da177e4 LT |
630 | } |
631 | ||
ee500aab | 632 | return handled; |
1da177e4 LT |
633 | } |
634 | ||
635 | static void pdc_irq_clear(struct ata_port *ap) | |
636 | { | |
cca3974e JG |
637 | struct ata_host *host = ap->host; |
638 | void __iomem *mmio = host->mmio_base; | |
1da177e4 LT |
639 | |
640 | readl(mmio + PDC_INT_SEQMASK); | |
641 | } | |
642 | ||
7d12e780 | 643 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance) |
1da177e4 | 644 | { |
cca3974e | 645 | struct ata_host *host = dev_instance; |
1da177e4 LT |
646 | struct ata_port *ap; |
647 | u32 mask = 0; | |
648 | unsigned int i, tmp; | |
649 | unsigned int handled = 0; | |
ea6ba10b | 650 | void __iomem *mmio_base; |
1da177e4 LT |
651 | |
652 | VPRINTK("ENTER\n"); | |
653 | ||
cca3974e | 654 | if (!host || !host->mmio_base) { |
1da177e4 LT |
655 | VPRINTK("QUICK EXIT\n"); |
656 | return IRQ_NONE; | |
657 | } | |
658 | ||
cca3974e | 659 | mmio_base = host->mmio_base; |
1da177e4 LT |
660 | |
661 | /* reading should also clear interrupts */ | |
662 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
663 | ||
664 | if (mask == 0xffffffff) { | |
665 | VPRINTK("QUICK EXIT 2\n"); | |
666 | return IRQ_NONE; | |
667 | } | |
6340f019 | 668 | |
cca3974e | 669 | spin_lock(&host->lock); |
6340f019 | 670 | |
1da177e4 LT |
671 | mask &= 0xffff; /* only 16 tags possible */ |
672 | if (!mask) { | |
673 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 674 | goto done_irq; |
1da177e4 LT |
675 | } |
676 | ||
1da177e4 LT |
677 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
678 | ||
cca3974e | 679 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 680 | VPRINTK("port %u\n", i); |
cca3974e | 681 | ap = host->ports[i]; |
1da177e4 | 682 | tmp = mask & (1 << (i + 1)); |
c1389503 | 683 | if (tmp && ap && |
029f5468 | 684 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
685 | struct ata_queued_cmd *qc; |
686 | ||
687 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 688 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
689 | handled += pdc_host_intr(ap, qc); |
690 | } | |
691 | } | |
692 | ||
1da177e4 LT |
693 | VPRINTK("EXIT\n"); |
694 | ||
6340f019 | 695 | done_irq: |
cca3974e | 696 | spin_unlock(&host->lock); |
1da177e4 LT |
697 | return IRQ_RETVAL(handled); |
698 | } | |
699 | ||
700 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
701 | { | |
702 | struct ata_port *ap = qc->ap; | |
703 | struct pdc_port_priv *pp = ap->private_data; | |
704 | unsigned int port_no = ap->port_no; | |
705 | u8 seq = (u8) (port_no + 1); | |
706 | ||
707 | VPRINTK("ENTER, ap %p\n", ap); | |
708 | ||
cca3974e JG |
709 | writel(0x00000001, ap->host->mmio_base + (seq * 4)); |
710 | readl(ap->host->mmio_base + (seq * 4)); /* flush */ | |
1da177e4 LT |
711 | |
712 | pp->pkt[2] = seq; | |
713 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
714 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
715 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
716 | } |
717 | ||
95006188 MP |
718 | static unsigned int pdc_wait_for_drq(struct ata_port *ap) |
719 | { | |
720 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
721 | unsigned int i; | |
722 | unsigned int status; | |
723 | ||
724 | /* Following pdc-ultra's WaitForDrq() we loop here until BSY | |
725 | * is clear and DRQ is set in altstatus. We could possibly call | |
726 | * ata_busy_wait() and loop until DRQ is set, but since we don't | |
727 | * know how much time a call to ata_busy_wait() took, we don't | |
728 | * know when to time out the outer loop. | |
729 | */ | |
730 | for(i = 0; i < 1000; ++i) { | |
731 | status = readb(port_mmio + 0x38); /* altstatus */ | |
732 | if (status == 0xFF) | |
733 | break; | |
734 | if (status & ATA_BUSY) | |
735 | ; | |
736 | else if (status & (ATA_DRQ | ATA_ERR)) | |
737 | break; | |
738 | mdelay(1); | |
739 | } | |
740 | if (i >= 1000) | |
741 | ata_port_printk(ap, KERN_WARNING, "%s timed out", __FUNCTION__); | |
742 | return status; | |
743 | } | |
744 | ||
745 | static void pdc_issue_atapi_pkt_cmd(struct ata_queued_cmd *qc) | |
746 | { | |
747 | struct ata_port *ap = qc->ap; | |
748 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
749 | void __iomem *host_mmio = ap->host->mmio_base; | |
750 | unsigned int nbytes; | |
751 | unsigned int tmp; | |
752 | ||
753 | writeb(0x00, port_mmio + PDC_CTLSTAT); /* route drive INT to SEQ 0 */ | |
754 | writeb(PDC_SEQCNTRL_INT_MASK, host_mmio + 0); /* but mask SEQ 0 INT */ | |
755 | ||
756 | /* select drive */ | |
757 | if (sata_scr_valid(ap)) { | |
758 | tmp = PDC_DEVICE_SATA; | |
759 | } else { | |
760 | tmp = ATA_DEVICE_OBS; | |
761 | if (qc->dev->devno != 0) | |
762 | tmp |= ATA_DEV1; | |
763 | } | |
764 | writeb(tmp, port_mmio + PDC_DEVICE); | |
765 | ata_busy_wait(ap, ATA_BUSY, 1000); | |
766 | ||
767 | writeb(0x00, port_mmio + PDC_SECTOR_COUNT); | |
768 | writeb(0x00, port_mmio + PDC_SECTOR_NUMBER); | |
769 | ||
770 | /* set feature and byte counter registers */ | |
771 | if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { | |
772 | tmp = PDC_FEATURE_ATAPI_PIO; | |
773 | /* set byte counter register to real transfer byte count */ | |
774 | nbytes = qc->nbytes; | |
775 | if (!nbytes) | |
776 | nbytes = qc->nsect << 9; | |
777 | if (nbytes > 0xffff) | |
778 | nbytes = 0xffff; | |
779 | } else { | |
780 | tmp = PDC_FEATURE_ATAPI_DMA; | |
781 | /* set byte counter register to 0 */ | |
782 | nbytes = 0; | |
783 | } | |
784 | writeb(tmp, port_mmio + PDC_FEATURE); | |
785 | writeb(nbytes & 0xFF, port_mmio + PDC_CYLINDER_LOW); | |
786 | writeb((nbytes >> 8) & 0xFF, port_mmio + PDC_CYLINDER_HIGH); | |
787 | ||
788 | /* send ATAPI packet command 0xA0 */ | |
789 | writeb(ATA_CMD_PACKET, port_mmio + PDC_COMMAND); | |
790 | ||
791 | /* | |
792 | * At this point in the issuing of a packet command, the Promise | |
793 | * driver busy-waits for INT (CTLSTAT bit 27) if it detected | |
794 | * (at port init time) that the device interrupts with assertion | |
795 | * of DRQ after receiving a packet command. | |
796 | * | |
797 | * XXX: Do we need to handle this case as well? Does libata detect | |
798 | * this case for us, or do we have to do our own per-port init? | |
799 | */ | |
800 | ||
801 | pdc_wait_for_drq(ap); | |
802 | ||
803 | /* now the device only waits for the CDB */ | |
804 | } | |
805 | ||
9a3d9eb0 | 806 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
807 | { |
808 | switch (qc->tf.protocol) { | |
95006188 MP |
809 | case ATA_PROT_ATAPI_DMA: |
810 | pdc_issue_atapi_pkt_cmd(qc); | |
811 | /*FALLTHROUGH*/ | |
1da177e4 LT |
812 | case ATA_PROT_DMA: |
813 | case ATA_PROT_NODATA: | |
814 | pdc_packet_start(qc); | |
815 | return 0; | |
816 | ||
1da177e4 LT |
817 | default: |
818 | break; | |
819 | } | |
820 | ||
821 | return ata_qc_issue_prot(qc); | |
822 | } | |
823 | ||
057ace5e | 824 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
825 | { |
826 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
827 | tf->protocol == ATA_PROT_NODATA); | |
828 | ata_tf_load(ap, tf); | |
829 | } | |
830 | ||
831 | ||
057ace5e | 832 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
833 | { |
834 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
835 | tf->protocol == ATA_PROT_NODATA); | |
836 | ata_exec_command(ap, tf); | |
837 | } | |
838 | ||
95006188 MP |
839 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
840 | { | |
841 | u8 *scsicmd = qc->scsicmd->cmnd; | |
842 | int pio = 1; /* atapi dma off by default */ | |
843 | ||
844 | /* Whitelist commands that may use DMA. */ | |
845 | switch (scsicmd[0]) { | |
846 | case WRITE_12: | |
847 | case WRITE_10: | |
848 | case WRITE_6: | |
849 | case READ_12: | |
850 | case READ_10: | |
851 | case READ_6: | |
852 | case 0xad: /* READ_DVD_STRUCTURE */ | |
853 | case 0xbe: /* READ_CD */ | |
854 | pio = 0; | |
855 | } | |
856 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
857 | if (scsicmd[0] == WRITE_10) { | |
858 | unsigned int lba; | |
859 | lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; | |
860 | if (lba >= 0xFFFF4FA2) | |
861 | pio = 1; | |
862 | } | |
863 | return pio; | |
864 | } | |
865 | ||
866 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc) | |
867 | { | |
868 | struct ata_port *ap = qc->ap; | |
869 | ||
870 | /* First generation chips cannot use ATAPI DMA on SATA ports */ | |
871 | if (sata_scr_valid(ap)) | |
872 | return 1; | |
873 | return pdc_check_atapi_dma(qc); | |
874 | } | |
1da177e4 LT |
875 | |
876 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
877 | { | |
878 | port->cmd_addr = base; | |
879 | port->data_addr = base; | |
880 | port->feature_addr = | |
881 | port->error_addr = base + 0x4; | |
882 | port->nsect_addr = base + 0x8; | |
883 | port->lbal_addr = base + 0xc; | |
884 | port->lbam_addr = base + 0x10; | |
885 | port->lbah_addr = base + 0x14; | |
886 | port->device_addr = base + 0x18; | |
887 | port->command_addr = | |
888 | port->status_addr = base + 0x1c; | |
889 | port->altstatus_addr = | |
890 | port->ctl_addr = base + 0x38; | |
891 | } | |
892 | ||
893 | ||
894 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
895 | { | |
ea6ba10b | 896 | void __iomem *mmio = pe->mmio_base; |
6340f019 | 897 | struct pdc_host_priv *hp = pe->private_data; |
d324d462 | 898 | int hotplug_offset; |
1da177e4 LT |
899 | u32 tmp; |
900 | ||
d324d462 MP |
901 | if (hp->flags & PDC_FLAG_GEN_II) |
902 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
903 | else | |
904 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
905 | ||
1da177e4 LT |
906 | /* |
907 | * Except for the hotplug stuff, this is voodoo from the | |
908 | * Promise driver. Label this entire section | |
909 | * "TODO: figure out why we do this" | |
910 | */ | |
911 | ||
b2d1eee1 | 912 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 913 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 MP |
914 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
915 | if (!(hp->flags & PDC_FLAG_GEN_II)) | |
916 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ | |
1da177e4 LT |
917 | writel(tmp, mmio + PDC_FLASH_CTL); |
918 | ||
919 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
920 | tmp = readl(mmio + hotplug_offset); |
921 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
922 | |
923 | /* mask plug/unplug ints */ | |
6340f019 LK |
924 | tmp = readl(mmio + hotplug_offset); |
925 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 | 926 | |
b2d1eee1 MP |
927 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
928 | if (hp->flags & PDC_FLAG_GEN_II) | |
929 | return; | |
930 | ||
1da177e4 LT |
931 | /* reduce TBG clock to 133 Mhz. */ |
932 | tmp = readl(mmio + PDC_TBG_MODE); | |
933 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
934 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
935 | writel(tmp, mmio + PDC_TBG_MODE); | |
936 | ||
937 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
938 | msleep(10); | |
939 | ||
940 | /* adjust slew rate control register. */ | |
941 | tmp = readl(mmio + PDC_SLEW_CTL); | |
942 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
943 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
944 | writel(tmp, mmio + PDC_SLEW_CTL); | |
945 | } | |
946 | ||
947 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
948 | { | |
949 | static int printed_version; | |
950 | struct ata_probe_ent *probe_ent = NULL; | |
6340f019 | 951 | struct pdc_host_priv *hp; |
1da177e4 | 952 | unsigned long base; |
ea6ba10b | 953 | void __iomem *mmio_base; |
1da177e4 LT |
954 | unsigned int board_idx = (unsigned int) ent->driver_data; |
955 | int pci_dev_busy = 0; | |
956 | int rc; | |
870ae337 | 957 | u8 tmp; |
1da177e4 LT |
958 | |
959 | if (!printed_version++) | |
a9524a76 | 960 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 961 | |
1da177e4 LT |
962 | rc = pci_enable_device(pdev); |
963 | if (rc) | |
964 | return rc; | |
965 | ||
966 | rc = pci_request_regions(pdev, DRV_NAME); | |
967 | if (rc) { | |
968 | pci_dev_busy = 1; | |
969 | goto err_out; | |
970 | } | |
971 | ||
972 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
973 | if (rc) | |
974 | goto err_out_regions; | |
975 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
976 | if (rc) | |
977 | goto err_out_regions; | |
978 | ||
6340f019 | 979 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
980 | if (probe_ent == NULL) { |
981 | rc = -ENOMEM; | |
982 | goto err_out_regions; | |
983 | } | |
984 | ||
1da177e4 LT |
985 | probe_ent->dev = pci_dev_to_dev(pdev); |
986 | INIT_LIST_HEAD(&probe_ent->node); | |
987 | ||
374b1873 | 988 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
989 | if (mmio_base == NULL) { |
990 | rc = -ENOMEM; | |
991 | goto err_out_free_ent; | |
992 | } | |
993 | base = (unsigned long) mmio_base; | |
994 | ||
6340f019 LK |
995 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); |
996 | if (hp == NULL) { | |
997 | rc = -ENOMEM; | |
998 | goto err_out_free_ent; | |
999 | } | |
1000 | ||
6340f019 LK |
1001 | probe_ent->private_data = hp; |
1002 | ||
1da177e4 | 1003 | probe_ent->sht = pdc_port_info[board_idx].sht; |
cca3974e | 1004 | probe_ent->port_flags = pdc_port_info[board_idx].flags; |
1da177e4 LT |
1005 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; |
1006 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
1007 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
1008 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
1009 | ||
1010 | probe_ent->irq = pdev->irq; | |
1d6f359a | 1011 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
1012 | probe_ent->mmio_base = mmio_base; |
1013 | ||
1014 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
1015 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
1016 | ||
1017 | probe_ent->port[0].scr_addr = base + 0x400; | |
1018 | probe_ent->port[1].scr_addr = base + 0x500; | |
1019 | ||
1020 | /* notice 4-port boards */ | |
1021 | switch (board_idx) { | |
6340f019 | 1022 | case board_40518: |
b2d1eee1 | 1023 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 1024 | /* Fall through */ |
1da177e4 LT |
1025 | case board_20319: |
1026 | probe_ent->n_ports = 4; | |
1027 | ||
1028 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1029 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
1030 | ||
1031 | probe_ent->port[2].scr_addr = base + 0x600; | |
1032 | probe_ent->port[3].scr_addr = base + 0x700; | |
1033 | break; | |
6340f019 | 1034 | case board_2057x: |
b2d1eee1 | 1035 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 1036 | /* Fall through */ |
1da177e4 | 1037 | case board_2037x: |
870ae337 MP |
1038 | /* TX2plus boards also have a PATA port */ |
1039 | tmp = readb(mmio_base + PDC_FLASH_CTL+1); | |
1040 | if (!(tmp & 0x80)) { | |
1041 | probe_ent->n_ports = 3; | |
1042 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1043 | hp->port_flags[2] = ATA_FLAG_SLAVE_POSS; | |
1044 | printk(KERN_INFO DRV_NAME " PATA port found\n"); | |
1045 | } else | |
1046 | probe_ent->n_ports = 2; | |
1047 | hp->port_flags[0] = ATA_FLAG_SATA; | |
1048 | hp->port_flags[1] = ATA_FLAG_SATA; | |
1da177e4 | 1049 | break; |
f497ba73 TL |
1050 | case board_20619: |
1051 | probe_ent->n_ports = 4; | |
1052 | ||
1053 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
1054 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
1055 | ||
1056 | probe_ent->port[2].scr_addr = base + 0x600; | |
1057 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 1058 | break; |
1da177e4 LT |
1059 | default: |
1060 | BUG(); | |
1061 | break; | |
1062 | } | |
1063 | ||
1064 | pci_set_master(pdev); | |
1065 | ||
1066 | /* initialize adapter */ | |
1067 | pdc_host_init(board_idx, probe_ent); | |
1068 | ||
6340f019 LK |
1069 | /* FIXME: Need any other frees than hp? */ |
1070 | if (!ata_device_add(probe_ent)) | |
1071 | kfree(hp); | |
1072 | ||
1da177e4 LT |
1073 | kfree(probe_ent); |
1074 | ||
1075 | return 0; | |
1076 | ||
1077 | err_out_free_ent: | |
1078 | kfree(probe_ent); | |
1079 | err_out_regions: | |
1080 | pci_release_regions(pdev); | |
1081 | err_out: | |
1082 | if (!pci_dev_busy) | |
1083 | pci_disable_device(pdev); | |
1084 | return rc; | |
1085 | } | |
1086 | ||
1087 | ||
1088 | static int __init pdc_ata_init(void) | |
1089 | { | |
b7887196 | 1090 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1091 | } |
1092 | ||
1093 | ||
1094 | static void __exit pdc_ata_exit(void) | |
1095 | { | |
1096 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1097 | } | |
1098 | ||
1099 | ||
1100 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 1101 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1102 | MODULE_LICENSE("GPL"); |
1103 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1104 | MODULE_VERSION(DRV_VERSION); | |
1105 | ||
1106 | module_init(pdc_ata_init); | |
1107 | module_exit(pdc_ata_exit); |