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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
95006188 | 42 | #include <scsi/scsi.h> |
1da177e4 | 43 | #include <scsi/scsi_host.h> |
193515d5 | 44 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 45 | #include <linux/libata.h> |
1da177e4 LT |
46 | #include "sata_promise.h" |
47 | ||
48 | #define DRV_NAME "sata_promise" | |
46b027cc | 49 | #define DRV_VERSION "1.05" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
0d5ff566 TH |
53 | PDC_MMIO_BAR = 3, |
54 | ||
95006188 MP |
55 | /* register offsets */ |
56 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | |
57 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
58 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
59 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
60 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
61 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
62 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 63 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 LT |
64 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
65 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 66 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
67 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
68 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
69 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 70 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
71 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
72 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 LT |
73 | |
74 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
75 | (1<<8) | (1<<9) | (1<<10), | |
76 | ||
77 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
78 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 79 | board_20619 = 2, /* FastTrak TX4000 */ |
d324d462 MP |
80 | board_2057x = 3, /* SATAII150 Tx2plus */ |
81 | board_40518 = 4, /* SATAII150 Tx4 */ | |
1da177e4 | 82 | |
6340f019 | 83 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 84 | |
95006188 MP |
85 | /* Sequence counter control registers bit definitions */ |
86 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
87 | ||
88 | /* Feature register values */ | |
89 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
90 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
91 | ||
92 | /* Device/Head register values */ | |
93 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
94 | ||
25b93d81 MP |
95 | /* PDC_CTLSTAT bit definitions */ |
96 | PDC_DMA_ENABLE = (1 << 7), | |
97 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 98 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 99 | |
25b93d81 | 100 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 101 | ATA_FLAG_MMIO | |
3d0a59c0 | 102 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 MP |
103 | |
104 | /* hp->flags bits */ | |
105 | PDC_FLAG_GEN_II = (1 << 0), | |
1da177e4 LT |
106 | }; |
107 | ||
108 | ||
109 | struct pdc_port_priv { | |
110 | u8 *pkt; | |
111 | dma_addr_t pkt_dma; | |
112 | }; | |
113 | ||
6340f019 | 114 | struct pdc_host_priv { |
b2d1eee1 | 115 | unsigned long flags; |
870ae337 | 116 | unsigned long port_flags[ATA_MAX_PORTS]; |
6340f019 LK |
117 | }; |
118 | ||
1da177e4 LT |
119 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
120 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
121 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
7d12e780 | 122 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance); |
1da177e4 LT |
123 | static void pdc_eng_timeout(struct ata_port *ap); |
124 | static int pdc_port_start(struct ata_port *ap); | |
2cba582a | 125 | static void pdc_pata_phy_reset(struct ata_port *ap); |
1da177e4 | 126 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
127 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
128 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 MP |
129 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
130 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc); | |
1da177e4 | 131 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 132 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
25b93d81 MP |
133 | static void pdc_freeze(struct ata_port *ap); |
134 | static void pdc_thaw(struct ata_port *ap); | |
135 | static void pdc_error_handler(struct ata_port *ap); | |
136 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); | |
1da177e4 | 137 | |
374b1873 | 138 | |
193515d5 | 139 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
140 | .module = THIS_MODULE, |
141 | .name = DRV_NAME, | |
142 | .ioctl = ata_scsi_ioctl, | |
143 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
144 | .can_queue = ATA_DEF_QUEUE, |
145 | .this_id = ATA_SHT_THIS_ID, | |
146 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
147 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
148 | .emulated = ATA_SHT_EMULATED, | |
149 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
150 | .proc_name = DRV_NAME, | |
151 | .dma_boundary = ATA_DMA_BOUNDARY, | |
152 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 153 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 154 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
155 | }; |
156 | ||
057ace5e | 157 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
158 | .port_disable = ata_port_disable, |
159 | .tf_load = pdc_tf_load_mmio, | |
160 | .tf_read = ata_tf_read, | |
161 | .check_status = ata_check_status, | |
162 | .exec_command = pdc_exec_command_mmio, | |
163 | .dev_select = ata_std_dev_select, | |
95006188 MP |
164 | .check_atapi_dma = pdc_check_atapi_dma, |
165 | ||
166 | .qc_prep = pdc_qc_prep, | |
167 | .qc_issue = pdc_qc_issue_prot, | |
168 | .freeze = pdc_freeze, | |
169 | .thaw = pdc_thaw, | |
170 | .error_handler = pdc_error_handler, | |
171 | .post_internal_cmd = pdc_post_internal_cmd, | |
0d5ff566 | 172 | .data_xfer = ata_data_xfer, |
95006188 MP |
173 | .irq_handler = pdc_interrupt, |
174 | .irq_clear = pdc_irq_clear, | |
246ce3b6 AI |
175 | .irq_on = ata_irq_on, |
176 | .irq_ack = ata_irq_ack, | |
95006188 MP |
177 | |
178 | .scr_read = pdc_sata_scr_read, | |
179 | .scr_write = pdc_sata_scr_write, | |
180 | .port_start = pdc_port_start, | |
95006188 MP |
181 | }; |
182 | ||
183 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ | |
184 | static const struct ata_port_operations pdc_old_sata_ops = { | |
185 | .port_disable = ata_port_disable, | |
186 | .tf_load = pdc_tf_load_mmio, | |
187 | .tf_read = ata_tf_read, | |
188 | .check_status = ata_check_status, | |
189 | .exec_command = pdc_exec_command_mmio, | |
190 | .dev_select = ata_std_dev_select, | |
191 | .check_atapi_dma = pdc_old_check_atapi_dma, | |
2cba582a | 192 | |
1da177e4 LT |
193 | .qc_prep = pdc_qc_prep, |
194 | .qc_issue = pdc_qc_issue_prot, | |
25b93d81 MP |
195 | .freeze = pdc_freeze, |
196 | .thaw = pdc_thaw, | |
197 | .error_handler = pdc_error_handler, | |
198 | .post_internal_cmd = pdc_post_internal_cmd, | |
0d5ff566 | 199 | .data_xfer = ata_data_xfer, |
1da177e4 LT |
200 | .irq_handler = pdc_interrupt, |
201 | .irq_clear = pdc_irq_clear, | |
246ce3b6 AI |
202 | .irq_on = ata_irq_on, |
203 | .irq_ack = ata_irq_ack, | |
2cba582a | 204 | |
1da177e4 LT |
205 | .scr_read = pdc_sata_scr_read, |
206 | .scr_write = pdc_sata_scr_write, | |
207 | .port_start = pdc_port_start, | |
1da177e4 LT |
208 | }; |
209 | ||
057ace5e | 210 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
211 | .port_disable = ata_port_disable, |
212 | .tf_load = pdc_tf_load_mmio, | |
213 | .tf_read = ata_tf_read, | |
214 | .check_status = ata_check_status, | |
215 | .exec_command = pdc_exec_command_mmio, | |
216 | .dev_select = ata_std_dev_select, | |
95006188 | 217 | .check_atapi_dma = pdc_check_atapi_dma, |
2cba582a JG |
218 | |
219 | .phy_reset = pdc_pata_phy_reset, | |
220 | ||
221 | .qc_prep = pdc_qc_prep, | |
222 | .qc_issue = pdc_qc_issue_prot, | |
0d5ff566 | 223 | .data_xfer = ata_data_xfer, |
2cba582a JG |
224 | .eng_timeout = pdc_eng_timeout, |
225 | .irq_handler = pdc_interrupt, | |
226 | .irq_clear = pdc_irq_clear, | |
246ce3b6 AI |
227 | .irq_on = ata_irq_on, |
228 | .irq_ack = ata_irq_ack, | |
2cba582a JG |
229 | |
230 | .port_start = pdc_port_start, | |
2cba582a JG |
231 | }; |
232 | ||
98ac62de | 233 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
234 | /* board_2037x */ |
235 | { | |
236 | .sht = &pdc_ata_sht, | |
870ae337 | 237 | .flags = PDC_COMMON_FLAGS, |
1da177e4 LT |
238 | .pio_mask = 0x1f, /* pio0-4 */ |
239 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
240 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 241 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
242 | }, |
243 | ||
244 | /* board_20319 */ | |
245 | { | |
246 | .sht = &pdc_ata_sht, | |
cca3974e | 247 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
248 | .pio_mask = 0x1f, /* pio0-4 */ |
249 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
250 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
95006188 | 251 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 252 | }, |
f497ba73 TL |
253 | |
254 | /* board_20619 */ | |
255 | { | |
256 | .sht = &pdc_ata_sht, | |
25b93d81 | 257 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
258 | .pio_mask = 0x1f, /* pio0-4 */ |
259 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
260 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 261 | .port_ops = &pdc_pata_ops, |
f497ba73 | 262 | }, |
5a46fe89 | 263 | |
6340f019 LK |
264 | /* board_2057x */ |
265 | { | |
266 | .sht = &pdc_ata_sht, | |
870ae337 | 267 | .flags = PDC_COMMON_FLAGS, |
6340f019 LK |
268 | .pio_mask = 0x1f, /* pio0-4 */ |
269 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
270 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
271 | .port_ops = &pdc_sata_ops, | |
272 | }, | |
273 | ||
274 | /* board_40518 */ | |
275 | { | |
276 | .sht = &pdc_ata_sht, | |
cca3974e | 277 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
6340f019 LK |
278 | .pio_mask = 0x1f, /* pio0-4 */ |
279 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
280 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
281 | .port_ops = &pdc_sata_ops, | |
282 | }, | |
1da177e4 LT |
283 | }; |
284 | ||
3b7d697d | 285 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 286 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
287 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
288 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
289 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
290 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
291 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 292 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 293 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 294 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 295 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
296 | |
297 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
298 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
299 | { PCI_VDEVICE(PROMISE, 0x3515), board_20319 }, | |
300 | { PCI_VDEVICE(PROMISE, 0x3519), board_20319 }, | |
b2d1eee1 | 301 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
302 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
303 | ||
304 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 305 | |
1da177e4 LT |
306 | { } /* terminate list */ |
307 | }; | |
308 | ||
309 | ||
310 | static struct pci_driver pdc_ata_pci_driver = { | |
311 | .name = DRV_NAME, | |
312 | .id_table = pdc_ata_pci_tbl, | |
313 | .probe = pdc_ata_init_one, | |
314 | .remove = ata_pci_remove_one, | |
315 | }; | |
316 | ||
317 | ||
318 | static int pdc_port_start(struct ata_port *ap) | |
319 | { | |
cca3974e | 320 | struct device *dev = ap->host->dev; |
599b7202 | 321 | struct pdc_host_priv *hp = ap->host->private_data; |
1da177e4 LT |
322 | struct pdc_port_priv *pp; |
323 | int rc; | |
324 | ||
870ae337 MP |
325 | /* fix up port flags and cable type for SATA+PATA chips */ |
326 | ap->flags |= hp->port_flags[ap->port_no]; | |
327 | if (ap->flags & ATA_FLAG_SATA) | |
328 | ap->cbl = ATA_CBL_SATA; | |
329 | ||
1da177e4 LT |
330 | rc = ata_port_start(ap); |
331 | if (rc) | |
332 | return rc; | |
333 | ||
24dc5f33 TH |
334 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
335 | if (!pp) | |
336 | return -ENOMEM; | |
1da177e4 | 337 | |
24dc5f33 TH |
338 | pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); |
339 | if (!pp->pkt) | |
340 | return -ENOMEM; | |
1da177e4 LT |
341 | |
342 | ap->private_data = pp; | |
343 | ||
599b7202 MP |
344 | /* fix up PHYMODE4 align timing */ |
345 | if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) { | |
346 | void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr; | |
347 | unsigned int tmp; | |
348 | ||
349 | tmp = readl(mmio + 0x014); | |
350 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | |
351 | writel(tmp, mmio + 0x014); | |
352 | } | |
353 | ||
1da177e4 | 354 | return 0; |
1da177e4 LT |
355 | } |
356 | ||
1da177e4 LT |
357 | static void pdc_reset_port(struct ata_port *ap) |
358 | { | |
0d5ff566 | 359 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
360 | unsigned int i; |
361 | u32 tmp; | |
362 | ||
363 | for (i = 11; i > 0; i--) { | |
364 | tmp = readl(mmio); | |
365 | if (tmp & PDC_RESET) | |
366 | break; | |
367 | ||
368 | udelay(100); | |
369 | ||
370 | tmp |= PDC_RESET; | |
371 | writel(tmp, mmio); | |
372 | } | |
373 | ||
374 | tmp &= ~PDC_RESET; | |
375 | writel(tmp, mmio); | |
376 | readl(mmio); /* flush */ | |
377 | } | |
378 | ||
d3fb4e8d | 379 | static void pdc_pata_cbl_detect(struct ata_port *ap) |
2cba582a | 380 | { |
d3fb4e8d | 381 | u8 tmp; |
03dc5506 | 382 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d JG |
383 | |
384 | tmp = readb(mmio); | |
385 | ||
386 | if (tmp & 0x01) { | |
387 | ap->cbl = ATA_CBL_PATA40; | |
388 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
389 | } else | |
390 | ap->cbl = ATA_CBL_PATA80; | |
391 | } | |
2cba582a | 392 | |
d3fb4e8d JG |
393 | static void pdc_pata_phy_reset(struct ata_port *ap) |
394 | { | |
395 | pdc_pata_cbl_detect(ap); | |
2cba582a JG |
396 | pdc_reset_port(ap); |
397 | ata_port_probe(ap); | |
398 | ata_bus_reset(ap); | |
399 | } | |
400 | ||
1da177e4 LT |
401 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
402 | { | |
870ae337 | 403 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 404 | return 0xffffffffU; |
0d5ff566 | 405 | return readl(ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
406 | } |
407 | ||
408 | ||
409 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
410 | u32 val) | |
411 | { | |
870ae337 | 412 | if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA) |
1da177e4 | 413 | return; |
0d5ff566 | 414 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
415 | } |
416 | ||
fba6edbd | 417 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
95006188 | 418 | { |
4113bb6b MP |
419 | struct ata_port *ap = qc->ap; |
420 | dma_addr_t sg_table = ap->prd_dma; | |
421 | unsigned int cdb_len = qc->dev->cdb_len; | |
422 | u8 *cdb = qc->cdb; | |
423 | struct pdc_port_priv *pp = ap->private_data; | |
424 | u8 *buf = pp->pkt; | |
95006188 | 425 | u32 *buf32 = (u32 *) buf; |
4113bb6b | 426 | unsigned int dev_sel, feature, nbytes; |
95006188 MP |
427 | |
428 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
429 | * and seq id (byte 2) | |
430 | */ | |
fba6edbd MP |
431 | switch (qc->tf.protocol) { |
432 | case ATA_PROT_ATAPI_DMA: | |
433 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | |
434 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
435 | else | |
436 | buf32[0] = 0; | |
437 | break; | |
438 | case ATA_PROT_ATAPI_NODATA: | |
439 | buf32[0] = cpu_to_le32(PDC_PKT_NODATA); | |
440 | break; | |
441 | default: | |
442 | BUG(); | |
443 | break; | |
444 | } | |
95006188 MP |
445 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ |
446 | buf32[2] = 0; /* no next-packet */ | |
447 | ||
4113bb6b MP |
448 | /* select drive */ |
449 | if (sata_scr_valid(ap)) { | |
450 | dev_sel = PDC_DEVICE_SATA; | |
451 | } else { | |
452 | dev_sel = ATA_DEVICE_OBS; | |
453 | if (qc->dev->devno != 0) | |
454 | dev_sel |= ATA_DEV1; | |
455 | } | |
456 | buf[12] = (1 << 5) | ATA_REG_DEVICE; | |
457 | buf[13] = dev_sel; | |
458 | buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; | |
459 | buf[15] = dev_sel; /* once more, waiting for BSY to clear */ | |
460 | ||
461 | buf[16] = (1 << 5) | ATA_REG_NSECT; | |
462 | buf[17] = 0x00; | |
463 | buf[18] = (1 << 5) | ATA_REG_LBAL; | |
464 | buf[19] = 0x00; | |
465 | ||
466 | /* set feature and byte counter registers */ | |
467 | if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { | |
468 | feature = PDC_FEATURE_ATAPI_PIO; | |
469 | /* set byte counter register to real transfer byte count */ | |
470 | nbytes = qc->nbytes; | |
4113bb6b MP |
471 | if (nbytes > 0xffff) |
472 | nbytes = 0xffff; | |
473 | } else { | |
474 | feature = PDC_FEATURE_ATAPI_DMA; | |
475 | /* set byte counter register to 0 */ | |
476 | nbytes = 0; | |
477 | } | |
478 | buf[20] = (1 << 5) | ATA_REG_FEATURE; | |
479 | buf[21] = feature; | |
480 | buf[22] = (1 << 5) | ATA_REG_BYTEL; | |
481 | buf[23] = nbytes & 0xFF; | |
482 | buf[24] = (1 << 5) | ATA_REG_BYTEH; | |
483 | buf[25] = (nbytes >> 8) & 0xFF; | |
484 | ||
485 | /* send ATAPI packet command 0xA0 */ | |
486 | buf[26] = (1 << 5) | ATA_REG_CMD; | |
487 | buf[27] = ATA_CMD_PACKET; | |
488 | ||
489 | /* select drive and check DRQ */ | |
490 | buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; | |
491 | buf[29] = dev_sel; | |
492 | ||
95006188 MP |
493 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ |
494 | BUG_ON(cdb_len & ~0x1E); | |
495 | ||
4113bb6b MP |
496 | /* append the CDB as the final part */ |
497 | buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
498 | memcpy(buf+31, cdb, cdb_len); | |
95006188 MP |
499 | } |
500 | ||
1da177e4 LT |
501 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
502 | { | |
503 | struct pdc_port_priv *pp = qc->ap->private_data; | |
504 | unsigned int i; | |
505 | ||
506 | VPRINTK("ENTER\n"); | |
507 | ||
508 | switch (qc->tf.protocol) { | |
509 | case ATA_PROT_DMA: | |
510 | ata_qc_prep(qc); | |
511 | /* fall through */ | |
512 | ||
513 | case ATA_PROT_NODATA: | |
514 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
515 | qc->dev->devno, pp->pkt); | |
516 | ||
517 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
518 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
519 | else | |
520 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
521 | ||
522 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
523 | break; | |
524 | ||
95006188 | 525 | case ATA_PROT_ATAPI: |
95006188 MP |
526 | ata_qc_prep(qc); |
527 | break; | |
528 | ||
529 | case ATA_PROT_ATAPI_DMA: | |
530 | ata_qc_prep(qc); | |
fba6edbd MP |
531 | /*FALLTHROUGH*/ |
532 | case ATA_PROT_ATAPI_NODATA: | |
533 | pdc_atapi_pkt(qc); | |
95006188 MP |
534 | break; |
535 | ||
1da177e4 LT |
536 | default: |
537 | break; | |
538 | } | |
539 | } | |
540 | ||
25b93d81 MP |
541 | static void pdc_freeze(struct ata_port *ap) |
542 | { | |
543 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
544 | u32 tmp; | |
545 | ||
546 | tmp = readl(mmio + PDC_CTLSTAT); | |
547 | tmp |= PDC_IRQ_DISABLE; | |
548 | tmp &= ~PDC_DMA_ENABLE; | |
549 | writel(tmp, mmio + PDC_CTLSTAT); | |
550 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
551 | } | |
552 | ||
553 | static void pdc_thaw(struct ata_port *ap) | |
554 | { | |
555 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
556 | u32 tmp; | |
557 | ||
558 | /* clear IRQ */ | |
559 | readl(mmio + PDC_INT_SEQMASK); | |
560 | ||
561 | /* turn IRQ back on */ | |
562 | tmp = readl(mmio + PDC_CTLSTAT); | |
563 | tmp &= ~PDC_IRQ_DISABLE; | |
564 | writel(tmp, mmio + PDC_CTLSTAT); | |
565 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
566 | } | |
567 | ||
568 | static void pdc_error_handler(struct ata_port *ap) | |
569 | { | |
570 | ata_reset_fn_t hardreset; | |
571 | ||
572 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) | |
573 | pdc_reset_port(ap); | |
574 | ||
575 | hardreset = NULL; | |
576 | if (sata_scr_valid(ap)) | |
577 | hardreset = sata_std_hardreset; | |
578 | ||
579 | /* perform recovery */ | |
580 | ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, | |
581 | ata_std_postreset); | |
582 | } | |
583 | ||
584 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) | |
585 | { | |
586 | struct ata_port *ap = qc->ap; | |
587 | ||
588 | if (qc->flags & ATA_QCFLAG_FAILED) | |
589 | qc->err_mask |= AC_ERR_OTHER; | |
590 | ||
591 | /* make DMA engine forget about the failed command */ | |
592 | if (qc->err_mask) | |
593 | pdc_reset_port(ap); | |
594 | } | |
595 | ||
1da177e4 LT |
596 | static void pdc_eng_timeout(struct ata_port *ap) |
597 | { | |
cca3974e | 598 | struct ata_host *host = ap->host; |
1da177e4 LT |
599 | u8 drv_stat; |
600 | struct ata_queued_cmd *qc; | |
b8f6153e | 601 | unsigned long flags; |
1da177e4 LT |
602 | |
603 | DPRINTK("ENTER\n"); | |
604 | ||
cca3974e | 605 | spin_lock_irqsave(&host->lock, flags); |
b8f6153e | 606 | |
1da177e4 | 607 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1da177e4 | 608 | |
1da177e4 LT |
609 | switch (qc->tf.protocol) { |
610 | case ATA_PROT_DMA: | |
611 | case ATA_PROT_NODATA: | |
f15a1daf | 612 | ata_port_printk(ap, KERN_ERR, "command timeout\n"); |
a7dac447 | 613 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 | 614 | qc->err_mask |= __ac_err_mask(drv_stat); |
1da177e4 LT |
615 | break; |
616 | ||
617 | default: | |
618 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
619 | ||
f15a1daf TH |
620 | ata_port_printk(ap, KERN_ERR, |
621 | "unknown timeout, cmd 0x%x stat 0x%x\n", | |
622 | qc->tf.command, drv_stat); | |
1da177e4 | 623 | |
a22e2eb0 | 624 | qc->err_mask |= ac_err_mask(drv_stat); |
1da177e4 LT |
625 | break; |
626 | } | |
627 | ||
cca3974e | 628 | spin_unlock_irqrestore(&host->lock, flags); |
f6379020 | 629 | ata_eh_qc_complete(qc); |
1da177e4 LT |
630 | DPRINTK("EXIT\n"); |
631 | } | |
632 | ||
633 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
634 | struct ata_queued_cmd *qc) | |
635 | { | |
a22e2eb0 | 636 | unsigned int handled = 0; |
1da177e4 | 637 | u32 tmp; |
0d5ff566 | 638 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
639 | |
640 | tmp = readl(mmio); | |
641 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 642 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
643 | pdc_reset_port(ap); |
644 | } | |
645 | ||
646 | switch (qc->tf.protocol) { | |
647 | case ATA_PROT_DMA: | |
648 | case ATA_PROT_NODATA: | |
95006188 | 649 | case ATA_PROT_ATAPI_DMA: |
fba6edbd | 650 | case ATA_PROT_ATAPI_NODATA: |
a22e2eb0 AL |
651 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
652 | ata_qc_complete(qc); | |
1da177e4 LT |
653 | handled = 1; |
654 | break; | |
655 | ||
656 | default: | |
ee500aab AL |
657 | ap->stats.idle_irq++; |
658 | break; | |
1da177e4 LT |
659 | } |
660 | ||
ee500aab | 661 | return handled; |
1da177e4 LT |
662 | } |
663 | ||
664 | static void pdc_irq_clear(struct ata_port *ap) | |
665 | { | |
cca3974e | 666 | struct ata_host *host = ap->host; |
0d5ff566 | 667 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
668 | |
669 | readl(mmio + PDC_INT_SEQMASK); | |
670 | } | |
671 | ||
7d12e780 | 672 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance) |
1da177e4 | 673 | { |
cca3974e | 674 | struct ata_host *host = dev_instance; |
1da177e4 LT |
675 | struct ata_port *ap; |
676 | u32 mask = 0; | |
677 | unsigned int i, tmp; | |
678 | unsigned int handled = 0; | |
ea6ba10b | 679 | void __iomem *mmio_base; |
1da177e4 LT |
680 | |
681 | VPRINTK("ENTER\n"); | |
682 | ||
0d5ff566 | 683 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
1da177e4 LT |
684 | VPRINTK("QUICK EXIT\n"); |
685 | return IRQ_NONE; | |
686 | } | |
687 | ||
0d5ff566 | 688 | mmio_base = host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
689 | |
690 | /* reading should also clear interrupts */ | |
691 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
692 | ||
693 | if (mask == 0xffffffff) { | |
694 | VPRINTK("QUICK EXIT 2\n"); | |
695 | return IRQ_NONE; | |
696 | } | |
6340f019 | 697 | |
cca3974e | 698 | spin_lock(&host->lock); |
6340f019 | 699 | |
1da177e4 LT |
700 | mask &= 0xffff; /* only 16 tags possible */ |
701 | if (!mask) { | |
702 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 703 | goto done_irq; |
1da177e4 LT |
704 | } |
705 | ||
1da177e4 LT |
706 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
707 | ||
cca3974e | 708 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 709 | VPRINTK("port %u\n", i); |
cca3974e | 710 | ap = host->ports[i]; |
1da177e4 | 711 | tmp = mask & (1 << (i + 1)); |
c1389503 | 712 | if (tmp && ap && |
029f5468 | 713 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
714 | struct ata_queued_cmd *qc; |
715 | ||
716 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 717 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
718 | handled += pdc_host_intr(ap, qc); |
719 | } | |
720 | } | |
721 | ||
1da177e4 LT |
722 | VPRINTK("EXIT\n"); |
723 | ||
6340f019 | 724 | done_irq: |
cca3974e | 725 | spin_unlock(&host->lock); |
1da177e4 LT |
726 | return IRQ_RETVAL(handled); |
727 | } | |
728 | ||
729 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
730 | { | |
731 | struct ata_port *ap = qc->ap; | |
732 | struct pdc_port_priv *pp = ap->private_data; | |
0d5ff566 | 733 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
734 | unsigned int port_no = ap->port_no; |
735 | u8 seq = (u8) (port_no + 1); | |
736 | ||
737 | VPRINTK("ENTER, ap %p\n", ap); | |
738 | ||
0d5ff566 TH |
739 | writel(0x00000001, mmio + (seq * 4)); |
740 | readl(mmio + (seq * 4)); /* flush */ | |
1da177e4 LT |
741 | |
742 | pp->pkt[2] = seq; | |
743 | wmb(); /* flush PRD, pkt writes */ | |
0d5ff566 TH |
744 | writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
745 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
746 | } |
747 | ||
9a3d9eb0 | 748 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
749 | { |
750 | switch (qc->tf.protocol) { | |
fba6edbd MP |
751 | case ATA_PROT_ATAPI_NODATA: |
752 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
753 | break; | |
754 | /*FALLTHROUGH*/ | |
95006188 | 755 | case ATA_PROT_ATAPI_DMA: |
1da177e4 LT |
756 | case ATA_PROT_DMA: |
757 | case ATA_PROT_NODATA: | |
758 | pdc_packet_start(qc); | |
759 | return 0; | |
760 | ||
1da177e4 LT |
761 | default: |
762 | break; | |
763 | } | |
764 | ||
765 | return ata_qc_issue_prot(qc); | |
766 | } | |
767 | ||
057ace5e | 768 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
769 | { |
770 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
771 | tf->protocol == ATA_PROT_NODATA); | |
772 | ata_tf_load(ap, tf); | |
773 | } | |
774 | ||
775 | ||
057ace5e | 776 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
777 | { |
778 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
779 | tf->protocol == ATA_PROT_NODATA); | |
780 | ata_exec_command(ap, tf); | |
781 | } | |
782 | ||
95006188 MP |
783 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
784 | { | |
785 | u8 *scsicmd = qc->scsicmd->cmnd; | |
786 | int pio = 1; /* atapi dma off by default */ | |
787 | ||
788 | /* Whitelist commands that may use DMA. */ | |
789 | switch (scsicmd[0]) { | |
790 | case WRITE_12: | |
791 | case WRITE_10: | |
792 | case WRITE_6: | |
793 | case READ_12: | |
794 | case READ_10: | |
795 | case READ_6: | |
796 | case 0xad: /* READ_DVD_STRUCTURE */ | |
797 | case 0xbe: /* READ_CD */ | |
798 | pio = 0; | |
799 | } | |
800 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
801 | if (scsicmd[0] == WRITE_10) { | |
802 | unsigned int lba; | |
803 | lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5]; | |
804 | if (lba >= 0xFFFF4FA2) | |
805 | pio = 1; | |
806 | } | |
807 | return pio; | |
808 | } | |
809 | ||
810 | static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc) | |
811 | { | |
812 | struct ata_port *ap = qc->ap; | |
813 | ||
814 | /* First generation chips cannot use ATAPI DMA on SATA ports */ | |
815 | if (sata_scr_valid(ap)) | |
816 | return 1; | |
817 | return pdc_check_atapi_dma(qc); | |
818 | } | |
1da177e4 | 819 | |
0d5ff566 | 820 | static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) |
1da177e4 LT |
821 | { |
822 | port->cmd_addr = base; | |
823 | port->data_addr = base; | |
824 | port->feature_addr = | |
825 | port->error_addr = base + 0x4; | |
826 | port->nsect_addr = base + 0x8; | |
827 | port->lbal_addr = base + 0xc; | |
828 | port->lbam_addr = base + 0x10; | |
829 | port->lbah_addr = base + 0x14; | |
830 | port->device_addr = base + 0x18; | |
831 | port->command_addr = | |
832 | port->status_addr = base + 0x1c; | |
833 | port->altstatus_addr = | |
834 | port->ctl_addr = base + 0x38; | |
835 | } | |
836 | ||
837 | ||
838 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
839 | { | |
0d5ff566 | 840 | void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; |
6340f019 | 841 | struct pdc_host_priv *hp = pe->private_data; |
d324d462 | 842 | int hotplug_offset; |
1da177e4 LT |
843 | u32 tmp; |
844 | ||
d324d462 MP |
845 | if (hp->flags & PDC_FLAG_GEN_II) |
846 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
847 | else | |
848 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
849 | ||
1da177e4 LT |
850 | /* |
851 | * Except for the hotplug stuff, this is voodoo from the | |
852 | * Promise driver. Label this entire section | |
853 | * "TODO: figure out why we do this" | |
854 | */ | |
855 | ||
b2d1eee1 | 856 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 857 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 MP |
858 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
859 | if (!(hp->flags & PDC_FLAG_GEN_II)) | |
860 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ | |
1da177e4 LT |
861 | writel(tmp, mmio + PDC_FLASH_CTL); |
862 | ||
863 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
864 | tmp = readl(mmio + hotplug_offset); |
865 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
866 | |
867 | /* mask plug/unplug ints */ | |
6340f019 LK |
868 | tmp = readl(mmio + hotplug_offset); |
869 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 | 870 | |
b2d1eee1 MP |
871 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
872 | if (hp->flags & PDC_FLAG_GEN_II) | |
873 | return; | |
874 | ||
1da177e4 LT |
875 | /* reduce TBG clock to 133 Mhz. */ |
876 | tmp = readl(mmio + PDC_TBG_MODE); | |
877 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
878 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
879 | writel(tmp, mmio + PDC_TBG_MODE); | |
880 | ||
881 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
882 | msleep(10); | |
883 | ||
884 | /* adjust slew rate control register. */ | |
885 | tmp = readl(mmio + PDC_SLEW_CTL); | |
886 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
887 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
888 | writel(tmp, mmio + PDC_SLEW_CTL); | |
889 | } | |
890 | ||
891 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
892 | { | |
893 | static int printed_version; | |
24dc5f33 | 894 | struct ata_probe_ent *probe_ent; |
6340f019 | 895 | struct pdc_host_priv *hp; |
0d5ff566 | 896 | void __iomem *base; |
1da177e4 | 897 | unsigned int board_idx = (unsigned int) ent->driver_data; |
1da177e4 | 898 | int rc; |
870ae337 | 899 | u8 tmp; |
1da177e4 LT |
900 | |
901 | if (!printed_version++) | |
a9524a76 | 902 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 903 | |
24dc5f33 | 904 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
905 | if (rc) |
906 | return rc; | |
907 | ||
0d5ff566 TH |
908 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
909 | if (rc == -EBUSY) | |
24dc5f33 | 910 | pcim_pin_device(pdev); |
0d5ff566 | 911 | if (rc) |
24dc5f33 | 912 | return rc; |
1da177e4 LT |
913 | |
914 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
915 | if (rc) | |
24dc5f33 | 916 | return rc; |
1da177e4 LT |
917 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
918 | if (rc) | |
24dc5f33 | 919 | return rc; |
1da177e4 | 920 | |
24dc5f33 TH |
921 | probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); |
922 | if (probe_ent == NULL) | |
923 | return -ENOMEM; | |
1da177e4 | 924 | |
1da177e4 LT |
925 | probe_ent->dev = pci_dev_to_dev(pdev); |
926 | INIT_LIST_HEAD(&probe_ent->node); | |
927 | ||
24dc5f33 TH |
928 | hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL); |
929 | if (hp == NULL) | |
930 | return -ENOMEM; | |
6340f019 | 931 | |
6340f019 LK |
932 | probe_ent->private_data = hp; |
933 | ||
1da177e4 | 934 | probe_ent->sht = pdc_port_info[board_idx].sht; |
cca3974e | 935 | probe_ent->port_flags = pdc_port_info[board_idx].flags; |
1da177e4 LT |
936 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; |
937 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
938 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
939 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
940 | ||
941 | probe_ent->irq = pdev->irq; | |
1d6f359a | 942 | probe_ent->irq_flags = IRQF_SHARED; |
0d5ff566 TH |
943 | probe_ent->iomap = pcim_iomap_table(pdev); |
944 | ||
945 | base = probe_ent->iomap[PDC_MMIO_BAR]; | |
1da177e4 LT |
946 | |
947 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
948 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
949 | ||
950 | probe_ent->port[0].scr_addr = base + 0x400; | |
951 | probe_ent->port[1].scr_addr = base + 0x500; | |
952 | ||
953 | /* notice 4-port boards */ | |
954 | switch (board_idx) { | |
6340f019 | 955 | case board_40518: |
b2d1eee1 | 956 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 957 | /* Fall through */ |
1da177e4 LT |
958 | case board_20319: |
959 | probe_ent->n_ports = 4; | |
960 | ||
961 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
962 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
963 | ||
964 | probe_ent->port[2].scr_addr = base + 0x600; | |
965 | probe_ent->port[3].scr_addr = base + 0x700; | |
966 | break; | |
6340f019 | 967 | case board_2057x: |
b2d1eee1 | 968 | hp->flags |= PDC_FLAG_GEN_II; |
6340f019 | 969 | /* Fall through */ |
1da177e4 | 970 | case board_2037x: |
870ae337 | 971 | /* TX2plus boards also have a PATA port */ |
0d5ff566 | 972 | tmp = readb(base + PDC_FLASH_CTL+1); |
870ae337 MP |
973 | if (!(tmp & 0x80)) { |
974 | probe_ent->n_ports = 3; | |
975 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
976 | hp->port_flags[2] = ATA_FLAG_SLAVE_POSS; | |
977 | printk(KERN_INFO DRV_NAME " PATA port found\n"); | |
978 | } else | |
979 | probe_ent->n_ports = 2; | |
980 | hp->port_flags[0] = ATA_FLAG_SATA; | |
981 | hp->port_flags[1] = ATA_FLAG_SATA; | |
1da177e4 | 982 | break; |
f497ba73 TL |
983 | case board_20619: |
984 | probe_ent->n_ports = 4; | |
985 | ||
986 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
987 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
988 | ||
989 | probe_ent->port[2].scr_addr = base + 0x600; | |
990 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 991 | break; |
1da177e4 LT |
992 | default: |
993 | BUG(); | |
994 | break; | |
995 | } | |
996 | ||
997 | pci_set_master(pdev); | |
998 | ||
999 | /* initialize adapter */ | |
1000 | pdc_host_init(board_idx, probe_ent); | |
1001 | ||
6340f019 | 1002 | if (!ata_device_add(probe_ent)) |
24dc5f33 | 1003 | return -ENODEV; |
1da177e4 | 1004 | |
24dc5f33 | 1005 | devm_kfree(&pdev->dev, probe_ent); |
1da177e4 | 1006 | return 0; |
1da177e4 LT |
1007 | } |
1008 | ||
1009 | ||
1010 | static int __init pdc_ata_init(void) | |
1011 | { | |
b7887196 | 1012 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1013 | } |
1014 | ||
1015 | ||
1016 | static void __exit pdc_ata_exit(void) | |
1017 | { | |
1018 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1019 | } | |
1020 | ||
1021 | ||
1022 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 1023 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1024 | MODULE_LICENSE("GPL"); |
1025 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1026 | MODULE_VERSION(DRV_VERSION); | |
1027 | ||
1028 | module_init(pdc_ata_init); | |
1029 | module_exit(pdc_ata_exit); |