Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
a9524a76 | 40 | #include <linux/device.h> |
95006188 | 41 | #include <scsi/scsi.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 44 | #include <linux/libata.h> |
1da177e4 LT |
45 | #include "sata_promise.h" |
46 | ||
47 | #define DRV_NAME "sata_promise" | |
7f9992a2 | 48 | #define DRV_VERSION "2.10" |
1da177e4 LT |
49 | |
50 | enum { | |
eca25dca | 51 | PDC_MAX_PORTS = 4, |
0d5ff566 TH |
52 | PDC_MMIO_BAR = 3, |
53 | ||
95006188 MP |
54 | /* register offsets */ |
55 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | |
56 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
57 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
58 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
59 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
60 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
61 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 62 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 LT |
63 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
64 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 65 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
66 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
67 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
68 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 69 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
70 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
71 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 | 72 | |
176efb05 MP |
73 | /* PDC_GLOBAL_CTL bit definitions */ |
74 | PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ | |
75 | PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ | |
76 | PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ | |
77 | PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ | |
78 | PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ | |
79 | PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ | |
80 | PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ | |
81 | PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ | |
82 | PDC_DRIVE_ERR = (1 << 21), /* drive error */ | |
83 | PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ | |
84 | PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ | |
85 | PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, | |
5796d1c4 JG |
86 | PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | |
87 | PDC2_ATA_DMA_CNT_ERR, | |
88 | PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | | |
89 | PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | | |
90 | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | | |
91 | PDC1_ERR_MASK | PDC2_ERR_MASK, | |
1da177e4 LT |
92 | |
93 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
eca25dca TH |
94 | board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ |
95 | board_20319 = 2, /* FastTrak S150 TX4 */ | |
96 | board_20619 = 3, /* FastTrak TX4000 */ | |
97 | board_2057x = 4, /* SATAII150 Tx2plus */ | |
d0e58031 | 98 | board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ |
eca25dca | 99 | board_40518 = 6, /* SATAII150 Tx4 */ |
1da177e4 | 100 | |
6340f019 | 101 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 102 | |
95006188 MP |
103 | /* Sequence counter control registers bit definitions */ |
104 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
105 | ||
106 | /* Feature register values */ | |
107 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
108 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
109 | ||
110 | /* Device/Head register values */ | |
111 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
112 | ||
25b93d81 MP |
113 | /* PDC_CTLSTAT bit definitions */ |
114 | PDC_DMA_ENABLE = (1 << 7), | |
115 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 116 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 117 | |
25b93d81 | 118 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 119 | ATA_FLAG_MMIO | |
3d0a59c0 | 120 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 | 121 | |
eca25dca TH |
122 | /* ap->flags bits */ |
123 | PDC_FLAG_GEN_II = (1 << 24), | |
124 | PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ | |
125 | PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ | |
1da177e4 LT |
126 | }; |
127 | ||
1da177e4 LT |
128 | struct pdc_port_priv { |
129 | u8 *pkt; | |
130 | dma_addr_t pkt_dma; | |
131 | }; | |
132 | ||
da3dbb17 TH |
133 | static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
134 | static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 135 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
eca25dca TH |
136 | static int pdc_common_port_start(struct ata_port *ap); |
137 | static int pdc_sata_port_start(struct ata_port *ap); | |
1da177e4 | 138 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
139 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
140 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 | 141 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
724114a5 | 142 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); |
1da177e4 | 143 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 144 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
25b93d81 MP |
145 | static void pdc_freeze(struct ata_port *ap); |
146 | static void pdc_thaw(struct ata_port *ap); | |
724114a5 MP |
147 | static void pdc_pata_error_handler(struct ata_port *ap); |
148 | static void pdc_sata_error_handler(struct ata_port *ap); | |
25b93d81 | 149 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); |
724114a5 MP |
150 | static int pdc_pata_cable_detect(struct ata_port *ap); |
151 | static int pdc_sata_cable_detect(struct ata_port *ap); | |
374b1873 | 152 | |
193515d5 | 153 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
154 | .module = THIS_MODULE, |
155 | .name = DRV_NAME, | |
156 | .ioctl = ata_scsi_ioctl, | |
157 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
158 | .can_queue = ATA_DEF_QUEUE, |
159 | .this_id = ATA_SHT_THIS_ID, | |
160 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
161 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
162 | .emulated = ATA_SHT_EMULATED, | |
163 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
164 | .proc_name = DRV_NAME, | |
165 | .dma_boundary = ATA_DMA_BOUNDARY, | |
166 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 167 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 168 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
169 | }; |
170 | ||
057ace5e | 171 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
172 | .tf_load = pdc_tf_load_mmio, |
173 | .tf_read = ata_tf_read, | |
174 | .check_status = ata_check_status, | |
175 | .exec_command = pdc_exec_command_mmio, | |
176 | .dev_select = ata_std_dev_select, | |
95006188 MP |
177 | .check_atapi_dma = pdc_check_atapi_dma, |
178 | ||
179 | .qc_prep = pdc_qc_prep, | |
180 | .qc_issue = pdc_qc_issue_prot, | |
181 | .freeze = pdc_freeze, | |
182 | .thaw = pdc_thaw, | |
724114a5 | 183 | .error_handler = pdc_sata_error_handler, |
95006188 | 184 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 185 | .cable_detect = pdc_sata_cable_detect, |
0d5ff566 | 186 | .data_xfer = ata_data_xfer, |
95006188 | 187 | .irq_clear = pdc_irq_clear, |
246ce3b6 | 188 | .irq_on = ata_irq_on, |
95006188 MP |
189 | |
190 | .scr_read = pdc_sata_scr_read, | |
191 | .scr_write = pdc_sata_scr_write, | |
eca25dca | 192 | .port_start = pdc_sata_port_start, |
95006188 MP |
193 | }; |
194 | ||
195 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ | |
196 | static const struct ata_port_operations pdc_old_sata_ops = { | |
95006188 MP |
197 | .tf_load = pdc_tf_load_mmio, |
198 | .tf_read = ata_tf_read, | |
199 | .check_status = ata_check_status, | |
200 | .exec_command = pdc_exec_command_mmio, | |
201 | .dev_select = ata_std_dev_select, | |
724114a5 | 202 | .check_atapi_dma = pdc_old_sata_check_atapi_dma, |
2cba582a | 203 | |
1da177e4 LT |
204 | .qc_prep = pdc_qc_prep, |
205 | .qc_issue = pdc_qc_issue_prot, | |
25b93d81 MP |
206 | .freeze = pdc_freeze, |
207 | .thaw = pdc_thaw, | |
724114a5 | 208 | .error_handler = pdc_sata_error_handler, |
25b93d81 | 209 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 210 | .cable_detect = pdc_sata_cable_detect, |
0d5ff566 | 211 | .data_xfer = ata_data_xfer, |
1da177e4 | 212 | .irq_clear = pdc_irq_clear, |
246ce3b6 | 213 | .irq_on = ata_irq_on, |
2cba582a | 214 | |
1da177e4 LT |
215 | .scr_read = pdc_sata_scr_read, |
216 | .scr_write = pdc_sata_scr_write, | |
eca25dca | 217 | .port_start = pdc_sata_port_start, |
1da177e4 LT |
218 | }; |
219 | ||
057ace5e | 220 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
221 | .tf_load = pdc_tf_load_mmio, |
222 | .tf_read = ata_tf_read, | |
223 | .check_status = ata_check_status, | |
224 | .exec_command = pdc_exec_command_mmio, | |
225 | .dev_select = ata_std_dev_select, | |
95006188 | 226 | .check_atapi_dma = pdc_check_atapi_dma, |
2cba582a | 227 | |
2cba582a JG |
228 | .qc_prep = pdc_qc_prep, |
229 | .qc_issue = pdc_qc_issue_prot, | |
5387373b MP |
230 | .freeze = pdc_freeze, |
231 | .thaw = pdc_thaw, | |
724114a5 | 232 | .error_handler = pdc_pata_error_handler, |
540477b4 | 233 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 234 | .cable_detect = pdc_pata_cable_detect, |
0d5ff566 | 235 | .data_xfer = ata_data_xfer, |
2cba582a | 236 | .irq_clear = pdc_irq_clear, |
246ce3b6 | 237 | .irq_on = ata_irq_on, |
2cba582a | 238 | |
eca25dca | 239 | .port_start = pdc_common_port_start, |
2cba582a JG |
240 | }; |
241 | ||
98ac62de | 242 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
243 | /* board_2037x */ |
244 | { | |
eca25dca TH |
245 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
246 | PDC_FLAG_SATA_PATA, | |
1da177e4 LT |
247 | .pio_mask = 0x1f, /* pio0-4 */ |
248 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 249 | .udma_mask = ATA_UDMA6, |
95006188 | 250 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
251 | }, |
252 | ||
eca25dca TH |
253 | /* board_2037x_pata */ |
254 | { | |
255 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, | |
256 | .pio_mask = 0x1f, /* pio0-4 */ | |
257 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 258 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
259 | .port_ops = &pdc_pata_ops, |
260 | }, | |
261 | ||
1da177e4 LT |
262 | /* board_20319 */ |
263 | { | |
eca25dca TH |
264 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
265 | PDC_FLAG_4_PORTS, | |
1da177e4 LT |
266 | .pio_mask = 0x1f, /* pio0-4 */ |
267 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 268 | .udma_mask = ATA_UDMA6, |
95006188 | 269 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 270 | }, |
f497ba73 TL |
271 | |
272 | /* board_20619 */ | |
273 | { | |
eca25dca TH |
274 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
275 | PDC_FLAG_4_PORTS, | |
f497ba73 TL |
276 | .pio_mask = 0x1f, /* pio0-4 */ |
277 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 278 | .udma_mask = ATA_UDMA6, |
2cba582a | 279 | .port_ops = &pdc_pata_ops, |
f497ba73 | 280 | }, |
5a46fe89 | 281 | |
6340f019 LK |
282 | /* board_2057x */ |
283 | { | |
eca25dca TH |
284 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
285 | PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, | |
6340f019 LK |
286 | .pio_mask = 0x1f, /* pio0-4 */ |
287 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 288 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
289 | .port_ops = &pdc_sata_ops, |
290 | }, | |
291 | ||
eca25dca TH |
292 | /* board_2057x_pata */ |
293 | { | |
bb312235 | 294 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
eca25dca TH |
295 | PDC_FLAG_GEN_II, |
296 | .pio_mask = 0x1f, /* pio0-4 */ | |
297 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 298 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
299 | .port_ops = &pdc_pata_ops, |
300 | }, | |
301 | ||
6340f019 LK |
302 | /* board_40518 */ |
303 | { | |
eca25dca TH |
304 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
305 | PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, | |
6340f019 LK |
306 | .pio_mask = 0x1f, /* pio0-4 */ |
307 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 308 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
309 | .port_ops = &pdc_sata_ops, |
310 | }, | |
1da177e4 LT |
311 | }; |
312 | ||
3b7d697d | 313 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 314 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
315 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
316 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
317 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
318 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
319 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 320 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 321 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 322 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 323 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
324 | |
325 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
326 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
7f9992a2 MP |
327 | { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, |
328 | { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, | |
b2d1eee1 | 329 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
330 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
331 | ||
332 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 333 | |
1da177e4 LT |
334 | { } /* terminate list */ |
335 | }; | |
336 | ||
1da177e4 LT |
337 | static struct pci_driver pdc_ata_pci_driver = { |
338 | .name = DRV_NAME, | |
339 | .id_table = pdc_ata_pci_tbl, | |
340 | .probe = pdc_ata_init_one, | |
341 | .remove = ata_pci_remove_one, | |
342 | }; | |
343 | ||
724114a5 | 344 | static int pdc_common_port_start(struct ata_port *ap) |
1da177e4 | 345 | { |
cca3974e | 346 | struct device *dev = ap->host->dev; |
1da177e4 LT |
347 | struct pdc_port_priv *pp; |
348 | int rc; | |
349 | ||
350 | rc = ata_port_start(ap); | |
351 | if (rc) | |
352 | return rc; | |
353 | ||
24dc5f33 TH |
354 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
355 | if (!pp) | |
356 | return -ENOMEM; | |
1da177e4 | 357 | |
24dc5f33 TH |
358 | pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); |
359 | if (!pp->pkt) | |
360 | return -ENOMEM; | |
1da177e4 LT |
361 | |
362 | ap->private_data = pp; | |
363 | ||
724114a5 MP |
364 | return 0; |
365 | } | |
366 | ||
367 | static int pdc_sata_port_start(struct ata_port *ap) | |
368 | { | |
724114a5 MP |
369 | int rc; |
370 | ||
371 | rc = pdc_common_port_start(ap); | |
372 | if (rc) | |
373 | return rc; | |
374 | ||
599b7202 | 375 | /* fix up PHYMODE4 align timing */ |
eca25dca | 376 | if (ap->flags & PDC_FLAG_GEN_II) { |
59f99880 | 377 | void __iomem *mmio = ap->ioaddr.scr_addr; |
599b7202 MP |
378 | unsigned int tmp; |
379 | ||
380 | tmp = readl(mmio + 0x014); | |
381 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | |
382 | writel(tmp, mmio + 0x014); | |
383 | } | |
384 | ||
1da177e4 | 385 | return 0; |
1da177e4 LT |
386 | } |
387 | ||
1da177e4 LT |
388 | static void pdc_reset_port(struct ata_port *ap) |
389 | { | |
0d5ff566 | 390 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
391 | unsigned int i; |
392 | u32 tmp; | |
393 | ||
394 | for (i = 11; i > 0; i--) { | |
395 | tmp = readl(mmio); | |
396 | if (tmp & PDC_RESET) | |
397 | break; | |
398 | ||
399 | udelay(100); | |
400 | ||
401 | tmp |= PDC_RESET; | |
402 | writel(tmp, mmio); | |
403 | } | |
404 | ||
405 | tmp &= ~PDC_RESET; | |
406 | writel(tmp, mmio); | |
407 | readl(mmio); /* flush */ | |
408 | } | |
409 | ||
724114a5 | 410 | static int pdc_pata_cable_detect(struct ata_port *ap) |
2cba582a | 411 | { |
d3fb4e8d | 412 | u8 tmp; |
59f99880 | 413 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d | 414 | |
724114a5 MP |
415 | tmp = readb(mmio); |
416 | if (tmp & 0x01) | |
417 | return ATA_CBL_PATA40; | |
418 | return ATA_CBL_PATA80; | |
419 | } | |
420 | ||
421 | static int pdc_sata_cable_detect(struct ata_port *ap) | |
422 | { | |
e2a9752a | 423 | return ATA_CBL_SATA; |
d3fb4e8d | 424 | } |
2cba582a | 425 | |
da3dbb17 | 426 | static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 427 | { |
724114a5 | 428 | if (sc_reg > SCR_CONTROL) |
da3dbb17 TH |
429 | return -EINVAL; |
430 | *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
431 | return 0; | |
1da177e4 LT |
432 | } |
433 | ||
da3dbb17 | 434 | static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 435 | { |
724114a5 | 436 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 437 | return -EINVAL; |
0d5ff566 | 438 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 439 | return 0; |
1da177e4 LT |
440 | } |
441 | ||
fba6edbd | 442 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
95006188 | 443 | { |
4113bb6b MP |
444 | struct ata_port *ap = qc->ap; |
445 | dma_addr_t sg_table = ap->prd_dma; | |
446 | unsigned int cdb_len = qc->dev->cdb_len; | |
447 | u8 *cdb = qc->cdb; | |
448 | struct pdc_port_priv *pp = ap->private_data; | |
449 | u8 *buf = pp->pkt; | |
95006188 | 450 | u32 *buf32 = (u32 *) buf; |
4113bb6b | 451 | unsigned int dev_sel, feature, nbytes; |
95006188 MP |
452 | |
453 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
454 | * and seq id (byte 2) | |
455 | */ | |
fba6edbd MP |
456 | switch (qc->tf.protocol) { |
457 | case ATA_PROT_ATAPI_DMA: | |
458 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | |
459 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
460 | else | |
461 | buf32[0] = 0; | |
462 | break; | |
463 | case ATA_PROT_ATAPI_NODATA: | |
464 | buf32[0] = cpu_to_le32(PDC_PKT_NODATA); | |
465 | break; | |
466 | default: | |
467 | BUG(); | |
468 | break; | |
469 | } | |
95006188 MP |
470 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ |
471 | buf32[2] = 0; /* no next-packet */ | |
472 | ||
4113bb6b | 473 | /* select drive */ |
936fd732 | 474 | if (sata_scr_valid(&ap->link)) { |
4113bb6b MP |
475 | dev_sel = PDC_DEVICE_SATA; |
476 | } else { | |
477 | dev_sel = ATA_DEVICE_OBS; | |
478 | if (qc->dev->devno != 0) | |
479 | dev_sel |= ATA_DEV1; | |
480 | } | |
481 | buf[12] = (1 << 5) | ATA_REG_DEVICE; | |
482 | buf[13] = dev_sel; | |
483 | buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; | |
484 | buf[15] = dev_sel; /* once more, waiting for BSY to clear */ | |
485 | ||
486 | buf[16] = (1 << 5) | ATA_REG_NSECT; | |
487 | buf[17] = 0x00; | |
488 | buf[18] = (1 << 5) | ATA_REG_LBAL; | |
489 | buf[19] = 0x00; | |
490 | ||
491 | /* set feature and byte counter registers */ | |
492 | if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) { | |
493 | feature = PDC_FEATURE_ATAPI_PIO; | |
494 | /* set byte counter register to real transfer byte count */ | |
495 | nbytes = qc->nbytes; | |
4113bb6b MP |
496 | if (nbytes > 0xffff) |
497 | nbytes = 0xffff; | |
498 | } else { | |
499 | feature = PDC_FEATURE_ATAPI_DMA; | |
500 | /* set byte counter register to 0 */ | |
501 | nbytes = 0; | |
502 | } | |
503 | buf[20] = (1 << 5) | ATA_REG_FEATURE; | |
504 | buf[21] = feature; | |
505 | buf[22] = (1 << 5) | ATA_REG_BYTEL; | |
506 | buf[23] = nbytes & 0xFF; | |
507 | buf[24] = (1 << 5) | ATA_REG_BYTEH; | |
508 | buf[25] = (nbytes >> 8) & 0xFF; | |
509 | ||
510 | /* send ATAPI packet command 0xA0 */ | |
511 | buf[26] = (1 << 5) | ATA_REG_CMD; | |
512 | buf[27] = ATA_CMD_PACKET; | |
513 | ||
514 | /* select drive and check DRQ */ | |
515 | buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; | |
516 | buf[29] = dev_sel; | |
517 | ||
95006188 MP |
518 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ |
519 | BUG_ON(cdb_len & ~0x1E); | |
520 | ||
4113bb6b MP |
521 | /* append the CDB as the final part */ |
522 | buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
523 | memcpy(buf+31, cdb, cdb_len); | |
95006188 MP |
524 | } |
525 | ||
1da177e4 LT |
526 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
527 | { | |
528 | struct pdc_port_priv *pp = qc->ap->private_data; | |
529 | unsigned int i; | |
530 | ||
531 | VPRINTK("ENTER\n"); | |
532 | ||
533 | switch (qc->tf.protocol) { | |
534 | case ATA_PROT_DMA: | |
535 | ata_qc_prep(qc); | |
536 | /* fall through */ | |
537 | ||
538 | case ATA_PROT_NODATA: | |
539 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
540 | qc->dev->devno, pp->pkt); | |
541 | ||
542 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
543 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
544 | else | |
545 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
546 | ||
547 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
548 | break; | |
549 | ||
95006188 | 550 | case ATA_PROT_ATAPI: |
95006188 MP |
551 | ata_qc_prep(qc); |
552 | break; | |
553 | ||
554 | case ATA_PROT_ATAPI_DMA: | |
555 | ata_qc_prep(qc); | |
fba6edbd MP |
556 | /*FALLTHROUGH*/ |
557 | case ATA_PROT_ATAPI_NODATA: | |
558 | pdc_atapi_pkt(qc); | |
95006188 MP |
559 | break; |
560 | ||
1da177e4 LT |
561 | default: |
562 | break; | |
563 | } | |
564 | } | |
565 | ||
25b93d81 MP |
566 | static void pdc_freeze(struct ata_port *ap) |
567 | { | |
59f99880 | 568 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
569 | u32 tmp; |
570 | ||
571 | tmp = readl(mmio + PDC_CTLSTAT); | |
572 | tmp |= PDC_IRQ_DISABLE; | |
573 | tmp &= ~PDC_DMA_ENABLE; | |
574 | writel(tmp, mmio + PDC_CTLSTAT); | |
575 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
576 | } | |
577 | ||
578 | static void pdc_thaw(struct ata_port *ap) | |
579 | { | |
59f99880 | 580 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
581 | u32 tmp; |
582 | ||
583 | /* clear IRQ */ | |
584 | readl(mmio + PDC_INT_SEQMASK); | |
585 | ||
586 | /* turn IRQ back on */ | |
587 | tmp = readl(mmio + PDC_CTLSTAT); | |
588 | tmp &= ~PDC_IRQ_DISABLE; | |
589 | writel(tmp, mmio + PDC_CTLSTAT); | |
590 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
591 | } | |
592 | ||
724114a5 | 593 | static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset) |
25b93d81 | 594 | { |
25b93d81 MP |
595 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) |
596 | pdc_reset_port(ap); | |
597 | ||
25b93d81 | 598 | /* perform recovery */ |
e2a9752a | 599 | ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, |
25b93d81 MP |
600 | ata_std_postreset); |
601 | } | |
602 | ||
724114a5 MP |
603 | static void pdc_pata_error_handler(struct ata_port *ap) |
604 | { | |
605 | pdc_common_error_handler(ap, NULL); | |
606 | } | |
607 | ||
608 | static void pdc_sata_error_handler(struct ata_port *ap) | |
609 | { | |
610 | pdc_common_error_handler(ap, sata_std_hardreset); | |
611 | } | |
612 | ||
25b93d81 MP |
613 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) |
614 | { | |
615 | struct ata_port *ap = qc->ap; | |
616 | ||
25b93d81 | 617 | /* make DMA engine forget about the failed command */ |
a51d644a | 618 | if (qc->flags & ATA_QCFLAG_FAILED) |
25b93d81 MP |
619 | pdc_reset_port(ap); |
620 | } | |
621 | ||
176efb05 MP |
622 | static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, |
623 | u32 port_status, u32 err_mask) | |
624 | { | |
9af5c9c9 | 625 | struct ata_eh_info *ehi = &ap->link.eh_info; |
176efb05 MP |
626 | unsigned int ac_err_mask = 0; |
627 | ||
628 | ata_ehi_clear_desc(ehi); | |
629 | ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); | |
630 | port_status &= err_mask; | |
631 | ||
632 | if (port_status & PDC_DRIVE_ERR) | |
633 | ac_err_mask |= AC_ERR_DEV; | |
634 | if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) | |
635 | ac_err_mask |= AC_ERR_HSM; | |
636 | if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) | |
637 | ac_err_mask |= AC_ERR_ATA_BUS; | |
638 | if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR | |
639 | | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) | |
640 | ac_err_mask |= AC_ERR_HOST_BUS; | |
641 | ||
936fd732 | 642 | if (sata_scr_valid(&ap->link)) { |
da3dbb17 TH |
643 | u32 serror; |
644 | ||
645 | pdc_sata_scr_read(ap, SCR_ERROR, &serror); | |
646 | ehi->serror |= serror; | |
647 | } | |
ce2d3abc | 648 | |
176efb05 | 649 | qc->err_mask |= ac_err_mask; |
ce2d3abc MP |
650 | |
651 | pdc_reset_port(ap); | |
8ffcfd9d MP |
652 | |
653 | ata_port_abort(ap); | |
176efb05 MP |
654 | } |
655 | ||
d0e58031 MP |
656 | static inline unsigned int pdc_host_intr(struct ata_port *ap, |
657 | struct ata_queued_cmd *qc) | |
1da177e4 | 658 | { |
a22e2eb0 | 659 | unsigned int handled = 0; |
176efb05 | 660 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
176efb05 MP |
661 | u32 port_status, err_mask; |
662 | ||
663 | err_mask = PDC_ERR_MASK; | |
eca25dca | 664 | if (ap->flags & PDC_FLAG_GEN_II) |
176efb05 MP |
665 | err_mask &= ~PDC1_ERR_MASK; |
666 | else | |
667 | err_mask &= ~PDC2_ERR_MASK; | |
668 | port_status = readl(port_mmio + PDC_GLOBAL_CTL); | |
669 | if (unlikely(port_status & err_mask)) { | |
670 | pdc_error_intr(ap, qc, port_status, err_mask); | |
671 | return 1; | |
1da177e4 LT |
672 | } |
673 | ||
674 | switch (qc->tf.protocol) { | |
675 | case ATA_PROT_DMA: | |
676 | case ATA_PROT_NODATA: | |
95006188 | 677 | case ATA_PROT_ATAPI_DMA: |
fba6edbd | 678 | case ATA_PROT_ATAPI_NODATA: |
a22e2eb0 AL |
679 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
680 | ata_qc_complete(qc); | |
1da177e4 LT |
681 | handled = 1; |
682 | break; | |
683 | ||
d0e58031 | 684 | default: |
ee500aab AL |
685 | ap->stats.idle_irq++; |
686 | break; | |
d0e58031 | 687 | } |
1da177e4 | 688 | |
ee500aab | 689 | return handled; |
1da177e4 LT |
690 | } |
691 | ||
692 | static void pdc_irq_clear(struct ata_port *ap) | |
693 | { | |
cca3974e | 694 | struct ata_host *host = ap->host; |
0d5ff566 | 695 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
696 | |
697 | readl(mmio + PDC_INT_SEQMASK); | |
698 | } | |
699 | ||
5796d1c4 | 700 | static int pdc_is_sataii_tx4(unsigned long flags) |
d0e58031 MP |
701 | { |
702 | const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; | |
703 | return (flags & mask) == mask; | |
704 | } | |
705 | ||
5796d1c4 JG |
706 | static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, |
707 | int is_sataii_tx4) | |
d0e58031 MP |
708 | { |
709 | static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; | |
710 | return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; | |
711 | } | |
712 | ||
5796d1c4 | 713 | static irqreturn_t pdc_interrupt(int irq, void *dev_instance) |
1da177e4 | 714 | { |
cca3974e | 715 | struct ata_host *host = dev_instance; |
1da177e4 LT |
716 | struct ata_port *ap; |
717 | u32 mask = 0; | |
718 | unsigned int i, tmp; | |
719 | unsigned int handled = 0; | |
ea6ba10b | 720 | void __iomem *mmio_base; |
a77720ad MP |
721 | unsigned int hotplug_offset, ata_no; |
722 | u32 hotplug_status; | |
723 | int is_sataii_tx4; | |
1da177e4 LT |
724 | |
725 | VPRINTK("ENTER\n"); | |
726 | ||
0d5ff566 | 727 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
1da177e4 LT |
728 | VPRINTK("QUICK EXIT\n"); |
729 | return IRQ_NONE; | |
730 | } | |
731 | ||
0d5ff566 | 732 | mmio_base = host->iomap[PDC_MMIO_BAR]; |
1da177e4 | 733 | |
a77720ad MP |
734 | /* read and clear hotplug flags for all ports */ |
735 | if (host->ports[0]->flags & PDC_FLAG_GEN_II) | |
736 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
737 | else | |
738 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
739 | hotplug_status = readl(mmio_base + hotplug_offset); | |
740 | if (hotplug_status & 0xff) | |
741 | writel(hotplug_status | 0xff, mmio_base + hotplug_offset); | |
742 | hotplug_status &= 0xff; /* clear uninteresting bits */ | |
743 | ||
1da177e4 LT |
744 | /* reading should also clear interrupts */ |
745 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
746 | ||
a77720ad | 747 | if (mask == 0xffffffff && hotplug_status == 0) { |
1da177e4 LT |
748 | VPRINTK("QUICK EXIT 2\n"); |
749 | return IRQ_NONE; | |
750 | } | |
6340f019 | 751 | |
cca3974e | 752 | spin_lock(&host->lock); |
6340f019 | 753 | |
1da177e4 | 754 | mask &= 0xffff; /* only 16 tags possible */ |
a77720ad | 755 | if (mask == 0 && hotplug_status == 0) { |
1da177e4 | 756 | VPRINTK("QUICK EXIT 3\n"); |
6340f019 | 757 | goto done_irq; |
1da177e4 LT |
758 | } |
759 | ||
1da177e4 LT |
760 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
761 | ||
a77720ad MP |
762 | is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); |
763 | ||
cca3974e | 764 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 765 | VPRINTK("port %u\n", i); |
cca3974e | 766 | ap = host->ports[i]; |
a77720ad MP |
767 | |
768 | /* check for a plug or unplug event */ | |
769 | ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); | |
770 | tmp = hotplug_status & (0x11 << ata_no); | |
771 | if (tmp && ap && | |
772 | !(ap->flags & ATA_FLAG_DISABLED)) { | |
9af5c9c9 | 773 | struct ata_eh_info *ehi = &ap->link.eh_info; |
a77720ad MP |
774 | ata_ehi_clear_desc(ehi); |
775 | ata_ehi_hotplugged(ehi); | |
776 | ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); | |
777 | ata_port_freeze(ap); | |
778 | ++handled; | |
779 | continue; | |
780 | } | |
781 | ||
782 | /* check for a packet interrupt */ | |
1da177e4 | 783 | tmp = mask & (1 << (i + 1)); |
c1389503 | 784 | if (tmp && ap && |
029f5468 | 785 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
786 | struct ata_queued_cmd *qc; |
787 | ||
9af5c9c9 | 788 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
e50362ec | 789 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
790 | handled += pdc_host_intr(ap, qc); |
791 | } | |
792 | } | |
793 | ||
1da177e4 LT |
794 | VPRINTK("EXIT\n"); |
795 | ||
6340f019 | 796 | done_irq: |
cca3974e | 797 | spin_unlock(&host->lock); |
1da177e4 LT |
798 | return IRQ_RETVAL(handled); |
799 | } | |
800 | ||
801 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
802 | { | |
803 | struct ata_port *ap = qc->ap; | |
804 | struct pdc_port_priv *pp = ap->private_data; | |
0d5ff566 | 805 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
806 | unsigned int port_no = ap->port_no; |
807 | u8 seq = (u8) (port_no + 1); | |
808 | ||
809 | VPRINTK("ENTER, ap %p\n", ap); | |
810 | ||
0d5ff566 TH |
811 | writel(0x00000001, mmio + (seq * 4)); |
812 | readl(mmio + (seq * 4)); /* flush */ | |
1da177e4 LT |
813 | |
814 | pp->pkt[2] = seq; | |
815 | wmb(); /* flush PRD, pkt writes */ | |
0d5ff566 TH |
816 | writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
817 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
818 | } |
819 | ||
9a3d9eb0 | 820 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
821 | { |
822 | switch (qc->tf.protocol) { | |
fba6edbd MP |
823 | case ATA_PROT_ATAPI_NODATA: |
824 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
825 | break; | |
826 | /*FALLTHROUGH*/ | |
51b94d2a TH |
827 | case ATA_PROT_NODATA: |
828 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
829 | break; | |
830 | /*FALLTHROUGH*/ | |
95006188 | 831 | case ATA_PROT_ATAPI_DMA: |
1da177e4 | 832 | case ATA_PROT_DMA: |
1da177e4 LT |
833 | pdc_packet_start(qc); |
834 | return 0; | |
835 | ||
1da177e4 LT |
836 | default: |
837 | break; | |
838 | } | |
839 | ||
840 | return ata_qc_issue_prot(qc); | |
841 | } | |
842 | ||
057ace5e | 843 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 | 844 | { |
5796d1c4 JG |
845 | WARN_ON(tf->protocol == ATA_PROT_DMA || |
846 | tf->protocol == ATA_PROT_ATAPI_DMA); | |
1da177e4 LT |
847 | ata_tf_load(ap, tf); |
848 | } | |
849 | ||
5796d1c4 JG |
850 | static void pdc_exec_command_mmio(struct ata_port *ap, |
851 | const struct ata_taskfile *tf) | |
1da177e4 | 852 | { |
5796d1c4 JG |
853 | WARN_ON(tf->protocol == ATA_PROT_DMA || |
854 | tf->protocol == ATA_PROT_ATAPI_DMA); | |
1da177e4 LT |
855 | ata_exec_command(ap, tf); |
856 | } | |
857 | ||
95006188 MP |
858 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
859 | { | |
860 | u8 *scsicmd = qc->scsicmd->cmnd; | |
861 | int pio = 1; /* atapi dma off by default */ | |
862 | ||
863 | /* Whitelist commands that may use DMA. */ | |
864 | switch (scsicmd[0]) { | |
865 | case WRITE_12: | |
866 | case WRITE_10: | |
867 | case WRITE_6: | |
868 | case READ_12: | |
869 | case READ_10: | |
870 | case READ_6: | |
871 | case 0xad: /* READ_DVD_STRUCTURE */ | |
872 | case 0xbe: /* READ_CD */ | |
873 | pio = 0; | |
874 | } | |
875 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
876 | if (scsicmd[0] == WRITE_10) { | |
5796d1c4 JG |
877 | unsigned int lba = |
878 | (scsicmd[2] << 24) | | |
879 | (scsicmd[3] << 16) | | |
880 | (scsicmd[4] << 8) | | |
881 | scsicmd[5]; | |
95006188 MP |
882 | if (lba >= 0xFFFF4FA2) |
883 | pio = 1; | |
884 | } | |
885 | return pio; | |
886 | } | |
887 | ||
724114a5 | 888 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
95006188 | 889 | { |
95006188 | 890 | /* First generation chips cannot use ATAPI DMA on SATA ports */ |
724114a5 | 891 | return 1; |
95006188 | 892 | } |
1da177e4 | 893 | |
eca25dca TH |
894 | static void pdc_ata_setup_port(struct ata_port *ap, |
895 | void __iomem *base, void __iomem *scr_addr) | |
1da177e4 | 896 | { |
eca25dca TH |
897 | ap->ioaddr.cmd_addr = base; |
898 | ap->ioaddr.data_addr = base; | |
899 | ap->ioaddr.feature_addr = | |
900 | ap->ioaddr.error_addr = base + 0x4; | |
901 | ap->ioaddr.nsect_addr = base + 0x8; | |
902 | ap->ioaddr.lbal_addr = base + 0xc; | |
903 | ap->ioaddr.lbam_addr = base + 0x10; | |
904 | ap->ioaddr.lbah_addr = base + 0x14; | |
905 | ap->ioaddr.device_addr = base + 0x18; | |
906 | ap->ioaddr.command_addr = | |
907 | ap->ioaddr.status_addr = base + 0x1c; | |
908 | ap->ioaddr.altstatus_addr = | |
909 | ap->ioaddr.ctl_addr = base + 0x38; | |
910 | ap->ioaddr.scr_addr = scr_addr; | |
1da177e4 LT |
911 | } |
912 | ||
eca25dca | 913 | static void pdc_host_init(struct ata_host *host) |
1da177e4 | 914 | { |
eca25dca TH |
915 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
916 | int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; | |
d324d462 | 917 | int hotplug_offset; |
1da177e4 LT |
918 | u32 tmp; |
919 | ||
eca25dca | 920 | if (is_gen2) |
d324d462 MP |
921 | hotplug_offset = PDC2_SATA_PLUG_CSR; |
922 | else | |
923 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
924 | ||
1da177e4 LT |
925 | /* |
926 | * Except for the hotplug stuff, this is voodoo from the | |
927 | * Promise driver. Label this entire section | |
928 | * "TODO: figure out why we do this" | |
929 | */ | |
930 | ||
b2d1eee1 | 931 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 932 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 | 933 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
eca25dca | 934 | if (!is_gen2) |
b2d1eee1 | 935 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ |
1da177e4 LT |
936 | writel(tmp, mmio + PDC_FLASH_CTL); |
937 | ||
938 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
939 | tmp = readl(mmio + hotplug_offset); |
940 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 | 941 | |
a77720ad | 942 | /* unmask plug/unplug ints */ |
6340f019 | 943 | tmp = readl(mmio + hotplug_offset); |
a77720ad | 944 | writel(tmp & ~0xff0000, mmio + hotplug_offset); |
1da177e4 | 945 | |
b2d1eee1 | 946 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
eca25dca | 947 | if (is_gen2) |
b2d1eee1 MP |
948 | return; |
949 | ||
1da177e4 LT |
950 | /* reduce TBG clock to 133 Mhz. */ |
951 | tmp = readl(mmio + PDC_TBG_MODE); | |
952 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
953 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
954 | writel(tmp, mmio + PDC_TBG_MODE); | |
955 | ||
956 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
957 | msleep(10); | |
958 | ||
959 | /* adjust slew rate control register. */ | |
960 | tmp = readl(mmio + PDC_SLEW_CTL); | |
961 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
962 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
963 | writel(tmp, mmio + PDC_SLEW_CTL); | |
964 | } | |
965 | ||
5796d1c4 JG |
966 | static int pdc_ata_init_one(struct pci_dev *pdev, |
967 | const struct pci_device_id *ent) | |
1da177e4 LT |
968 | { |
969 | static int printed_version; | |
eca25dca TH |
970 | const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; |
971 | const struct ata_port_info *ppi[PDC_MAX_PORTS]; | |
972 | struct ata_host *host; | |
0d5ff566 | 973 | void __iomem *base; |
eca25dca | 974 | int n_ports, i, rc; |
5ac2fe57 | 975 | int is_sataii_tx4; |
1da177e4 LT |
976 | |
977 | if (!printed_version++) | |
a9524a76 | 978 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 979 | |
eca25dca | 980 | /* enable and acquire resources */ |
24dc5f33 | 981 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
982 | if (rc) |
983 | return rc; | |
984 | ||
0d5ff566 TH |
985 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
986 | if (rc == -EBUSY) | |
24dc5f33 | 987 | pcim_pin_device(pdev); |
0d5ff566 | 988 | if (rc) |
24dc5f33 | 989 | return rc; |
eca25dca | 990 | base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; |
1da177e4 | 991 | |
eca25dca TH |
992 | /* determine port configuration and setup host */ |
993 | n_ports = 2; | |
994 | if (pi->flags & PDC_FLAG_4_PORTS) | |
995 | n_ports = 4; | |
996 | for (i = 0; i < n_ports; i++) | |
997 | ppi[i] = pi; | |
1da177e4 | 998 | |
eca25dca TH |
999 | if (pi->flags & PDC_FLAG_SATA_PATA) { |
1000 | u8 tmp = readb(base + PDC_FLASH_CTL+1); | |
d0e58031 | 1001 | if (!(tmp & 0x80)) |
eca25dca | 1002 | ppi[n_ports++] = pi + 1; |
eca25dca | 1003 | } |
1da177e4 | 1004 | |
eca25dca TH |
1005 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
1006 | if (!host) { | |
1007 | dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); | |
24dc5f33 | 1008 | return -ENOMEM; |
1da177e4 | 1009 | } |
eca25dca | 1010 | host->iomap = pcim_iomap_table(pdev); |
1da177e4 | 1011 | |
d0e58031 | 1012 | is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); |
5ac2fe57 | 1013 | for (i = 0; i < host->n_ports; i++) { |
cbcdd875 | 1014 | struct ata_port *ap = host->ports[i]; |
d0e58031 | 1015 | unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); |
cbcdd875 TH |
1016 | unsigned int port_offset = 0x200 + ata_no * 0x80; |
1017 | unsigned int scr_offset = 0x400 + ata_no * 0x100; | |
1018 | ||
1019 | pdc_ata_setup_port(ap, base + port_offset, base + scr_offset); | |
1020 | ||
1021 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); | |
1022 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port"); | |
5ac2fe57 | 1023 | } |
1da177e4 LT |
1024 | |
1025 | /* initialize adapter */ | |
eca25dca | 1026 | pdc_host_init(host); |
1da177e4 | 1027 | |
eca25dca TH |
1028 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1029 | if (rc) | |
1030 | return rc; | |
1031 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1032 | if (rc) | |
1033 | return rc; | |
1da177e4 | 1034 | |
eca25dca TH |
1035 | /* start host, request IRQ and attach */ |
1036 | pci_set_master(pdev); | |
1037 | return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, | |
1038 | &pdc_ata_sht); | |
1da177e4 LT |
1039 | } |
1040 | ||
1da177e4 LT |
1041 | static int __init pdc_ata_init(void) |
1042 | { | |
b7887196 | 1043 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1044 | } |
1045 | ||
1da177e4 LT |
1046 | static void __exit pdc_ata_exit(void) |
1047 | { | |
1048 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1049 | } | |
1050 | ||
1da177e4 | 1051 | MODULE_AUTHOR("Jeff Garzik"); |
f497ba73 | 1052 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1053 | MODULE_LICENSE("GPL"); |
1054 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1055 | MODULE_VERSION(DRV_VERSION); | |
1056 | ||
1057 | module_init(pdc_ata_init); | |
1058 | module_exit(pdc_ata_exit); |