[deliverable/linux.git] / drivers / ata / sata_sis.c

/*
 *  sata_sis.c - Silicon Integrated Systems SATA
 *
 *  Maintained by:  Uwe Koziolek
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 Uwe Koziolek
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include "sis.h"

#define DRV_NAME	"sata_sis"
#define DRV_VERSION	"0.8"

enum {
	sis_180			= 0,
	SIS_SCR_PCI_BAR		= 5,

	/* PCI configuration registers */
	SIS_GENCTL		= 0x54, /* IDE General Control register */
	SIS_SCR_BASE		= 0xc0, /* sata0 phy SCR registers */
	SIS180_SATA1_OFS	= 0x10, /* offset from sata0->sata1 phy regs */
	SIS182_SATA1_OFS	= 0x20, /* offset from sata0->sata1 phy regs */
	SIS_PMR			= 0x90, /* port mapping register */
	SIS_PMR_COMBINED	= 0x30,

	/* random bits */
	SIS_FLAG_CFGSCR		= (1 << 30), /* host flag: SCRs via PCI cfg */

	GENCTL_IOMAPPED_SCR	= (1 << 26), /* if set, SCRs are in IO space */
};

static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);

static const struct pci_device_id sis_pci_tbl[] = {
	{ PCI_VDEVICE(SI, 0x0180), sis_180 },		/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0181), sis_180 },		/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0182), sis_180 },		/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x0183), sis_180 },		/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x1182), sis_180 },		/* SiS 966/966L */
	{ PCI_VDEVICE(SI, 0x1183), sis_180 },		/* SiS 966/966L */

	{ }	/* terminate list */
};

static struct pci_driver sis_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sis_pci_tbl,
	.probe			= sis_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template sis_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= ATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations sis_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,
	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
	.scr_read		= sis_scr_read,
	.scr_write		= sis_scr_write,
	.port_start		= ata_port_start,
};

static const struct ata_port_info sis_port_info = {
	.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x7,
	.udma_mask	= 0x7f,
	.port_ops	= &sis_ops,
};

MODULE_AUTHOR("Uwe Koziolek");
MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
	u8 pmr;

	if (ap->port_no)  {
		switch (pdev->device) {
			case 0x0180:
			case 0x0181:
				pci_read_config_byte(pdev, SIS_PMR, &pmr);
				if ((pmr & SIS_PMR_COMBINED) == 0)
					addr += SIS180_SATA1_OFS;
				break;

			case 0x0182:
			case 0x0183:
			case 0x1182:
			case 0x1183:
				addr += SIS182_SATA1_OFS;
				break;
		}
	}
	return addr;
}

static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
	u32 val, val2 = 0;
	u8 pmr;

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return 0xffffffff;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	pci_read_config_dword(pdev, cfg_addr, &val);

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
	    (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
		pci_read_config_dword(pdev, cfg_addr+0x10, &val2);

	return (val|val2) &  0xfffffffb; /* avoid problems with powerdowned ports */
}

static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
	u8 pmr;

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	pci_write_config_dword(pdev, cfg_addr, val);

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
	    (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
		pci_write_config_dword(pdev, cfg_addr+0x10, val);
}

static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 val, val2 = 0;
	u8 pmr;

	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_read(ap, sc_reg);

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));

	if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
	    (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
		val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);

	return (val | val2) &  0xfffffffb;
}

static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 pmr;

	if (sc_reg > SCR_CONTROL)
		return;

	pci_read_config_byte(pdev, SIS_PMR, &pmr);

	if (ap->flags & SIS_FLAG_CFGSCR)
		sis_scr_cfg_write(ap, sc_reg, val);
	else {
		iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
		if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
		    (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
			iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
	}
}

static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_port_info pi = sis_port_info;
	const struct ata_port_info *ppi[] = { &pi, &pi };
	struct ata_host *host;
	u32 genctl, val;
	u8 pmr;
	u8 port2_start = 0x20;
	int rc;

	if (!printed_version++)
		dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check and see if the SCRs are in IO space or PCI cfg space */
	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
		pi.flags |= SIS_FLAG_CFGSCR;

	/* if hardware thinks SCRs are in IO space, but there are
	 * no IO resources assigned, change to PCI cfg space.
	 */
	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
	    ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
	     (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
		genctl &= ~GENCTL_IOMAPPED_SCR;
		pci_write_config_dword(pdev, SIS_GENCTL, genctl);
		pi.flags |= SIS_FLAG_CFGSCR;
	}

	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	switch (ent->device) {
	case 0x0180:
	case 0x0181:

		/* The PATA-handling is provided by pata_sis */
		switch (pmr & 0x30) {
		case 0x10:
			ppi[1] = &sis_info133;
			break;

		case 0x30:
			ppi[0] = &sis_info133;
			break;
		}
		if ((pmr & SIS_PMR_COMBINED) == 0) {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 180/181/964 chipset in SATA mode\n");
			port2_start = 64;
		} else {
			dev_printk(KERN_INFO, &pdev->dev,
				   "Detected SiS 180/181 chipset in combined mode\n");
			port2_start=0;
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		}
		break;

	case 0x0182:
	case 0x0183:
		pci_read_config_dword ( pdev, 0x6C, &val);
		if (val & (1L << 31)) {
			dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		} else {
			dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
		}
		break;

	case 0x1182:
	case 0x1183:
		pci_read_config_dword(pdev, 0x64, &val);
		if (val & 0x10000000) {
			dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
		} else {
			dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		}
		break;
	}

	rc = ata_pci_prepare_native_host(pdev, ppi, &host);
	if (rc)
		return rc;

	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
		void __iomem *mmio;

		rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
		if (rc)
			return rc;
		mmio = host->iomap[SIS_SCR_PCI_BAR];

		host->ports[0]->ioaddr.scr_addr = mmio;
		host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
	}

	pci_set_master(pdev);
	pci_intx(pdev, 1);
	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
				 &sis_sht);
}

static int __init sis_init(void)
{
	return pci_register_driver(&sis_pci_driver);
}

static void __exit sis_exit(void)
{
	pci_unregister_driver(&sis_pci_driver);
}

module_init(sis_init);
module_exit(sis_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sis.c - Silicon Integrated Systems SATA
	3	*
	4	* Maintained by: Uwe Koziolek
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 Uwe Koziolek
	9	*
af36d7f0 JG	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; see the file COPYING. If not, write to
	23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*
	25	*
	26	* libata documentation is available via 'make {ps\|pdf}docs',
	27	* as Documentation/DocBook/libata.*
	28	*
	29	* Hardware documentation available under NDA.
1da177e4 LT	30	*
	31	*/
	32
1da177e4 LT	33	#include <linux/kernel.h>
	34	#include <linux/module.h>
	35	#include <linux/pci.h>
	36	#include <linux/init.h>
	37	#include <linux/blkdev.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
a9524a76	40	#include <linux/device.h>
1da177e4 LT	41	#include <scsi/scsi_host.h>
1da177e4 LT	42	#include <linux/libata.h>
4bb64fb9	43	#include "sis.h"
1da177e4 LT	44
1da177e4 LT	45	#define DRV_NAME "sata_sis"
8bc3fc47	46	#define DRV_VERSION "0.8"
1da177e4 LT	47
	48	enum {
	49	sis_180 = 0,
	50	SIS_SCR_PCI_BAR = 5,
	51
	52	/* PCI configuration registers */
	53	SIS_GENCTL = 0x54, /* IDE General Control register */
	54	SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
f2c853bc AP	55	SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
	56	SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
	57	SIS_PMR = 0x90, /* port mapping register */
8add7885	58	SIS_PMR_COMBINED = 0x30,
1da177e4 LT	59
	60	/* random bits */
	61	SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
	62
	63	GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
	64	};
	65
	66	static int sis_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	67	static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
	68	static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	69
3b7d697d	70	static const struct pci_device_id sis_pci_tbl[] = {
3f3e7313 UK	71	{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
	72	{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
	73	{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
	74	{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
	75	{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */
	76	{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */
2d2744fc	77
1da177e4 LT	78	{ } /* terminate list */
	79	};
	80
1da177e4 LT	81	static struct pci_driver sis_pci_driver = {
	82	.name = DRV_NAME,
	83	.id_table = sis_pci_tbl,
	84	.probe = sis_init_one,
	85	.remove = ata_pci_remove_one,
	86	};
	87
193515d5	88	static struct scsi_host_template sis_sht = {
1da177e4 LT	89	.module = THIS_MODULE,
	90	.name = DRV_NAME,
	91	.ioctl = ata_scsi_ioctl,
	92	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	93	.can_queue = ATA_DEF_QUEUE,
	94	.this_id = ATA_SHT_THIS_ID,
	95	.sg_tablesize = ATA_MAX_PRD,
1da177e4 LT	96	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	97	.emulated = ATA_SHT_EMULATED,
	98	.use_clustering = ATA_SHT_USE_CLUSTERING,
	99	.proc_name = DRV_NAME,
	100	.dma_boundary = ATA_DMA_BOUNDARY,
	101	.slave_configure = ata_scsi_slave_config,
ccf68c34	102	.slave_destroy = ata_scsi_slave_destroy,
1da177e4	103	.bios_param = ata_std_bios_param,
1da177e4 LT	104	};
1da177e4 LT	105
057ace5e	106	static const struct ata_port_operations sis_ops = {
1da177e4 LT	107	.port_disable = ata_port_disable,
	108	.tf_load = ata_tf_load,
	109	.tf_read = ata_tf_read,
	110	.check_status = ata_check_status,
	111	.exec_command = ata_exec_command,
	112	.dev_select = ata_std_dev_select,
1da177e4 LT	113	.bmdma_setup = ata_bmdma_setup,
	114	.bmdma_start = ata_bmdma_start,
	115	.bmdma_stop = ata_bmdma_stop,
	116	.bmdma_status = ata_bmdma_status,
	117	.qc_prep = ata_qc_prep,
	118	.qc_issue = ata_qc_issue_prot,
0d5ff566	119	.data_xfer = ata_data_xfer,
d7a80dad TH	120	.freeze = ata_bmdma_freeze,
	121	.thaw = ata_bmdma_thaw,
	122	.error_handler = ata_bmdma_error_handler,
	123	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4	124	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	125	.irq_on = ata_irq_on,
246ce3b6 AI	126	.irq_ack = ata_irq_ack,
1da177e4 LT	127	.scr_read = sis_scr_read,
	128	.scr_write = sis_scr_write,
	129	.port_start = ata_port_start,
1da177e4 LT	130	};
1da177e4 LT	131
1626aeb8	132	static const struct ata_port_info sis_port_info = {
cca3974e	133	.flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY,
1da177e4 LT	134	.pio_mask = 0x1f,
	135	.mwdma_mask = 0x7,
	136	.udma_mask = 0x7f,
	137	.port_ops = &sis_ops,
	138	};
	139
1da177e4 LT	140	MODULE_AUTHOR("Uwe Koziolek");
	141	MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
	142	MODULE_LICENSE("GPL");
	143	MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
	144	MODULE_VERSION(DRV_VERSION);
	145
9b14dec5	146	static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
1da177e4	147	{
9b14dec5	148	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4	149	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
9b14dec5	150	u8 pmr;
1da177e4	151
9b14dec5	152	if (ap->port_no) {
3f3e7313 UK	153	switch (pdev->device) {
	154	case 0x0180:
	155	case 0x0181:
9b14dec5 A	156	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	157	if ((pmr & SIS_PMR_COMBINED) == 0)
	158	addr += SIS180_SATA1_OFS;
3f3e7313 UK	159	break;
	160
	161	case 0x0182:
	162	case 0x0183:
	163	case 0x1182:
	164	case 0x1183:
	165	addr += SIS182_SATA1_OFS;
	166	break;
	167	}
8add7885	168	}
1da177e4 LT	169	return addr;
	170	}
	171
	172	static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
	173	{
cca3974e	174	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
9b14dec5	175	unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
668e4bc7	176	u32 val, val2 = 0;
f2c853bc	177	u8 pmr;
1da177e4 LT	178
	179	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
	180	return 0xffffffff;
f2c853bc AP	181
f2c853bc AP	182	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	183
1da177e4	184	pci_read_config_dword(pdev, cfg_addr, &val);
f2c853bc	185
3f3e7313 UK	186	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\| (pdev->device == 0x1182) \|\|
3f3e7313 UK	187	(pdev->device == 0x1183) \|\| (pmr & SIS_PMR_COMBINED))
f2c853bc AP	188	pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
f2c853bc AP	189
4adccf6f	190	return (val\|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */
1da177e4 LT	191	}
1da177e4 LT	192
9b14dec5	193	static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
1da177e4	194	{
cca3974e	195	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
9b14dec5	196	unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
f2c853bc	197	u8 pmr;
1da177e4	198
9b14dec5	199	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
1da177e4	200	return;
f2c853bc AP	201
f2c853bc AP	202	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	203
1da177e4	204	pci_write_config_dword(pdev, cfg_addr, val);
f2c853bc	205
3f3e7313 UK	206	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\| (pdev->device == 0x1182) \|\|
3f3e7313 UK	207	(pdev->device == 0x1183) \|\| (pmr & SIS_PMR_COMBINED))
f2c853bc	208	pci_write_config_dword(pdev, cfg_addr+0x10, val);
1da177e4 LT	209	}
	210
	211	static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
	212	{
cca3974e	213	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
8add7885	214	u32 val, val2 = 0;
f2c853bc AP	215	u8 pmr;
f2c853bc AP	216
1da177e4 LT	217	if (sc_reg > SCR_CONTROL)
	218	return 0xffffffffU;
	219
	220	if (ap->flags & SIS_FLAG_CFGSCR)
	221	return sis_scr_cfg_read(ap, sc_reg);
f2c853bc AP	222
	223	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	224
0d5ff566	225	val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
f2c853bc	226
3f3e7313 UK	227	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\| (pdev->device == 0x1182) \|\|
3f3e7313 UK	228	(pdev->device == 0x1183) \|\| (pmr & SIS_PMR_COMBINED))
0d5ff566	229	val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
f2c853bc	230
4adccf6f	231	return (val \| val2) & 0xfffffffb;
1da177e4 LT	232	}
	233
	234	static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	235	{
cca3974e	236	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
f2c853bc AP	237	u8 pmr;
f2c853bc AP	238
1da177e4 LT	239	if (sc_reg > SCR_CONTROL)
	240	return;
	241
f2c853bc	242	pci_read_config_byte(pdev, SIS_PMR, &pmr);
8add7885	243
1da177e4 LT	244	if (ap->flags & SIS_FLAG_CFGSCR)
1da177e4 LT	245	sis_scr_cfg_write(ap, sc_reg, val);
f2c853bc	246	else {
0d5ff566	247	iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
3f3e7313 UK	248	if ((pdev->device == 0x0182) \|\| (pdev->device == 0x0183) \|\| (pdev->device == 0x1182) \|\|
3f3e7313 UK	249	(pdev->device == 0x1183) \|\| (pmr & SIS_PMR_COMBINED))
0d5ff566	250	iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
f2c853bc	251	}
1da177e4 LT	252	}
1da177e4 LT	253
1da177e4 LT	254	static int sis_init_one (struct pci_dev pdev, const struct pci_device_id ent)
1da177e4 LT	255	{
a9524a76	256	static int printed_version;
9a829ccf	257	struct ata_port_info pi = sis_port_info;
ddfc87a0	258	const struct ata_port_info *ppi[] = { &pi, &pi };
9a829ccf	259	struct ata_host *host;
4adccf6f	260	u32 genctl, val;
f2c853bc	261	u8 pmr;
3f3e7313	262	u8 port2_start = 0x20;
9a829ccf	263	int rc;
1da177e4	264
a9524a76 JG	265	if (!printed_version++)
	266	dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
	267
24dc5f33	268	rc = pcim_enable_device(pdev);
1da177e4 LT	269	if (rc)
	270	return rc;
	271
1da177e4 LT	272	/* check and see if the SCRs are in IO space or PCI cfg space */
	273	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	274	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
cf0e812f	275	pi.flags \|= SIS_FLAG_CFGSCR;
8a60a071	276
1da177e4 LT	277	/* if hardware thinks SCRs are in IO space, but there are
	278	* no IO resources assigned, change to PCI cfg space.
	279	*/
cf0e812f	280	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
1da177e4 LT	281	((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) \|\|
	282	(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
	283	genctl &= ~GENCTL_IOMAPPED_SCR;
	284	pci_write_config_dword(pdev, SIS_GENCTL, genctl);
cf0e812f	285	pi.flags \|= SIS_FLAG_CFGSCR;
1da177e4 LT	286	}
1da177e4 LT	287
f2c853bc	288	pci_read_config_byte(pdev, SIS_PMR, &pmr);
3f3e7313 UK	289	switch (ent->device) {
	290	case 0x0180:
	291	case 0x0181:
9b14dec5 A	292
	293	/* The PATA-handling is provided by pata_sis */
	294	switch (pmr & 0x30) {
	295	case 0x10:
	296	ppi[1] = &sis_info133;
	297	break;
a84471fe	298
9b14dec5 A	299	case 0x30:
	300	ppi[0] = &sis_info133;
	301	break;
	302	}
f2c853bc	303	if ((pmr & SIS_PMR_COMBINED) == 0) {
a9524a76	304	dev_printk(KERN_INFO, &pdev->dev,
4adccf6f	305	"Detected SiS 180/181/964 chipset in SATA mode\n");
39eb936c	306	port2_start = 64;
3f3e7313	307	} else {
a9524a76 JG	308	dev_printk(KERN_INFO, &pdev->dev,
a9524a76 JG	309	"Detected SiS 180/181 chipset in combined mode\n");
f2c853bc	310	port2_start=0;
4adccf6f	311	pi.flags \|= ATA_FLAG_SLAVE_POSS;
f2c853bc	312	}
3f3e7313	313	break;
f20b16ff	314
3f3e7313 UK	315	case 0x0182:
3f3e7313 UK	316	case 0x0183:
4adccf6f UK	317	pci_read_config_dword ( pdev, 0x6C, &val);
	318	if (val & (1L << 31)) {
	319	dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
	320	pi.flags \|= ATA_FLAG_SLAVE_POSS;
3f3e7313	321	} else {
4adccf6f	322	dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
3f3e7313 UK	323	}
	324	break;
	325
	326	case 0x1182:
	327	case 0x1183:
	328	pci_read_config_dword(pdev, 0x64, &val);
	329	if (val & 0x10000000) {
	330	dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
	331	} else {
	332	dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
	333	pi.flags \|= ATA_FLAG_SLAVE_POSS;
	334	}
	335	break;
f2c853bc AP	336	}
f2c853bc AP	337
1626aeb8	338	rc = ata_pci_prepare_native_host(pdev, ppi, &host);
9a829ccf TH	339	if (rc)
9a829ccf TH	340	return rc;
cf0e812f	341
9a829ccf	342	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
edceec3d	343	void __iomem *mmio;
0d5ff566	344
9a829ccf TH	345	rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
	346	if (rc)
	347	return rc;
	348	mmio = host->iomap[SIS_SCR_PCI_BAR];
0d5ff566	349
9a829ccf TH	350	host->ports[0]->ioaddr.scr_addr = mmio;
9a829ccf TH	351	host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
1da177e4 LT	352	}
	353
	354	pci_set_master(pdev);
a04ce0ff	355	pci_intx(pdev, 1);
9a829ccf TH	356	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
9a829ccf TH	357	&sis_sht);
1da177e4 LT	358	}
	359
	360	static int __init sis_init(void)
	361	{
b7887196	362	return pci_register_driver(&sis_pci_driver);
1da177e4 LT	363	}
	364
	365	static void __exit sis_exit(void)
	366	{
	367	pci_unregister_driver(&sis_pci_driver);
	368	}
	369
	370	module_init(sis_init);
	371	module_exit(sis_exit);