Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/kernel.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
a9524a76 | 40 | #include <linux/device.h> |
1da177e4 LT |
41 | #include <scsi/scsi_host.h> |
42 | #include <linux/libata.h> | |
77a527ea | 43 | #include "libata.h" |
1da177e4 | 44 | |
fda0efc5 | 45 | #undef DRV_NAME /* already defined in libata.h, for libata-core */ |
1da177e4 | 46 | #define DRV_NAME "sata_sis" |
3f3e7313 | 47 | #define DRV_VERSION "0.7" |
1da177e4 LT |
48 | |
49 | enum { | |
50 | sis_180 = 0, | |
51 | SIS_SCR_PCI_BAR = 5, | |
52 | ||
53 | /* PCI configuration registers */ | |
54 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
55 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
f2c853bc AP |
56 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
57 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | |
58 | SIS_PMR = 0x90, /* port mapping register */ | |
8add7885 | 59 | SIS_PMR_COMBINED = 0x30, |
1da177e4 LT |
60 | |
61 | /* random bits */ | |
62 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
63 | ||
64 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
65 | }; | |
66 | ||
67 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
68 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
69 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
70 | ||
3b7d697d | 71 | static const struct pci_device_id sis_pci_tbl[] = { |
3f3e7313 UK |
72 | { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */ |
73 | { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */ | |
74 | { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */ | |
75 | { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */ | |
76 | { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */ | |
77 | { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */ | |
2d2744fc | 78 | |
1da177e4 LT |
79 | { } /* terminate list */ |
80 | }; | |
81 | ||
1da177e4 LT |
82 | static struct pci_driver sis_pci_driver = { |
83 | .name = DRV_NAME, | |
84 | .id_table = sis_pci_tbl, | |
85 | .probe = sis_init_one, | |
86 | .remove = ata_pci_remove_one, | |
87 | }; | |
88 | ||
193515d5 | 89 | static struct scsi_host_template sis_sht = { |
1da177e4 LT |
90 | .module = THIS_MODULE, |
91 | .name = DRV_NAME, | |
92 | .ioctl = ata_scsi_ioctl, | |
93 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
94 | .can_queue = ATA_DEF_QUEUE, |
95 | .this_id = ATA_SHT_THIS_ID, | |
96 | .sg_tablesize = ATA_MAX_PRD, | |
1da177e4 LT |
97 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
98 | .emulated = ATA_SHT_EMULATED, | |
99 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
100 | .proc_name = DRV_NAME, | |
101 | .dma_boundary = ATA_DMA_BOUNDARY, | |
102 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 103 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 104 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
105 | }; |
106 | ||
057ace5e | 107 | static const struct ata_port_operations sis_ops = { |
1da177e4 LT |
108 | .port_disable = ata_port_disable, |
109 | .tf_load = ata_tf_load, | |
110 | .tf_read = ata_tf_read, | |
111 | .check_status = ata_check_status, | |
112 | .exec_command = ata_exec_command, | |
113 | .dev_select = ata_std_dev_select, | |
1da177e4 LT |
114 | .bmdma_setup = ata_bmdma_setup, |
115 | .bmdma_start = ata_bmdma_start, | |
116 | .bmdma_stop = ata_bmdma_stop, | |
117 | .bmdma_status = ata_bmdma_status, | |
118 | .qc_prep = ata_qc_prep, | |
119 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 120 | .data_xfer = ata_data_xfer, |
d7a80dad TH |
121 | .freeze = ata_bmdma_freeze, |
122 | .thaw = ata_bmdma_thaw, | |
123 | .error_handler = ata_bmdma_error_handler, | |
124 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1da177e4 LT |
125 | .irq_handler = ata_interrupt, |
126 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
127 | .irq_on = ata_irq_on, |
128 | .irq_ack = ata_irq_ack, | |
1da177e4 LT |
129 | .scr_read = sis_scr_read, |
130 | .scr_write = sis_scr_write, | |
131 | .port_start = ata_port_start, | |
1da177e4 LT |
132 | }; |
133 | ||
134 | static struct ata_port_info sis_port_info = { | |
135 | .sht = &sis_sht, | |
cca3974e | 136 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
1da177e4 LT |
137 | .pio_mask = 0x1f, |
138 | .mwdma_mask = 0x7, | |
139 | .udma_mask = 0x7f, | |
140 | .port_ops = &sis_ops, | |
141 | }; | |
142 | ||
1da177e4 LT |
143 | MODULE_AUTHOR("Uwe Koziolek"); |
144 | MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller"); | |
145 | MODULE_LICENSE("GPL"); | |
146 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
147 | MODULE_VERSION(DRV_VERSION); | |
148 | ||
9b14dec5 | 149 | static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 150 | { |
9b14dec5 | 151 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 152 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); |
9b14dec5 | 153 | u8 pmr; |
1da177e4 | 154 | |
9b14dec5 | 155 | if (ap->port_no) { |
3f3e7313 UK |
156 | switch (pdev->device) { |
157 | case 0x0180: | |
158 | case 0x0181: | |
9b14dec5 A |
159 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
160 | if ((pmr & SIS_PMR_COMBINED) == 0) | |
161 | addr += SIS180_SATA1_OFS; | |
3f3e7313 UK |
162 | break; |
163 | ||
164 | case 0x0182: | |
165 | case 0x0183: | |
166 | case 0x1182: | |
167 | case 0x1183: | |
168 | addr += SIS182_SATA1_OFS; | |
169 | break; | |
170 | } | |
8add7885 | 171 | } |
1da177e4 LT |
172 | return addr; |
173 | } | |
174 | ||
175 | static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg) | |
176 | { | |
cca3974e | 177 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
9b14dec5 | 178 | unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg); |
668e4bc7 | 179 | u32 val, val2 = 0; |
f2c853bc | 180 | u8 pmr; |
1da177e4 LT |
181 | |
182 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
183 | return 0xffffffff; | |
f2c853bc AP |
184 | |
185 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 186 | |
1da177e4 | 187 | pci_read_config_dword(pdev, cfg_addr, &val); |
f2c853bc | 188 | |
3f3e7313 UK |
189 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
190 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc AP |
191 | pci_read_config_dword(pdev, cfg_addr+0x10, &val2); |
192 | ||
4adccf6f | 193 | return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */ |
1da177e4 LT |
194 | } |
195 | ||
9b14dec5 | 196 | static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 197 | { |
cca3974e | 198 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
9b14dec5 | 199 | unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg); |
f2c853bc | 200 | u8 pmr; |
1da177e4 | 201 | |
9b14dec5 | 202 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ |
1da177e4 | 203 | return; |
f2c853bc AP |
204 | |
205 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 206 | |
1da177e4 | 207 | pci_write_config_dword(pdev, cfg_addr, val); |
f2c853bc | 208 | |
3f3e7313 UK |
209 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
210 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc | 211 | pci_write_config_dword(pdev, cfg_addr+0x10, val); |
1da177e4 LT |
212 | } |
213 | ||
214 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
215 | { | |
cca3974e | 216 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
8add7885 | 217 | u32 val, val2 = 0; |
f2c853bc AP |
218 | u8 pmr; |
219 | ||
1da177e4 LT |
220 | if (sc_reg > SCR_CONTROL) |
221 | return 0xffffffffU; | |
222 | ||
223 | if (ap->flags & SIS_FLAG_CFGSCR) | |
224 | return sis_scr_cfg_read(ap, sc_reg); | |
f2c853bc AP |
225 | |
226 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
227 | ||
0d5ff566 | 228 | val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4)); |
f2c853bc | 229 | |
3f3e7313 UK |
230 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
231 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
0d5ff566 | 232 | val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); |
f2c853bc | 233 | |
4adccf6f | 234 | return (val | val2) & 0xfffffffb; |
1da177e4 LT |
235 | } |
236 | ||
237 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
238 | { | |
cca3974e | 239 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
f2c853bc AP |
240 | u8 pmr; |
241 | ||
1da177e4 LT |
242 | if (sc_reg > SCR_CONTROL) |
243 | return; | |
244 | ||
f2c853bc | 245 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
8add7885 | 246 | |
1da177e4 LT |
247 | if (ap->flags & SIS_FLAG_CFGSCR) |
248 | sis_scr_cfg_write(ap, sc_reg, val); | |
f2c853bc | 249 | else { |
0d5ff566 | 250 | iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
3f3e7313 UK |
251 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
252 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
0d5ff566 | 253 | iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); |
f2c853bc | 254 | } |
1da177e4 LT |
255 | } |
256 | ||
1da177e4 LT |
257 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
258 | { | |
a9524a76 | 259 | static int printed_version; |
1da177e4 LT |
260 | struct ata_probe_ent *probe_ent = NULL; |
261 | int rc; | |
4adccf6f | 262 | u32 genctl, val; |
cf0e812f | 263 | struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi }; |
f2c853bc | 264 | u8 pmr; |
3f3e7313 | 265 | u8 port2_start = 0x20; |
1da177e4 | 266 | |
a9524a76 JG |
267 | if (!printed_version++) |
268 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
269 | ||
24dc5f33 | 270 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
271 | if (rc) |
272 | return rc; | |
273 | ||
274 | rc = pci_request_regions(pdev, DRV_NAME); | |
275 | if (rc) { | |
24dc5f33 TH |
276 | pcim_pin_device(pdev); |
277 | return rc; | |
1da177e4 LT |
278 | } |
279 | ||
280 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
281 | if (rc) | |
24dc5f33 | 282 | return rc; |
1da177e4 LT |
283 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
284 | if (rc) | |
24dc5f33 | 285 | return rc; |
1da177e4 | 286 | |
1da177e4 LT |
287 | /* check and see if the SCRs are in IO space or PCI cfg space */ |
288 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
289 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
cf0e812f | 290 | pi.flags |= SIS_FLAG_CFGSCR; |
8a60a071 | 291 | |
1da177e4 LT |
292 | /* if hardware thinks SCRs are in IO space, but there are |
293 | * no IO resources assigned, change to PCI cfg space. | |
294 | */ | |
cf0e812f | 295 | if ((!(pi.flags & SIS_FLAG_CFGSCR)) && |
1da177e4 LT |
296 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || |
297 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
298 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
299 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
cf0e812f | 300 | pi.flags |= SIS_FLAG_CFGSCR; |
1da177e4 LT |
301 | } |
302 | ||
f2c853bc | 303 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
3f3e7313 UK |
304 | switch (ent->device) { |
305 | case 0x0180: | |
306 | case 0x0181: | |
9b14dec5 A |
307 | |
308 | /* The PATA-handling is provided by pata_sis */ | |
309 | switch (pmr & 0x30) { | |
310 | case 0x10: | |
311 | ppi[1] = &sis_info133; | |
312 | break; | |
313 | ||
314 | case 0x30: | |
315 | ppi[0] = &sis_info133; | |
316 | break; | |
317 | } | |
f2c853bc | 318 | if ((pmr & SIS_PMR_COMBINED) == 0) { |
a9524a76 | 319 | dev_printk(KERN_INFO, &pdev->dev, |
4adccf6f | 320 | "Detected SiS 180/181/964 chipset in SATA mode\n"); |
39eb936c | 321 | port2_start = 64; |
3f3e7313 | 322 | } else { |
a9524a76 JG |
323 | dev_printk(KERN_INFO, &pdev->dev, |
324 | "Detected SiS 180/181 chipset in combined mode\n"); | |
f2c853bc | 325 | port2_start=0; |
4adccf6f | 326 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
f2c853bc | 327 | } |
3f3e7313 | 328 | break; |
f20b16ff | 329 | |
3f3e7313 UK |
330 | case 0x0182: |
331 | case 0x0183: | |
4adccf6f UK |
332 | pci_read_config_dword ( pdev, 0x6C, &val); |
333 | if (val & (1L << 31)) { | |
334 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n"); | |
335 | pi.flags |= ATA_FLAG_SLAVE_POSS; | |
3f3e7313 | 336 | } else { |
4adccf6f | 337 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n"); |
3f3e7313 UK |
338 | } |
339 | break; | |
340 | ||
341 | case 0x1182: | |
342 | case 0x1183: | |
343 | pci_read_config_dword(pdev, 0x64, &val); | |
344 | if (val & 0x10000000) { | |
345 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n"); | |
346 | } else { | |
347 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n"); | |
348 | pi.flags |= ATA_FLAG_SLAVE_POSS; | |
349 | } | |
350 | break; | |
f2c853bc AP |
351 | } |
352 | ||
cf0e812f | 353 | probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); |
24dc5f33 TH |
354 | if (!probe_ent) |
355 | return -ENOMEM; | |
cf0e812f | 356 | |
cca3974e | 357 | if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) { |
0d5ff566 TH |
358 | void *mmio; |
359 | ||
360 | mmio = pcim_iomap(pdev, SIS_SCR_PCI_BAR, 0); | |
361 | if (!mmio) | |
362 | return -ENOMEM; | |
363 | ||
364 | probe_ent->port[0].scr_addr = mmio; | |
365 | probe_ent->port[1].scr_addr = mmio + port2_start; | |
1da177e4 LT |
366 | } |
367 | ||
368 | pci_set_master(pdev); | |
a04ce0ff | 369 | pci_intx(pdev, 1); |
1da177e4 | 370 | |
24dc5f33 TH |
371 | if (!ata_device_add(probe_ent)) |
372 | return -EIO; | |
1da177e4 | 373 | |
24dc5f33 | 374 | devm_kfree(&pdev->dev, probe_ent); |
1da177e4 LT |
375 | return 0; |
376 | ||
1da177e4 LT |
377 | } |
378 | ||
379 | static int __init sis_init(void) | |
380 | { | |
b7887196 | 381 | return pci_register_driver(&sis_pci_driver); |
1da177e4 LT |
382 | } |
383 | ||
384 | static void __exit sis_exit(void) | |
385 | { | |
386 | pci_unregister_driver(&sis_pci_driver); | |
387 | } | |
388 | ||
389 | module_init(sis_init); | |
390 | module_exit(sis_exit); |