[deliverable/linux.git] / drivers / base / regmap / regmap-irq.c

/*
 * regmap based irq_chip
 *
 * Copyright 2011 Wolfson Microelectronics plc
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/export.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/slab.h>

#include "internal.h"

struct regmap_irq_chip_data {
	struct mutex lock;

	struct regmap *map;
	const struct regmap_irq_chip *chip;

	int irq_base;
	struct irq_domain *domain;

	int irq;
	int wake_count;

	unsigned int *status_buf;
	unsigned int *mask_buf;
	unsigned int *mask_buf_def;
	unsigned int *wake_buf;

	unsigned int irq_reg_stride;
};

static inline const
struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
				     int irq)
{
	return &data->chip->irqs[irq];
}

static void regmap_irq_lock(struct irq_data *data)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);

	mutex_lock(&d->lock);
}

static void regmap_irq_sync_unlock(struct irq_data *data)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
	struct regmap *map = d->map;
	int i, ret;
	u32 reg;

	/*
	 * If there's been a change in the mask write it back to the
	 * hardware.  We rely on the use of the regmap core cache to
	 * suppress pointless writes.
	 */
	for (i = 0; i < d->chip->num_regs; i++) {
		reg = d->chip->mask_base +
			(i * map->reg_stride * d->irq_reg_stride);
		ret = regmap_update_bits(d->map, reg,
					 d->mask_buf_def[i], d->mask_buf[i]);
		if (ret != 0)
			dev_err(d->map->dev, "Failed to sync masks in %x\n",
				reg);
	}

	/* If we've changed our wakeup count propagate it to the parent */
	if (d->wake_count < 0)
		for (i = d->wake_count; i < 0; i++)
			irq_set_irq_wake(d->irq, 0);
	else if (d->wake_count > 0)
		for (i = 0; i < d->wake_count; i++)
			irq_set_irq_wake(d->irq, 1);

	d->wake_count = 0;

	mutex_unlock(&d->lock);
}

static void regmap_irq_enable(struct irq_data *data)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
	struct regmap *map = d->map;
	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);

	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
}

static void regmap_irq_disable(struct irq_data *data)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
	struct regmap *map = d->map;
	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);

	d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
}

static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
{
	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
	struct regmap *map = d->map;
	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);

	if (!d->chip->wake_base)
		return -EINVAL;

	if (on) {
		d->wake_buf[irq_data->reg_offset / map->reg_stride]
			&= ~irq_data->mask;
		d->wake_count++;
	} else {
		d->wake_buf[irq_data->reg_offset / map->reg_stride]
			|= irq_data->mask;
		d->wake_count--;
	}

	return 0;
}

static struct irq_chip regmap_irq_chip = {
	.name			= "regmap",
	.irq_bus_lock		= regmap_irq_lock,
	.irq_bus_sync_unlock	= regmap_irq_sync_unlock,
	.irq_disable		= regmap_irq_disable,
	.irq_enable		= regmap_irq_enable,
	.irq_set_wake		= regmap_irq_set_wake,
};

static irqreturn_t regmap_irq_thread(int irq, void *d)
{
	struct regmap_irq_chip_data *data = d;
	const struct regmap_irq_chip *chip = data->chip;
	struct regmap *map = data->map;
	int ret, i;
	bool handled = false;
	u32 reg;

	/*
	 * Ignore masked IRQs and ack if we need to; we ack early so
	 * there is no race between handling and acknowleding the
	 * interrupt.  We assume that typically few of the interrupts
	 * will fire simultaneously so don't worry about overhead from
	 * doing a write per register.
	 */
	for (i = 0; i < data->chip->num_regs; i++) {
		ret = regmap_read(map, chip->status_base + (i * map->reg_stride
				   * data->irq_reg_stride),
				   &data->status_buf[i]);

		if (ret != 0) {
			dev_err(map->dev, "Failed to read IRQ status: %d\n",
					ret);
			return IRQ_NONE;
		}

		data->status_buf[i] &= ~data->mask_buf[i];

		if (data->status_buf[i] && chip->ack_base) {
			reg = chip->ack_base +
				(i * map->reg_stride * data->irq_reg_stride);
			ret = regmap_write(map, reg, data->status_buf[i]);
			if (ret != 0)
				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
					reg, ret);
		}
	}

	for (i = 0; i < chip->num_irqs; i++) {
		if (data->status_buf[chip->irqs[i].reg_offset /
				     map->reg_stride] & chip->irqs[i].mask) {
			handle_nested_irq(irq_find_mapping(data->domain, i));
			handled = true;
		}
	}

	if (handled)
		return IRQ_HANDLED;
	else
		return IRQ_NONE;
}

static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	struct regmap_irq_chip_data *data = h->host_data;

	irq_set_chip_data(virq, data);
	irq_set_chip_and_handler(virq, &regmap_irq_chip, handle_edge_irq);
	irq_set_nested_thread(virq, 1);

	/* ARM needs us to explicitly flag the IRQ as valid
	 * and will set them noprobe when we do so. */
#ifdef CONFIG_ARM
	set_irq_flags(virq, IRQF_VALID);
#else
	irq_set_noprobe(virq);
#endif

	return 0;
}

static struct irq_domain_ops regmap_domain_ops = {
	.map	= regmap_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

/**
 * regmap_add_irq_chip(): Use standard regmap IRQ controller handling
 *
 * map:       The regmap for the device.
 * irq:       The IRQ the device uses to signal interrupts
 * irq_flags: The IRQF_ flags to use for the primary interrupt.
 * chip:      Configuration for the interrupt controller.
 * data:      Runtime data structure for the controller, allocated on success
 *
 * Returns 0 on success or an errno on failure.
 *
 * In order for this to be efficient the chip really should use a
 * register cache.  The chip driver is responsible for restoring the
 * register values used by the IRQ controller over suspend and resume.
 */
int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
			int irq_base, const struct regmap_irq_chip *chip,
			struct regmap_irq_chip_data **data)
{
	struct regmap_irq_chip_data *d;
	int i;
	int ret = -ENOMEM;
	u32 reg;

	for (i = 0; i < chip->num_irqs; i++) {
		if (chip->irqs[i].reg_offset % map->reg_stride)
			return -EINVAL;
		if (chip->irqs[i].reg_offset / map->reg_stride >=
		    chip->num_regs)
			return -EINVAL;
	}

	if (irq_base) {
		irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
		if (irq_base < 0) {
			dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
				 irq_base);
			return irq_base;
		}
	}

	d = kzalloc(sizeof(*d), GFP_KERNEL);
	if (!d)
		return -ENOMEM;

	*data = d;

	d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
				GFP_KERNEL);
	if (!d->status_buf)
		goto err_alloc;

	d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
			      GFP_KERNEL);
	if (!d->mask_buf)
		goto err_alloc;

	d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
				  GFP_KERNEL);
	if (!d->mask_buf_def)
		goto err_alloc;

	if (chip->wake_base) {
		d->wake_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
				      GFP_KERNEL);
		if (!d->wake_buf)
			goto err_alloc;
	}

	d->irq = irq;
	d->map = map;
	d->chip = chip;
	d->irq_base = irq_base;

	if (chip->irq_reg_stride)
		d->irq_reg_stride = chip->irq_reg_stride;
	else
		d->irq_reg_stride = 1;

	mutex_init(&d->lock);

	for (i = 0; i < chip->num_irqs; i++)
		d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
			|= chip->irqs[i].mask;

	/* Mask all the interrupts by default */
	for (i = 0; i < chip->num_regs; i++) {
		d->mask_buf[i] = d->mask_buf_def[i];
		reg = chip->mask_base +
			(i * map->reg_stride * d->irq_reg_stride);
		ret = regmap_update_bits(map, reg,
					 d->mask_buf[i], d->mask_buf[i]);
		if (ret != 0) {
			dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
				reg, ret);
			goto err_alloc;
		}
	}

	if (irq_base)
		d->domain = irq_domain_add_legacy(map->dev->of_node,
						  chip->num_irqs, irq_base, 0,
						  &regmap_domain_ops, d);
	else
		d->domain = irq_domain_add_linear(map->dev->of_node,
						  chip->num_irqs,
						  &regmap_domain_ops, d);
	if (!d->domain) {
		dev_err(map->dev, "Failed to create IRQ domain\n");
		ret = -ENOMEM;
		goto err_alloc;
	}

	ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
				   chip->name, d);
	if (ret != 0) {
		dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret);
		goto err_domain;
	}

	return 0;

err_domain:
	/* Should really dispose of the domain but... */
err_alloc:
	kfree(d->wake_buf);
	kfree(d->mask_buf_def);
	kfree(d->mask_buf);
	kfree(d->status_buf);
	kfree(d);
	return ret;
}
EXPORT_SYMBOL_GPL(regmap_add_irq_chip);

/**
 * regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
 *
 * @irq: Primary IRQ for the device
 * @d:   regmap_irq_chip_data allocated by regmap_add_irq_chip()
 */
void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
{
	if (!d)
		return;

	free_irq(irq, d);
	/* We should unmap the domain but... */
	kfree(d->wake_buf);
	kfree(d->mask_buf_def);
	kfree(d->mask_buf);
	kfree(d->status_buf);
	kfree(d);
}
EXPORT_SYMBOL_GPL(regmap_del_irq_chip);

/**
 * regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
 *
 * Useful for drivers to request their own IRQs.
 *
 * @data: regmap_irq controller to operate on.
 */
int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
{
	WARN_ON(!data->irq_base);
	return data->irq_base;
}
EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);

/**
 * regmap_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
 *
 * Useful for drivers to request their own IRQs.
 *
 * @data: regmap_irq controller to operate on.
 * @irq: index of the interrupt requested in the chip IRQs
 */
int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
{
	/* Handle holes in the IRQ list */
	if (!data->chip->irqs[irq].mask)
		return -EINVAL;

	return irq_create_mapping(data->domain, irq);
}
EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
Commit	Line	Data
f8beab2b MB	1	/*
	2	* regmap based irq_chip
	3	*
	4	* Copyright 2011 Wolfson Microelectronics plc
	5	*
	6	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/export.h>
51990e82	14	#include <linux/device.h>
f8beab2b MB	15	#include <linux/regmap.h>
	16	#include <linux/irq.h>
	17	#include <linux/interrupt.h>
4af8be67	18	#include <linux/irqdomain.h>
f8beab2b MB	19	#include <linux/slab.h>
	20
	21	#include "internal.h"
	22
	23	struct regmap_irq_chip_data {
	24	struct mutex lock;
	25
	26	struct regmap *map;
b026ddbb	27	const struct regmap_irq_chip *chip;
f8beab2b MB	28
f8beab2b MB	29	int irq_base;
4af8be67	30	struct irq_domain *domain;
f8beab2b	31
a43fd50d MB	32	int irq;
	33	int wake_count;
	34
f8beab2b MB	35	unsigned int *status_buf;
	36	unsigned int *mask_buf;
	37	unsigned int *mask_buf_def;
a43fd50d	38	unsigned int *wake_buf;
022f926a GG	39
022f926a GG	40	unsigned int irq_reg_stride;
f8beab2b MB	41	};
	42
	43	static inline const
	44	struct regmap_irq irq_to_regmap_irq(struct regmap_irq_chip_data data,
	45	int irq)
	46	{
4af8be67	47	return &data->chip->irqs[irq];
f8beab2b MB	48	}
	49
	50	static void regmap_irq_lock(struct irq_data *data)
	51	{
	52	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
	53
	54	mutex_lock(&d->lock);
	55	}
	56
	57	static void regmap_irq_sync_unlock(struct irq_data *data)
	58	{
	59	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
56806555	60	struct regmap *map = d->map;
f8beab2b	61	int i, ret;
16032624	62	u32 reg;
f8beab2b MB	63
	64	/*
	65	* If there's been a change in the mask write it back to the
	66	* hardware. We rely on the use of the regmap core cache to
	67	* suppress pointless writes.
	68	*/
	69	for (i = 0; i < d->chip->num_regs; i++) {
16032624 SW	70	reg = d->chip->mask_base +
	71	(i * map->reg_stride * d->irq_reg_stride);
	72	ret = regmap_update_bits(d->map, reg,
f8beab2b MB	73	d->mask_buf_def[i], d->mask_buf[i]);
	74	if (ret != 0)
	75	dev_err(d->map->dev, "Failed to sync masks in %x\n",
16032624	76	reg);
f8beab2b MB	77	}
f8beab2b MB	78
a43fd50d MB	79	/* If we've changed our wakeup count propagate it to the parent */
	80	if (d->wake_count < 0)
	81	for (i = d->wake_count; i < 0; i++)
	82	irq_set_irq_wake(d->irq, 0);
	83	else if (d->wake_count > 0)
	84	for (i = 0; i < d->wake_count; i++)
	85	irq_set_irq_wake(d->irq, 1);
	86
	87	d->wake_count = 0;
	88
f8beab2b MB	89	mutex_unlock(&d->lock);
	90	}
	91
	92	static void regmap_irq_enable(struct irq_data *data)
	93	{
	94	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
56806555	95	struct regmap *map = d->map;
4af8be67	96	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
f8beab2b	97
f01ee60f	98	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~irq_data->mask;
f8beab2b MB	99	}
	100
	101	static void regmap_irq_disable(struct irq_data *data)
	102	{
	103	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
56806555	104	struct regmap *map = d->map;
4af8be67	105	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
f8beab2b	106
f01ee60f	107	d->mask_buf[irq_data->reg_offset / map->reg_stride] \|= irq_data->mask;
f8beab2b MB	108	}
f8beab2b MB	109
a43fd50d MB	110	static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
	111	{
	112	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
	113	struct regmap *map = d->map;
	114	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
	115
	116	if (!d->chip->wake_base)
	117	return -EINVAL;
	118
	119	if (on) {
	120	d->wake_buf[irq_data->reg_offset / map->reg_stride]
	121	&= ~irq_data->mask;
	122	d->wake_count++;
	123	} else {
	124	d->wake_buf[irq_data->reg_offset / map->reg_stride]
	125	\|= irq_data->mask;
	126	d->wake_count--;
	127	}
	128
	129	return 0;
	130	}
	131
f8beab2b MB	132	static struct irq_chip regmap_irq_chip = {
	133	.name = "regmap",
	134	.irq_bus_lock = regmap_irq_lock,
	135	.irq_bus_sync_unlock = regmap_irq_sync_unlock,
	136	.irq_disable = regmap_irq_disable,
	137	.irq_enable = regmap_irq_enable,
a43fd50d	138	.irq_set_wake = regmap_irq_set_wake,
f8beab2b MB	139	};
	140
	141	static irqreturn_t regmap_irq_thread(int irq, void *d)
	142	{
	143	struct regmap_irq_chip_data *data = d;
b026ddbb	144	const struct regmap_irq_chip *chip = data->chip;
f8beab2b MB	145	struct regmap *map = data->map;
f8beab2b MB	146	int ret, i;
d23511f9	147	bool handled = false;
16032624	148	u32 reg;
f8beab2b	149
f8beab2b MB	150	/*
	151	* Ignore masked IRQs and ack if we need to; we ack early so
	152	* there is no race between handling and acknowleding the
	153	* interrupt. We assume that typically few of the interrupts
	154	* will fire simultaneously so don't worry about overhead from
	155	* doing a write per register.
	156	*/
	157	for (i = 0; i < data->chip->num_regs; i++) {
38e7f5d1	158	ret = regmap_read(map, chip->status_base + (i * map->reg_stride
022f926a GG	159	* data->irq_reg_stride),
	160	&data->status_buf[i]);
	161
	162	if (ret != 0) {
	163	dev_err(map->dev, "Failed to read IRQ status: %d\n",
	164	ret);
f8beab2b MB	165	return IRQ_NONE;
	166	}
	167
	168	data->status_buf[i] &= ~data->mask_buf[i];
	169
	170	if (data->status_buf[i] && chip->ack_base) {
16032624 SW	171	reg = chip->ack_base +
	172	(i * map->reg_stride * data->irq_reg_stride);
	173	ret = regmap_write(map, reg, data->status_buf[i]);
f8beab2b MB	174	if (ret != 0)
f8beab2b MB	175	dev_err(map->dev, "Failed to ack 0x%x: %d\n",
16032624	176	reg, ret);
f8beab2b MB	177	}
	178	}
	179
	180	for (i = 0; i < chip->num_irqs; i++) {
f01ee60f SW	181	if (data->status_buf[chip->irqs[i].reg_offset /
f01ee60f SW	182	map->reg_stride] & chip->irqs[i].mask) {
4af8be67	183	handle_nested_irq(irq_find_mapping(data->domain, i));
d23511f9	184	handled = true;
f8beab2b MB	185	}
	186	}
	187
d23511f9 MB	188	if (handled)
	189	return IRQ_HANDLED;
	190	else
	191	return IRQ_NONE;
f8beab2b MB	192	}
f8beab2b MB	193
4af8be67 MB	194	static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
	195	irq_hw_number_t hw)
	196	{
	197	struct regmap_irq_chip_data *data = h->host_data;
	198
	199	irq_set_chip_data(virq, data);
	200	irq_set_chip_and_handler(virq, &regmap_irq_chip, handle_edge_irq);
	201	irq_set_nested_thread(virq, 1);
	202
	203	/* ARM needs us to explicitly flag the IRQ as valid
	204	* and will set them noprobe when we do so. */
	205	#ifdef CONFIG_ARM
	206	set_irq_flags(virq, IRQF_VALID);
	207	#else
	208	irq_set_noprobe(virq);
	209	#endif
	210
	211	return 0;
	212	}
	213
	214	static struct irq_domain_ops regmap_domain_ops = {
	215	.map = regmap_irq_map,
	216	.xlate = irq_domain_xlate_twocell,
	217	};
	218
f8beab2b MB	219	/**
	220	* regmap_add_irq_chip(): Use standard regmap IRQ controller handling
	221	*
	222	* map: The regmap for the device.
	223	* irq: The IRQ the device uses to signal interrupts
	224	* irq_flags: The IRQF_ flags to use for the primary interrupt.
	225	* chip: Configuration for the interrupt controller.
	226	* data: Runtime data structure for the controller, allocated on success
	227	*
	228	* Returns 0 on success or an errno on failure.
	229	*
	230	* In order for this to be efficient the chip really should use a
	231	* register cache. The chip driver is responsible for restoring the
	232	* register values used by the IRQ controller over suspend and resume.
	233	*/
	234	int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
b026ddbb	235	int irq_base, const struct regmap_irq_chip *chip,
f8beab2b MB	236	struct regmap_irq_chip_data **data)
	237	{
	238	struct regmap_irq_chip_data *d;
4af8be67	239	int i;
f8beab2b	240	int ret = -ENOMEM;
16032624	241	u32 reg;
f8beab2b	242
f01ee60f SW	243	for (i = 0; i < chip->num_irqs; i++) {
	244	if (chip->irqs[i].reg_offset % map->reg_stride)
	245	return -EINVAL;
	246	if (chip->irqs[i].reg_offset / map->reg_stride >=
	247	chip->num_regs)
	248	return -EINVAL;
	249	}
	250
4af8be67 MB	251	if (irq_base) {
	252	irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
	253	if (irq_base < 0) {
	254	dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
	255	irq_base);
	256	return irq_base;
	257	}
f8beab2b MB	258	}
	259
	260	d = kzalloc(sizeof(*d), GFP_KERNEL);
	261	if (!d)
	262	return -ENOMEM;
	263
2431d0a1 MB	264	*data = d;
2431d0a1 MB	265
f8beab2b MB	266	d->status_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
	267	GFP_KERNEL);
	268	if (!d->status_buf)
	269	goto err_alloc;
	270
f8beab2b MB	271	d->mask_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
	272	GFP_KERNEL);
	273	if (!d->mask_buf)
	274	goto err_alloc;
	275
	276	d->mask_buf_def = kzalloc(sizeof(unsigned int) * chip->num_regs,
	277	GFP_KERNEL);
	278	if (!d->mask_buf_def)
	279	goto err_alloc;
	280
a43fd50d MB	281	if (chip->wake_base) {
	282	d->wake_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
	283	GFP_KERNEL);
	284	if (!d->wake_buf)
	285	goto err_alloc;
	286	}
	287
	288	d->irq = irq;
f8beab2b MB	289	d->map = map;
	290	d->chip = chip;
	291	d->irq_base = irq_base;
022f926a GG	292
	293	if (chip->irq_reg_stride)
	294	d->irq_reg_stride = chip->irq_reg_stride;
	295	else
	296	d->irq_reg_stride = 1;
	297
f8beab2b MB	298	mutex_init(&d->lock);
	299
	300	for (i = 0; i < chip->num_irqs; i++)
f01ee60f	301	d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
f8beab2b MB	302	\|= chip->irqs[i].mask;
	303
	304	/* Mask all the interrupts by default */
	305	for (i = 0; i < chip->num_regs; i++) {
	306	d->mask_buf[i] = d->mask_buf_def[i];
16032624 SW	307	reg = chip->mask_base +
16032624 SW	308	(i * map->reg_stride * d->irq_reg_stride);
0eb46ad0 MB	309	ret = regmap_update_bits(map, reg,
0eb46ad0 MB	310	d->mask_buf[i], d->mask_buf[i]);
f8beab2b MB	311	if (ret != 0) {
f8beab2b MB	312	dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
16032624	313	reg, ret);
f8beab2b MB	314	goto err_alloc;
	315	}
	316	}
	317
4af8be67 MB	318	if (irq_base)
	319	d->domain = irq_domain_add_legacy(map->dev->of_node,
	320	chip->num_irqs, irq_base, 0,
	321	&regmap_domain_ops, d);
	322	else
	323	d->domain = irq_domain_add_linear(map->dev->of_node,
	324	chip->num_irqs,
	325	&regmap_domain_ops, d);
	326	if (!d->domain) {
	327	dev_err(map->dev, "Failed to create IRQ domain\n");
	328	ret = -ENOMEM;
	329	goto err_alloc;
f8beab2b MB	330	}
	331
	332	ret = request_threaded_irq(irq, NULL, regmap_irq_thread, irq_flags,
	333	chip->name, d);
	334	if (ret != 0) {
	335	dev_err(map->dev, "Failed to request IRQ %d: %d\n", irq, ret);
4af8be67	336	goto err_domain;
f8beab2b MB	337	}
	338
	339	return 0;
	340
4af8be67 MB	341	err_domain:
4af8be67 MB	342	/* Should really dispose of the domain but... */
f8beab2b	343	err_alloc:
a43fd50d	344	kfree(d->wake_buf);
f8beab2b MB	345	kfree(d->mask_buf_def);
f8beab2b MB	346	kfree(d->mask_buf);
f8beab2b MB	347	kfree(d->status_buf);
	348	kfree(d);
	349	return ret;
	350	}
	351	EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
	352
	353	/**
	354	* regmap_del_irq_chip(): Stop interrupt handling for a regmap IRQ chip
	355	*
	356	* @irq: Primary IRQ for the device
	357	* @d: regmap_irq_chip_data allocated by regmap_add_irq_chip()
	358	*/
	359	void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
	360	{
	361	if (!d)
	362	return;
	363
	364	free_irq(irq, d);
4af8be67	365	/* We should unmap the domain but... */
a43fd50d	366	kfree(d->wake_buf);
f8beab2b MB	367	kfree(d->mask_buf_def);
f8beab2b MB	368	kfree(d->mask_buf);
f8beab2b MB	369	kfree(d->status_buf);
	370	kfree(d);
	371	}
	372	EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
209a6006 MB	373
	374	/**
	375	* regmap_irq_chip_get_base(): Retrieve interrupt base for a regmap IRQ chip
	376	*
	377	* Useful for drivers to request their own IRQs.
	378	*
	379	* @data: regmap_irq controller to operate on.
	380	*/
	381	int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
	382	{
4af8be67	383	WARN_ON(!data->irq_base);
209a6006 MB	384	return data->irq_base;
	385	}
	386	EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
4af8be67 MB	387
	388	/**
	389	* regmap_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
	390	*
	391	* Useful for drivers to request their own IRQs.
	392	*
	393	* @data: regmap_irq controller to operate on.
	394	* @irq: index of the interrupt requested in the chip IRQs
	395	*/
	396	int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
	397	{
bfd6185d MB	398	/* Handle holes in the IRQ list */
	399	if (!data->chip->irqs[irq].mask)
	400	return -EINVAL;
	401
4af8be67 MB	402	return irq_create_mapping(data->domain, irq);
	403	}
	404	EXPORT_SYMBOL_GPL(regmap_irq_get_virq);