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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
8de05535 | 21 | #include <linux/bitops.h> |
b60503ba | 22 | #include <linux/blkdev.h> |
fd63e9ce | 23 | #include <linux/delay.h> |
b60503ba MW |
24 | #include <linux/errno.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/genhd.h> | |
5aff9382 | 27 | #include <linux/idr.h> |
b60503ba MW |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kdev_t.h> | |
1fa6aead | 32 | #include <linux/kthread.h> |
b60503ba MW |
33 | #include <linux/kernel.h> |
34 | #include <linux/mm.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/pci.h> | |
be7b6275 | 38 | #include <linux/poison.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
5d0f6131 | 42 | #include <scsi/sg.h> |
797a796a HM |
43 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
44 | ||
b60503ba MW |
45 | #define NVME_Q_DEPTH 1024 |
46 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
47 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
48 | #define NVME_MINORS 64 | |
e85248e5 | 49 | #define ADMIN_TIMEOUT (60 * HZ) |
b60503ba MW |
50 | |
51 | static int nvme_major; | |
52 | module_param(nvme_major, int, 0); | |
53 | ||
58ffacb5 MW |
54 | static int use_threaded_interrupts; |
55 | module_param(use_threaded_interrupts, int, 0); | |
56 | ||
1fa6aead MW |
57 | static DEFINE_SPINLOCK(dev_list_lock); |
58 | static LIST_HEAD(dev_list); | |
59 | static struct task_struct *nvme_thread; | |
60 | ||
b60503ba MW |
61 | /* |
62 | * An NVM Express queue. Each device has at least two (one for admin | |
63 | * commands and one for I/O commands). | |
64 | */ | |
65 | struct nvme_queue { | |
66 | struct device *q_dmadev; | |
091b6092 | 67 | struct nvme_dev *dev; |
b60503ba MW |
68 | spinlock_t q_lock; |
69 | struct nvme_command *sq_cmds; | |
70 | volatile struct nvme_completion *cqes; | |
71 | dma_addr_t sq_dma_addr; | |
72 | dma_addr_t cq_dma_addr; | |
73 | wait_queue_head_t sq_full; | |
1fa6aead | 74 | wait_queue_t sq_cong_wait; |
b60503ba MW |
75 | struct bio_list sq_cong; |
76 | u32 __iomem *q_db; | |
77 | u16 q_depth; | |
78 | u16 cq_vector; | |
79 | u16 sq_head; | |
80 | u16 sq_tail; | |
81 | u16 cq_head; | |
82123460 | 82 | u16 cq_phase; |
b60503ba MW |
83 | unsigned long cmdid_data[]; |
84 | }; | |
85 | ||
86 | /* | |
87 | * Check we didin't inadvertently grow the command struct | |
88 | */ | |
89 | static inline void _nvme_check_size(void) | |
90 | { | |
91 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
92 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
93 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
94 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
95 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 96 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
b60503ba MW |
97 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
98 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
99 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
100 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 101 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
102 | } |
103 | ||
5c1281a3 | 104 | typedef void (*nvme_completion_fn)(struct nvme_dev *, void *, |
c2f5b650 MW |
105 | struct nvme_completion *); |
106 | ||
e85248e5 | 107 | struct nvme_cmd_info { |
c2f5b650 MW |
108 | nvme_completion_fn fn; |
109 | void *ctx; | |
e85248e5 MW |
110 | unsigned long timeout; |
111 | }; | |
112 | ||
113 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
114 | { | |
115 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
116 | } | |
117 | ||
b60503ba | 118 | /** |
714a7a22 MW |
119 | * alloc_cmdid() - Allocate a Command ID |
120 | * @nvmeq: The queue that will be used for this command | |
121 | * @ctx: A pointer that will be passed to the handler | |
c2f5b650 | 122 | * @handler: The function to call on completion |
b60503ba MW |
123 | * |
124 | * Allocate a Command ID for a queue. The data passed in will | |
125 | * be passed to the completion handler. This is implemented by using | |
126 | * the bottom two bits of the ctx pointer to store the handler ID. | |
127 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
128 | * We can change this if it becomes a problem. | |
184d2944 MW |
129 | * |
130 | * May be called with local interrupts disabled and the q_lock held, | |
131 | * or with interrupts enabled and no locks held. | |
b60503ba | 132 | */ |
c2f5b650 MW |
133 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, |
134 | nvme_completion_fn handler, unsigned timeout) | |
b60503ba | 135 | { |
e6d15f79 | 136 | int depth = nvmeq->q_depth - 1; |
e85248e5 | 137 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
138 | int cmdid; |
139 | ||
b60503ba MW |
140 | do { |
141 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
142 | if (cmdid >= depth) | |
143 | return -EBUSY; | |
144 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
145 | ||
c2f5b650 MW |
146 | info[cmdid].fn = handler; |
147 | info[cmdid].ctx = ctx; | |
e85248e5 | 148 | info[cmdid].timeout = jiffies + timeout; |
b60503ba MW |
149 | return cmdid; |
150 | } | |
151 | ||
152 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
c2f5b650 | 153 | nvme_completion_fn handler, unsigned timeout) |
b60503ba MW |
154 | { |
155 | int cmdid; | |
156 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 157 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
158 | return (cmdid < 0) ? -EINTR : cmdid; |
159 | } | |
160 | ||
c2f5b650 MW |
161 | /* Special values must be less than 0x1000 */ |
162 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
163 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
164 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
165 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
00df5cb4 | 166 | #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE) |
be7b6275 | 167 | |
5c1281a3 | 168 | static void special_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
169 | struct nvme_completion *cqe) |
170 | { | |
171 | if (ctx == CMD_CTX_CANCELLED) | |
172 | return; | |
173 | if (ctx == CMD_CTX_FLUSH) | |
174 | return; | |
175 | if (ctx == CMD_CTX_COMPLETED) { | |
5c1281a3 | 176 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
177 | "completed id %d twice on queue %d\n", |
178 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
179 | return; | |
180 | } | |
181 | if (ctx == CMD_CTX_INVALID) { | |
5c1281a3 | 182 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
183 | "invalid id %d completed on queue %d\n", |
184 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
185 | return; | |
186 | } | |
187 | ||
5c1281a3 | 188 | dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
189 | } |
190 | ||
184d2944 MW |
191 | /* |
192 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
193 | */ | |
c2f5b650 MW |
194 | static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid, |
195 | nvme_completion_fn *fn) | |
b60503ba | 196 | { |
c2f5b650 | 197 | void *ctx; |
e85248e5 | 198 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 199 | |
c2f5b650 MW |
200 | if (cmdid >= nvmeq->q_depth) { |
201 | *fn = special_completion; | |
48e3d398 | 202 | return CMD_CTX_INVALID; |
c2f5b650 | 203 | } |
859361a2 KB |
204 | if (fn) |
205 | *fn = info[cmdid].fn; | |
c2f5b650 MW |
206 | ctx = info[cmdid].ctx; |
207 | info[cmdid].fn = special_completion; | |
e85248e5 | 208 | info[cmdid].ctx = CMD_CTX_COMPLETED; |
b60503ba MW |
209 | clear_bit(cmdid, nvmeq->cmdid_data); |
210 | wake_up(&nvmeq->sq_full); | |
c2f5b650 | 211 | return ctx; |
b60503ba MW |
212 | } |
213 | ||
c2f5b650 MW |
214 | static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid, |
215 | nvme_completion_fn *fn) | |
3c0cf138 | 216 | { |
c2f5b650 | 217 | void *ctx; |
e85248e5 | 218 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
c2f5b650 MW |
219 | if (fn) |
220 | *fn = info[cmdid].fn; | |
221 | ctx = info[cmdid].ctx; | |
222 | info[cmdid].fn = special_completion; | |
e85248e5 | 223 | info[cmdid].ctx = CMD_CTX_CANCELLED; |
c2f5b650 | 224 | return ctx; |
3c0cf138 MW |
225 | } |
226 | ||
5d0f6131 | 227 | struct nvme_queue *get_nvmeq(struct nvme_dev *dev) |
b60503ba | 228 | { |
040a93b5 | 229 | return dev->queues[get_cpu() + 1]; |
b60503ba MW |
230 | } |
231 | ||
5d0f6131 | 232 | void put_nvmeq(struct nvme_queue *nvmeq) |
b60503ba | 233 | { |
1b23484b | 234 | put_cpu(); |
b60503ba MW |
235 | } |
236 | ||
237 | /** | |
714a7a22 | 238 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
239 | * @nvmeq: The queue to use |
240 | * @cmd: The command to send | |
241 | * | |
242 | * Safe to use from interrupt context | |
243 | */ | |
244 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
245 | { | |
246 | unsigned long flags; | |
247 | u16 tail; | |
b60503ba MW |
248 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
249 | tail = nvmeq->sq_tail; | |
250 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
b60503ba MW |
251 | if (++tail == nvmeq->q_depth) |
252 | tail = 0; | |
7547881d | 253 | writel(tail, nvmeq->q_db); |
b60503ba MW |
254 | nvmeq->sq_tail = tail; |
255 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
eca18b23 | 260 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 261 | { |
eca18b23 | 262 | return ((void *)iod) + iod->offset; |
e025344c SMM |
263 | } |
264 | ||
eca18b23 MW |
265 | /* |
266 | * Will slightly overestimate the number of pages needed. This is OK | |
267 | * as it only leads to a small amount of wasted memory for the lifetime of | |
268 | * the I/O. | |
269 | */ | |
270 | static int nvme_npages(unsigned size) | |
271 | { | |
272 | unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE); | |
273 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
274 | } | |
b60503ba | 275 | |
eca18b23 MW |
276 | static struct nvme_iod * |
277 | nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp) | |
b60503ba | 278 | { |
eca18b23 MW |
279 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
280 | sizeof(__le64 *) * nvme_npages(nbytes) + | |
281 | sizeof(struct scatterlist) * nseg, gfp); | |
282 | ||
283 | if (iod) { | |
284 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
285 | iod->npages = -1; | |
286 | iod->length = nbytes; | |
2b196034 | 287 | iod->nents = 0; |
eca18b23 MW |
288 | } |
289 | ||
290 | return iod; | |
b60503ba MW |
291 | } |
292 | ||
5d0f6131 | 293 | void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 294 | { |
eca18b23 MW |
295 | const int last_prp = PAGE_SIZE / 8 - 1; |
296 | int i; | |
297 | __le64 **list = iod_list(iod); | |
298 | dma_addr_t prp_dma = iod->first_dma; | |
299 | ||
300 | if (iod->npages == 0) | |
301 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
302 | for (i = 0; i < iod->npages; i++) { | |
303 | __le64 *prp_list = list[i]; | |
304 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
305 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
306 | prp_dma = next_prp_dma; | |
307 | } | |
308 | kfree(iod); | |
b60503ba MW |
309 | } |
310 | ||
5c1281a3 MW |
311 | static void requeue_bio(struct nvme_dev *dev, struct bio *bio) |
312 | { | |
313 | struct nvme_queue *nvmeq = get_nvmeq(dev); | |
314 | if (bio_list_empty(&nvmeq->sq_cong)) | |
315 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
316 | bio_list_add(&nvmeq->sq_cong, bio); | |
317 | put_nvmeq(nvmeq); | |
318 | wake_up_process(nvme_thread); | |
319 | } | |
320 | ||
321 | static void bio_completion(struct nvme_dev *dev, void *ctx, | |
b60503ba MW |
322 | struct nvme_completion *cqe) |
323 | { | |
eca18b23 MW |
324 | struct nvme_iod *iod = ctx; |
325 | struct bio *bio = iod->private; | |
b60503ba MW |
326 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
327 | ||
2b196034 KB |
328 | if (iod->nents) |
329 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, | |
b60503ba | 330 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
eca18b23 | 331 | nvme_free_iod(dev, iod); |
09a58f53 | 332 | if (status) { |
1ad2f893 | 333 | bio_endio(bio, -EIO); |
09a58f53 | 334 | } else if (bio->bi_vcnt > bio->bi_idx) { |
5c1281a3 | 335 | requeue_bio(dev, bio); |
1ad2f893 MW |
336 | } else { |
337 | bio_endio(bio, 0); | |
338 | } | |
b60503ba MW |
339 | } |
340 | ||
184d2944 | 341 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
5d0f6131 VV |
342 | int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd, |
343 | struct nvme_iod *iod, int total_len, gfp_t gfp) | |
ff22b54f | 344 | { |
99802a7a | 345 | struct dma_pool *pool; |
eca18b23 MW |
346 | int length = total_len; |
347 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
348 | int dma_len = sg_dma_len(sg); |
349 | u64 dma_addr = sg_dma_address(sg); | |
350 | int offset = offset_in_page(dma_addr); | |
e025344c | 351 | __le64 *prp_list; |
eca18b23 | 352 | __le64 **list = iod_list(iod); |
e025344c | 353 | dma_addr_t prp_dma; |
eca18b23 | 354 | int nprps, i; |
ff22b54f MW |
355 | |
356 | cmd->prp1 = cpu_to_le64(dma_addr); | |
357 | length -= (PAGE_SIZE - offset); | |
358 | if (length <= 0) | |
eca18b23 | 359 | return total_len; |
ff22b54f MW |
360 | |
361 | dma_len -= (PAGE_SIZE - offset); | |
362 | if (dma_len) { | |
363 | dma_addr += (PAGE_SIZE - offset); | |
364 | } else { | |
365 | sg = sg_next(sg); | |
366 | dma_addr = sg_dma_address(sg); | |
367 | dma_len = sg_dma_len(sg); | |
368 | } | |
369 | ||
370 | if (length <= PAGE_SIZE) { | |
371 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 | 372 | return total_len; |
e025344c SMM |
373 | } |
374 | ||
375 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
99802a7a MW |
376 | if (nprps <= (256 / 8)) { |
377 | pool = dev->prp_small_pool; | |
eca18b23 | 378 | iod->npages = 0; |
99802a7a MW |
379 | } else { |
380 | pool = dev->prp_page_pool; | |
eca18b23 | 381 | iod->npages = 1; |
99802a7a MW |
382 | } |
383 | ||
b77954cb MW |
384 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
385 | if (!prp_list) { | |
386 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 MW |
387 | iod->npages = -1; |
388 | return (total_len - length) + PAGE_SIZE; | |
b77954cb | 389 | } |
eca18b23 MW |
390 | list[0] = prp_list; |
391 | iod->first_dma = prp_dma; | |
e025344c SMM |
392 | cmd->prp2 = cpu_to_le64(prp_dma); |
393 | i = 0; | |
394 | for (;;) { | |
7523d834 | 395 | if (i == PAGE_SIZE / 8) { |
e025344c | 396 | __le64 *old_prp_list = prp_list; |
b77954cb | 397 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
398 | if (!prp_list) |
399 | return total_len - length; | |
400 | list[iod->npages++] = prp_list; | |
7523d834 MW |
401 | prp_list[0] = old_prp_list[i - 1]; |
402 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
403 | i = 1; | |
e025344c SMM |
404 | } |
405 | prp_list[i++] = cpu_to_le64(dma_addr); | |
406 | dma_len -= PAGE_SIZE; | |
407 | dma_addr += PAGE_SIZE; | |
408 | length -= PAGE_SIZE; | |
409 | if (length <= 0) | |
410 | break; | |
411 | if (dma_len > 0) | |
412 | continue; | |
413 | BUG_ON(dma_len < 0); | |
414 | sg = sg_next(sg); | |
415 | dma_addr = sg_dma_address(sg); | |
416 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
417 | } |
418 | ||
eca18b23 | 419 | return total_len; |
ff22b54f MW |
420 | } |
421 | ||
1ad2f893 MW |
422 | /* NVMe scatterlists require no holes in the virtual address */ |
423 | #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \ | |
424 | (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE)) | |
425 | ||
eca18b23 | 426 | static int nvme_map_bio(struct device *dev, struct nvme_iod *iod, |
b60503ba MW |
427 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
428 | { | |
76830840 MW |
429 | struct bio_vec *bvec, *bvprv = NULL; |
430 | struct scatterlist *sg = NULL; | |
1ad2f893 | 431 | int i, old_idx, length = 0, nsegs = 0; |
b60503ba | 432 | |
eca18b23 | 433 | sg_init_table(iod->sg, psegs); |
1ad2f893 | 434 | old_idx = bio->bi_idx; |
b60503ba | 435 | bio_for_each_segment(bvec, bio, i) { |
76830840 MW |
436 | if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { |
437 | sg->length += bvec->bv_len; | |
438 | } else { | |
1ad2f893 MW |
439 | if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec)) |
440 | break; | |
eca18b23 | 441 | sg = sg ? sg + 1 : iod->sg; |
76830840 MW |
442 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, |
443 | bvec->bv_offset); | |
444 | nsegs++; | |
445 | } | |
1ad2f893 | 446 | length += bvec->bv_len; |
76830840 | 447 | bvprv = bvec; |
b60503ba | 448 | } |
1ad2f893 | 449 | bio->bi_idx = i; |
eca18b23 | 450 | iod->nents = nsegs; |
76830840 | 451 | sg_mark_end(sg); |
eca18b23 | 452 | if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) { |
1ad2f893 MW |
453 | bio->bi_idx = old_idx; |
454 | return -ENOMEM; | |
455 | } | |
456 | return length; | |
b60503ba MW |
457 | } |
458 | ||
0e5e4f0e KB |
459 | /* |
460 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
461 | * worth having a special pool for these or additional cases to handle freeing | |
462 | * the iod. | |
463 | */ | |
464 | static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
465 | struct bio *bio, struct nvme_iod *iod, int cmdid) | |
466 | { | |
467 | struct nvme_dsm_range *range; | |
468 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
469 | ||
470 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
471 | &iod->first_dma); | |
472 | if (!range) | |
473 | return -ENOMEM; | |
474 | ||
475 | iod_list(iod)[0] = (__le64 *)range; | |
476 | iod->npages = 0; | |
477 | ||
478 | range->cattr = cpu_to_le32(0); | |
479 | range->nlb = cpu_to_le32(bio->bi_size >> ns->lba_shift); | |
063cc6d5 | 480 | range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector)); |
0e5e4f0e KB |
481 | |
482 | memset(cmnd, 0, sizeof(*cmnd)); | |
483 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
484 | cmnd->dsm.command_id = cmdid; | |
485 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
486 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
487 | cmnd->dsm.nr = 0; | |
488 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
489 | ||
490 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
491 | nvmeq->sq_tail = 0; | |
492 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
00df5cb4 MW |
497 | static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
498 | int cmdid) | |
499 | { | |
500 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
501 | ||
502 | memset(cmnd, 0, sizeof(*cmnd)); | |
503 | cmnd->common.opcode = nvme_cmd_flush; | |
504 | cmnd->common.command_id = cmdid; | |
505 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
506 | ||
507 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
508 | nvmeq->sq_tail = 0; | |
509 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
5d0f6131 | 514 | int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) |
00df5cb4 MW |
515 | { |
516 | int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, | |
ff976d72 | 517 | special_completion, NVME_IO_TIMEOUT); |
00df5cb4 MW |
518 | if (unlikely(cmdid < 0)) |
519 | return cmdid; | |
520 | ||
521 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
522 | } | |
523 | ||
184d2944 MW |
524 | /* |
525 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
526 | */ | |
b60503ba MW |
527 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
528 | struct bio *bio) | |
529 | { | |
ff22b54f | 530 | struct nvme_command *cmnd; |
eca18b23 | 531 | struct nvme_iod *iod; |
b60503ba | 532 | enum dma_data_direction dma_dir; |
1ad2f893 | 533 | int cmdid, length, result = -ENOMEM; |
b60503ba MW |
534 | u16 control; |
535 | u32 dsmgmt; | |
b60503ba MW |
536 | int psegs = bio_phys_segments(ns->queue, bio); |
537 | ||
00df5cb4 MW |
538 | if ((bio->bi_rw & REQ_FLUSH) && psegs) { |
539 | result = nvme_submit_flush_data(nvmeq, ns); | |
540 | if (result) | |
541 | return result; | |
542 | } | |
543 | ||
eca18b23 MW |
544 | iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC); |
545 | if (!iod) | |
eeee3226 | 546 | goto nomem; |
eca18b23 | 547 | iod->private = bio; |
b60503ba | 548 | |
eeee3226 | 549 | result = -EBUSY; |
ff976d72 | 550 | cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT); |
b60503ba | 551 | if (unlikely(cmdid < 0)) |
eca18b23 | 552 | goto free_iod; |
b60503ba | 553 | |
0e5e4f0e KB |
554 | if (bio->bi_rw & REQ_DISCARD) { |
555 | result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid); | |
556 | if (result) | |
557 | goto free_cmdid; | |
558 | return result; | |
559 | } | |
00df5cb4 MW |
560 | if ((bio->bi_rw & REQ_FLUSH) && !psegs) |
561 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
562 | ||
b60503ba MW |
563 | control = 0; |
564 | if (bio->bi_rw & REQ_FUA) | |
565 | control |= NVME_RW_FUA; | |
566 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
567 | control |= NVME_RW_LR; | |
568 | ||
569 | dsmgmt = 0; | |
570 | if (bio->bi_rw & REQ_RAHEAD) | |
571 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
572 | ||
ff22b54f | 573 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 574 | |
b8deb62c | 575 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 576 | if (bio_data_dir(bio)) { |
ff22b54f | 577 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
578 | dma_dir = DMA_TO_DEVICE; |
579 | } else { | |
ff22b54f | 580 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
581 | dma_dir = DMA_FROM_DEVICE; |
582 | } | |
583 | ||
eca18b23 | 584 | result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs); |
1ad2f893 | 585 | if (result < 0) |
859361a2 | 586 | goto free_cmdid; |
1ad2f893 | 587 | length = result; |
b60503ba | 588 | |
ff22b54f MW |
589 | cmnd->rw.command_id = cmdid; |
590 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
eca18b23 MW |
591 | length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length, |
592 | GFP_ATOMIC); | |
063cc6d5 | 593 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector)); |
1ad2f893 | 594 | cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1); |
ff22b54f MW |
595 | cmnd->rw.control = cpu_to_le16(control); |
596 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 597 | |
d8ee9d69 MW |
598 | bio->bi_sector += length >> 9; |
599 | ||
b60503ba MW |
600 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
601 | nvmeq->sq_tail = 0; | |
7547881d | 602 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 603 | |
1974b1ae MW |
604 | return 0; |
605 | ||
859361a2 KB |
606 | free_cmdid: |
607 | free_cmdid(nvmeq, cmdid, NULL); | |
eca18b23 MW |
608 | free_iod: |
609 | nvme_free_iod(nvmeq->dev, iod); | |
eeee3226 MW |
610 | nomem: |
611 | return result; | |
b60503ba MW |
612 | } |
613 | ||
93c3d65b | 614 | static void nvme_make_request(struct request_queue *q, struct bio *bio) |
b60503ba MW |
615 | { |
616 | struct nvme_ns *ns = q->queuedata; | |
040a93b5 | 617 | struct nvme_queue *nvmeq = get_nvmeq(ns->dev); |
eeee3226 MW |
618 | int result = -EBUSY; |
619 | ||
620 | spin_lock_irq(&nvmeq->q_lock); | |
621 | if (bio_list_empty(&nvmeq->sq_cong)) | |
622 | result = nvme_submit_bio_queue(nvmeq, ns, bio); | |
623 | if (unlikely(result)) { | |
624 | if (bio_list_empty(&nvmeq->sq_cong)) | |
625 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
b60503ba MW |
626 | bio_list_add(&nvmeq->sq_cong, bio); |
627 | } | |
eeee3226 MW |
628 | |
629 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba | 630 | put_nvmeq(nvmeq); |
b60503ba MW |
631 | } |
632 | ||
b60503ba MW |
633 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) |
634 | { | |
82123460 | 635 | u16 head, phase; |
b60503ba | 636 | |
b60503ba | 637 | head = nvmeq->cq_head; |
82123460 | 638 | phase = nvmeq->cq_phase; |
b60503ba MW |
639 | |
640 | for (;;) { | |
c2f5b650 MW |
641 | void *ctx; |
642 | nvme_completion_fn fn; | |
b60503ba | 643 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 644 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
645 | break; |
646 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
647 | if (++head == nvmeq->q_depth) { | |
648 | head = 0; | |
82123460 | 649 | phase = !phase; |
b60503ba MW |
650 | } |
651 | ||
c2f5b650 | 652 | ctx = free_cmdid(nvmeq, cqe.command_id, &fn); |
5c1281a3 | 653 | fn(nvmeq->dev, ctx, &cqe); |
b60503ba MW |
654 | } |
655 | ||
656 | /* If the controller ignores the cq head doorbell and continuously | |
657 | * writes to the queue, it is theoretically possible to wrap around | |
658 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
659 | * requires that 0.1% of your interrupts are handled, so this isn't | |
660 | * a big problem. | |
661 | */ | |
82123460 | 662 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
663 | return IRQ_NONE; |
664 | ||
f1938f6e | 665 | writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride)); |
b60503ba | 666 | nvmeq->cq_head = head; |
82123460 | 667 | nvmeq->cq_phase = phase; |
b60503ba MW |
668 | |
669 | return IRQ_HANDLED; | |
670 | } | |
671 | ||
672 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
673 | { |
674 | irqreturn_t result; | |
675 | struct nvme_queue *nvmeq = data; | |
676 | spin_lock(&nvmeq->q_lock); | |
677 | result = nvme_process_cq(nvmeq); | |
678 | spin_unlock(&nvmeq->q_lock); | |
679 | return result; | |
680 | } | |
681 | ||
682 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
683 | { | |
684 | struct nvme_queue *nvmeq = data; | |
685 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
686 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
687 | return IRQ_NONE; | |
688 | return IRQ_WAKE_THREAD; | |
689 | } | |
690 | ||
3c0cf138 MW |
691 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
692 | { | |
693 | spin_lock_irq(&nvmeq->q_lock); | |
c2f5b650 | 694 | cancel_cmdid(nvmeq, cmdid, NULL); |
3c0cf138 MW |
695 | spin_unlock_irq(&nvmeq->q_lock); |
696 | } | |
697 | ||
c2f5b650 MW |
698 | struct sync_cmd_info { |
699 | struct task_struct *task; | |
700 | u32 result; | |
701 | int status; | |
702 | }; | |
703 | ||
5c1281a3 | 704 | static void sync_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
705 | struct nvme_completion *cqe) |
706 | { | |
707 | struct sync_cmd_info *cmdinfo = ctx; | |
708 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
709 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
710 | wake_up_process(cmdinfo->task); | |
711 | } | |
712 | ||
b60503ba MW |
713 | /* |
714 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
715 | * if the result is positive, it's an NVM Express status code | |
716 | */ | |
5d0f6131 VV |
717 | int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, |
718 | u32 *result, unsigned timeout) | |
b60503ba MW |
719 | { |
720 | int cmdid; | |
721 | struct sync_cmd_info cmdinfo; | |
722 | ||
723 | cmdinfo.task = current; | |
724 | cmdinfo.status = -EINTR; | |
725 | ||
c2f5b650 | 726 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion, |
e85248e5 | 727 | timeout); |
b60503ba MW |
728 | if (cmdid < 0) |
729 | return cmdid; | |
730 | cmd->common.command_id = cmdid; | |
731 | ||
3c0cf138 MW |
732 | set_current_state(TASK_KILLABLE); |
733 | nvme_submit_cmd(nvmeq, cmd); | |
b60503ba MW |
734 | schedule(); |
735 | ||
3c0cf138 MW |
736 | if (cmdinfo.status == -EINTR) { |
737 | nvme_abort_command(nvmeq, cmdid); | |
738 | return -EINTR; | |
739 | } | |
740 | ||
b60503ba MW |
741 | if (result) |
742 | *result = cmdinfo.result; | |
743 | ||
744 | return cmdinfo.status; | |
745 | } | |
746 | ||
5d0f6131 | 747 | int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
b60503ba MW |
748 | u32 *result) |
749 | { | |
e85248e5 | 750 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
751 | } |
752 | ||
753 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
754 | { | |
755 | int status; | |
756 | struct nvme_command c; | |
757 | ||
758 | memset(&c, 0, sizeof(c)); | |
759 | c.delete_queue.opcode = opcode; | |
760 | c.delete_queue.qid = cpu_to_le16(id); | |
761 | ||
762 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
763 | if (status) | |
764 | return -EIO; | |
765 | return 0; | |
766 | } | |
767 | ||
768 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
769 | struct nvme_queue *nvmeq) | |
770 | { | |
771 | int status; | |
772 | struct nvme_command c; | |
773 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
774 | ||
775 | memset(&c, 0, sizeof(c)); | |
776 | c.create_cq.opcode = nvme_admin_create_cq; | |
777 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
778 | c.create_cq.cqid = cpu_to_le16(qid); | |
779 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
780 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
781 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
782 | ||
783 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
784 | if (status) | |
785 | return -EIO; | |
786 | return 0; | |
787 | } | |
788 | ||
789 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
790 | struct nvme_queue *nvmeq) | |
791 | { | |
792 | int status; | |
793 | struct nvme_command c; | |
794 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
795 | ||
796 | memset(&c, 0, sizeof(c)); | |
797 | c.create_sq.opcode = nvme_admin_create_sq; | |
798 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
799 | c.create_sq.sqid = cpu_to_le16(qid); | |
800 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
801 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
802 | c.create_sq.cqid = cpu_to_le16(qid); | |
803 | ||
804 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
805 | if (status) | |
806 | return -EIO; | |
807 | return 0; | |
808 | } | |
809 | ||
810 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
811 | { | |
812 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
813 | } | |
814 | ||
815 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
816 | { | |
817 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
818 | } | |
819 | ||
5d0f6131 | 820 | int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
bc5fc7e4 MW |
821 | dma_addr_t dma_addr) |
822 | { | |
823 | struct nvme_command c; | |
824 | ||
825 | memset(&c, 0, sizeof(c)); | |
826 | c.identify.opcode = nvme_admin_identify; | |
827 | c.identify.nsid = cpu_to_le32(nsid); | |
828 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
829 | c.identify.cns = cpu_to_le32(cns); | |
830 | ||
831 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
832 | } | |
833 | ||
5d0f6131 | 834 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
08df1e05 | 835 | dma_addr_t dma_addr, u32 *result) |
bc5fc7e4 MW |
836 | { |
837 | struct nvme_command c; | |
838 | ||
839 | memset(&c, 0, sizeof(c)); | |
840 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 841 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
842 | c.features.prp1 = cpu_to_le64(dma_addr); |
843 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 844 | |
08df1e05 | 845 | return nvme_submit_admin_cmd(dev, &c, result); |
df348139 MW |
846 | } |
847 | ||
5d0f6131 VV |
848 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
849 | dma_addr_t dma_addr, u32 *result) | |
df348139 MW |
850 | { |
851 | struct nvme_command c; | |
852 | ||
853 | memset(&c, 0, sizeof(c)); | |
854 | c.features.opcode = nvme_admin_set_features; | |
855 | c.features.prp1 = cpu_to_le64(dma_addr); | |
856 | c.features.fid = cpu_to_le32(fid); | |
857 | c.features.dword11 = cpu_to_le32(dword11); | |
858 | ||
bc5fc7e4 MW |
859 | return nvme_submit_admin_cmd(dev, &c, result); |
860 | } | |
861 | ||
a09115b2 MW |
862 | /** |
863 | * nvme_cancel_ios - Cancel outstanding I/Os | |
864 | * @queue: The queue to cancel I/Os on | |
865 | * @timeout: True to only cancel I/Os which have timed out | |
866 | */ | |
867 | static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout) | |
868 | { | |
869 | int depth = nvmeq->q_depth - 1; | |
870 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
871 | unsigned long now = jiffies; | |
872 | int cmdid; | |
873 | ||
874 | for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) { | |
875 | void *ctx; | |
876 | nvme_completion_fn fn; | |
877 | static struct nvme_completion cqe = { | |
af2d9ca7 | 878 | .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1), |
a09115b2 MW |
879 | }; |
880 | ||
881 | if (timeout && !time_after(now, info[cmdid].timeout)) | |
882 | continue; | |
883 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid); | |
884 | ctx = cancel_cmdid(nvmeq, cmdid, &fn); | |
885 | fn(nvmeq->dev, ctx, &cqe); | |
886 | } | |
887 | } | |
888 | ||
9e866774 MW |
889 | static void nvme_free_queue_mem(struct nvme_queue *nvmeq) |
890 | { | |
891 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
892 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
893 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
894 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
895 | kfree(nvmeq); | |
896 | } | |
897 | ||
b60503ba MW |
898 | static void nvme_free_queue(struct nvme_dev *dev, int qid) |
899 | { | |
900 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
aba2080f | 901 | int vector = dev->entry[nvmeq->cq_vector].vector; |
b60503ba | 902 | |
a09115b2 MW |
903 | spin_lock_irq(&nvmeq->q_lock); |
904 | nvme_cancel_ios(nvmeq, false); | |
3295874b KB |
905 | while (bio_list_peek(&nvmeq->sq_cong)) { |
906 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
907 | bio_endio(bio, -EIO); | |
908 | } | |
a09115b2 MW |
909 | spin_unlock_irq(&nvmeq->q_lock); |
910 | ||
aba2080f MW |
911 | irq_set_affinity_hint(vector, NULL); |
912 | free_irq(vector, nvmeq); | |
b60503ba MW |
913 | |
914 | /* Don't tell the adapter to delete the admin queue */ | |
915 | if (qid) { | |
916 | adapter_delete_sq(dev, qid); | |
917 | adapter_delete_cq(dev, qid); | |
918 | } | |
919 | ||
9e866774 | 920 | nvme_free_queue_mem(nvmeq); |
b60503ba MW |
921 | } |
922 | ||
923 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
924 | int depth, int vector) | |
925 | { | |
926 | struct device *dmadev = &dev->pci_dev->dev; | |
a0cadb85 KB |
927 | unsigned extra = DIV_ROUND_UP(depth, 8) + (depth * |
928 | sizeof(struct nvme_cmd_info)); | |
b60503ba MW |
929 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
930 | if (!nvmeq) | |
931 | return NULL; | |
932 | ||
933 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
934 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
935 | if (!nvmeq->cqes) | |
936 | goto free_nvmeq; | |
937 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
938 | ||
939 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
940 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
941 | if (!nvmeq->sq_cmds) | |
942 | goto free_cqdma; | |
943 | ||
944 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 945 | nvmeq->dev = dev; |
b60503ba MW |
946 | spin_lock_init(&nvmeq->q_lock); |
947 | nvmeq->cq_head = 0; | |
82123460 | 948 | nvmeq->cq_phase = 1; |
b60503ba | 949 | init_waitqueue_head(&nvmeq->sq_full); |
1fa6aead | 950 | init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread); |
b60503ba | 951 | bio_list_init(&nvmeq->sq_cong); |
f1938f6e | 952 | nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)]; |
b60503ba MW |
953 | nvmeq->q_depth = depth; |
954 | nvmeq->cq_vector = vector; | |
955 | ||
956 | return nvmeq; | |
957 | ||
958 | free_cqdma: | |
959 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
960 | nvmeq->cq_dma_addr); | |
961 | free_nvmeq: | |
962 | kfree(nvmeq); | |
963 | return NULL; | |
964 | } | |
965 | ||
3001082c MW |
966 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
967 | const char *name) | |
968 | { | |
58ffacb5 MW |
969 | if (use_threaded_interrupts) |
970 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 971 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
972 | IRQF_DISABLED | IRQF_SHARED, |
973 | name, nvmeq); | |
3001082c MW |
974 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
975 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
976 | } | |
977 | ||
8d85fce7 GKH |
978 | static struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, int qid, |
979 | int cq_size, int vector) | |
b60503ba MW |
980 | { |
981 | int result; | |
982 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
983 | ||
3f85d50b | 984 | if (!nvmeq) |
6f0f5449 | 985 | return ERR_PTR(-ENOMEM); |
3f85d50b | 986 | |
b60503ba MW |
987 | result = adapter_alloc_cq(dev, qid, nvmeq); |
988 | if (result < 0) | |
989 | goto free_nvmeq; | |
990 | ||
991 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
992 | if (result < 0) | |
993 | goto release_cq; | |
994 | ||
3001082c | 995 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
996 | if (result < 0) |
997 | goto release_sq; | |
998 | ||
999 | return nvmeq; | |
1000 | ||
1001 | release_sq: | |
1002 | adapter_delete_sq(dev, qid); | |
1003 | release_cq: | |
1004 | adapter_delete_cq(dev, qid); | |
1005 | free_nvmeq: | |
1006 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
1007 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1008 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1009 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
1010 | kfree(nvmeq); | |
6f0f5449 | 1011 | return ERR_PTR(result); |
b60503ba MW |
1012 | } |
1013 | ||
8d85fce7 | 1014 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1015 | { |
9e866774 | 1016 | int result = 0; |
b60503ba | 1017 | u32 aqa; |
22605f96 MW |
1018 | u64 cap; |
1019 | unsigned long timeout; | |
b60503ba MW |
1020 | struct nvme_queue *nvmeq; |
1021 | ||
1022 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
1023 | ||
1024 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
1025 | if (!nvmeq) |
1026 | return -ENOMEM; | |
b60503ba MW |
1027 | |
1028 | aqa = nvmeq->q_depth - 1; | |
1029 | aqa |= aqa << 16; | |
1030 | ||
1031 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
1032 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
1033 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
7f53f9d2 | 1034 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba | 1035 | |
5911f200 | 1036 | writel(0, &dev->bar->cc); |
b60503ba MW |
1037 | writel(aqa, &dev->bar->aqa); |
1038 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1039 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
1040 | writel(dev->ctrl_config, &dev->bar->cc); | |
1041 | ||
22605f96 MW |
1042 | cap = readq(&dev->bar->cap); |
1043 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
f1938f6e | 1044 | dev->db_stride = NVME_CAP_STRIDE(cap); |
22605f96 | 1045 | |
9e866774 | 1046 | while (!result && !(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { |
b60503ba MW |
1047 | msleep(100); |
1048 | if (fatal_signal_pending(current)) | |
9e866774 | 1049 | result = -EINTR; |
22605f96 MW |
1050 | if (time_after(jiffies, timeout)) { |
1051 | dev_err(&dev->pci_dev->dev, | |
1052 | "Device not ready; aborting initialisation\n"); | |
9e866774 | 1053 | result = -ENODEV; |
22605f96 | 1054 | } |
b60503ba MW |
1055 | } |
1056 | ||
9e866774 MW |
1057 | if (result) { |
1058 | nvme_free_queue_mem(nvmeq); | |
1059 | return result; | |
1060 | } | |
1061 | ||
3001082c | 1062 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
1063 | dev->queues[0] = nvmeq; |
1064 | return result; | |
1065 | } | |
1066 | ||
5d0f6131 | 1067 | struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
eca18b23 | 1068 | unsigned long addr, unsigned length) |
b60503ba | 1069 | { |
36c14ed9 | 1070 | int i, err, count, nents, offset; |
7fc3cdab MW |
1071 | struct scatterlist *sg; |
1072 | struct page **pages; | |
eca18b23 | 1073 | struct nvme_iod *iod; |
36c14ed9 MW |
1074 | |
1075 | if (addr & 3) | |
eca18b23 | 1076 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1077 | if (!length) |
eca18b23 | 1078 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1079 | |
36c14ed9 | 1080 | offset = offset_in_page(addr); |
7fc3cdab MW |
1081 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1082 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
22fff826 DC |
1083 | if (!pages) |
1084 | return ERR_PTR(-ENOMEM); | |
36c14ed9 MW |
1085 | |
1086 | err = get_user_pages_fast(addr, count, 1, pages); | |
1087 | if (err < count) { | |
1088 | count = err; | |
1089 | err = -EFAULT; | |
1090 | goto put_pages; | |
1091 | } | |
7fc3cdab | 1092 | |
eca18b23 MW |
1093 | iod = nvme_alloc_iod(count, length, GFP_KERNEL); |
1094 | sg = iod->sg; | |
36c14ed9 | 1095 | sg_init_table(sg, count); |
d0ba1e49 MW |
1096 | for (i = 0; i < count; i++) { |
1097 | sg_set_page(&sg[i], pages[i], | |
1098 | min_t(int, length, PAGE_SIZE - offset), offset); | |
1099 | length -= (PAGE_SIZE - offset); | |
1100 | offset = 0; | |
7fc3cdab | 1101 | } |
fe304c43 | 1102 | sg_mark_end(&sg[i - 1]); |
1c2ad9fa | 1103 | iod->nents = count; |
7fc3cdab MW |
1104 | |
1105 | err = -ENOMEM; | |
1106 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
1107 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 | 1108 | if (!nents) |
eca18b23 | 1109 | goto free_iod; |
b60503ba | 1110 | |
7fc3cdab | 1111 | kfree(pages); |
eca18b23 | 1112 | return iod; |
b60503ba | 1113 | |
eca18b23 MW |
1114 | free_iod: |
1115 | kfree(iod); | |
7fc3cdab MW |
1116 | put_pages: |
1117 | for (i = 0; i < count; i++) | |
1118 | put_page(pages[i]); | |
1119 | kfree(pages); | |
eca18b23 | 1120 | return ERR_PTR(err); |
7fc3cdab | 1121 | } |
b60503ba | 1122 | |
5d0f6131 | 1123 | void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1c2ad9fa | 1124 | struct nvme_iod *iod) |
7fc3cdab | 1125 | { |
1c2ad9fa | 1126 | int i; |
b60503ba | 1127 | |
1c2ad9fa MW |
1128 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
1129 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
7fc3cdab | 1130 | |
1c2ad9fa MW |
1131 | for (i = 0; i < iod->nents; i++) |
1132 | put_page(sg_page(&iod->sg[i])); | |
7fc3cdab | 1133 | } |
b60503ba | 1134 | |
a53295b6 MW |
1135 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1136 | { | |
1137 | struct nvme_dev *dev = ns->dev; | |
1138 | struct nvme_queue *nvmeq; | |
1139 | struct nvme_user_io io; | |
1140 | struct nvme_command c; | |
1141 | unsigned length; | |
eca18b23 MW |
1142 | int status; |
1143 | struct nvme_iod *iod; | |
a53295b6 MW |
1144 | |
1145 | if (copy_from_user(&io, uio, sizeof(io))) | |
1146 | return -EFAULT; | |
6c7d4945 MW |
1147 | length = (io.nblocks + 1) << ns->lba_shift; |
1148 | ||
1149 | switch (io.opcode) { | |
1150 | case nvme_cmd_write: | |
1151 | case nvme_cmd_read: | |
6bbf1acd | 1152 | case nvme_cmd_compare: |
eca18b23 | 1153 | iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length); |
6413214c | 1154 | break; |
6c7d4945 | 1155 | default: |
6bbf1acd | 1156 | return -EINVAL; |
6c7d4945 MW |
1157 | } |
1158 | ||
eca18b23 MW |
1159 | if (IS_ERR(iod)) |
1160 | return PTR_ERR(iod); | |
a53295b6 MW |
1161 | |
1162 | memset(&c, 0, sizeof(c)); | |
1163 | c.rw.opcode = io.opcode; | |
1164 | c.rw.flags = io.flags; | |
6c7d4945 | 1165 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1166 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1167 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1168 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1169 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1170 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1171 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1172 | c.rw.appmask = cpu_to_le16(io.appmask); | |
a53295b6 | 1173 | /* XXX: metadata */ |
eca18b23 | 1174 | length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL); |
a53295b6 | 1175 | |
040a93b5 | 1176 | nvmeq = get_nvmeq(dev); |
fa922821 MW |
1177 | /* |
1178 | * Since nvme_submit_sync_cmd sleeps, we can't keep preemption | |
b1ad37ef MW |
1179 | * disabled. We may be preempted at any point, and be rescheduled |
1180 | * to a different CPU. That will cause cacheline bouncing, but no | |
1181 | * additional races since q_lock already protects against other CPUs. | |
1182 | */ | |
a53295b6 | 1183 | put_nvmeq(nvmeq); |
b77954cb MW |
1184 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1185 | status = -ENOMEM; | |
1186 | else | |
ff976d72 | 1187 | status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT); |
a53295b6 | 1188 | |
1c2ad9fa | 1189 | nvme_unmap_user_pages(dev, io.opcode & 1, iod); |
eca18b23 | 1190 | nvme_free_iod(dev, iod); |
a53295b6 MW |
1191 | return status; |
1192 | } | |
1193 | ||
50af8bae | 1194 | static int nvme_user_admin_cmd(struct nvme_dev *dev, |
6bbf1acd | 1195 | struct nvme_admin_cmd __user *ucmd) |
6ee44cdc | 1196 | { |
6bbf1acd | 1197 | struct nvme_admin_cmd cmd; |
6ee44cdc | 1198 | struct nvme_command c; |
eca18b23 | 1199 | int status, length; |
c7d36ab8 | 1200 | struct nvme_iod *uninitialized_var(iod); |
6ee44cdc | 1201 | |
6bbf1acd MW |
1202 | if (!capable(CAP_SYS_ADMIN)) |
1203 | return -EACCES; | |
1204 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1205 | return -EFAULT; |
6ee44cdc MW |
1206 | |
1207 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1208 | c.common.opcode = cmd.opcode; |
1209 | c.common.flags = cmd.flags; | |
1210 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1211 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1212 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1213 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1214 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1215 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1216 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1217 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1218 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1219 | ||
1220 | length = cmd.data_len; | |
1221 | if (cmd.data_len) { | |
49742188 MW |
1222 | iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr, |
1223 | length); | |
eca18b23 MW |
1224 | if (IS_ERR(iod)) |
1225 | return PTR_ERR(iod); | |
1226 | length = nvme_setup_prps(dev, &c.common, iod, length, | |
1227 | GFP_KERNEL); | |
6bbf1acd MW |
1228 | } |
1229 | ||
1230 | if (length != cmd.data_len) | |
b77954cb MW |
1231 | status = -ENOMEM; |
1232 | else | |
f4f117f6 | 1233 | status = nvme_submit_admin_cmd(dev, &c, &cmd.result); |
eca18b23 | 1234 | |
6bbf1acd | 1235 | if (cmd.data_len) { |
1c2ad9fa | 1236 | nvme_unmap_user_pages(dev, cmd.opcode & 1, iod); |
eca18b23 | 1237 | nvme_free_iod(dev, iod); |
6bbf1acd | 1238 | } |
f4f117f6 KB |
1239 | |
1240 | if (!status && copy_to_user(&ucmd->result, &cmd.result, | |
1241 | sizeof(cmd.result))) | |
1242 | status = -EFAULT; | |
1243 | ||
6ee44cdc MW |
1244 | return status; |
1245 | } | |
1246 | ||
b60503ba MW |
1247 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1248 | unsigned long arg) | |
1249 | { | |
1250 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1251 | ||
1252 | switch (cmd) { | |
6bbf1acd MW |
1253 | case NVME_IOCTL_ID: |
1254 | return ns->ns_id; | |
1255 | case NVME_IOCTL_ADMIN_CMD: | |
50af8bae | 1256 | return nvme_user_admin_cmd(ns->dev, (void __user *)arg); |
a53295b6 MW |
1257 | case NVME_IOCTL_SUBMIT_IO: |
1258 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1259 | case SG_GET_VERSION_NUM: |
1260 | return nvme_sg_get_version_num((void __user *)arg); | |
1261 | case SG_IO: | |
1262 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1263 | default: |
1264 | return -ENOTTY; | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | static const struct block_device_operations nvme_fops = { | |
1269 | .owner = THIS_MODULE, | |
1270 | .ioctl = nvme_ioctl, | |
49481682 | 1271 | .compat_ioctl = nvme_ioctl, |
b60503ba MW |
1272 | }; |
1273 | ||
1fa6aead MW |
1274 | static void nvme_resubmit_bios(struct nvme_queue *nvmeq) |
1275 | { | |
1276 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1277 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1278 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
1279 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
1280 | bio_list_add_head(&nvmeq->sq_cong, bio); | |
1281 | break; | |
1282 | } | |
3cb967c0 MW |
1283 | if (bio_list_empty(&nvmeq->sq_cong)) |
1284 | remove_wait_queue(&nvmeq->sq_full, | |
1285 | &nvmeq->sq_cong_wait); | |
1fa6aead MW |
1286 | } |
1287 | } | |
1288 | ||
1289 | static int nvme_kthread(void *data) | |
1290 | { | |
1291 | struct nvme_dev *dev; | |
1292 | ||
1293 | while (!kthread_should_stop()) { | |
1294 | __set_current_state(TASK_RUNNING); | |
1295 | spin_lock(&dev_list_lock); | |
1296 | list_for_each_entry(dev, &dev_list, node) { | |
1297 | int i; | |
1298 | for (i = 0; i < dev->queue_count; i++) { | |
1299 | struct nvme_queue *nvmeq = dev->queues[i]; | |
740216fc MW |
1300 | if (!nvmeq) |
1301 | continue; | |
1fa6aead MW |
1302 | spin_lock_irq(&nvmeq->q_lock); |
1303 | if (nvme_process_cq(nvmeq)) | |
1304 | printk("process_cq did something\n"); | |
a09115b2 | 1305 | nvme_cancel_ios(nvmeq, true); |
1fa6aead MW |
1306 | nvme_resubmit_bios(nvmeq); |
1307 | spin_unlock_irq(&nvmeq->q_lock); | |
1308 | } | |
1309 | } | |
1310 | spin_unlock(&dev_list_lock); | |
1311 | set_current_state(TASK_INTERRUPTIBLE); | |
acb7aa0d | 1312 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1313 | } |
1314 | return 0; | |
1315 | } | |
1316 | ||
5aff9382 MW |
1317 | static DEFINE_IDA(nvme_index_ida); |
1318 | ||
1319 | static int nvme_get_ns_idx(void) | |
1320 | { | |
1321 | int index, error; | |
1322 | ||
1323 | do { | |
1324 | if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL)) | |
1325 | return -1; | |
1326 | ||
1327 | spin_lock(&dev_list_lock); | |
1328 | error = ida_get_new(&nvme_index_ida, &index); | |
1329 | spin_unlock(&dev_list_lock); | |
1330 | } while (error == -EAGAIN); | |
1331 | ||
1332 | if (error) | |
1333 | index = -1; | |
1334 | return index; | |
1335 | } | |
1336 | ||
1337 | static void nvme_put_ns_idx(int index) | |
1338 | { | |
1339 | spin_lock(&dev_list_lock); | |
1340 | ida_remove(&nvme_index_ida, index); | |
1341 | spin_unlock(&dev_list_lock); | |
1342 | } | |
1343 | ||
0e5e4f0e KB |
1344 | static void nvme_config_discard(struct nvme_ns *ns) |
1345 | { | |
1346 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1347 | ns->queue->limits.discard_zeroes_data = 0; | |
1348 | ns->queue->limits.discard_alignment = logical_block_size; | |
1349 | ns->queue->limits.discard_granularity = logical_block_size; | |
1350 | ns->queue->limits.max_discard_sectors = 0xffffffff; | |
1351 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); | |
1352 | } | |
1353 | ||
5aff9382 | 1354 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid, |
b60503ba MW |
1355 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) |
1356 | { | |
1357 | struct nvme_ns *ns; | |
1358 | struct gendisk *disk; | |
1359 | int lbaf; | |
1360 | ||
1361 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1362 | return NULL; | |
1363 | ||
1364 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1365 | if (!ns) | |
1366 | return NULL; | |
1367 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1368 | if (!ns->queue) | |
1369 | goto out_free_ns; | |
4eeb9215 MW |
1370 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT; |
1371 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); | |
1372 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
b60503ba MW |
1373 | blk_queue_make_request(ns->queue, nvme_make_request); |
1374 | ns->dev = dev; | |
1375 | ns->queue->queuedata = ns; | |
1376 | ||
1377 | disk = alloc_disk(NVME_MINORS); | |
1378 | if (!disk) | |
1379 | goto out_free_queue; | |
5aff9382 | 1380 | ns->ns_id = nsid; |
b60503ba MW |
1381 | ns->disk = disk; |
1382 | lbaf = id->flbas & 0xf; | |
1383 | ns->lba_shift = id->lbaf[lbaf].ds; | |
e9ef4636 | 1384 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
1385 | if (dev->max_hw_sectors) |
1386 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
b60503ba MW |
1387 | |
1388 | disk->major = nvme_major; | |
1389 | disk->minors = NVME_MINORS; | |
5aff9382 | 1390 | disk->first_minor = NVME_MINORS * nvme_get_ns_idx(); |
b60503ba MW |
1391 | disk->fops = &nvme_fops; |
1392 | disk->private_data = ns; | |
1393 | disk->queue = ns->queue; | |
388f037f | 1394 | disk->driverfs_dev = &dev->pci_dev->dev; |
5aff9382 | 1395 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba MW |
1396 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); |
1397 | ||
0e5e4f0e KB |
1398 | if (dev->oncs & NVME_CTRL_ONCS_DSM) |
1399 | nvme_config_discard(ns); | |
1400 | ||
b60503ba MW |
1401 | return ns; |
1402 | ||
1403 | out_free_queue: | |
1404 | blk_cleanup_queue(ns->queue); | |
1405 | out_free_ns: | |
1406 | kfree(ns); | |
1407 | return NULL; | |
1408 | } | |
1409 | ||
1410 | static void nvme_ns_free(struct nvme_ns *ns) | |
1411 | { | |
5aff9382 | 1412 | int index = ns->disk->first_minor / NVME_MINORS; |
b60503ba | 1413 | put_disk(ns->disk); |
5aff9382 | 1414 | nvme_put_ns_idx(index); |
b60503ba MW |
1415 | blk_cleanup_queue(ns->queue); |
1416 | kfree(ns); | |
1417 | } | |
1418 | ||
b3b06812 | 1419 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1420 | { |
1421 | int status; | |
1422 | u32 result; | |
b3b06812 | 1423 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 1424 | |
df348139 | 1425 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 1426 | &result); |
b60503ba MW |
1427 | if (status) |
1428 | return -EIO; | |
1429 | return min(result & 0xffff, result >> 16) + 1; | |
1430 | } | |
1431 | ||
8d85fce7 | 1432 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1433 | { |
a0cadb85 | 1434 | int result, cpu, i, nr_io_queues, db_bar_size, q_depth; |
b60503ba | 1435 | |
b348b7d5 MW |
1436 | nr_io_queues = num_online_cpus(); |
1437 | result = set_queue_count(dev, nr_io_queues); | |
1b23484b MW |
1438 | if (result < 0) |
1439 | return result; | |
b348b7d5 MW |
1440 | if (result < nr_io_queues) |
1441 | nr_io_queues = result; | |
b60503ba | 1442 | |
1b23484b MW |
1443 | /* Deregister the admin queue's interrupt */ |
1444 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1445 | ||
f1938f6e MW |
1446 | db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3)); |
1447 | if (db_bar_size > 8192) { | |
1448 | iounmap(dev->bar); | |
1449 | dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0), | |
1450 | db_bar_size); | |
1451 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
1452 | dev->queues[0]->q_db = dev->dbs; | |
1453 | } | |
1454 | ||
b348b7d5 | 1455 | for (i = 0; i < nr_io_queues; i++) |
1b23484b MW |
1456 | dev->entry[i].entry = i; |
1457 | for (;;) { | |
b348b7d5 MW |
1458 | result = pci_enable_msix(dev->pci_dev, dev->entry, |
1459 | nr_io_queues); | |
1b23484b MW |
1460 | if (result == 0) { |
1461 | break; | |
1462 | } else if (result > 0) { | |
b348b7d5 | 1463 | nr_io_queues = result; |
1b23484b MW |
1464 | continue; |
1465 | } else { | |
b348b7d5 | 1466 | nr_io_queues = 1; |
1b23484b MW |
1467 | break; |
1468 | } | |
1469 | } | |
1470 | ||
1471 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
1472 | /* XXX: handle failure here */ | |
1473 | ||
1474 | cpu = cpumask_first(cpu_online_mask); | |
b348b7d5 | 1475 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1476 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); |
1477 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1478 | } | |
1479 | ||
a0cadb85 KB |
1480 | q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1, |
1481 | NVME_Q_DEPTH); | |
b348b7d5 | 1482 | for (i = 0; i < nr_io_queues; i++) { |
a0cadb85 | 1483 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i); |
6f0f5449 MW |
1484 | if (IS_ERR(dev->queues[i + 1])) |
1485 | return PTR_ERR(dev->queues[i + 1]); | |
1b23484b MW |
1486 | dev->queue_count++; |
1487 | } | |
b60503ba | 1488 | |
9ecdc946 MW |
1489 | for (; i < num_possible_cpus(); i++) { |
1490 | int target = i % rounddown_pow_of_two(dev->queue_count - 1); | |
1491 | dev->queues[i + 1] = dev->queues[target + 1]; | |
1492 | } | |
1493 | ||
b60503ba MW |
1494 | return 0; |
1495 | } | |
1496 | ||
1497 | static void nvme_free_queues(struct nvme_dev *dev) | |
1498 | { | |
1499 | int i; | |
1500 | ||
1501 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1502 | nvme_free_queue(dev, i); | |
1503 | } | |
1504 | ||
422ef0c7 MW |
1505 | /* |
1506 | * Return: error value if an error occurred setting up the queues or calling | |
1507 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1508 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1509 | * failures should be reported. | |
1510 | */ | |
8d85fce7 | 1511 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba MW |
1512 | { |
1513 | int res, nn, i; | |
1514 | struct nvme_ns *ns, *next; | |
51814232 | 1515 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 MW |
1516 | struct nvme_id_ns *id_ns; |
1517 | void *mem; | |
b60503ba | 1518 | dma_addr_t dma_addr; |
b60503ba MW |
1519 | |
1520 | res = nvme_setup_io_queues(dev); | |
1521 | if (res) | |
1522 | return res; | |
1523 | ||
bc5fc7e4 | 1524 | mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, |
b60503ba MW |
1525 | GFP_KERNEL); |
1526 | ||
bc5fc7e4 | 1527 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba MW |
1528 | if (res) { |
1529 | res = -EIO; | |
1530 | goto out_free; | |
1531 | } | |
1532 | ||
bc5fc7e4 | 1533 | ctrl = mem; |
51814232 | 1534 | nn = le32_to_cpup(&ctrl->nn); |
0e5e4f0e | 1535 | dev->oncs = le16_to_cpup(&ctrl->oncs); |
51814232 MW |
1536 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
1537 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1538 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
8fc23e03 KB |
1539 | if (ctrl->mdts) { |
1540 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; | |
1541 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); | |
1542 | } | |
b60503ba | 1543 | |
bc5fc7e4 | 1544 | id_ns = mem; |
2b2c1896 | 1545 | for (i = 1; i <= nn; i++) { |
bc5fc7e4 | 1546 | res = nvme_identify(dev, i, 0, dma_addr); |
b60503ba MW |
1547 | if (res) |
1548 | continue; | |
1549 | ||
bc5fc7e4 | 1550 | if (id_ns->ncap == 0) |
b60503ba MW |
1551 | continue; |
1552 | ||
bc5fc7e4 | 1553 | res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i, |
08df1e05 | 1554 | dma_addr + 4096, NULL); |
b60503ba | 1555 | if (res) |
12209036 | 1556 | memset(mem + 4096, 0, 4096); |
b60503ba | 1557 | |
bc5fc7e4 | 1558 | ns = nvme_alloc_ns(dev, i, mem, mem + 4096); |
b60503ba MW |
1559 | if (ns) |
1560 | list_add_tail(&ns->list, &dev->namespaces); | |
1561 | } | |
1562 | list_for_each_entry(ns, &dev->namespaces, list) | |
1563 | add_disk(ns->disk); | |
422ef0c7 | 1564 | res = 0; |
bc5fc7e4 | 1565 | goto out; |
b60503ba MW |
1566 | |
1567 | out_free: | |
1568 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1569 | list_del(&ns->list); | |
1570 | nvme_ns_free(ns); | |
1571 | } | |
1572 | ||
bc5fc7e4 | 1573 | out: |
684f5c20 | 1574 | dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr); |
b60503ba MW |
1575 | return res; |
1576 | } | |
1577 | ||
1578 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1579 | { | |
1580 | struct nvme_ns *ns, *next; | |
1581 | ||
1fa6aead MW |
1582 | spin_lock(&dev_list_lock); |
1583 | list_del(&dev->node); | |
1584 | spin_unlock(&dev_list_lock); | |
1585 | ||
b60503ba MW |
1586 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { |
1587 | list_del(&ns->list); | |
1588 | del_gendisk(ns->disk); | |
1589 | nvme_ns_free(ns); | |
1590 | } | |
1591 | ||
1592 | nvme_free_queues(dev); | |
1593 | ||
1594 | return 0; | |
1595 | } | |
1596 | ||
091b6092 MW |
1597 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1598 | { | |
1599 | struct device *dmadev = &dev->pci_dev->dev; | |
1600 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
1601 | PAGE_SIZE, PAGE_SIZE, 0); | |
1602 | if (!dev->prp_page_pool) | |
1603 | return -ENOMEM; | |
1604 | ||
99802a7a MW |
1605 | /* Optimisation for I/Os between 4k and 128k */ |
1606 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
1607 | 256, 256, 0); | |
1608 | if (!dev->prp_small_pool) { | |
1609 | dma_pool_destroy(dev->prp_page_pool); | |
1610 | return -ENOMEM; | |
1611 | } | |
091b6092 MW |
1612 | return 0; |
1613 | } | |
1614 | ||
1615 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1616 | { | |
1617 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1618 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1619 | } |
1620 | ||
cd58ad7d QSA |
1621 | static DEFINE_IDA(nvme_instance_ida); |
1622 | ||
1623 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 1624 | { |
cd58ad7d QSA |
1625 | int instance, error; |
1626 | ||
1627 | do { | |
1628 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
1629 | return -ENODEV; | |
1630 | ||
1631 | spin_lock(&dev_list_lock); | |
1632 | error = ida_get_new(&nvme_instance_ida, &instance); | |
1633 | spin_unlock(&dev_list_lock); | |
1634 | } while (error == -EAGAIN); | |
1635 | ||
1636 | if (error) | |
1637 | return -ENODEV; | |
1638 | ||
1639 | dev->instance = instance; | |
1640 | return 0; | |
b60503ba MW |
1641 | } |
1642 | ||
1643 | static void nvme_release_instance(struct nvme_dev *dev) | |
1644 | { | |
cd58ad7d QSA |
1645 | spin_lock(&dev_list_lock); |
1646 | ida_remove(&nvme_instance_ida, dev->instance); | |
1647 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
1648 | } |
1649 | ||
8d85fce7 | 1650 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 1651 | { |
574e8b95 | 1652 | int bars, result = -ENOMEM; |
b60503ba MW |
1653 | struct nvme_dev *dev; |
1654 | ||
1655 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1656 | if (!dev) | |
1657 | return -ENOMEM; | |
1658 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1659 | GFP_KERNEL); | |
1660 | if (!dev->entry) | |
1661 | goto free; | |
1b23484b MW |
1662 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1663 | GFP_KERNEL); | |
b60503ba MW |
1664 | if (!dev->queues) |
1665 | goto free; | |
1666 | ||
0ee5a7d7 SMM |
1667 | if (pci_enable_device_mem(pdev)) |
1668 | goto free; | |
f64d3365 | 1669 | pci_set_master(pdev); |
574e8b95 MW |
1670 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1671 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1672 | goto disable; | |
0ee5a7d7 | 1673 | |
b60503ba MW |
1674 | INIT_LIST_HEAD(&dev->namespaces); |
1675 | dev->pci_dev = pdev; | |
1676 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1677 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1678 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
cd58ad7d QSA |
1679 | result = nvme_set_instance(dev); |
1680 | if (result) | |
1681 | goto disable; | |
1682 | ||
53c9577e | 1683 | dev->entry[0].vector = pdev->irq; |
b60503ba | 1684 | |
091b6092 MW |
1685 | result = nvme_setup_prp_pools(dev); |
1686 | if (result) | |
1687 | goto disable_msix; | |
1688 | ||
b60503ba MW |
1689 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1690 | if (!dev->bar) { | |
1691 | result = -ENOMEM; | |
574e8b95 | 1692 | goto disable_msix; |
b60503ba MW |
1693 | } |
1694 | ||
1695 | result = nvme_configure_admin_queue(dev); | |
1696 | if (result) | |
1697 | goto unmap; | |
1698 | dev->queue_count++; | |
1699 | ||
1fa6aead MW |
1700 | spin_lock(&dev_list_lock); |
1701 | list_add(&dev->node, &dev_list); | |
1702 | spin_unlock(&dev_list_lock); | |
1703 | ||
740216fc MW |
1704 | result = nvme_dev_add(dev); |
1705 | if (result) | |
1706 | goto delete; | |
1707 | ||
b60503ba MW |
1708 | return 0; |
1709 | ||
1710 | delete: | |
740216fc MW |
1711 | spin_lock(&dev_list_lock); |
1712 | list_del(&dev->node); | |
1713 | spin_unlock(&dev_list_lock); | |
1714 | ||
b60503ba MW |
1715 | nvme_free_queues(dev); |
1716 | unmap: | |
1717 | iounmap(dev->bar); | |
574e8b95 | 1718 | disable_msix: |
b60503ba MW |
1719 | pci_disable_msix(pdev); |
1720 | nvme_release_instance(dev); | |
091b6092 | 1721 | nvme_release_prp_pools(dev); |
574e8b95 | 1722 | disable: |
0ee5a7d7 | 1723 | pci_disable_device(pdev); |
574e8b95 | 1724 | pci_release_regions(pdev); |
b60503ba MW |
1725 | free: |
1726 | kfree(dev->queues); | |
1727 | kfree(dev->entry); | |
1728 | kfree(dev); | |
1729 | return result; | |
1730 | } | |
1731 | ||
8d85fce7 | 1732 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
1733 | { |
1734 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1735 | nvme_dev_remove(dev); | |
1736 | pci_disable_msix(pdev); | |
1737 | iounmap(dev->bar); | |
1738 | nvme_release_instance(dev); | |
091b6092 | 1739 | nvme_release_prp_pools(dev); |
0ee5a7d7 | 1740 | pci_disable_device(pdev); |
574e8b95 | 1741 | pci_release_regions(pdev); |
b60503ba MW |
1742 | kfree(dev->queues); |
1743 | kfree(dev->entry); | |
1744 | kfree(dev); | |
1745 | } | |
1746 | ||
1747 | /* These functions are yet to be implemented */ | |
1748 | #define nvme_error_detected NULL | |
1749 | #define nvme_dump_registers NULL | |
1750 | #define nvme_link_reset NULL | |
1751 | #define nvme_slot_reset NULL | |
1752 | #define nvme_error_resume NULL | |
1753 | #define nvme_suspend NULL | |
1754 | #define nvme_resume NULL | |
1755 | ||
1d352035 | 1756 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
1757 | .error_detected = nvme_error_detected, |
1758 | .mmio_enabled = nvme_dump_registers, | |
1759 | .link_reset = nvme_link_reset, | |
1760 | .slot_reset = nvme_slot_reset, | |
1761 | .resume = nvme_error_resume, | |
1762 | }; | |
1763 | ||
1764 | /* Move to pci_ids.h later */ | |
1765 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1766 | ||
1767 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1768 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1769 | { 0, } | |
1770 | }; | |
1771 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1772 | ||
1773 | static struct pci_driver nvme_driver = { | |
1774 | .name = "nvme", | |
1775 | .id_table = nvme_id_table, | |
1776 | .probe = nvme_probe, | |
8d85fce7 | 1777 | .remove = nvme_remove, |
b60503ba MW |
1778 | .suspend = nvme_suspend, |
1779 | .resume = nvme_resume, | |
1780 | .err_handler = &nvme_err_handler, | |
1781 | }; | |
1782 | ||
1783 | static int __init nvme_init(void) | |
1784 | { | |
0ac13140 | 1785 | int result; |
1fa6aead MW |
1786 | |
1787 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1788 | if (IS_ERR(nvme_thread)) | |
1789 | return PTR_ERR(nvme_thread); | |
b60503ba | 1790 | |
5c42ea16 KB |
1791 | result = register_blkdev(nvme_major, "nvme"); |
1792 | if (result < 0) | |
1fa6aead | 1793 | goto kill_kthread; |
5c42ea16 | 1794 | else if (result > 0) |
0ac13140 | 1795 | nvme_major = result; |
b60503ba MW |
1796 | |
1797 | result = pci_register_driver(&nvme_driver); | |
1fa6aead MW |
1798 | if (result) |
1799 | goto unregister_blkdev; | |
1800 | return 0; | |
b60503ba | 1801 | |
1fa6aead | 1802 | unregister_blkdev: |
b60503ba | 1803 | unregister_blkdev(nvme_major, "nvme"); |
1fa6aead MW |
1804 | kill_kthread: |
1805 | kthread_stop(nvme_thread); | |
b60503ba MW |
1806 | return result; |
1807 | } | |
1808 | ||
1809 | static void __exit nvme_exit(void) | |
1810 | { | |
1811 | pci_unregister_driver(&nvme_driver); | |
1812 | unregister_blkdev(nvme_major, "nvme"); | |
1fa6aead | 1813 | kthread_stop(nvme_thread); |
b60503ba MW |
1814 | } |
1815 | ||
1816 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1817 | MODULE_LICENSE("GPL"); | |
366e8217 | 1818 | MODULE_VERSION("0.8"); |
b60503ba MW |
1819 | module_init(nvme_init); |
1820 | module_exit(nvme_exit); |