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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
8de05535 | 21 | #include <linux/bitops.h> |
b60503ba | 22 | #include <linux/blkdev.h> |
fd63e9ce | 23 | #include <linux/delay.h> |
b60503ba MW |
24 | #include <linux/errno.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/genhd.h> | |
5aff9382 | 27 | #include <linux/idr.h> |
b60503ba MW |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kdev_t.h> | |
1fa6aead | 32 | #include <linux/kthread.h> |
b60503ba MW |
33 | #include <linux/kernel.h> |
34 | #include <linux/mm.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/pci.h> | |
be7b6275 | 38 | #include <linux/poison.h> |
c3bfe717 | 39 | #include <linux/ptrace.h> |
b60503ba MW |
40 | #include <linux/sched.h> |
41 | #include <linux/slab.h> | |
42 | #include <linux/types.h> | |
5d0f6131 | 43 | #include <scsi/sg.h> |
797a796a HM |
44 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
45 | ||
b60503ba MW |
46 | #define NVME_Q_DEPTH 1024 |
47 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
48 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
49 | #define NVME_MINORS 64 | |
e85248e5 | 50 | #define ADMIN_TIMEOUT (60 * HZ) |
b60503ba MW |
51 | |
52 | static int nvme_major; | |
53 | module_param(nvme_major, int, 0); | |
54 | ||
58ffacb5 MW |
55 | static int use_threaded_interrupts; |
56 | module_param(use_threaded_interrupts, int, 0); | |
57 | ||
1fa6aead MW |
58 | static DEFINE_SPINLOCK(dev_list_lock); |
59 | static LIST_HEAD(dev_list); | |
60 | static struct task_struct *nvme_thread; | |
61 | ||
b60503ba MW |
62 | /* |
63 | * An NVM Express queue. Each device has at least two (one for admin | |
64 | * commands and one for I/O commands). | |
65 | */ | |
66 | struct nvme_queue { | |
67 | struct device *q_dmadev; | |
091b6092 | 68 | struct nvme_dev *dev; |
b60503ba MW |
69 | spinlock_t q_lock; |
70 | struct nvme_command *sq_cmds; | |
71 | volatile struct nvme_completion *cqes; | |
72 | dma_addr_t sq_dma_addr; | |
73 | dma_addr_t cq_dma_addr; | |
74 | wait_queue_head_t sq_full; | |
1fa6aead | 75 | wait_queue_t sq_cong_wait; |
b60503ba MW |
76 | struct bio_list sq_cong; |
77 | u32 __iomem *q_db; | |
78 | u16 q_depth; | |
79 | u16 cq_vector; | |
80 | u16 sq_head; | |
81 | u16 sq_tail; | |
82 | u16 cq_head; | |
e9539f47 MW |
83 | u8 cq_phase; |
84 | u8 cqe_seen; | |
b60503ba MW |
85 | unsigned long cmdid_data[]; |
86 | }; | |
87 | ||
88 | /* | |
89 | * Check we didin't inadvertently grow the command struct | |
90 | */ | |
91 | static inline void _nvme_check_size(void) | |
92 | { | |
93 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
94 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
95 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
96 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
97 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 98 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
b60503ba MW |
99 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
100 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
101 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
102 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 103 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
104 | } |
105 | ||
5c1281a3 | 106 | typedef void (*nvme_completion_fn)(struct nvme_dev *, void *, |
c2f5b650 MW |
107 | struct nvme_completion *); |
108 | ||
e85248e5 | 109 | struct nvme_cmd_info { |
c2f5b650 MW |
110 | nvme_completion_fn fn; |
111 | void *ctx; | |
e85248e5 MW |
112 | unsigned long timeout; |
113 | }; | |
114 | ||
115 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
116 | { | |
117 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
118 | } | |
119 | ||
b60503ba | 120 | /** |
714a7a22 MW |
121 | * alloc_cmdid() - Allocate a Command ID |
122 | * @nvmeq: The queue that will be used for this command | |
123 | * @ctx: A pointer that will be passed to the handler | |
c2f5b650 | 124 | * @handler: The function to call on completion |
b60503ba MW |
125 | * |
126 | * Allocate a Command ID for a queue. The data passed in will | |
127 | * be passed to the completion handler. This is implemented by using | |
128 | * the bottom two bits of the ctx pointer to store the handler ID. | |
129 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
130 | * We can change this if it becomes a problem. | |
184d2944 MW |
131 | * |
132 | * May be called with local interrupts disabled and the q_lock held, | |
133 | * or with interrupts enabled and no locks held. | |
b60503ba | 134 | */ |
c2f5b650 MW |
135 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, |
136 | nvme_completion_fn handler, unsigned timeout) | |
b60503ba | 137 | { |
e6d15f79 | 138 | int depth = nvmeq->q_depth - 1; |
e85248e5 | 139 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
140 | int cmdid; |
141 | ||
b60503ba MW |
142 | do { |
143 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
144 | if (cmdid >= depth) | |
145 | return -EBUSY; | |
146 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
147 | ||
c2f5b650 MW |
148 | info[cmdid].fn = handler; |
149 | info[cmdid].ctx = ctx; | |
e85248e5 | 150 | info[cmdid].timeout = jiffies + timeout; |
b60503ba MW |
151 | return cmdid; |
152 | } | |
153 | ||
154 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
c2f5b650 | 155 | nvme_completion_fn handler, unsigned timeout) |
b60503ba MW |
156 | { |
157 | int cmdid; | |
158 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 159 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
160 | return (cmdid < 0) ? -EINTR : cmdid; |
161 | } | |
162 | ||
c2f5b650 MW |
163 | /* Special values must be less than 0x1000 */ |
164 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
165 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
166 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
167 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
00df5cb4 | 168 | #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE) |
be7b6275 | 169 | |
5c1281a3 | 170 | static void special_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
171 | struct nvme_completion *cqe) |
172 | { | |
173 | if (ctx == CMD_CTX_CANCELLED) | |
174 | return; | |
175 | if (ctx == CMD_CTX_FLUSH) | |
176 | return; | |
177 | if (ctx == CMD_CTX_COMPLETED) { | |
5c1281a3 | 178 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
179 | "completed id %d twice on queue %d\n", |
180 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
181 | return; | |
182 | } | |
183 | if (ctx == CMD_CTX_INVALID) { | |
5c1281a3 | 184 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
185 | "invalid id %d completed on queue %d\n", |
186 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
187 | return; | |
188 | } | |
189 | ||
5c1281a3 | 190 | dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
191 | } |
192 | ||
184d2944 MW |
193 | /* |
194 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
195 | */ | |
c2f5b650 MW |
196 | static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid, |
197 | nvme_completion_fn *fn) | |
b60503ba | 198 | { |
c2f5b650 | 199 | void *ctx; |
e85248e5 | 200 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 201 | |
c2f5b650 MW |
202 | if (cmdid >= nvmeq->q_depth) { |
203 | *fn = special_completion; | |
48e3d398 | 204 | return CMD_CTX_INVALID; |
c2f5b650 | 205 | } |
859361a2 KB |
206 | if (fn) |
207 | *fn = info[cmdid].fn; | |
c2f5b650 MW |
208 | ctx = info[cmdid].ctx; |
209 | info[cmdid].fn = special_completion; | |
e85248e5 | 210 | info[cmdid].ctx = CMD_CTX_COMPLETED; |
b60503ba MW |
211 | clear_bit(cmdid, nvmeq->cmdid_data); |
212 | wake_up(&nvmeq->sq_full); | |
c2f5b650 | 213 | return ctx; |
b60503ba MW |
214 | } |
215 | ||
c2f5b650 MW |
216 | static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid, |
217 | nvme_completion_fn *fn) | |
3c0cf138 | 218 | { |
c2f5b650 | 219 | void *ctx; |
e85248e5 | 220 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
c2f5b650 MW |
221 | if (fn) |
222 | *fn = info[cmdid].fn; | |
223 | ctx = info[cmdid].ctx; | |
224 | info[cmdid].fn = special_completion; | |
e85248e5 | 225 | info[cmdid].ctx = CMD_CTX_CANCELLED; |
c2f5b650 | 226 | return ctx; |
3c0cf138 MW |
227 | } |
228 | ||
5d0f6131 | 229 | struct nvme_queue *get_nvmeq(struct nvme_dev *dev) |
b60503ba | 230 | { |
040a93b5 | 231 | return dev->queues[get_cpu() + 1]; |
b60503ba MW |
232 | } |
233 | ||
5d0f6131 | 234 | void put_nvmeq(struct nvme_queue *nvmeq) |
b60503ba | 235 | { |
1b23484b | 236 | put_cpu(); |
b60503ba MW |
237 | } |
238 | ||
239 | /** | |
714a7a22 | 240 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
241 | * @nvmeq: The queue to use |
242 | * @cmd: The command to send | |
243 | * | |
244 | * Safe to use from interrupt context | |
245 | */ | |
246 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
247 | { | |
248 | unsigned long flags; | |
249 | u16 tail; | |
b60503ba MW |
250 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
251 | tail = nvmeq->sq_tail; | |
252 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
b60503ba MW |
253 | if (++tail == nvmeq->q_depth) |
254 | tail = 0; | |
7547881d | 255 | writel(tail, nvmeq->q_db); |
b60503ba MW |
256 | nvmeq->sq_tail = tail; |
257 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
eca18b23 | 262 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 263 | { |
eca18b23 | 264 | return ((void *)iod) + iod->offset; |
e025344c SMM |
265 | } |
266 | ||
eca18b23 MW |
267 | /* |
268 | * Will slightly overestimate the number of pages needed. This is OK | |
269 | * as it only leads to a small amount of wasted memory for the lifetime of | |
270 | * the I/O. | |
271 | */ | |
272 | static int nvme_npages(unsigned size) | |
273 | { | |
274 | unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE); | |
275 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
276 | } | |
b60503ba | 277 | |
eca18b23 MW |
278 | static struct nvme_iod * |
279 | nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp) | |
b60503ba | 280 | { |
eca18b23 MW |
281 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
282 | sizeof(__le64 *) * nvme_npages(nbytes) + | |
283 | sizeof(struct scatterlist) * nseg, gfp); | |
284 | ||
285 | if (iod) { | |
286 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
287 | iod->npages = -1; | |
288 | iod->length = nbytes; | |
2b196034 | 289 | iod->nents = 0; |
6198221f | 290 | iod->start_time = jiffies; |
eca18b23 MW |
291 | } |
292 | ||
293 | return iod; | |
b60503ba MW |
294 | } |
295 | ||
5d0f6131 | 296 | void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 297 | { |
eca18b23 MW |
298 | const int last_prp = PAGE_SIZE / 8 - 1; |
299 | int i; | |
300 | __le64 **list = iod_list(iod); | |
301 | dma_addr_t prp_dma = iod->first_dma; | |
302 | ||
303 | if (iod->npages == 0) | |
304 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
305 | for (i = 0; i < iod->npages; i++) { | |
306 | __le64 *prp_list = list[i]; | |
307 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
308 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
309 | prp_dma = next_prp_dma; | |
310 | } | |
311 | kfree(iod); | |
b60503ba MW |
312 | } |
313 | ||
6198221f KB |
314 | static void nvme_start_io_acct(struct bio *bio) |
315 | { | |
316 | struct gendisk *disk = bio->bi_bdev->bd_disk; | |
317 | const int rw = bio_data_dir(bio); | |
318 | int cpu = part_stat_lock(); | |
319 | part_round_stats(cpu, &disk->part0); | |
320 | part_stat_inc(cpu, &disk->part0, ios[rw]); | |
321 | part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio)); | |
322 | part_inc_in_flight(&disk->part0, rw); | |
323 | part_stat_unlock(); | |
324 | } | |
325 | ||
326 | static void nvme_end_io_acct(struct bio *bio, unsigned long start_time) | |
327 | { | |
328 | struct gendisk *disk = bio->bi_bdev->bd_disk; | |
329 | const int rw = bio_data_dir(bio); | |
330 | unsigned long duration = jiffies - start_time; | |
331 | int cpu = part_stat_lock(); | |
332 | part_stat_add(cpu, &disk->part0, ticks[rw], duration); | |
333 | part_round_stats(cpu, &disk->part0); | |
334 | part_dec_in_flight(&disk->part0, rw); | |
335 | part_stat_unlock(); | |
336 | } | |
337 | ||
5c1281a3 | 338 | static void bio_completion(struct nvme_dev *dev, void *ctx, |
b60503ba MW |
339 | struct nvme_completion *cqe) |
340 | { | |
eca18b23 MW |
341 | struct nvme_iod *iod = ctx; |
342 | struct bio *bio = iod->private; | |
b60503ba MW |
343 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
344 | ||
2b196034 KB |
345 | if (iod->nents) |
346 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, | |
b60503ba | 347 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
6198221f KB |
348 | |
349 | nvme_end_io_acct(bio, iod->start_time); | |
eca18b23 | 350 | nvme_free_iod(dev, iod); |
427e9708 | 351 | if (status) |
1ad2f893 | 352 | bio_endio(bio, -EIO); |
427e9708 | 353 | else |
1ad2f893 | 354 | bio_endio(bio, 0); |
b60503ba MW |
355 | } |
356 | ||
184d2944 | 357 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
5d0f6131 VV |
358 | int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd, |
359 | struct nvme_iod *iod, int total_len, gfp_t gfp) | |
ff22b54f | 360 | { |
99802a7a | 361 | struct dma_pool *pool; |
eca18b23 MW |
362 | int length = total_len; |
363 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
364 | int dma_len = sg_dma_len(sg); |
365 | u64 dma_addr = sg_dma_address(sg); | |
366 | int offset = offset_in_page(dma_addr); | |
e025344c | 367 | __le64 *prp_list; |
eca18b23 | 368 | __le64 **list = iod_list(iod); |
e025344c | 369 | dma_addr_t prp_dma; |
eca18b23 | 370 | int nprps, i; |
ff22b54f MW |
371 | |
372 | cmd->prp1 = cpu_to_le64(dma_addr); | |
373 | length -= (PAGE_SIZE - offset); | |
374 | if (length <= 0) | |
eca18b23 | 375 | return total_len; |
ff22b54f MW |
376 | |
377 | dma_len -= (PAGE_SIZE - offset); | |
378 | if (dma_len) { | |
379 | dma_addr += (PAGE_SIZE - offset); | |
380 | } else { | |
381 | sg = sg_next(sg); | |
382 | dma_addr = sg_dma_address(sg); | |
383 | dma_len = sg_dma_len(sg); | |
384 | } | |
385 | ||
386 | if (length <= PAGE_SIZE) { | |
387 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 | 388 | return total_len; |
e025344c SMM |
389 | } |
390 | ||
391 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
99802a7a MW |
392 | if (nprps <= (256 / 8)) { |
393 | pool = dev->prp_small_pool; | |
eca18b23 | 394 | iod->npages = 0; |
99802a7a MW |
395 | } else { |
396 | pool = dev->prp_page_pool; | |
eca18b23 | 397 | iod->npages = 1; |
99802a7a MW |
398 | } |
399 | ||
b77954cb MW |
400 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
401 | if (!prp_list) { | |
402 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 MW |
403 | iod->npages = -1; |
404 | return (total_len - length) + PAGE_SIZE; | |
b77954cb | 405 | } |
eca18b23 MW |
406 | list[0] = prp_list; |
407 | iod->first_dma = prp_dma; | |
e025344c SMM |
408 | cmd->prp2 = cpu_to_le64(prp_dma); |
409 | i = 0; | |
410 | for (;;) { | |
7523d834 | 411 | if (i == PAGE_SIZE / 8) { |
e025344c | 412 | __le64 *old_prp_list = prp_list; |
b77954cb | 413 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
414 | if (!prp_list) |
415 | return total_len - length; | |
416 | list[iod->npages++] = prp_list; | |
7523d834 MW |
417 | prp_list[0] = old_prp_list[i - 1]; |
418 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
419 | i = 1; | |
e025344c SMM |
420 | } |
421 | prp_list[i++] = cpu_to_le64(dma_addr); | |
422 | dma_len -= PAGE_SIZE; | |
423 | dma_addr += PAGE_SIZE; | |
424 | length -= PAGE_SIZE; | |
425 | if (length <= 0) | |
426 | break; | |
427 | if (dma_len > 0) | |
428 | continue; | |
429 | BUG_ON(dma_len < 0); | |
430 | sg = sg_next(sg); | |
431 | dma_addr = sg_dma_address(sg); | |
432 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
433 | } |
434 | ||
eca18b23 | 435 | return total_len; |
ff22b54f MW |
436 | } |
437 | ||
427e9708 KB |
438 | struct nvme_bio_pair { |
439 | struct bio b1, b2, *parent; | |
440 | struct bio_vec *bv1, *bv2; | |
441 | int err; | |
442 | atomic_t cnt; | |
443 | }; | |
444 | ||
445 | static void nvme_bio_pair_endio(struct bio *bio, int err) | |
446 | { | |
447 | struct nvme_bio_pair *bp = bio->bi_private; | |
448 | ||
449 | if (err) | |
450 | bp->err = err; | |
451 | ||
452 | if (atomic_dec_and_test(&bp->cnt)) { | |
453 | bio_endio(bp->parent, bp->err); | |
1b56749e KB |
454 | kfree(bp->bv1); |
455 | kfree(bp->bv2); | |
427e9708 KB |
456 | kfree(bp); |
457 | } | |
458 | } | |
459 | ||
460 | static struct nvme_bio_pair *nvme_bio_split(struct bio *bio, int idx, | |
461 | int len, int offset) | |
462 | { | |
463 | struct nvme_bio_pair *bp; | |
464 | ||
465 | BUG_ON(len > bio->bi_size); | |
466 | BUG_ON(idx > bio->bi_vcnt); | |
467 | ||
468 | bp = kmalloc(sizeof(*bp), GFP_ATOMIC); | |
469 | if (!bp) | |
470 | return NULL; | |
471 | bp->err = 0; | |
472 | ||
473 | bp->b1 = *bio; | |
474 | bp->b2 = *bio; | |
475 | ||
476 | bp->b1.bi_size = len; | |
477 | bp->b2.bi_size -= len; | |
478 | bp->b1.bi_vcnt = idx; | |
479 | bp->b2.bi_idx = idx; | |
480 | bp->b2.bi_sector += len >> 9; | |
481 | ||
482 | if (offset) { | |
483 | bp->bv1 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec), | |
484 | GFP_ATOMIC); | |
485 | if (!bp->bv1) | |
486 | goto split_fail_1; | |
487 | ||
488 | bp->bv2 = kmalloc(bio->bi_max_vecs * sizeof(struct bio_vec), | |
489 | GFP_ATOMIC); | |
490 | if (!bp->bv2) | |
491 | goto split_fail_2; | |
492 | ||
493 | memcpy(bp->bv1, bio->bi_io_vec, | |
494 | bio->bi_max_vecs * sizeof(struct bio_vec)); | |
495 | memcpy(bp->bv2, bio->bi_io_vec, | |
496 | bio->bi_max_vecs * sizeof(struct bio_vec)); | |
497 | ||
498 | bp->b1.bi_io_vec = bp->bv1; | |
499 | bp->b2.bi_io_vec = bp->bv2; | |
500 | bp->b2.bi_io_vec[idx].bv_offset += offset; | |
501 | bp->b2.bi_io_vec[idx].bv_len -= offset; | |
502 | bp->b1.bi_io_vec[idx].bv_len = offset; | |
503 | bp->b1.bi_vcnt++; | |
504 | } else | |
505 | bp->bv1 = bp->bv2 = NULL; | |
506 | ||
507 | bp->b1.bi_private = bp; | |
508 | bp->b2.bi_private = bp; | |
509 | ||
510 | bp->b1.bi_end_io = nvme_bio_pair_endio; | |
511 | bp->b2.bi_end_io = nvme_bio_pair_endio; | |
512 | ||
513 | bp->parent = bio; | |
514 | atomic_set(&bp->cnt, 2); | |
515 | ||
516 | return bp; | |
517 | ||
518 | split_fail_2: | |
519 | kfree(bp->bv1); | |
520 | split_fail_1: | |
521 | kfree(bp); | |
522 | return NULL; | |
523 | } | |
524 | ||
525 | static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq, | |
526 | int idx, int len, int offset) | |
527 | { | |
528 | struct nvme_bio_pair *bp = nvme_bio_split(bio, idx, len, offset); | |
529 | if (!bp) | |
530 | return -ENOMEM; | |
531 | ||
532 | if (bio_list_empty(&nvmeq->sq_cong)) | |
533 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
534 | bio_list_add(&nvmeq->sq_cong, &bp->b1); | |
535 | bio_list_add(&nvmeq->sq_cong, &bp->b2); | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
1ad2f893 MW |
540 | /* NVMe scatterlists require no holes in the virtual address */ |
541 | #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \ | |
542 | (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE)) | |
543 | ||
427e9708 | 544 | static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod, |
b60503ba MW |
545 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
546 | { | |
76830840 MW |
547 | struct bio_vec *bvec, *bvprv = NULL; |
548 | struct scatterlist *sg = NULL; | |
159b67d7 KB |
549 | int i, length = 0, nsegs = 0, split_len = bio->bi_size; |
550 | ||
551 | if (nvmeq->dev->stripe_size) | |
552 | split_len = nvmeq->dev->stripe_size - | |
553 | ((bio->bi_sector << 9) & (nvmeq->dev->stripe_size - 1)); | |
b60503ba | 554 | |
eca18b23 | 555 | sg_init_table(iod->sg, psegs); |
b60503ba | 556 | bio_for_each_segment(bvec, bio, i) { |
76830840 MW |
557 | if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { |
558 | sg->length += bvec->bv_len; | |
559 | } else { | |
1ad2f893 | 560 | if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec)) |
427e9708 KB |
561 | return nvme_split_and_submit(bio, nvmeq, i, |
562 | length, 0); | |
563 | ||
eca18b23 | 564 | sg = sg ? sg + 1 : iod->sg; |
76830840 MW |
565 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, |
566 | bvec->bv_offset); | |
567 | nsegs++; | |
568 | } | |
159b67d7 KB |
569 | |
570 | if (split_len - length < bvec->bv_len) | |
571 | return nvme_split_and_submit(bio, nvmeq, i, split_len, | |
572 | split_len - length); | |
1ad2f893 | 573 | length += bvec->bv_len; |
76830840 | 574 | bvprv = bvec; |
b60503ba | 575 | } |
eca18b23 | 576 | iod->nents = nsegs; |
76830840 | 577 | sg_mark_end(sg); |
427e9708 | 578 | if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0) |
1ad2f893 | 579 | return -ENOMEM; |
427e9708 | 580 | |
159b67d7 | 581 | BUG_ON(length != bio->bi_size); |
1ad2f893 | 582 | return length; |
b60503ba MW |
583 | } |
584 | ||
0e5e4f0e KB |
585 | /* |
586 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
587 | * worth having a special pool for these or additional cases to handle freeing | |
588 | * the iod. | |
589 | */ | |
590 | static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
591 | struct bio *bio, struct nvme_iod *iod, int cmdid) | |
592 | { | |
593 | struct nvme_dsm_range *range; | |
594 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
595 | ||
596 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
597 | &iod->first_dma); | |
598 | if (!range) | |
599 | return -ENOMEM; | |
600 | ||
601 | iod_list(iod)[0] = (__le64 *)range; | |
602 | iod->npages = 0; | |
603 | ||
604 | range->cattr = cpu_to_le32(0); | |
605 | range->nlb = cpu_to_le32(bio->bi_size >> ns->lba_shift); | |
063cc6d5 | 606 | range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector)); |
0e5e4f0e KB |
607 | |
608 | memset(cmnd, 0, sizeof(*cmnd)); | |
609 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
610 | cmnd->dsm.command_id = cmdid; | |
611 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
612 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
613 | cmnd->dsm.nr = 0; | |
614 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
615 | ||
616 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
617 | nvmeq->sq_tail = 0; | |
618 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
00df5cb4 MW |
623 | static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
624 | int cmdid) | |
625 | { | |
626 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
627 | ||
628 | memset(cmnd, 0, sizeof(*cmnd)); | |
629 | cmnd->common.opcode = nvme_cmd_flush; | |
630 | cmnd->common.command_id = cmdid; | |
631 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
632 | ||
633 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
634 | nvmeq->sq_tail = 0; | |
635 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
5d0f6131 | 640 | int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) |
00df5cb4 MW |
641 | { |
642 | int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, | |
ff976d72 | 643 | special_completion, NVME_IO_TIMEOUT); |
00df5cb4 MW |
644 | if (unlikely(cmdid < 0)) |
645 | return cmdid; | |
646 | ||
647 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
648 | } | |
649 | ||
184d2944 MW |
650 | /* |
651 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
652 | */ | |
b60503ba MW |
653 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
654 | struct bio *bio) | |
655 | { | |
ff22b54f | 656 | struct nvme_command *cmnd; |
eca18b23 | 657 | struct nvme_iod *iod; |
b60503ba | 658 | enum dma_data_direction dma_dir; |
1287dabd | 659 | int cmdid, length, result; |
b60503ba MW |
660 | u16 control; |
661 | u32 dsmgmt; | |
b60503ba MW |
662 | int psegs = bio_phys_segments(ns->queue, bio); |
663 | ||
00df5cb4 MW |
664 | if ((bio->bi_rw & REQ_FLUSH) && psegs) { |
665 | result = nvme_submit_flush_data(nvmeq, ns); | |
666 | if (result) | |
667 | return result; | |
668 | } | |
669 | ||
1287dabd | 670 | result = -ENOMEM; |
eca18b23 MW |
671 | iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC); |
672 | if (!iod) | |
eeee3226 | 673 | goto nomem; |
eca18b23 | 674 | iod->private = bio; |
b60503ba | 675 | |
eeee3226 | 676 | result = -EBUSY; |
ff976d72 | 677 | cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT); |
b60503ba | 678 | if (unlikely(cmdid < 0)) |
eca18b23 | 679 | goto free_iod; |
b60503ba | 680 | |
0e5e4f0e KB |
681 | if (bio->bi_rw & REQ_DISCARD) { |
682 | result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid); | |
683 | if (result) | |
684 | goto free_cmdid; | |
685 | return result; | |
686 | } | |
00df5cb4 MW |
687 | if ((bio->bi_rw & REQ_FLUSH) && !psegs) |
688 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
689 | ||
b60503ba MW |
690 | control = 0; |
691 | if (bio->bi_rw & REQ_FUA) | |
692 | control |= NVME_RW_FUA; | |
693 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
694 | control |= NVME_RW_LR; | |
695 | ||
696 | dsmgmt = 0; | |
697 | if (bio->bi_rw & REQ_RAHEAD) | |
698 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
699 | ||
ff22b54f | 700 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 701 | |
b8deb62c | 702 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 703 | if (bio_data_dir(bio)) { |
ff22b54f | 704 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
705 | dma_dir = DMA_TO_DEVICE; |
706 | } else { | |
ff22b54f | 707 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
708 | dma_dir = DMA_FROM_DEVICE; |
709 | } | |
710 | ||
427e9708 KB |
711 | result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs); |
712 | if (result <= 0) | |
859361a2 | 713 | goto free_cmdid; |
1ad2f893 | 714 | length = result; |
b60503ba | 715 | |
ff22b54f MW |
716 | cmnd->rw.command_id = cmdid; |
717 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
eca18b23 MW |
718 | length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length, |
719 | GFP_ATOMIC); | |
063cc6d5 | 720 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_sector)); |
1ad2f893 | 721 | cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1); |
ff22b54f MW |
722 | cmnd->rw.control = cpu_to_le16(control); |
723 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 724 | |
6198221f | 725 | nvme_start_io_acct(bio); |
b60503ba MW |
726 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
727 | nvmeq->sq_tail = 0; | |
7547881d | 728 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 729 | |
1974b1ae MW |
730 | return 0; |
731 | ||
859361a2 KB |
732 | free_cmdid: |
733 | free_cmdid(nvmeq, cmdid, NULL); | |
eca18b23 MW |
734 | free_iod: |
735 | nvme_free_iod(nvmeq->dev, iod); | |
eeee3226 MW |
736 | nomem: |
737 | return result; | |
b60503ba MW |
738 | } |
739 | ||
e9539f47 | 740 | static int nvme_process_cq(struct nvme_queue *nvmeq) |
b60503ba | 741 | { |
82123460 | 742 | u16 head, phase; |
b60503ba | 743 | |
b60503ba | 744 | head = nvmeq->cq_head; |
82123460 | 745 | phase = nvmeq->cq_phase; |
b60503ba MW |
746 | |
747 | for (;;) { | |
c2f5b650 MW |
748 | void *ctx; |
749 | nvme_completion_fn fn; | |
b60503ba | 750 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 751 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
752 | break; |
753 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
754 | if (++head == nvmeq->q_depth) { | |
755 | head = 0; | |
82123460 | 756 | phase = !phase; |
b60503ba MW |
757 | } |
758 | ||
c2f5b650 | 759 | ctx = free_cmdid(nvmeq, cqe.command_id, &fn); |
5c1281a3 | 760 | fn(nvmeq->dev, ctx, &cqe); |
b60503ba MW |
761 | } |
762 | ||
763 | /* If the controller ignores the cq head doorbell and continuously | |
764 | * writes to the queue, it is theoretically possible to wrap around | |
765 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
766 | * requires that 0.1% of your interrupts are handled, so this isn't | |
767 | * a big problem. | |
768 | */ | |
82123460 | 769 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
e9539f47 | 770 | return 0; |
b60503ba | 771 | |
f1938f6e | 772 | writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride)); |
b60503ba | 773 | nvmeq->cq_head = head; |
82123460 | 774 | nvmeq->cq_phase = phase; |
b60503ba | 775 | |
e9539f47 MW |
776 | nvmeq->cqe_seen = 1; |
777 | return 1; | |
b60503ba MW |
778 | } |
779 | ||
7d822457 MW |
780 | static void nvme_make_request(struct request_queue *q, struct bio *bio) |
781 | { | |
782 | struct nvme_ns *ns = q->queuedata; | |
783 | struct nvme_queue *nvmeq = get_nvmeq(ns->dev); | |
784 | int result = -EBUSY; | |
785 | ||
786 | spin_lock_irq(&nvmeq->q_lock); | |
787 | if (bio_list_empty(&nvmeq->sq_cong)) | |
788 | result = nvme_submit_bio_queue(nvmeq, ns, bio); | |
789 | if (unlikely(result)) { | |
790 | if (bio_list_empty(&nvmeq->sq_cong)) | |
791 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
792 | bio_list_add(&nvmeq->sq_cong, bio); | |
793 | } | |
794 | ||
795 | nvme_process_cq(nvmeq); | |
796 | spin_unlock_irq(&nvmeq->q_lock); | |
797 | put_nvmeq(nvmeq); | |
798 | } | |
799 | ||
b60503ba | 800 | static irqreturn_t nvme_irq(int irq, void *data) |
58ffacb5 MW |
801 | { |
802 | irqreturn_t result; | |
803 | struct nvme_queue *nvmeq = data; | |
804 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
805 | nvme_process_cq(nvmeq); |
806 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
807 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
808 | spin_unlock(&nvmeq->q_lock); |
809 | return result; | |
810 | } | |
811 | ||
812 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
813 | { | |
814 | struct nvme_queue *nvmeq = data; | |
815 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
816 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
817 | return IRQ_NONE; | |
818 | return IRQ_WAKE_THREAD; | |
819 | } | |
820 | ||
3c0cf138 MW |
821 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
822 | { | |
823 | spin_lock_irq(&nvmeq->q_lock); | |
c2f5b650 | 824 | cancel_cmdid(nvmeq, cmdid, NULL); |
3c0cf138 MW |
825 | spin_unlock_irq(&nvmeq->q_lock); |
826 | } | |
827 | ||
c2f5b650 MW |
828 | struct sync_cmd_info { |
829 | struct task_struct *task; | |
830 | u32 result; | |
831 | int status; | |
832 | }; | |
833 | ||
5c1281a3 | 834 | static void sync_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
835 | struct nvme_completion *cqe) |
836 | { | |
837 | struct sync_cmd_info *cmdinfo = ctx; | |
838 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
839 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
840 | wake_up_process(cmdinfo->task); | |
841 | } | |
842 | ||
b60503ba MW |
843 | /* |
844 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
845 | * if the result is positive, it's an NVM Express status code | |
846 | */ | |
5d0f6131 VV |
847 | int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, |
848 | u32 *result, unsigned timeout) | |
b60503ba MW |
849 | { |
850 | int cmdid; | |
851 | struct sync_cmd_info cmdinfo; | |
852 | ||
853 | cmdinfo.task = current; | |
854 | cmdinfo.status = -EINTR; | |
855 | ||
c2f5b650 | 856 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion, |
e85248e5 | 857 | timeout); |
b60503ba MW |
858 | if (cmdid < 0) |
859 | return cmdid; | |
860 | cmd->common.command_id = cmdid; | |
861 | ||
3c0cf138 MW |
862 | set_current_state(TASK_KILLABLE); |
863 | nvme_submit_cmd(nvmeq, cmd); | |
78f8d257 | 864 | schedule_timeout(timeout); |
b60503ba | 865 | |
3c0cf138 MW |
866 | if (cmdinfo.status == -EINTR) { |
867 | nvme_abort_command(nvmeq, cmdid); | |
868 | return -EINTR; | |
869 | } | |
870 | ||
b60503ba MW |
871 | if (result) |
872 | *result = cmdinfo.result; | |
873 | ||
874 | return cmdinfo.status; | |
875 | } | |
876 | ||
5d0f6131 | 877 | int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
b60503ba MW |
878 | u32 *result) |
879 | { | |
e85248e5 | 880 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
881 | } |
882 | ||
883 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
884 | { | |
885 | int status; | |
886 | struct nvme_command c; | |
887 | ||
888 | memset(&c, 0, sizeof(c)); | |
889 | c.delete_queue.opcode = opcode; | |
890 | c.delete_queue.qid = cpu_to_le16(id); | |
891 | ||
892 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
893 | if (status) | |
894 | return -EIO; | |
895 | return 0; | |
896 | } | |
897 | ||
898 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
899 | struct nvme_queue *nvmeq) | |
900 | { | |
901 | int status; | |
902 | struct nvme_command c; | |
903 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
904 | ||
905 | memset(&c, 0, sizeof(c)); | |
906 | c.create_cq.opcode = nvme_admin_create_cq; | |
907 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
908 | c.create_cq.cqid = cpu_to_le16(qid); | |
909 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
910 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
911 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
912 | ||
913 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
914 | if (status) | |
915 | return -EIO; | |
916 | return 0; | |
917 | } | |
918 | ||
919 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
920 | struct nvme_queue *nvmeq) | |
921 | { | |
922 | int status; | |
923 | struct nvme_command c; | |
924 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
925 | ||
926 | memset(&c, 0, sizeof(c)); | |
927 | c.create_sq.opcode = nvme_admin_create_sq; | |
928 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
929 | c.create_sq.sqid = cpu_to_le16(qid); | |
930 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
931 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
932 | c.create_sq.cqid = cpu_to_le16(qid); | |
933 | ||
934 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
935 | if (status) | |
936 | return -EIO; | |
937 | return 0; | |
938 | } | |
939 | ||
940 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
941 | { | |
942 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
943 | } | |
944 | ||
945 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
946 | { | |
947 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
948 | } | |
949 | ||
5d0f6131 | 950 | int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
bc5fc7e4 MW |
951 | dma_addr_t dma_addr) |
952 | { | |
953 | struct nvme_command c; | |
954 | ||
955 | memset(&c, 0, sizeof(c)); | |
956 | c.identify.opcode = nvme_admin_identify; | |
957 | c.identify.nsid = cpu_to_le32(nsid); | |
958 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
959 | c.identify.cns = cpu_to_le32(cns); | |
960 | ||
961 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
962 | } | |
963 | ||
5d0f6131 | 964 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
08df1e05 | 965 | dma_addr_t dma_addr, u32 *result) |
bc5fc7e4 MW |
966 | { |
967 | struct nvme_command c; | |
968 | ||
969 | memset(&c, 0, sizeof(c)); | |
970 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 971 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
972 | c.features.prp1 = cpu_to_le64(dma_addr); |
973 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 974 | |
08df1e05 | 975 | return nvme_submit_admin_cmd(dev, &c, result); |
df348139 MW |
976 | } |
977 | ||
5d0f6131 VV |
978 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
979 | dma_addr_t dma_addr, u32 *result) | |
df348139 MW |
980 | { |
981 | struct nvme_command c; | |
982 | ||
983 | memset(&c, 0, sizeof(c)); | |
984 | c.features.opcode = nvme_admin_set_features; | |
985 | c.features.prp1 = cpu_to_le64(dma_addr); | |
986 | c.features.fid = cpu_to_le32(fid); | |
987 | c.features.dword11 = cpu_to_le32(dword11); | |
988 | ||
bc5fc7e4 MW |
989 | return nvme_submit_admin_cmd(dev, &c, result); |
990 | } | |
991 | ||
a09115b2 MW |
992 | /** |
993 | * nvme_cancel_ios - Cancel outstanding I/Os | |
994 | * @queue: The queue to cancel I/Os on | |
995 | * @timeout: True to only cancel I/Os which have timed out | |
996 | */ | |
997 | static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout) | |
998 | { | |
999 | int depth = nvmeq->q_depth - 1; | |
1000 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
1001 | unsigned long now = jiffies; | |
1002 | int cmdid; | |
1003 | ||
1004 | for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) { | |
1005 | void *ctx; | |
1006 | nvme_completion_fn fn; | |
1007 | static struct nvme_completion cqe = { | |
af2d9ca7 | 1008 | .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1), |
a09115b2 MW |
1009 | }; |
1010 | ||
1011 | if (timeout && !time_after(now, info[cmdid].timeout)) | |
1012 | continue; | |
053ab702 KB |
1013 | if (info[cmdid].ctx == CMD_CTX_CANCELLED) |
1014 | continue; | |
a09115b2 MW |
1015 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid); |
1016 | ctx = cancel_cmdid(nvmeq, cmdid, &fn); | |
1017 | fn(nvmeq->dev, ctx, &cqe); | |
1018 | } | |
1019 | } | |
1020 | ||
9e866774 MW |
1021 | static void nvme_free_queue_mem(struct nvme_queue *nvmeq) |
1022 | { | |
1023 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
1024 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1025 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1026 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
1027 | kfree(nvmeq); | |
1028 | } | |
1029 | ||
b60503ba MW |
1030 | static void nvme_free_queue(struct nvme_dev *dev, int qid) |
1031 | { | |
1032 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
aba2080f | 1033 | int vector = dev->entry[nvmeq->cq_vector].vector; |
b60503ba | 1034 | |
a09115b2 MW |
1035 | spin_lock_irq(&nvmeq->q_lock); |
1036 | nvme_cancel_ios(nvmeq, false); | |
3295874b KB |
1037 | while (bio_list_peek(&nvmeq->sq_cong)) { |
1038 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1039 | bio_endio(bio, -EIO); | |
1040 | } | |
a09115b2 MW |
1041 | spin_unlock_irq(&nvmeq->q_lock); |
1042 | ||
aba2080f MW |
1043 | irq_set_affinity_hint(vector, NULL); |
1044 | free_irq(vector, nvmeq); | |
b60503ba MW |
1045 | |
1046 | /* Don't tell the adapter to delete the admin queue */ | |
1047 | if (qid) { | |
1048 | adapter_delete_sq(dev, qid); | |
1049 | adapter_delete_cq(dev, qid); | |
1050 | } | |
1051 | ||
9e866774 | 1052 | nvme_free_queue_mem(nvmeq); |
b60503ba MW |
1053 | } |
1054 | ||
1055 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
1056 | int depth, int vector) | |
1057 | { | |
1058 | struct device *dmadev = &dev->pci_dev->dev; | |
a0cadb85 KB |
1059 | unsigned extra = DIV_ROUND_UP(depth, 8) + (depth * |
1060 | sizeof(struct nvme_cmd_info)); | |
b60503ba MW |
1061 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
1062 | if (!nvmeq) | |
1063 | return NULL; | |
1064 | ||
1065 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
1066 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
1067 | if (!nvmeq->cqes) | |
1068 | goto free_nvmeq; | |
1069 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
1070 | ||
1071 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
1072 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1073 | if (!nvmeq->sq_cmds) | |
1074 | goto free_cqdma; | |
1075 | ||
1076 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 1077 | nvmeq->dev = dev; |
b60503ba MW |
1078 | spin_lock_init(&nvmeq->q_lock); |
1079 | nvmeq->cq_head = 0; | |
82123460 | 1080 | nvmeq->cq_phase = 1; |
b60503ba | 1081 | init_waitqueue_head(&nvmeq->sq_full); |
1fa6aead | 1082 | init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread); |
b60503ba | 1083 | bio_list_init(&nvmeq->sq_cong); |
f1938f6e | 1084 | nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)]; |
b60503ba MW |
1085 | nvmeq->q_depth = depth; |
1086 | nvmeq->cq_vector = vector; | |
1087 | ||
1088 | return nvmeq; | |
1089 | ||
1090 | free_cqdma: | |
68b8eca5 | 1091 | dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1092 | nvmeq->cq_dma_addr); |
1093 | free_nvmeq: | |
1094 | kfree(nvmeq); | |
1095 | return NULL; | |
1096 | } | |
1097 | ||
3001082c MW |
1098 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1099 | const char *name) | |
1100 | { | |
58ffacb5 MW |
1101 | if (use_threaded_interrupts) |
1102 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 1103 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
1104 | IRQF_DISABLED | IRQF_SHARED, |
1105 | name, nvmeq); | |
3001082c MW |
1106 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
1107 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
1108 | } | |
1109 | ||
8d85fce7 GKH |
1110 | static struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, int qid, |
1111 | int cq_size, int vector) | |
b60503ba MW |
1112 | { |
1113 | int result; | |
1114 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
1115 | ||
3f85d50b | 1116 | if (!nvmeq) |
6f0f5449 | 1117 | return ERR_PTR(-ENOMEM); |
3f85d50b | 1118 | |
b60503ba MW |
1119 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1120 | if (result < 0) | |
1121 | goto free_nvmeq; | |
1122 | ||
1123 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1124 | if (result < 0) | |
1125 | goto release_cq; | |
1126 | ||
3001082c | 1127 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
1128 | if (result < 0) |
1129 | goto release_sq; | |
1130 | ||
1131 | return nvmeq; | |
1132 | ||
1133 | release_sq: | |
1134 | adapter_delete_sq(dev, qid); | |
1135 | release_cq: | |
1136 | adapter_delete_cq(dev, qid); | |
1137 | free_nvmeq: | |
1138 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
1139 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1140 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1141 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
1142 | kfree(nvmeq); | |
6f0f5449 | 1143 | return ERR_PTR(result); |
b60503ba MW |
1144 | } |
1145 | ||
ba47e386 MW |
1146 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1147 | { | |
1148 | unsigned long timeout; | |
1149 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1150 | ||
1151 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1152 | ||
1153 | while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) { | |
1154 | msleep(100); | |
1155 | if (fatal_signal_pending(current)) | |
1156 | return -EINTR; | |
1157 | if (time_after(jiffies, timeout)) { | |
1158 | dev_err(&dev->pci_dev->dev, | |
1159 | "Device not ready; aborting initialisation\n"); | |
1160 | return -ENODEV; | |
1161 | } | |
1162 | } | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | /* | |
1168 | * If the device has been passed off to us in an enabled state, just clear | |
1169 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1170 | * bits', but doing so may cause the device to complete commands to the | |
1171 | * admin queue ... and we don't know what memory that might be pointing at! | |
1172 | */ | |
1173 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1174 | { | |
44af146a MW |
1175 | u32 cc = readl(&dev->bar->cc); |
1176 | ||
1177 | if (cc & NVME_CC_ENABLE) | |
1178 | writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc); | |
ba47e386 MW |
1179 | return nvme_wait_ready(dev, cap, false); |
1180 | } | |
1181 | ||
1182 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1183 | { | |
1184 | return nvme_wait_ready(dev, cap, true); | |
1185 | } | |
1186 | ||
8d85fce7 | 1187 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1188 | { |
ba47e386 | 1189 | int result; |
b60503ba | 1190 | u32 aqa; |
ba47e386 | 1191 | u64 cap = readq(&dev->bar->cap); |
b60503ba MW |
1192 | struct nvme_queue *nvmeq; |
1193 | ||
1194 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
ba47e386 MW |
1195 | dev->db_stride = NVME_CAP_STRIDE(cap); |
1196 | ||
1197 | result = nvme_disable_ctrl(dev, cap); | |
1198 | if (result < 0) | |
1199 | return result; | |
b60503ba MW |
1200 | |
1201 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
1202 | if (!nvmeq) |
1203 | return -ENOMEM; | |
b60503ba MW |
1204 | |
1205 | aqa = nvmeq->q_depth - 1; | |
1206 | aqa |= aqa << 16; | |
1207 | ||
1208 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
1209 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
1210 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
7f53f9d2 | 1211 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba MW |
1212 | |
1213 | writel(aqa, &dev->bar->aqa); | |
1214 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1215 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
1216 | writel(dev->ctrl_config, &dev->bar->cc); | |
1217 | ||
ba47e386 | 1218 | result = nvme_enable_ctrl(dev, cap); |
025c557a KB |
1219 | if (result) |
1220 | goto free_q; | |
9e866774 | 1221 | |
3001082c | 1222 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
025c557a KB |
1223 | if (result) |
1224 | goto free_q; | |
1225 | ||
b60503ba MW |
1226 | dev->queues[0] = nvmeq; |
1227 | return result; | |
025c557a KB |
1228 | |
1229 | free_q: | |
1230 | nvme_free_queue_mem(nvmeq); | |
1231 | return result; | |
b60503ba MW |
1232 | } |
1233 | ||
5d0f6131 | 1234 | struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
eca18b23 | 1235 | unsigned long addr, unsigned length) |
b60503ba | 1236 | { |
36c14ed9 | 1237 | int i, err, count, nents, offset; |
7fc3cdab MW |
1238 | struct scatterlist *sg; |
1239 | struct page **pages; | |
eca18b23 | 1240 | struct nvme_iod *iod; |
36c14ed9 MW |
1241 | |
1242 | if (addr & 3) | |
eca18b23 | 1243 | return ERR_PTR(-EINVAL); |
5460fc03 | 1244 | if (!length || length > INT_MAX - PAGE_SIZE) |
eca18b23 | 1245 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1246 | |
36c14ed9 | 1247 | offset = offset_in_page(addr); |
7fc3cdab MW |
1248 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1249 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
22fff826 DC |
1250 | if (!pages) |
1251 | return ERR_PTR(-ENOMEM); | |
36c14ed9 MW |
1252 | |
1253 | err = get_user_pages_fast(addr, count, 1, pages); | |
1254 | if (err < count) { | |
1255 | count = err; | |
1256 | err = -EFAULT; | |
1257 | goto put_pages; | |
1258 | } | |
7fc3cdab | 1259 | |
eca18b23 MW |
1260 | iod = nvme_alloc_iod(count, length, GFP_KERNEL); |
1261 | sg = iod->sg; | |
36c14ed9 | 1262 | sg_init_table(sg, count); |
d0ba1e49 MW |
1263 | for (i = 0; i < count; i++) { |
1264 | sg_set_page(&sg[i], pages[i], | |
5460fc03 DC |
1265 | min_t(unsigned, length, PAGE_SIZE - offset), |
1266 | offset); | |
d0ba1e49 MW |
1267 | length -= (PAGE_SIZE - offset); |
1268 | offset = 0; | |
7fc3cdab | 1269 | } |
fe304c43 | 1270 | sg_mark_end(&sg[i - 1]); |
1c2ad9fa | 1271 | iod->nents = count; |
7fc3cdab MW |
1272 | |
1273 | err = -ENOMEM; | |
1274 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
1275 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 | 1276 | if (!nents) |
eca18b23 | 1277 | goto free_iod; |
b60503ba | 1278 | |
7fc3cdab | 1279 | kfree(pages); |
eca18b23 | 1280 | return iod; |
b60503ba | 1281 | |
eca18b23 MW |
1282 | free_iod: |
1283 | kfree(iod); | |
7fc3cdab MW |
1284 | put_pages: |
1285 | for (i = 0; i < count; i++) | |
1286 | put_page(pages[i]); | |
1287 | kfree(pages); | |
eca18b23 | 1288 | return ERR_PTR(err); |
7fc3cdab | 1289 | } |
b60503ba | 1290 | |
5d0f6131 | 1291 | void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1c2ad9fa | 1292 | struct nvme_iod *iod) |
7fc3cdab | 1293 | { |
1c2ad9fa | 1294 | int i; |
b60503ba | 1295 | |
1c2ad9fa MW |
1296 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
1297 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
7fc3cdab | 1298 | |
1c2ad9fa MW |
1299 | for (i = 0; i < iod->nents; i++) |
1300 | put_page(sg_page(&iod->sg[i])); | |
7fc3cdab | 1301 | } |
b60503ba | 1302 | |
a53295b6 MW |
1303 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1304 | { | |
1305 | struct nvme_dev *dev = ns->dev; | |
1306 | struct nvme_queue *nvmeq; | |
1307 | struct nvme_user_io io; | |
1308 | struct nvme_command c; | |
f410c680 KB |
1309 | unsigned length, meta_len; |
1310 | int status, i; | |
1311 | struct nvme_iod *iod, *meta_iod = NULL; | |
1312 | dma_addr_t meta_dma_addr; | |
1313 | void *meta, *uninitialized_var(meta_mem); | |
a53295b6 MW |
1314 | |
1315 | if (copy_from_user(&io, uio, sizeof(io))) | |
1316 | return -EFAULT; | |
6c7d4945 | 1317 | length = (io.nblocks + 1) << ns->lba_shift; |
f410c680 KB |
1318 | meta_len = (io.nblocks + 1) * ns->ms; |
1319 | ||
1320 | if (meta_len && ((io.metadata & 3) || !io.metadata)) | |
1321 | return -EINVAL; | |
6c7d4945 MW |
1322 | |
1323 | switch (io.opcode) { | |
1324 | case nvme_cmd_write: | |
1325 | case nvme_cmd_read: | |
6bbf1acd | 1326 | case nvme_cmd_compare: |
eca18b23 | 1327 | iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length); |
6413214c | 1328 | break; |
6c7d4945 | 1329 | default: |
6bbf1acd | 1330 | return -EINVAL; |
6c7d4945 MW |
1331 | } |
1332 | ||
eca18b23 MW |
1333 | if (IS_ERR(iod)) |
1334 | return PTR_ERR(iod); | |
a53295b6 MW |
1335 | |
1336 | memset(&c, 0, sizeof(c)); | |
1337 | c.rw.opcode = io.opcode; | |
1338 | c.rw.flags = io.flags; | |
6c7d4945 | 1339 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1340 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1341 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1342 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1343 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1344 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1345 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1346 | c.rw.appmask = cpu_to_le16(io.appmask); | |
f410c680 KB |
1347 | |
1348 | if (meta_len) { | |
1b56749e KB |
1349 | meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata, |
1350 | meta_len); | |
f410c680 KB |
1351 | if (IS_ERR(meta_iod)) { |
1352 | status = PTR_ERR(meta_iod); | |
1353 | meta_iod = NULL; | |
1354 | goto unmap; | |
1355 | } | |
1356 | ||
1357 | meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len, | |
1358 | &meta_dma_addr, GFP_KERNEL); | |
1359 | if (!meta_mem) { | |
1360 | status = -ENOMEM; | |
1361 | goto unmap; | |
1362 | } | |
1363 | ||
1364 | if (io.opcode & 1) { | |
1365 | int meta_offset = 0; | |
1366 | ||
1367 | for (i = 0; i < meta_iod->nents; i++) { | |
1368 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1369 | meta_iod->sg[i].offset; | |
1370 | memcpy(meta_mem + meta_offset, meta, | |
1371 | meta_iod->sg[i].length); | |
1372 | kunmap_atomic(meta); | |
1373 | meta_offset += meta_iod->sg[i].length; | |
1374 | } | |
1375 | } | |
1376 | ||
1377 | c.rw.metadata = cpu_to_le64(meta_dma_addr); | |
1378 | } | |
1379 | ||
eca18b23 | 1380 | length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL); |
a53295b6 | 1381 | |
040a93b5 | 1382 | nvmeq = get_nvmeq(dev); |
fa922821 MW |
1383 | /* |
1384 | * Since nvme_submit_sync_cmd sleeps, we can't keep preemption | |
b1ad37ef MW |
1385 | * disabled. We may be preempted at any point, and be rescheduled |
1386 | * to a different CPU. That will cause cacheline bouncing, but no | |
1387 | * additional races since q_lock already protects against other CPUs. | |
1388 | */ | |
a53295b6 | 1389 | put_nvmeq(nvmeq); |
b77954cb MW |
1390 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1391 | status = -ENOMEM; | |
1392 | else | |
ff976d72 | 1393 | status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT); |
a53295b6 | 1394 | |
f410c680 KB |
1395 | if (meta_len) { |
1396 | if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) { | |
1397 | int meta_offset = 0; | |
1398 | ||
1399 | for (i = 0; i < meta_iod->nents; i++) { | |
1400 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1401 | meta_iod->sg[i].offset; | |
1402 | memcpy(meta, meta_mem + meta_offset, | |
1403 | meta_iod->sg[i].length); | |
1404 | kunmap_atomic(meta); | |
1405 | meta_offset += meta_iod->sg[i].length; | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem, | |
1410 | meta_dma_addr); | |
1411 | } | |
1412 | ||
1413 | unmap: | |
1c2ad9fa | 1414 | nvme_unmap_user_pages(dev, io.opcode & 1, iod); |
eca18b23 | 1415 | nvme_free_iod(dev, iod); |
f410c680 KB |
1416 | |
1417 | if (meta_iod) { | |
1418 | nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod); | |
1419 | nvme_free_iod(dev, meta_iod); | |
1420 | } | |
1421 | ||
a53295b6 MW |
1422 | return status; |
1423 | } | |
1424 | ||
50af8bae | 1425 | static int nvme_user_admin_cmd(struct nvme_dev *dev, |
6bbf1acd | 1426 | struct nvme_admin_cmd __user *ucmd) |
6ee44cdc | 1427 | { |
6bbf1acd | 1428 | struct nvme_admin_cmd cmd; |
6ee44cdc | 1429 | struct nvme_command c; |
eca18b23 | 1430 | int status, length; |
c7d36ab8 | 1431 | struct nvme_iod *uninitialized_var(iod); |
94f370ca | 1432 | unsigned timeout; |
6ee44cdc | 1433 | |
6bbf1acd MW |
1434 | if (!capable(CAP_SYS_ADMIN)) |
1435 | return -EACCES; | |
1436 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1437 | return -EFAULT; |
6ee44cdc MW |
1438 | |
1439 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1440 | c.common.opcode = cmd.opcode; |
1441 | c.common.flags = cmd.flags; | |
1442 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1443 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1444 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1445 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1446 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1447 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1448 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1449 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1450 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1451 | ||
1452 | length = cmd.data_len; | |
1453 | if (cmd.data_len) { | |
49742188 MW |
1454 | iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr, |
1455 | length); | |
eca18b23 MW |
1456 | if (IS_ERR(iod)) |
1457 | return PTR_ERR(iod); | |
1458 | length = nvme_setup_prps(dev, &c.common, iod, length, | |
1459 | GFP_KERNEL); | |
6bbf1acd MW |
1460 | } |
1461 | ||
94f370ca KB |
1462 | timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) : |
1463 | ADMIN_TIMEOUT; | |
6bbf1acd | 1464 | if (length != cmd.data_len) |
b77954cb MW |
1465 | status = -ENOMEM; |
1466 | else | |
94f370ca KB |
1467 | status = nvme_submit_sync_cmd(dev->queues[0], &c, &cmd.result, |
1468 | timeout); | |
eca18b23 | 1469 | |
6bbf1acd | 1470 | if (cmd.data_len) { |
1c2ad9fa | 1471 | nvme_unmap_user_pages(dev, cmd.opcode & 1, iod); |
eca18b23 | 1472 | nvme_free_iod(dev, iod); |
6bbf1acd | 1473 | } |
f4f117f6 | 1474 | |
cf90bc48 | 1475 | if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result, |
f4f117f6 KB |
1476 | sizeof(cmd.result))) |
1477 | status = -EFAULT; | |
1478 | ||
6ee44cdc MW |
1479 | return status; |
1480 | } | |
1481 | ||
b60503ba MW |
1482 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1483 | unsigned long arg) | |
1484 | { | |
1485 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1486 | ||
1487 | switch (cmd) { | |
6bbf1acd | 1488 | case NVME_IOCTL_ID: |
c3bfe717 | 1489 | force_successful_syscall_return(); |
6bbf1acd MW |
1490 | return ns->ns_id; |
1491 | case NVME_IOCTL_ADMIN_CMD: | |
50af8bae | 1492 | return nvme_user_admin_cmd(ns->dev, (void __user *)arg); |
a53295b6 MW |
1493 | case NVME_IOCTL_SUBMIT_IO: |
1494 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1495 | case SG_GET_VERSION_NUM: |
1496 | return nvme_sg_get_version_num((void __user *)arg); | |
1497 | case SG_IO: | |
1498 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1499 | default: |
1500 | return -ENOTTY; | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | static const struct block_device_operations nvme_fops = { | |
1505 | .owner = THIS_MODULE, | |
1506 | .ioctl = nvme_ioctl, | |
49481682 | 1507 | .compat_ioctl = nvme_ioctl, |
b60503ba MW |
1508 | }; |
1509 | ||
1fa6aead MW |
1510 | static void nvme_resubmit_bios(struct nvme_queue *nvmeq) |
1511 | { | |
1512 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1513 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1514 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
427e9708 KB |
1515 | |
1516 | if (bio_list_empty(&nvmeq->sq_cong)) | |
1517 | remove_wait_queue(&nvmeq->sq_full, | |
1518 | &nvmeq->sq_cong_wait); | |
1fa6aead | 1519 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { |
427e9708 KB |
1520 | if (bio_list_empty(&nvmeq->sq_cong)) |
1521 | add_wait_queue(&nvmeq->sq_full, | |
1522 | &nvmeq->sq_cong_wait); | |
1fa6aead MW |
1523 | bio_list_add_head(&nvmeq->sq_cong, bio); |
1524 | break; | |
1525 | } | |
1526 | } | |
1527 | } | |
1528 | ||
1529 | static int nvme_kthread(void *data) | |
1530 | { | |
1531 | struct nvme_dev *dev; | |
1532 | ||
1533 | while (!kthread_should_stop()) { | |
564a232c | 1534 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead MW |
1535 | spin_lock(&dev_list_lock); |
1536 | list_for_each_entry(dev, &dev_list, node) { | |
1537 | int i; | |
1538 | for (i = 0; i < dev->queue_count; i++) { | |
1539 | struct nvme_queue *nvmeq = dev->queues[i]; | |
740216fc MW |
1540 | if (!nvmeq) |
1541 | continue; | |
1fa6aead | 1542 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 1543 | nvme_process_cq(nvmeq); |
a09115b2 | 1544 | nvme_cancel_ios(nvmeq, true); |
1fa6aead MW |
1545 | nvme_resubmit_bios(nvmeq); |
1546 | spin_unlock_irq(&nvmeq->q_lock); | |
1547 | } | |
1548 | } | |
1549 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1550 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1551 | } |
1552 | return 0; | |
1553 | } | |
1554 | ||
5aff9382 MW |
1555 | static DEFINE_IDA(nvme_index_ida); |
1556 | ||
1557 | static int nvme_get_ns_idx(void) | |
1558 | { | |
1559 | int index, error; | |
1560 | ||
1561 | do { | |
1562 | if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL)) | |
1563 | return -1; | |
1564 | ||
1565 | spin_lock(&dev_list_lock); | |
1566 | error = ida_get_new(&nvme_index_ida, &index); | |
1567 | spin_unlock(&dev_list_lock); | |
1568 | } while (error == -EAGAIN); | |
1569 | ||
1570 | if (error) | |
1571 | index = -1; | |
1572 | return index; | |
1573 | } | |
1574 | ||
1575 | static void nvme_put_ns_idx(int index) | |
1576 | { | |
1577 | spin_lock(&dev_list_lock); | |
1578 | ida_remove(&nvme_index_ida, index); | |
1579 | spin_unlock(&dev_list_lock); | |
1580 | } | |
1581 | ||
0e5e4f0e KB |
1582 | static void nvme_config_discard(struct nvme_ns *ns) |
1583 | { | |
1584 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1585 | ns->queue->limits.discard_zeroes_data = 0; | |
1586 | ns->queue->limits.discard_alignment = logical_block_size; | |
1587 | ns->queue->limits.discard_granularity = logical_block_size; | |
1588 | ns->queue->limits.max_discard_sectors = 0xffffffff; | |
1589 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); | |
1590 | } | |
1591 | ||
c3bfe717 | 1592 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid, |
b60503ba MW |
1593 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) |
1594 | { | |
1595 | struct nvme_ns *ns; | |
1596 | struct gendisk *disk; | |
1597 | int lbaf; | |
1598 | ||
1599 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1600 | return NULL; | |
1601 | ||
1602 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1603 | if (!ns) | |
1604 | return NULL; | |
1605 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1606 | if (!ns->queue) | |
1607 | goto out_free_ns; | |
4eeb9215 MW |
1608 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT; |
1609 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); | |
1610 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
b60503ba MW |
1611 | blk_queue_make_request(ns->queue, nvme_make_request); |
1612 | ns->dev = dev; | |
1613 | ns->queue->queuedata = ns; | |
1614 | ||
1615 | disk = alloc_disk(NVME_MINORS); | |
1616 | if (!disk) | |
1617 | goto out_free_queue; | |
5aff9382 | 1618 | ns->ns_id = nsid; |
b60503ba MW |
1619 | ns->disk = disk; |
1620 | lbaf = id->flbas & 0xf; | |
1621 | ns->lba_shift = id->lbaf[lbaf].ds; | |
f410c680 | 1622 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
e9ef4636 | 1623 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
1624 | if (dev->max_hw_sectors) |
1625 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
b60503ba MW |
1626 | |
1627 | disk->major = nvme_major; | |
1628 | disk->minors = NVME_MINORS; | |
5aff9382 | 1629 | disk->first_minor = NVME_MINORS * nvme_get_ns_idx(); |
b60503ba MW |
1630 | disk->fops = &nvme_fops; |
1631 | disk->private_data = ns; | |
1632 | disk->queue = ns->queue; | |
388f037f | 1633 | disk->driverfs_dev = &dev->pci_dev->dev; |
5aff9382 | 1634 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba MW |
1635 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); |
1636 | ||
0e5e4f0e KB |
1637 | if (dev->oncs & NVME_CTRL_ONCS_DSM) |
1638 | nvme_config_discard(ns); | |
1639 | ||
b60503ba MW |
1640 | return ns; |
1641 | ||
1642 | out_free_queue: | |
1643 | blk_cleanup_queue(ns->queue); | |
1644 | out_free_ns: | |
1645 | kfree(ns); | |
1646 | return NULL; | |
1647 | } | |
1648 | ||
1649 | static void nvme_ns_free(struct nvme_ns *ns) | |
1650 | { | |
5aff9382 | 1651 | int index = ns->disk->first_minor / NVME_MINORS; |
b60503ba | 1652 | put_disk(ns->disk); |
5aff9382 | 1653 | nvme_put_ns_idx(index); |
b60503ba MW |
1654 | blk_cleanup_queue(ns->queue); |
1655 | kfree(ns); | |
1656 | } | |
1657 | ||
b3b06812 | 1658 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1659 | { |
1660 | int status; | |
1661 | u32 result; | |
b3b06812 | 1662 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 1663 | |
df348139 | 1664 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 1665 | &result); |
b60503ba | 1666 | if (status) |
7e03b124 | 1667 | return status < 0 ? -EIO : -EBUSY; |
b60503ba MW |
1668 | return min(result & 0xffff, result >> 16) + 1; |
1669 | } | |
1670 | ||
8d85fce7 | 1671 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1672 | { |
fa08a396 | 1673 | struct pci_dev *pdev = dev->pci_dev; |
063a8096 | 1674 | int result, cpu, i, vecs, nr_io_queues, db_bar_size, q_depth; |
b60503ba | 1675 | |
b348b7d5 MW |
1676 | nr_io_queues = num_online_cpus(); |
1677 | result = set_queue_count(dev, nr_io_queues); | |
1b23484b MW |
1678 | if (result < 0) |
1679 | return result; | |
b348b7d5 MW |
1680 | if (result < nr_io_queues) |
1681 | nr_io_queues = result; | |
b60503ba | 1682 | |
1b23484b MW |
1683 | /* Deregister the admin queue's interrupt */ |
1684 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1685 | ||
f1938f6e MW |
1686 | db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3)); |
1687 | if (db_bar_size > 8192) { | |
1688 | iounmap(dev->bar); | |
fa08a396 | 1689 | dev->bar = ioremap(pci_resource_start(pdev, 0), db_bar_size); |
f1938f6e MW |
1690 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
1691 | dev->queues[0]->q_db = dev->dbs; | |
1692 | } | |
1693 | ||
063a8096 MW |
1694 | vecs = nr_io_queues; |
1695 | for (i = 0; i < vecs; i++) | |
1b23484b MW |
1696 | dev->entry[i].entry = i; |
1697 | for (;;) { | |
063a8096 MW |
1698 | result = pci_enable_msix(pdev, dev->entry, vecs); |
1699 | if (result <= 0) | |
1b23484b | 1700 | break; |
063a8096 | 1701 | vecs = result; |
1b23484b MW |
1702 | } |
1703 | ||
063a8096 MW |
1704 | if (result < 0) { |
1705 | vecs = nr_io_queues; | |
1706 | if (vecs > 32) | |
1707 | vecs = 32; | |
fa08a396 | 1708 | for (;;) { |
063a8096 | 1709 | result = pci_enable_msi_block(pdev, vecs); |
fa08a396 | 1710 | if (result == 0) { |
063a8096 | 1711 | for (i = 0; i < vecs; i++) |
fa08a396 RRG |
1712 | dev->entry[i].vector = i + pdev->irq; |
1713 | break; | |
063a8096 MW |
1714 | } else if (result < 0) { |
1715 | vecs = 1; | |
fa08a396 RRG |
1716 | break; |
1717 | } | |
063a8096 | 1718 | vecs = result; |
fa08a396 RRG |
1719 | } |
1720 | } | |
1721 | ||
063a8096 MW |
1722 | /* |
1723 | * Should investigate if there's a performance win from allocating | |
1724 | * more queues than interrupt vectors; it might allow the submission | |
1725 | * path to scale better, even if the receive path is limited by the | |
1726 | * number of interrupts. | |
1727 | */ | |
1728 | nr_io_queues = vecs; | |
1729 | ||
1b23484b MW |
1730 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); |
1731 | /* XXX: handle failure here */ | |
1732 | ||
1733 | cpu = cpumask_first(cpu_online_mask); | |
b348b7d5 | 1734 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1735 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); |
1736 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1737 | } | |
1738 | ||
a0cadb85 KB |
1739 | q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1, |
1740 | NVME_Q_DEPTH); | |
b348b7d5 | 1741 | for (i = 0; i < nr_io_queues; i++) { |
a0cadb85 | 1742 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i); |
6f0f5449 MW |
1743 | if (IS_ERR(dev->queues[i + 1])) |
1744 | return PTR_ERR(dev->queues[i + 1]); | |
1b23484b MW |
1745 | dev->queue_count++; |
1746 | } | |
b60503ba | 1747 | |
9ecdc946 MW |
1748 | for (; i < num_possible_cpus(); i++) { |
1749 | int target = i % rounddown_pow_of_two(dev->queue_count - 1); | |
1750 | dev->queues[i + 1] = dev->queues[target + 1]; | |
1751 | } | |
1752 | ||
b60503ba MW |
1753 | return 0; |
1754 | } | |
1755 | ||
1756 | static void nvme_free_queues(struct nvme_dev *dev) | |
1757 | { | |
1758 | int i; | |
1759 | ||
1760 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1761 | nvme_free_queue(dev, i); | |
1762 | } | |
1763 | ||
422ef0c7 MW |
1764 | /* |
1765 | * Return: error value if an error occurred setting up the queues or calling | |
1766 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1767 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1768 | * failures should be reported. | |
1769 | */ | |
8d85fce7 | 1770 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1771 | { |
c3bfe717 MW |
1772 | int res; |
1773 | unsigned nn, i; | |
cbb6218f | 1774 | struct nvme_ns *ns; |
51814232 | 1775 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 MW |
1776 | struct nvme_id_ns *id_ns; |
1777 | void *mem; | |
b60503ba | 1778 | dma_addr_t dma_addr; |
159b67d7 | 1779 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; |
b60503ba MW |
1780 | |
1781 | res = nvme_setup_io_queues(dev); | |
1782 | if (res) | |
1783 | return res; | |
1784 | ||
bc5fc7e4 | 1785 | mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, |
b60503ba | 1786 | GFP_KERNEL); |
a9ef4343 KB |
1787 | if (!mem) |
1788 | return -ENOMEM; | |
b60503ba | 1789 | |
bc5fc7e4 | 1790 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba MW |
1791 | if (res) { |
1792 | res = -EIO; | |
cbb6218f | 1793 | goto out; |
b60503ba MW |
1794 | } |
1795 | ||
bc5fc7e4 | 1796 | ctrl = mem; |
51814232 | 1797 | nn = le32_to_cpup(&ctrl->nn); |
0e5e4f0e | 1798 | dev->oncs = le16_to_cpup(&ctrl->oncs); |
51814232 MW |
1799 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
1800 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1801 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 1802 | if (ctrl->mdts) |
8fc23e03 | 1803 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
159b67d7 KB |
1804 | if ((dev->pci_dev->vendor == PCI_VENDOR_ID_INTEL) && |
1805 | (dev->pci_dev->device == 0x0953) && ctrl->vs[3]) | |
1806 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); | |
b60503ba | 1807 | |
bc5fc7e4 | 1808 | id_ns = mem; |
2b2c1896 | 1809 | for (i = 1; i <= nn; i++) { |
bc5fc7e4 | 1810 | res = nvme_identify(dev, i, 0, dma_addr); |
b60503ba MW |
1811 | if (res) |
1812 | continue; | |
1813 | ||
bc5fc7e4 | 1814 | if (id_ns->ncap == 0) |
b60503ba MW |
1815 | continue; |
1816 | ||
bc5fc7e4 | 1817 | res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i, |
08df1e05 | 1818 | dma_addr + 4096, NULL); |
b60503ba | 1819 | if (res) |
12209036 | 1820 | memset(mem + 4096, 0, 4096); |
b60503ba | 1821 | |
bc5fc7e4 | 1822 | ns = nvme_alloc_ns(dev, i, mem, mem + 4096); |
b60503ba MW |
1823 | if (ns) |
1824 | list_add_tail(&ns->list, &dev->namespaces); | |
1825 | } | |
1826 | list_for_each_entry(ns, &dev->namespaces, list) | |
1827 | add_disk(ns->disk); | |
422ef0c7 | 1828 | res = 0; |
b60503ba | 1829 | |
bc5fc7e4 | 1830 | out: |
684f5c20 | 1831 | dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr); |
b60503ba MW |
1832 | return res; |
1833 | } | |
1834 | ||
1835 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1836 | { | |
1837 | struct nvme_ns *ns, *next; | |
1838 | ||
1fa6aead MW |
1839 | spin_lock(&dev_list_lock); |
1840 | list_del(&dev->node); | |
1841 | spin_unlock(&dev_list_lock); | |
1842 | ||
b60503ba MW |
1843 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { |
1844 | list_del(&ns->list); | |
1845 | del_gendisk(ns->disk); | |
1846 | nvme_ns_free(ns); | |
1847 | } | |
1848 | ||
1849 | nvme_free_queues(dev); | |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
091b6092 MW |
1854 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1855 | { | |
1856 | struct device *dmadev = &dev->pci_dev->dev; | |
1857 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
1858 | PAGE_SIZE, PAGE_SIZE, 0); | |
1859 | if (!dev->prp_page_pool) | |
1860 | return -ENOMEM; | |
1861 | ||
99802a7a MW |
1862 | /* Optimisation for I/Os between 4k and 128k */ |
1863 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
1864 | 256, 256, 0); | |
1865 | if (!dev->prp_small_pool) { | |
1866 | dma_pool_destroy(dev->prp_page_pool); | |
1867 | return -ENOMEM; | |
1868 | } | |
091b6092 MW |
1869 | return 0; |
1870 | } | |
1871 | ||
1872 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1873 | { | |
1874 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1875 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1876 | } |
1877 | ||
cd58ad7d QSA |
1878 | static DEFINE_IDA(nvme_instance_ida); |
1879 | ||
1880 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 1881 | { |
cd58ad7d QSA |
1882 | int instance, error; |
1883 | ||
1884 | do { | |
1885 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
1886 | return -ENODEV; | |
1887 | ||
1888 | spin_lock(&dev_list_lock); | |
1889 | error = ida_get_new(&nvme_instance_ida, &instance); | |
1890 | spin_unlock(&dev_list_lock); | |
1891 | } while (error == -EAGAIN); | |
1892 | ||
1893 | if (error) | |
1894 | return -ENODEV; | |
1895 | ||
1896 | dev->instance = instance; | |
1897 | return 0; | |
b60503ba MW |
1898 | } |
1899 | ||
1900 | static void nvme_release_instance(struct nvme_dev *dev) | |
1901 | { | |
cd58ad7d QSA |
1902 | spin_lock(&dev_list_lock); |
1903 | ida_remove(&nvme_instance_ida, dev->instance); | |
1904 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
1905 | } |
1906 | ||
5e82e952 KB |
1907 | static void nvme_free_dev(struct kref *kref) |
1908 | { | |
1909 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
1910 | nvme_dev_remove(dev); | |
fa08a396 RRG |
1911 | if (dev->pci_dev->msi_enabled) |
1912 | pci_disable_msi(dev->pci_dev); | |
1913 | else if (dev->pci_dev->msix_enabled) | |
1914 | pci_disable_msix(dev->pci_dev); | |
5e82e952 KB |
1915 | iounmap(dev->bar); |
1916 | nvme_release_instance(dev); | |
1917 | nvme_release_prp_pools(dev); | |
1918 | pci_disable_device(dev->pci_dev); | |
1919 | pci_release_regions(dev->pci_dev); | |
1920 | kfree(dev->queues); | |
1921 | kfree(dev->entry); | |
1922 | kfree(dev); | |
1923 | } | |
1924 | ||
1925 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
1926 | { | |
1927 | struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev, | |
1928 | miscdev); | |
1929 | kref_get(&dev->kref); | |
1930 | f->private_data = dev; | |
1931 | return 0; | |
1932 | } | |
1933 | ||
1934 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
1935 | { | |
1936 | struct nvme_dev *dev = f->private_data; | |
1937 | kref_put(&dev->kref, nvme_free_dev); | |
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
1942 | { | |
1943 | struct nvme_dev *dev = f->private_data; | |
1944 | switch (cmd) { | |
1945 | case NVME_IOCTL_ADMIN_CMD: | |
1946 | return nvme_user_admin_cmd(dev, (void __user *)arg); | |
1947 | default: | |
1948 | return -ENOTTY; | |
1949 | } | |
1950 | } | |
1951 | ||
1952 | static const struct file_operations nvme_dev_fops = { | |
1953 | .owner = THIS_MODULE, | |
1954 | .open = nvme_dev_open, | |
1955 | .release = nvme_dev_release, | |
1956 | .unlocked_ioctl = nvme_dev_ioctl, | |
1957 | .compat_ioctl = nvme_dev_ioctl, | |
1958 | }; | |
1959 | ||
8d85fce7 | 1960 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 1961 | { |
574e8b95 | 1962 | int bars, result = -ENOMEM; |
b60503ba MW |
1963 | struct nvme_dev *dev; |
1964 | ||
1965 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1966 | if (!dev) | |
1967 | return -ENOMEM; | |
1968 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1969 | GFP_KERNEL); | |
1970 | if (!dev->entry) | |
1971 | goto free; | |
1b23484b MW |
1972 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1973 | GFP_KERNEL); | |
b60503ba MW |
1974 | if (!dev->queues) |
1975 | goto free; | |
1976 | ||
0ee5a7d7 SMM |
1977 | if (pci_enable_device_mem(pdev)) |
1978 | goto free; | |
f64d3365 | 1979 | pci_set_master(pdev); |
574e8b95 MW |
1980 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1981 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1982 | goto disable; | |
0ee5a7d7 | 1983 | |
b60503ba MW |
1984 | INIT_LIST_HEAD(&dev->namespaces); |
1985 | dev->pci_dev = pdev; | |
1986 | pci_set_drvdata(pdev, dev); | |
cf9f123b MW |
1987 | |
1988 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) | |
1989 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
1990 | else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) | |
1991 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
1992 | else | |
1993 | goto disable; | |
1994 | ||
cd58ad7d QSA |
1995 | result = nvme_set_instance(dev); |
1996 | if (result) | |
1997 | goto disable; | |
1998 | ||
53c9577e | 1999 | dev->entry[0].vector = pdev->irq; |
b60503ba | 2000 | |
091b6092 MW |
2001 | result = nvme_setup_prp_pools(dev); |
2002 | if (result) | |
2003 | goto disable_msix; | |
2004 | ||
b60503ba MW |
2005 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
2006 | if (!dev->bar) { | |
2007 | result = -ENOMEM; | |
574e8b95 | 2008 | goto disable_msix; |
b60503ba MW |
2009 | } |
2010 | ||
2011 | result = nvme_configure_admin_queue(dev); | |
2012 | if (result) | |
2013 | goto unmap; | |
2014 | dev->queue_count++; | |
2015 | ||
1fa6aead MW |
2016 | spin_lock(&dev_list_lock); |
2017 | list_add(&dev->node, &dev_list); | |
2018 | spin_unlock(&dev_list_lock); | |
2019 | ||
740216fc | 2020 | result = nvme_dev_add(dev); |
7e03b124 | 2021 | if (result && result != -EBUSY) |
740216fc MW |
2022 | goto delete; |
2023 | ||
5e82e952 KB |
2024 | scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance); |
2025 | dev->miscdev.minor = MISC_DYNAMIC_MINOR; | |
2026 | dev->miscdev.parent = &pdev->dev; | |
2027 | dev->miscdev.name = dev->name; | |
2028 | dev->miscdev.fops = &nvme_dev_fops; | |
2029 | result = misc_register(&dev->miscdev); | |
2030 | if (result) | |
2031 | goto remove; | |
2032 | ||
2033 | kref_init(&dev->kref); | |
b60503ba MW |
2034 | return 0; |
2035 | ||
5e82e952 KB |
2036 | remove: |
2037 | nvme_dev_remove(dev); | |
b60503ba | 2038 | delete: |
740216fc MW |
2039 | spin_lock(&dev_list_lock); |
2040 | list_del(&dev->node); | |
2041 | spin_unlock(&dev_list_lock); | |
2042 | ||
b60503ba MW |
2043 | nvme_free_queues(dev); |
2044 | unmap: | |
2045 | iounmap(dev->bar); | |
574e8b95 | 2046 | disable_msix: |
fa08a396 RRG |
2047 | if (dev->pci_dev->msi_enabled) |
2048 | pci_disable_msi(dev->pci_dev); | |
2049 | else if (dev->pci_dev->msix_enabled) | |
2050 | pci_disable_msix(dev->pci_dev); | |
b60503ba | 2051 | nvme_release_instance(dev); |
091b6092 | 2052 | nvme_release_prp_pools(dev); |
574e8b95 | 2053 | disable: |
0ee5a7d7 | 2054 | pci_disable_device(pdev); |
574e8b95 | 2055 | pci_release_regions(pdev); |
b60503ba MW |
2056 | free: |
2057 | kfree(dev->queues); | |
2058 | kfree(dev->entry); | |
2059 | kfree(dev); | |
2060 | return result; | |
2061 | } | |
2062 | ||
8d85fce7 | 2063 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2064 | { |
2065 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
5e82e952 KB |
2066 | misc_deregister(&dev->miscdev); |
2067 | kref_put(&dev->kref, nvme_free_dev); | |
b60503ba MW |
2068 | } |
2069 | ||
2070 | /* These functions are yet to be implemented */ | |
2071 | #define nvme_error_detected NULL | |
2072 | #define nvme_dump_registers NULL | |
2073 | #define nvme_link_reset NULL | |
2074 | #define nvme_slot_reset NULL | |
2075 | #define nvme_error_resume NULL | |
2076 | #define nvme_suspend NULL | |
2077 | #define nvme_resume NULL | |
2078 | ||
1d352035 | 2079 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
2080 | .error_detected = nvme_error_detected, |
2081 | .mmio_enabled = nvme_dump_registers, | |
2082 | .link_reset = nvme_link_reset, | |
2083 | .slot_reset = nvme_slot_reset, | |
2084 | .resume = nvme_error_resume, | |
2085 | }; | |
2086 | ||
2087 | /* Move to pci_ids.h later */ | |
2088 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2089 | ||
2090 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
2091 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
2092 | { 0, } | |
2093 | }; | |
2094 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2095 | ||
2096 | static struct pci_driver nvme_driver = { | |
2097 | .name = "nvme", | |
2098 | .id_table = nvme_id_table, | |
2099 | .probe = nvme_probe, | |
8d85fce7 | 2100 | .remove = nvme_remove, |
b60503ba MW |
2101 | .suspend = nvme_suspend, |
2102 | .resume = nvme_resume, | |
2103 | .err_handler = &nvme_err_handler, | |
2104 | }; | |
2105 | ||
2106 | static int __init nvme_init(void) | |
2107 | { | |
0ac13140 | 2108 | int result; |
1fa6aead MW |
2109 | |
2110 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
2111 | if (IS_ERR(nvme_thread)) | |
2112 | return PTR_ERR(nvme_thread); | |
b60503ba | 2113 | |
5c42ea16 KB |
2114 | result = register_blkdev(nvme_major, "nvme"); |
2115 | if (result < 0) | |
1fa6aead | 2116 | goto kill_kthread; |
5c42ea16 | 2117 | else if (result > 0) |
0ac13140 | 2118 | nvme_major = result; |
b60503ba MW |
2119 | |
2120 | result = pci_register_driver(&nvme_driver); | |
1fa6aead MW |
2121 | if (result) |
2122 | goto unregister_blkdev; | |
2123 | return 0; | |
b60503ba | 2124 | |
1fa6aead | 2125 | unregister_blkdev: |
b60503ba | 2126 | unregister_blkdev(nvme_major, "nvme"); |
1fa6aead MW |
2127 | kill_kthread: |
2128 | kthread_stop(nvme_thread); | |
b60503ba MW |
2129 | return result; |
2130 | } | |
2131 | ||
2132 | static void __exit nvme_exit(void) | |
2133 | { | |
2134 | pci_unregister_driver(&nvme_driver); | |
2135 | unregister_blkdev(nvme_major, "nvme"); | |
1fa6aead | 2136 | kthread_stop(nvme_thread); |
b60503ba MW |
2137 | } |
2138 | ||
2139 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2140 | MODULE_LICENSE("GPL"); | |
366e8217 | 2141 | MODULE_VERSION("0.8"); |
b60503ba MW |
2142 | module_init(nvme_init); |
2143 | module_exit(nvme_exit); |