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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
8de05535 | 21 | #include <linux/bitops.h> |
b60503ba | 22 | #include <linux/blkdev.h> |
42f61420 | 23 | #include <linux/cpu.h> |
fd63e9ce | 24 | #include <linux/delay.h> |
b60503ba MW |
25 | #include <linux/errno.h> |
26 | #include <linux/fs.h> | |
27 | #include <linux/genhd.h> | |
5aff9382 | 28 | #include <linux/idr.h> |
b60503ba MW |
29 | #include <linux/init.h> |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/kdev_t.h> | |
1fa6aead | 33 | #include <linux/kthread.h> |
b60503ba MW |
34 | #include <linux/kernel.h> |
35 | #include <linux/mm.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/moduleparam.h> | |
38 | #include <linux/pci.h> | |
42f61420 | 39 | #include <linux/percpu.h> |
be7b6275 | 40 | #include <linux/poison.h> |
c3bfe717 | 41 | #include <linux/ptrace.h> |
b60503ba MW |
42 | #include <linux/sched.h> |
43 | #include <linux/slab.h> | |
44 | #include <linux/types.h> | |
5d0f6131 | 45 | #include <scsi/sg.h> |
797a796a HM |
46 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
47 | ||
b60503ba MW |
48 | #define NVME_Q_DEPTH 1024 |
49 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
50 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
e85248e5 | 51 | #define ADMIN_TIMEOUT (60 * HZ) |
b60503ba | 52 | |
b355084a KB |
53 | unsigned char io_timeout = 30; |
54 | module_param(io_timeout, byte, 0644); | |
55 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); | |
56 | ||
b60503ba MW |
57 | static int nvme_major; |
58 | module_param(nvme_major, int, 0); | |
59 | ||
58ffacb5 MW |
60 | static int use_threaded_interrupts; |
61 | module_param(use_threaded_interrupts, int, 0); | |
62 | ||
1fa6aead MW |
63 | static DEFINE_SPINLOCK(dev_list_lock); |
64 | static LIST_HEAD(dev_list); | |
65 | static struct task_struct *nvme_thread; | |
9a6b9458 | 66 | static struct workqueue_struct *nvme_workq; |
1fa6aead | 67 | |
d4b4ff8e KB |
68 | static void nvme_reset_failed_dev(struct work_struct *ws); |
69 | ||
4d115420 KB |
70 | struct async_cmd_info { |
71 | struct kthread_work work; | |
72 | struct kthread_worker *worker; | |
73 | u32 result; | |
74 | int status; | |
75 | void *ctx; | |
76 | }; | |
1fa6aead | 77 | |
b60503ba MW |
78 | /* |
79 | * An NVM Express queue. Each device has at least two (one for admin | |
80 | * commands and one for I/O commands). | |
81 | */ | |
82 | struct nvme_queue { | |
5a92e700 | 83 | struct rcu_head r_head; |
b60503ba | 84 | struct device *q_dmadev; |
091b6092 | 85 | struct nvme_dev *dev; |
3193f07b | 86 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
87 | spinlock_t q_lock; |
88 | struct nvme_command *sq_cmds; | |
89 | volatile struct nvme_completion *cqes; | |
90 | dma_addr_t sq_dma_addr; | |
91 | dma_addr_t cq_dma_addr; | |
92 | wait_queue_head_t sq_full; | |
1fa6aead | 93 | wait_queue_t sq_cong_wait; |
b60503ba MW |
94 | struct bio_list sq_cong; |
95 | u32 __iomem *q_db; | |
96 | u16 q_depth; | |
97 | u16 cq_vector; | |
98 | u16 sq_head; | |
99 | u16 sq_tail; | |
100 | u16 cq_head; | |
c30341dc | 101 | u16 qid; |
e9539f47 MW |
102 | u8 cq_phase; |
103 | u8 cqe_seen; | |
22404274 | 104 | u8 q_suspended; |
42f61420 | 105 | cpumask_var_t cpu_mask; |
4d115420 | 106 | struct async_cmd_info cmdinfo; |
b60503ba MW |
107 | unsigned long cmdid_data[]; |
108 | }; | |
109 | ||
110 | /* | |
111 | * Check we didin't inadvertently grow the command struct | |
112 | */ | |
113 | static inline void _nvme_check_size(void) | |
114 | { | |
115 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
116 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
117 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
118 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
119 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 120 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 121 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
122 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
123 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
124 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
125 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 126 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
127 | } |
128 | ||
5c1281a3 | 129 | typedef void (*nvme_completion_fn)(struct nvme_dev *, void *, |
c2f5b650 MW |
130 | struct nvme_completion *); |
131 | ||
e85248e5 | 132 | struct nvme_cmd_info { |
c2f5b650 MW |
133 | nvme_completion_fn fn; |
134 | void *ctx; | |
e85248e5 | 135 | unsigned long timeout; |
c30341dc | 136 | int aborted; |
e85248e5 MW |
137 | }; |
138 | ||
139 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
140 | { | |
141 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
142 | } | |
143 | ||
22404274 KB |
144 | static unsigned nvme_queue_extra(int depth) |
145 | { | |
146 | return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info)); | |
147 | } | |
148 | ||
b60503ba | 149 | /** |
714a7a22 MW |
150 | * alloc_cmdid() - Allocate a Command ID |
151 | * @nvmeq: The queue that will be used for this command | |
152 | * @ctx: A pointer that will be passed to the handler | |
c2f5b650 | 153 | * @handler: The function to call on completion |
b60503ba MW |
154 | * |
155 | * Allocate a Command ID for a queue. The data passed in will | |
156 | * be passed to the completion handler. This is implemented by using | |
157 | * the bottom two bits of the ctx pointer to store the handler ID. | |
158 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
159 | * We can change this if it becomes a problem. | |
184d2944 MW |
160 | * |
161 | * May be called with local interrupts disabled and the q_lock held, | |
162 | * or with interrupts enabled and no locks held. | |
b60503ba | 163 | */ |
c2f5b650 MW |
164 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, |
165 | nvme_completion_fn handler, unsigned timeout) | |
b60503ba | 166 | { |
e6d15f79 | 167 | int depth = nvmeq->q_depth - 1; |
e85248e5 | 168 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
169 | int cmdid; |
170 | ||
b60503ba MW |
171 | do { |
172 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
173 | if (cmdid >= depth) | |
174 | return -EBUSY; | |
175 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
176 | ||
c2f5b650 MW |
177 | info[cmdid].fn = handler; |
178 | info[cmdid].ctx = ctx; | |
e85248e5 | 179 | info[cmdid].timeout = jiffies + timeout; |
c30341dc | 180 | info[cmdid].aborted = 0; |
b60503ba MW |
181 | return cmdid; |
182 | } | |
183 | ||
184 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
c2f5b650 | 185 | nvme_completion_fn handler, unsigned timeout) |
b60503ba MW |
186 | { |
187 | int cmdid; | |
188 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 189 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
190 | return (cmdid < 0) ? -EINTR : cmdid; |
191 | } | |
192 | ||
c2f5b650 MW |
193 | /* Special values must be less than 0x1000 */ |
194 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
195 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
196 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
197 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
00df5cb4 | 198 | #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE) |
c30341dc | 199 | #define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE) |
be7b6275 | 200 | |
5c1281a3 | 201 | static void special_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
202 | struct nvme_completion *cqe) |
203 | { | |
204 | if (ctx == CMD_CTX_CANCELLED) | |
205 | return; | |
206 | if (ctx == CMD_CTX_FLUSH) | |
207 | return; | |
c30341dc KB |
208 | if (ctx == CMD_CTX_ABORT) { |
209 | ++dev->abort_limit; | |
210 | return; | |
211 | } | |
c2f5b650 | 212 | if (ctx == CMD_CTX_COMPLETED) { |
5c1281a3 | 213 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
214 | "completed id %d twice on queue %d\n", |
215 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
216 | return; | |
217 | } | |
218 | if (ctx == CMD_CTX_INVALID) { | |
5c1281a3 | 219 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
220 | "invalid id %d completed on queue %d\n", |
221 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
222 | return; | |
223 | } | |
224 | ||
5c1281a3 | 225 | dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
226 | } |
227 | ||
4d115420 KB |
228 | static void async_completion(struct nvme_dev *dev, void *ctx, |
229 | struct nvme_completion *cqe) | |
230 | { | |
231 | struct async_cmd_info *cmdinfo = ctx; | |
232 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
233 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
234 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
235 | } | |
236 | ||
184d2944 MW |
237 | /* |
238 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
239 | */ | |
c2f5b650 MW |
240 | static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid, |
241 | nvme_completion_fn *fn) | |
b60503ba | 242 | { |
c2f5b650 | 243 | void *ctx; |
e85248e5 | 244 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 245 | |
c2f5b650 MW |
246 | if (cmdid >= nvmeq->q_depth) { |
247 | *fn = special_completion; | |
48e3d398 | 248 | return CMD_CTX_INVALID; |
c2f5b650 | 249 | } |
859361a2 KB |
250 | if (fn) |
251 | *fn = info[cmdid].fn; | |
c2f5b650 MW |
252 | ctx = info[cmdid].ctx; |
253 | info[cmdid].fn = special_completion; | |
e85248e5 | 254 | info[cmdid].ctx = CMD_CTX_COMPLETED; |
b60503ba MW |
255 | clear_bit(cmdid, nvmeq->cmdid_data); |
256 | wake_up(&nvmeq->sq_full); | |
c2f5b650 | 257 | return ctx; |
b60503ba MW |
258 | } |
259 | ||
c2f5b650 MW |
260 | static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid, |
261 | nvme_completion_fn *fn) | |
3c0cf138 | 262 | { |
c2f5b650 | 263 | void *ctx; |
e85248e5 | 264 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
c2f5b650 MW |
265 | if (fn) |
266 | *fn = info[cmdid].fn; | |
267 | ctx = info[cmdid].ctx; | |
268 | info[cmdid].fn = special_completion; | |
e85248e5 | 269 | info[cmdid].ctx = CMD_CTX_CANCELLED; |
c2f5b650 | 270 | return ctx; |
3c0cf138 MW |
271 | } |
272 | ||
5a92e700 | 273 | static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid) |
b60503ba | 274 | { |
5a92e700 | 275 | return rcu_dereference_raw(dev->queues[qid]); |
b60503ba MW |
276 | } |
277 | ||
4f5099af | 278 | static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU) |
5a92e700 | 279 | { |
42f61420 | 280 | unsigned queue_id = get_cpu_var(*dev->io_queue); |
5a92e700 | 281 | rcu_read_lock(); |
42f61420 | 282 | return rcu_dereference(dev->queues[queue_id]); |
5a92e700 KB |
283 | } |
284 | ||
4f5099af | 285 | static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU) |
b60503ba | 286 | { |
5a92e700 | 287 | rcu_read_unlock(); |
42f61420 | 288 | put_cpu_var(nvmeq->dev->io_queue); |
b60503ba MW |
289 | } |
290 | ||
4f5099af KB |
291 | static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx) |
292 | __acquires(RCU) | |
293 | { | |
294 | rcu_read_lock(); | |
295 | return rcu_dereference(dev->queues[q_idx]); | |
296 | } | |
297 | ||
298 | static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU) | |
299 | { | |
300 | rcu_read_unlock(); | |
301 | } | |
302 | ||
b60503ba | 303 | /** |
714a7a22 | 304 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
305 | * @nvmeq: The queue to use |
306 | * @cmd: The command to send | |
307 | * | |
308 | * Safe to use from interrupt context | |
309 | */ | |
310 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
311 | { | |
312 | unsigned long flags; | |
313 | u16 tail; | |
b60503ba | 314 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
4f5099af KB |
315 | if (nvmeq->q_suspended) { |
316 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
317 | return -EBUSY; | |
318 | } | |
b60503ba MW |
319 | tail = nvmeq->sq_tail; |
320 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
b60503ba MW |
321 | if (++tail == nvmeq->q_depth) |
322 | tail = 0; | |
7547881d | 323 | writel(tail, nvmeq->q_db); |
b60503ba MW |
324 | nvmeq->sq_tail = tail; |
325 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
eca18b23 | 330 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 331 | { |
eca18b23 | 332 | return ((void *)iod) + iod->offset; |
e025344c SMM |
333 | } |
334 | ||
eca18b23 MW |
335 | /* |
336 | * Will slightly overestimate the number of pages needed. This is OK | |
337 | * as it only leads to a small amount of wasted memory for the lifetime of | |
338 | * the I/O. | |
339 | */ | |
340 | static int nvme_npages(unsigned size) | |
341 | { | |
342 | unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE); | |
343 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
344 | } | |
b60503ba | 345 | |
eca18b23 MW |
346 | static struct nvme_iod * |
347 | nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp) | |
b60503ba | 348 | { |
eca18b23 MW |
349 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
350 | sizeof(__le64 *) * nvme_npages(nbytes) + | |
351 | sizeof(struct scatterlist) * nseg, gfp); | |
352 | ||
353 | if (iod) { | |
354 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
355 | iod->npages = -1; | |
356 | iod->length = nbytes; | |
2b196034 | 357 | iod->nents = 0; |
6198221f | 358 | iod->start_time = jiffies; |
eca18b23 MW |
359 | } |
360 | ||
361 | return iod; | |
b60503ba MW |
362 | } |
363 | ||
5d0f6131 | 364 | void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 365 | { |
eca18b23 MW |
366 | const int last_prp = PAGE_SIZE / 8 - 1; |
367 | int i; | |
368 | __le64 **list = iod_list(iod); | |
369 | dma_addr_t prp_dma = iod->first_dma; | |
370 | ||
371 | if (iod->npages == 0) | |
372 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
373 | for (i = 0; i < iod->npages; i++) { | |
374 | __le64 *prp_list = list[i]; | |
375 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
376 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
377 | prp_dma = next_prp_dma; | |
378 | } | |
379 | kfree(iod); | |
b60503ba MW |
380 | } |
381 | ||
6198221f KB |
382 | static void nvme_start_io_acct(struct bio *bio) |
383 | { | |
384 | struct gendisk *disk = bio->bi_bdev->bd_disk; | |
385 | const int rw = bio_data_dir(bio); | |
386 | int cpu = part_stat_lock(); | |
387 | part_round_stats(cpu, &disk->part0); | |
388 | part_stat_inc(cpu, &disk->part0, ios[rw]); | |
389 | part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio)); | |
390 | part_inc_in_flight(&disk->part0, rw); | |
391 | part_stat_unlock(); | |
392 | } | |
393 | ||
394 | static void nvme_end_io_acct(struct bio *bio, unsigned long start_time) | |
395 | { | |
396 | struct gendisk *disk = bio->bi_bdev->bd_disk; | |
397 | const int rw = bio_data_dir(bio); | |
398 | unsigned long duration = jiffies - start_time; | |
399 | int cpu = part_stat_lock(); | |
400 | part_stat_add(cpu, &disk->part0, ticks[rw], duration); | |
401 | part_round_stats(cpu, &disk->part0); | |
402 | part_dec_in_flight(&disk->part0, rw); | |
403 | part_stat_unlock(); | |
404 | } | |
405 | ||
5c1281a3 | 406 | static void bio_completion(struct nvme_dev *dev, void *ctx, |
b60503ba MW |
407 | struct nvme_completion *cqe) |
408 | { | |
eca18b23 MW |
409 | struct nvme_iod *iod = ctx; |
410 | struct bio *bio = iod->private; | |
b60503ba MW |
411 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
412 | ||
9e59d091 | 413 | if (iod->nents) { |
2b196034 | 414 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
b60503ba | 415 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
9e59d091 KB |
416 | nvme_end_io_acct(bio, iod->start_time); |
417 | } | |
eca18b23 | 418 | nvme_free_iod(dev, iod); |
427e9708 | 419 | if (status) |
1ad2f893 | 420 | bio_endio(bio, -EIO); |
427e9708 | 421 | else |
1ad2f893 | 422 | bio_endio(bio, 0); |
b60503ba MW |
423 | } |
424 | ||
184d2944 | 425 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
5d0f6131 VV |
426 | int nvme_setup_prps(struct nvme_dev *dev, struct nvme_common_command *cmd, |
427 | struct nvme_iod *iod, int total_len, gfp_t gfp) | |
ff22b54f | 428 | { |
99802a7a | 429 | struct dma_pool *pool; |
eca18b23 MW |
430 | int length = total_len; |
431 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
432 | int dma_len = sg_dma_len(sg); |
433 | u64 dma_addr = sg_dma_address(sg); | |
434 | int offset = offset_in_page(dma_addr); | |
e025344c | 435 | __le64 *prp_list; |
eca18b23 | 436 | __le64 **list = iod_list(iod); |
e025344c | 437 | dma_addr_t prp_dma; |
eca18b23 | 438 | int nprps, i; |
ff22b54f MW |
439 | |
440 | cmd->prp1 = cpu_to_le64(dma_addr); | |
441 | length -= (PAGE_SIZE - offset); | |
442 | if (length <= 0) | |
eca18b23 | 443 | return total_len; |
ff22b54f MW |
444 | |
445 | dma_len -= (PAGE_SIZE - offset); | |
446 | if (dma_len) { | |
447 | dma_addr += (PAGE_SIZE - offset); | |
448 | } else { | |
449 | sg = sg_next(sg); | |
450 | dma_addr = sg_dma_address(sg); | |
451 | dma_len = sg_dma_len(sg); | |
452 | } | |
453 | ||
454 | if (length <= PAGE_SIZE) { | |
455 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 | 456 | return total_len; |
e025344c SMM |
457 | } |
458 | ||
459 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
99802a7a MW |
460 | if (nprps <= (256 / 8)) { |
461 | pool = dev->prp_small_pool; | |
eca18b23 | 462 | iod->npages = 0; |
99802a7a MW |
463 | } else { |
464 | pool = dev->prp_page_pool; | |
eca18b23 | 465 | iod->npages = 1; |
99802a7a MW |
466 | } |
467 | ||
b77954cb MW |
468 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
469 | if (!prp_list) { | |
470 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 MW |
471 | iod->npages = -1; |
472 | return (total_len - length) + PAGE_SIZE; | |
b77954cb | 473 | } |
eca18b23 MW |
474 | list[0] = prp_list; |
475 | iod->first_dma = prp_dma; | |
e025344c SMM |
476 | cmd->prp2 = cpu_to_le64(prp_dma); |
477 | i = 0; | |
478 | for (;;) { | |
7523d834 | 479 | if (i == PAGE_SIZE / 8) { |
e025344c | 480 | __le64 *old_prp_list = prp_list; |
b77954cb | 481 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
482 | if (!prp_list) |
483 | return total_len - length; | |
484 | list[iod->npages++] = prp_list; | |
7523d834 MW |
485 | prp_list[0] = old_prp_list[i - 1]; |
486 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
487 | i = 1; | |
e025344c SMM |
488 | } |
489 | prp_list[i++] = cpu_to_le64(dma_addr); | |
490 | dma_len -= PAGE_SIZE; | |
491 | dma_addr += PAGE_SIZE; | |
492 | length -= PAGE_SIZE; | |
493 | if (length <= 0) | |
494 | break; | |
495 | if (dma_len > 0) | |
496 | continue; | |
497 | BUG_ON(dma_len < 0); | |
498 | sg = sg_next(sg); | |
499 | dma_addr = sg_dma_address(sg); | |
500 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
501 | } |
502 | ||
eca18b23 | 503 | return total_len; |
ff22b54f MW |
504 | } |
505 | ||
427e9708 | 506 | static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq, |
20d0189b | 507 | int len) |
427e9708 | 508 | { |
20d0189b KO |
509 | struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL); |
510 | if (!split) | |
427e9708 KB |
511 | return -ENOMEM; |
512 | ||
20d0189b KO |
513 | bio_chain(split, bio); |
514 | ||
427e9708 KB |
515 | if (bio_list_empty(&nvmeq->sq_cong)) |
516 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
20d0189b KO |
517 | bio_list_add(&nvmeq->sq_cong, split); |
518 | bio_list_add(&nvmeq->sq_cong, bio); | |
427e9708 KB |
519 | |
520 | return 0; | |
521 | } | |
522 | ||
1ad2f893 MW |
523 | /* NVMe scatterlists require no holes in the virtual address */ |
524 | #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \ | |
525 | (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE)) | |
526 | ||
427e9708 | 527 | static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod, |
b60503ba MW |
528 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
529 | { | |
7988613b KO |
530 | struct bio_vec bvec, bvprv; |
531 | struct bvec_iter iter; | |
76830840 | 532 | struct scatterlist *sg = NULL; |
7988613b KO |
533 | int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size; |
534 | int first = 1; | |
159b67d7 KB |
535 | |
536 | if (nvmeq->dev->stripe_size) | |
537 | split_len = nvmeq->dev->stripe_size - | |
4f024f37 KO |
538 | ((bio->bi_iter.bi_sector << 9) & |
539 | (nvmeq->dev->stripe_size - 1)); | |
b60503ba | 540 | |
eca18b23 | 541 | sg_init_table(iod->sg, psegs); |
7988613b KO |
542 | bio_for_each_segment(bvec, bio, iter) { |
543 | if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) { | |
544 | sg->length += bvec.bv_len; | |
76830840 | 545 | } else { |
7988613b KO |
546 | if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec)) |
547 | return nvme_split_and_submit(bio, nvmeq, | |
20d0189b | 548 | length); |
427e9708 | 549 | |
eca18b23 | 550 | sg = sg ? sg + 1 : iod->sg; |
7988613b KO |
551 | sg_set_page(sg, bvec.bv_page, |
552 | bvec.bv_len, bvec.bv_offset); | |
76830840 MW |
553 | nsegs++; |
554 | } | |
159b67d7 | 555 | |
7988613b | 556 | if (split_len - length < bvec.bv_len) |
20d0189b | 557 | return nvme_split_and_submit(bio, nvmeq, split_len); |
7988613b | 558 | length += bvec.bv_len; |
76830840 | 559 | bvprv = bvec; |
7988613b | 560 | first = 0; |
b60503ba | 561 | } |
eca18b23 | 562 | iod->nents = nsegs; |
76830840 | 563 | sg_mark_end(sg); |
427e9708 | 564 | if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0) |
1ad2f893 | 565 | return -ENOMEM; |
427e9708 | 566 | |
4f024f37 | 567 | BUG_ON(length != bio->bi_iter.bi_size); |
1ad2f893 | 568 | return length; |
b60503ba MW |
569 | } |
570 | ||
0e5e4f0e KB |
571 | /* |
572 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
573 | * worth having a special pool for these or additional cases to handle freeing | |
574 | * the iod. | |
575 | */ | |
576 | static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
577 | struct bio *bio, struct nvme_iod *iod, int cmdid) | |
578 | { | |
579 | struct nvme_dsm_range *range; | |
580 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
581 | ||
582 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, | |
583 | &iod->first_dma); | |
584 | if (!range) | |
585 | return -ENOMEM; | |
586 | ||
587 | iod_list(iod)[0] = (__le64 *)range; | |
588 | iod->npages = 0; | |
589 | ||
590 | range->cattr = cpu_to_le32(0); | |
4f024f37 KO |
591 | range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift); |
592 | range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector)); | |
0e5e4f0e KB |
593 | |
594 | memset(cmnd, 0, sizeof(*cmnd)); | |
595 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
596 | cmnd->dsm.command_id = cmdid; | |
597 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); | |
598 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
599 | cmnd->dsm.nr = 0; | |
600 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
601 | ||
602 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
603 | nvmeq->sq_tail = 0; | |
604 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
00df5cb4 MW |
609 | static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
610 | int cmdid) | |
611 | { | |
612 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
613 | ||
614 | memset(cmnd, 0, sizeof(*cmnd)); | |
615 | cmnd->common.opcode = nvme_cmd_flush; | |
616 | cmnd->common.command_id = cmdid; | |
617 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
618 | ||
619 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
620 | nvmeq->sq_tail = 0; | |
621 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
5d0f6131 | 626 | int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) |
00df5cb4 MW |
627 | { |
628 | int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, | |
ff976d72 | 629 | special_completion, NVME_IO_TIMEOUT); |
00df5cb4 MW |
630 | if (unlikely(cmdid < 0)) |
631 | return cmdid; | |
632 | ||
633 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
634 | } | |
635 | ||
184d2944 MW |
636 | /* |
637 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
638 | */ | |
b60503ba MW |
639 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
640 | struct bio *bio) | |
641 | { | |
ff22b54f | 642 | struct nvme_command *cmnd; |
eca18b23 | 643 | struct nvme_iod *iod; |
b60503ba | 644 | enum dma_data_direction dma_dir; |
1287dabd | 645 | int cmdid, length, result; |
b60503ba MW |
646 | u16 control; |
647 | u32 dsmgmt; | |
b60503ba MW |
648 | int psegs = bio_phys_segments(ns->queue, bio); |
649 | ||
00df5cb4 MW |
650 | if ((bio->bi_rw & REQ_FLUSH) && psegs) { |
651 | result = nvme_submit_flush_data(nvmeq, ns); | |
652 | if (result) | |
653 | return result; | |
654 | } | |
655 | ||
1287dabd | 656 | result = -ENOMEM; |
4f024f37 | 657 | iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC); |
eca18b23 | 658 | if (!iod) |
eeee3226 | 659 | goto nomem; |
eca18b23 | 660 | iod->private = bio; |
b60503ba | 661 | |
eeee3226 | 662 | result = -EBUSY; |
ff976d72 | 663 | cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT); |
b60503ba | 664 | if (unlikely(cmdid < 0)) |
eca18b23 | 665 | goto free_iod; |
b60503ba | 666 | |
0e5e4f0e KB |
667 | if (bio->bi_rw & REQ_DISCARD) { |
668 | result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid); | |
669 | if (result) | |
670 | goto free_cmdid; | |
671 | return result; | |
672 | } | |
00df5cb4 MW |
673 | if ((bio->bi_rw & REQ_FLUSH) && !psegs) |
674 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
675 | ||
b60503ba MW |
676 | control = 0; |
677 | if (bio->bi_rw & REQ_FUA) | |
678 | control |= NVME_RW_FUA; | |
679 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
680 | control |= NVME_RW_LR; | |
681 | ||
682 | dsmgmt = 0; | |
683 | if (bio->bi_rw & REQ_RAHEAD) | |
684 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
685 | ||
ff22b54f | 686 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 687 | |
b8deb62c | 688 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 689 | if (bio_data_dir(bio)) { |
ff22b54f | 690 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
691 | dma_dir = DMA_TO_DEVICE; |
692 | } else { | |
ff22b54f | 693 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
694 | dma_dir = DMA_FROM_DEVICE; |
695 | } | |
696 | ||
427e9708 KB |
697 | result = nvme_map_bio(nvmeq, iod, bio, dma_dir, psegs); |
698 | if (result <= 0) | |
859361a2 | 699 | goto free_cmdid; |
1ad2f893 | 700 | length = result; |
b60503ba | 701 | |
ff22b54f MW |
702 | cmnd->rw.command_id = cmdid; |
703 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
eca18b23 MW |
704 | length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length, |
705 | GFP_ATOMIC); | |
4f024f37 | 706 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector)); |
1ad2f893 | 707 | cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1); |
ff22b54f MW |
708 | cmnd->rw.control = cpu_to_le16(control); |
709 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 710 | |
6198221f | 711 | nvme_start_io_acct(bio); |
b60503ba MW |
712 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
713 | nvmeq->sq_tail = 0; | |
7547881d | 714 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 715 | |
1974b1ae MW |
716 | return 0; |
717 | ||
859361a2 KB |
718 | free_cmdid: |
719 | free_cmdid(nvmeq, cmdid, NULL); | |
eca18b23 MW |
720 | free_iod: |
721 | nvme_free_iod(nvmeq->dev, iod); | |
eeee3226 MW |
722 | nomem: |
723 | return result; | |
b60503ba MW |
724 | } |
725 | ||
e9539f47 | 726 | static int nvme_process_cq(struct nvme_queue *nvmeq) |
b60503ba | 727 | { |
82123460 | 728 | u16 head, phase; |
b60503ba | 729 | |
b60503ba | 730 | head = nvmeq->cq_head; |
82123460 | 731 | phase = nvmeq->cq_phase; |
b60503ba MW |
732 | |
733 | for (;;) { | |
c2f5b650 MW |
734 | void *ctx; |
735 | nvme_completion_fn fn; | |
b60503ba | 736 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 737 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
738 | break; |
739 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
740 | if (++head == nvmeq->q_depth) { | |
741 | head = 0; | |
82123460 | 742 | phase = !phase; |
b60503ba MW |
743 | } |
744 | ||
c2f5b650 | 745 | ctx = free_cmdid(nvmeq, cqe.command_id, &fn); |
5c1281a3 | 746 | fn(nvmeq->dev, ctx, &cqe); |
b60503ba MW |
747 | } |
748 | ||
749 | /* If the controller ignores the cq head doorbell and continuously | |
750 | * writes to the queue, it is theoretically possible to wrap around | |
751 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
752 | * requires that 0.1% of your interrupts are handled, so this isn't | |
753 | * a big problem. | |
754 | */ | |
82123460 | 755 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
e9539f47 | 756 | return 0; |
b60503ba | 757 | |
b80d5ccc | 758 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
b60503ba | 759 | nvmeq->cq_head = head; |
82123460 | 760 | nvmeq->cq_phase = phase; |
b60503ba | 761 | |
e9539f47 MW |
762 | nvmeq->cqe_seen = 1; |
763 | return 1; | |
b60503ba MW |
764 | } |
765 | ||
7d822457 MW |
766 | static void nvme_make_request(struct request_queue *q, struct bio *bio) |
767 | { | |
768 | struct nvme_ns *ns = q->queuedata; | |
769 | struct nvme_queue *nvmeq = get_nvmeq(ns->dev); | |
770 | int result = -EBUSY; | |
771 | ||
cd638946 KB |
772 | if (!nvmeq) { |
773 | put_nvmeq(NULL); | |
774 | bio_endio(bio, -EIO); | |
775 | return; | |
776 | } | |
777 | ||
7d822457 | 778 | spin_lock_irq(&nvmeq->q_lock); |
22404274 | 779 | if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong)) |
7d822457 MW |
780 | result = nvme_submit_bio_queue(nvmeq, ns, bio); |
781 | if (unlikely(result)) { | |
782 | if (bio_list_empty(&nvmeq->sq_cong)) | |
783 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
784 | bio_list_add(&nvmeq->sq_cong, bio); | |
785 | } | |
786 | ||
787 | nvme_process_cq(nvmeq); | |
788 | spin_unlock_irq(&nvmeq->q_lock); | |
789 | put_nvmeq(nvmeq); | |
790 | } | |
791 | ||
b60503ba | 792 | static irqreturn_t nvme_irq(int irq, void *data) |
58ffacb5 MW |
793 | { |
794 | irqreturn_t result; | |
795 | struct nvme_queue *nvmeq = data; | |
796 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
797 | nvme_process_cq(nvmeq); |
798 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
799 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
800 | spin_unlock(&nvmeq->q_lock); |
801 | return result; | |
802 | } | |
803 | ||
804 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
805 | { | |
806 | struct nvme_queue *nvmeq = data; | |
807 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
808 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
809 | return IRQ_NONE; | |
810 | return IRQ_WAKE_THREAD; | |
811 | } | |
812 | ||
3c0cf138 MW |
813 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
814 | { | |
815 | spin_lock_irq(&nvmeq->q_lock); | |
c2f5b650 | 816 | cancel_cmdid(nvmeq, cmdid, NULL); |
3c0cf138 MW |
817 | spin_unlock_irq(&nvmeq->q_lock); |
818 | } | |
819 | ||
c2f5b650 MW |
820 | struct sync_cmd_info { |
821 | struct task_struct *task; | |
822 | u32 result; | |
823 | int status; | |
824 | }; | |
825 | ||
5c1281a3 | 826 | static void sync_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
827 | struct nvme_completion *cqe) |
828 | { | |
829 | struct sync_cmd_info *cmdinfo = ctx; | |
830 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
831 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
832 | wake_up_process(cmdinfo->task); | |
833 | } | |
834 | ||
b60503ba MW |
835 | /* |
836 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
837 | * if the result is positive, it's an NVM Express status code | |
838 | */ | |
4f5099af KB |
839 | static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx, |
840 | struct nvme_command *cmd, | |
5d0f6131 | 841 | u32 *result, unsigned timeout) |
b60503ba | 842 | { |
4f5099af | 843 | int cmdid, ret; |
b60503ba | 844 | struct sync_cmd_info cmdinfo; |
4f5099af KB |
845 | struct nvme_queue *nvmeq; |
846 | ||
847 | nvmeq = lock_nvmeq(dev, q_idx); | |
848 | if (!nvmeq) { | |
849 | unlock_nvmeq(nvmeq); | |
850 | return -ENODEV; | |
851 | } | |
b60503ba MW |
852 | |
853 | cmdinfo.task = current; | |
854 | cmdinfo.status = -EINTR; | |
855 | ||
4f5099af KB |
856 | cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout); |
857 | if (cmdid < 0) { | |
858 | unlock_nvmeq(nvmeq); | |
b60503ba | 859 | return cmdid; |
4f5099af | 860 | } |
b60503ba MW |
861 | cmd->common.command_id = cmdid; |
862 | ||
3c0cf138 | 863 | set_current_state(TASK_KILLABLE); |
4f5099af KB |
864 | ret = nvme_submit_cmd(nvmeq, cmd); |
865 | if (ret) { | |
866 | free_cmdid(nvmeq, cmdid, NULL); | |
867 | unlock_nvmeq(nvmeq); | |
868 | set_current_state(TASK_RUNNING); | |
869 | return ret; | |
870 | } | |
871 | unlock_nvmeq(nvmeq); | |
78f8d257 | 872 | schedule_timeout(timeout); |
b60503ba | 873 | |
3c0cf138 | 874 | if (cmdinfo.status == -EINTR) { |
4f5099af KB |
875 | nvmeq = lock_nvmeq(dev, q_idx); |
876 | if (nvmeq) | |
877 | nvme_abort_command(nvmeq, cmdid); | |
878 | unlock_nvmeq(nvmeq); | |
3c0cf138 MW |
879 | return -EINTR; |
880 | } | |
881 | ||
b60503ba MW |
882 | if (result) |
883 | *result = cmdinfo.result; | |
884 | ||
885 | return cmdinfo.status; | |
886 | } | |
887 | ||
4d115420 KB |
888 | static int nvme_submit_async_cmd(struct nvme_queue *nvmeq, |
889 | struct nvme_command *cmd, | |
890 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
891 | { | |
892 | int cmdid; | |
893 | ||
894 | cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout); | |
895 | if (cmdid < 0) | |
896 | return cmdid; | |
897 | cmdinfo->status = -EINTR; | |
898 | cmd->common.command_id = cmdid; | |
4f5099af | 899 | return nvme_submit_cmd(nvmeq, cmd); |
4d115420 KB |
900 | } |
901 | ||
5d0f6131 | 902 | int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
b60503ba MW |
903 | u32 *result) |
904 | { | |
4f5099af KB |
905 | return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT); |
906 | } | |
907 | ||
908 | int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
909 | u32 *result) | |
910 | { | |
911 | return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result, | |
912 | NVME_IO_TIMEOUT); | |
b60503ba MW |
913 | } |
914 | ||
4d115420 KB |
915 | static int nvme_submit_admin_cmd_async(struct nvme_dev *dev, |
916 | struct nvme_command *cmd, struct async_cmd_info *cmdinfo) | |
917 | { | |
5a92e700 | 918 | return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo, |
4d115420 KB |
919 | ADMIN_TIMEOUT); |
920 | } | |
921 | ||
b60503ba MW |
922 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
923 | { | |
924 | int status; | |
925 | struct nvme_command c; | |
926 | ||
927 | memset(&c, 0, sizeof(c)); | |
928 | c.delete_queue.opcode = opcode; | |
929 | c.delete_queue.qid = cpu_to_le16(id); | |
930 | ||
931 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
932 | if (status) | |
933 | return -EIO; | |
934 | return 0; | |
935 | } | |
936 | ||
937 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
938 | struct nvme_queue *nvmeq) | |
939 | { | |
940 | int status; | |
941 | struct nvme_command c; | |
942 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
943 | ||
944 | memset(&c, 0, sizeof(c)); | |
945 | c.create_cq.opcode = nvme_admin_create_cq; | |
946 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
947 | c.create_cq.cqid = cpu_to_le16(qid); | |
948 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
949 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
950 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
951 | ||
952 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
953 | if (status) | |
954 | return -EIO; | |
955 | return 0; | |
956 | } | |
957 | ||
958 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
959 | struct nvme_queue *nvmeq) | |
960 | { | |
961 | int status; | |
962 | struct nvme_command c; | |
963 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
964 | ||
965 | memset(&c, 0, sizeof(c)); | |
966 | c.create_sq.opcode = nvme_admin_create_sq; | |
967 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
968 | c.create_sq.sqid = cpu_to_le16(qid); | |
969 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
970 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
971 | c.create_sq.cqid = cpu_to_le16(qid); | |
972 | ||
973 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
974 | if (status) | |
975 | return -EIO; | |
976 | return 0; | |
977 | } | |
978 | ||
979 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
980 | { | |
981 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
982 | } | |
983 | ||
984 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
985 | { | |
986 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
987 | } | |
988 | ||
5d0f6131 | 989 | int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
bc5fc7e4 MW |
990 | dma_addr_t dma_addr) |
991 | { | |
992 | struct nvme_command c; | |
993 | ||
994 | memset(&c, 0, sizeof(c)); | |
995 | c.identify.opcode = nvme_admin_identify; | |
996 | c.identify.nsid = cpu_to_le32(nsid); | |
997 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
998 | c.identify.cns = cpu_to_le32(cns); | |
999 | ||
1000 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
1001 | } | |
1002 | ||
5d0f6131 | 1003 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
08df1e05 | 1004 | dma_addr_t dma_addr, u32 *result) |
bc5fc7e4 MW |
1005 | { |
1006 | struct nvme_command c; | |
1007 | ||
1008 | memset(&c, 0, sizeof(c)); | |
1009 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 1010 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
1011 | c.features.prp1 = cpu_to_le64(dma_addr); |
1012 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 1013 | |
08df1e05 | 1014 | return nvme_submit_admin_cmd(dev, &c, result); |
df348139 MW |
1015 | } |
1016 | ||
5d0f6131 VV |
1017 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
1018 | dma_addr_t dma_addr, u32 *result) | |
df348139 MW |
1019 | { |
1020 | struct nvme_command c; | |
1021 | ||
1022 | memset(&c, 0, sizeof(c)); | |
1023 | c.features.opcode = nvme_admin_set_features; | |
1024 | c.features.prp1 = cpu_to_le64(dma_addr); | |
1025 | c.features.fid = cpu_to_le32(fid); | |
1026 | c.features.dword11 = cpu_to_le32(dword11); | |
1027 | ||
bc5fc7e4 MW |
1028 | return nvme_submit_admin_cmd(dev, &c, result); |
1029 | } | |
1030 | ||
c30341dc KB |
1031 | /** |
1032 | * nvme_abort_cmd - Attempt aborting a command | |
1033 | * @cmdid: Command id of a timed out IO | |
1034 | * @queue: The queue with timed out IO | |
1035 | * | |
1036 | * Schedule controller reset if the command was already aborted once before and | |
1037 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1038 | */ | |
1039 | static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq) | |
1040 | { | |
1041 | int a_cmdid; | |
1042 | struct nvme_command cmd; | |
1043 | struct nvme_dev *dev = nvmeq->dev; | |
1044 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
5a92e700 | 1045 | struct nvme_queue *adminq; |
c30341dc KB |
1046 | |
1047 | if (!nvmeq->qid || info[cmdid].aborted) { | |
1048 | if (work_busy(&dev->reset_work)) | |
1049 | return; | |
1050 | list_del_init(&dev->node); | |
1051 | dev_warn(&dev->pci_dev->dev, | |
1052 | "I/O %d QID %d timeout, reset controller\n", cmdid, | |
1053 | nvmeq->qid); | |
bdfd70fd | 1054 | PREPARE_WORK(&dev->reset_work, nvme_reset_failed_dev); |
c30341dc KB |
1055 | queue_work(nvme_workq, &dev->reset_work); |
1056 | return; | |
1057 | } | |
1058 | ||
1059 | if (!dev->abort_limit) | |
1060 | return; | |
1061 | ||
5a92e700 KB |
1062 | adminq = rcu_dereference(dev->queues[0]); |
1063 | a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion, | |
c30341dc KB |
1064 | ADMIN_TIMEOUT); |
1065 | if (a_cmdid < 0) | |
1066 | return; | |
1067 | ||
1068 | memset(&cmd, 0, sizeof(cmd)); | |
1069 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
1070 | cmd.abort.cid = cmdid; | |
1071 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); | |
1072 | cmd.abort.command_id = a_cmdid; | |
1073 | ||
1074 | --dev->abort_limit; | |
1075 | info[cmdid].aborted = 1; | |
1076 | info[cmdid].timeout = jiffies + ADMIN_TIMEOUT; | |
1077 | ||
1078 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid, | |
1079 | nvmeq->qid); | |
5a92e700 | 1080 | nvme_submit_cmd(adminq, &cmd); |
c30341dc KB |
1081 | } |
1082 | ||
a09115b2 MW |
1083 | /** |
1084 | * nvme_cancel_ios - Cancel outstanding I/Os | |
1085 | * @queue: The queue to cancel I/Os on | |
1086 | * @timeout: True to only cancel I/Os which have timed out | |
1087 | */ | |
1088 | static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout) | |
1089 | { | |
1090 | int depth = nvmeq->q_depth - 1; | |
1091 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
1092 | unsigned long now = jiffies; | |
1093 | int cmdid; | |
1094 | ||
1095 | for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) { | |
1096 | void *ctx; | |
1097 | nvme_completion_fn fn; | |
1098 | static struct nvme_completion cqe = { | |
af2d9ca7 | 1099 | .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1), |
a09115b2 MW |
1100 | }; |
1101 | ||
1102 | if (timeout && !time_after(now, info[cmdid].timeout)) | |
1103 | continue; | |
053ab702 KB |
1104 | if (info[cmdid].ctx == CMD_CTX_CANCELLED) |
1105 | continue; | |
c30341dc KB |
1106 | if (timeout && nvmeq->dev->initialized) { |
1107 | nvme_abort_cmd(cmdid, nvmeq); | |
1108 | continue; | |
1109 | } | |
1110 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid, | |
1111 | nvmeq->qid); | |
a09115b2 MW |
1112 | ctx = cancel_cmdid(nvmeq, cmdid, &fn); |
1113 | fn(nvmeq->dev, ctx, &cqe); | |
1114 | } | |
1115 | } | |
1116 | ||
5a92e700 | 1117 | static void nvme_free_queue(struct rcu_head *r) |
9e866774 | 1118 | { |
5a92e700 KB |
1119 | struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head); |
1120 | ||
22404274 KB |
1121 | spin_lock_irq(&nvmeq->q_lock); |
1122 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1123 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1124 | bio_endio(bio, -EIO); | |
1125 | } | |
1126 | spin_unlock_irq(&nvmeq->q_lock); | |
1127 | ||
9e866774 MW |
1128 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1129 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1130 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1131 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
42f61420 KB |
1132 | if (nvmeq->qid) |
1133 | free_cpumask_var(nvmeq->cpu_mask); | |
9e866774 MW |
1134 | kfree(nvmeq); |
1135 | } | |
1136 | ||
a1a5ef99 | 1137 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1138 | { |
1139 | int i; | |
1140 | ||
a1a5ef99 | 1141 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
5a92e700 KB |
1142 | struct nvme_queue *nvmeq = raw_nvmeq(dev, i); |
1143 | rcu_assign_pointer(dev->queues[i], NULL); | |
1144 | call_rcu(&nvmeq->r_head, nvme_free_queue); | |
22404274 | 1145 | dev->queue_count--; |
22404274 KB |
1146 | } |
1147 | } | |
1148 | ||
4d115420 KB |
1149 | /** |
1150 | * nvme_suspend_queue - put queue into suspended state | |
1151 | * @nvmeq - queue to suspend | |
1152 | * | |
1153 | * Returns 1 if already suspended, 0 otherwise. | |
1154 | */ | |
1155 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1156 | { |
4d115420 | 1157 | int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; |
b60503ba | 1158 | |
a09115b2 | 1159 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1160 | if (nvmeq->q_suspended) { |
1161 | spin_unlock_irq(&nvmeq->q_lock); | |
4d115420 | 1162 | return 1; |
3295874b | 1163 | } |
22404274 | 1164 | nvmeq->q_suspended = 1; |
42f61420 | 1165 | nvmeq->dev->online_queues--; |
a09115b2 MW |
1166 | spin_unlock_irq(&nvmeq->q_lock); |
1167 | ||
aba2080f MW |
1168 | irq_set_affinity_hint(vector, NULL); |
1169 | free_irq(vector, nvmeq); | |
b60503ba | 1170 | |
4d115420 KB |
1171 | return 0; |
1172 | } | |
b60503ba | 1173 | |
4d115420 KB |
1174 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1175 | { | |
22404274 KB |
1176 | spin_lock_irq(&nvmeq->q_lock); |
1177 | nvme_process_cq(nvmeq); | |
1178 | nvme_cancel_ios(nvmeq, false); | |
1179 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1180 | } |
1181 | ||
4d115420 KB |
1182 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1183 | { | |
5a92e700 | 1184 | struct nvme_queue *nvmeq = raw_nvmeq(dev, qid); |
4d115420 KB |
1185 | |
1186 | if (!nvmeq) | |
1187 | return; | |
1188 | if (nvme_suspend_queue(nvmeq)) | |
1189 | return; | |
1190 | ||
0e53d180 KB |
1191 | /* Don't tell the adapter to delete the admin queue. |
1192 | * Don't tell a removed adapter to delete IO queues. */ | |
1193 | if (qid && readl(&dev->bar->csts) != -1) { | |
b60503ba MW |
1194 | adapter_delete_sq(dev, qid); |
1195 | adapter_delete_cq(dev, qid); | |
1196 | } | |
4d115420 | 1197 | nvme_clear_queue(nvmeq); |
b60503ba MW |
1198 | } |
1199 | ||
1200 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
1201 | int depth, int vector) | |
1202 | { | |
1203 | struct device *dmadev = &dev->pci_dev->dev; | |
22404274 | 1204 | unsigned extra = nvme_queue_extra(depth); |
b60503ba MW |
1205 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
1206 | if (!nvmeq) | |
1207 | return NULL; | |
1208 | ||
1209 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
1210 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
1211 | if (!nvmeq->cqes) | |
1212 | goto free_nvmeq; | |
1213 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
1214 | ||
1215 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
1216 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1217 | if (!nvmeq->sq_cmds) | |
1218 | goto free_cqdma; | |
1219 | ||
42f61420 KB |
1220 | if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL)) |
1221 | goto free_sqdma; | |
1222 | ||
b60503ba | 1223 | nvmeq->q_dmadev = dmadev; |
091b6092 | 1224 | nvmeq->dev = dev; |
3193f07b MW |
1225 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1226 | dev->instance, qid); | |
b60503ba MW |
1227 | spin_lock_init(&nvmeq->q_lock); |
1228 | nvmeq->cq_head = 0; | |
82123460 | 1229 | nvmeq->cq_phase = 1; |
b60503ba | 1230 | init_waitqueue_head(&nvmeq->sq_full); |
1fa6aead | 1231 | init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread); |
b60503ba | 1232 | bio_list_init(&nvmeq->sq_cong); |
b80d5ccc | 1233 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba MW |
1234 | nvmeq->q_depth = depth; |
1235 | nvmeq->cq_vector = vector; | |
c30341dc | 1236 | nvmeq->qid = qid; |
22404274 KB |
1237 | nvmeq->q_suspended = 1; |
1238 | dev->queue_count++; | |
5a92e700 | 1239 | rcu_assign_pointer(dev->queues[qid], nvmeq); |
b60503ba MW |
1240 | |
1241 | return nvmeq; | |
1242 | ||
42f61420 KB |
1243 | free_sqdma: |
1244 | dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds, | |
1245 | nvmeq->sq_dma_addr); | |
b60503ba | 1246 | free_cqdma: |
68b8eca5 | 1247 | dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1248 | nvmeq->cq_dma_addr); |
1249 | free_nvmeq: | |
1250 | kfree(nvmeq); | |
1251 | return NULL; | |
1252 | } | |
1253 | ||
3001082c MW |
1254 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1255 | const char *name) | |
1256 | { | |
58ffacb5 MW |
1257 | if (use_threaded_interrupts) |
1258 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1259 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1260 | name, nvmeq); |
3001082c | 1261 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1262 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1263 | } |
1264 | ||
22404274 | 1265 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1266 | { |
22404274 KB |
1267 | struct nvme_dev *dev = nvmeq->dev; |
1268 | unsigned extra = nvme_queue_extra(nvmeq->q_depth); | |
b60503ba | 1269 | |
22404274 KB |
1270 | nvmeq->sq_tail = 0; |
1271 | nvmeq->cq_head = 0; | |
1272 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1273 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 KB |
1274 | memset(nvmeq->cmdid_data, 0, extra); |
1275 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); | |
1276 | nvme_cancel_ios(nvmeq, false); | |
1277 | nvmeq->q_suspended = 0; | |
42f61420 | 1278 | dev->online_queues++; |
22404274 KB |
1279 | } |
1280 | ||
1281 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1282 | { | |
1283 | struct nvme_dev *dev = nvmeq->dev; | |
1284 | int result; | |
3f85d50b | 1285 | |
b60503ba MW |
1286 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1287 | if (result < 0) | |
22404274 | 1288 | return result; |
b60503ba MW |
1289 | |
1290 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1291 | if (result < 0) | |
1292 | goto release_cq; | |
1293 | ||
3193f07b | 1294 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1295 | if (result < 0) |
1296 | goto release_sq; | |
1297 | ||
0a8d44cb | 1298 | spin_lock_irq(&nvmeq->q_lock); |
22404274 | 1299 | nvme_init_queue(nvmeq, qid); |
0a8d44cb | 1300 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1301 | |
1302 | return result; | |
b60503ba MW |
1303 | |
1304 | release_sq: | |
1305 | adapter_delete_sq(dev, qid); | |
1306 | release_cq: | |
1307 | adapter_delete_cq(dev, qid); | |
22404274 | 1308 | return result; |
b60503ba MW |
1309 | } |
1310 | ||
ba47e386 MW |
1311 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1312 | { | |
1313 | unsigned long timeout; | |
1314 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1315 | ||
1316 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1317 | ||
1318 | while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) { | |
1319 | msleep(100); | |
1320 | if (fatal_signal_pending(current)) | |
1321 | return -EINTR; | |
1322 | if (time_after(jiffies, timeout)) { | |
1323 | dev_err(&dev->pci_dev->dev, | |
1324 | "Device not ready; aborting initialisation\n"); | |
1325 | return -ENODEV; | |
1326 | } | |
1327 | } | |
1328 | ||
1329 | return 0; | |
1330 | } | |
1331 | ||
1332 | /* | |
1333 | * If the device has been passed off to us in an enabled state, just clear | |
1334 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1335 | * bits', but doing so may cause the device to complete commands to the | |
1336 | * admin queue ... and we don't know what memory that might be pointing at! | |
1337 | */ | |
1338 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1339 | { | |
44af146a MW |
1340 | u32 cc = readl(&dev->bar->cc); |
1341 | ||
1342 | if (cc & NVME_CC_ENABLE) | |
1343 | writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc); | |
ba47e386 MW |
1344 | return nvme_wait_ready(dev, cap, false); |
1345 | } | |
1346 | ||
1347 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1348 | { | |
1349 | return nvme_wait_ready(dev, cap, true); | |
1350 | } | |
1351 | ||
1894d8f1 KB |
1352 | static int nvme_shutdown_ctrl(struct nvme_dev *dev) |
1353 | { | |
1354 | unsigned long timeout; | |
1355 | u32 cc; | |
1356 | ||
1357 | cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL; | |
1358 | writel(cc, &dev->bar->cc); | |
1359 | ||
1360 | timeout = 2 * HZ + jiffies; | |
1361 | while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) != | |
1362 | NVME_CSTS_SHST_CMPLT) { | |
1363 | msleep(100); | |
1364 | if (fatal_signal_pending(current)) | |
1365 | return -EINTR; | |
1366 | if (time_after(jiffies, timeout)) { | |
1367 | dev_err(&dev->pci_dev->dev, | |
1368 | "Device shutdown incomplete; abort shutdown\n"); | |
1369 | return -ENODEV; | |
1370 | } | |
1371 | } | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
8d85fce7 | 1376 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1377 | { |
ba47e386 | 1378 | int result; |
b60503ba | 1379 | u32 aqa; |
ba47e386 | 1380 | u64 cap = readq(&dev->bar->cap); |
b60503ba MW |
1381 | struct nvme_queue *nvmeq; |
1382 | ||
ba47e386 MW |
1383 | result = nvme_disable_ctrl(dev, cap); |
1384 | if (result < 0) | |
1385 | return result; | |
b60503ba | 1386 | |
5a92e700 | 1387 | nvmeq = raw_nvmeq(dev, 0); |
cd638946 KB |
1388 | if (!nvmeq) { |
1389 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
1390 | if (!nvmeq) | |
1391 | return -ENOMEM; | |
cd638946 | 1392 | } |
b60503ba MW |
1393 | |
1394 | aqa = nvmeq->q_depth - 1; | |
1395 | aqa |= aqa << 16; | |
1396 | ||
1397 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
1398 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
1399 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
7f53f9d2 | 1400 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba MW |
1401 | |
1402 | writel(aqa, &dev->bar->aqa); | |
1403 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1404 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
1405 | writel(dev->ctrl_config, &dev->bar->cc); | |
1406 | ||
ba47e386 | 1407 | result = nvme_enable_ctrl(dev, cap); |
025c557a | 1408 | if (result) |
cd638946 | 1409 | return result; |
9e866774 | 1410 | |
3193f07b | 1411 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
025c557a | 1412 | if (result) |
cd638946 | 1413 | return result; |
025c557a | 1414 | |
0a8d44cb | 1415 | spin_lock_irq(&nvmeq->q_lock); |
22404274 | 1416 | nvme_init_queue(nvmeq, 0); |
0a8d44cb | 1417 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1418 | return result; |
1419 | } | |
1420 | ||
5d0f6131 | 1421 | struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
eca18b23 | 1422 | unsigned long addr, unsigned length) |
b60503ba | 1423 | { |
36c14ed9 | 1424 | int i, err, count, nents, offset; |
7fc3cdab MW |
1425 | struct scatterlist *sg; |
1426 | struct page **pages; | |
eca18b23 | 1427 | struct nvme_iod *iod; |
36c14ed9 MW |
1428 | |
1429 | if (addr & 3) | |
eca18b23 | 1430 | return ERR_PTR(-EINVAL); |
5460fc03 | 1431 | if (!length || length > INT_MAX - PAGE_SIZE) |
eca18b23 | 1432 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1433 | |
36c14ed9 | 1434 | offset = offset_in_page(addr); |
7fc3cdab MW |
1435 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1436 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
22fff826 DC |
1437 | if (!pages) |
1438 | return ERR_PTR(-ENOMEM); | |
36c14ed9 MW |
1439 | |
1440 | err = get_user_pages_fast(addr, count, 1, pages); | |
1441 | if (err < count) { | |
1442 | count = err; | |
1443 | err = -EFAULT; | |
1444 | goto put_pages; | |
1445 | } | |
7fc3cdab | 1446 | |
eca18b23 MW |
1447 | iod = nvme_alloc_iod(count, length, GFP_KERNEL); |
1448 | sg = iod->sg; | |
36c14ed9 | 1449 | sg_init_table(sg, count); |
d0ba1e49 MW |
1450 | for (i = 0; i < count; i++) { |
1451 | sg_set_page(&sg[i], pages[i], | |
5460fc03 DC |
1452 | min_t(unsigned, length, PAGE_SIZE - offset), |
1453 | offset); | |
d0ba1e49 MW |
1454 | length -= (PAGE_SIZE - offset); |
1455 | offset = 0; | |
7fc3cdab | 1456 | } |
fe304c43 | 1457 | sg_mark_end(&sg[i - 1]); |
1c2ad9fa | 1458 | iod->nents = count; |
7fc3cdab MW |
1459 | |
1460 | err = -ENOMEM; | |
1461 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
1462 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 | 1463 | if (!nents) |
eca18b23 | 1464 | goto free_iod; |
b60503ba | 1465 | |
7fc3cdab | 1466 | kfree(pages); |
eca18b23 | 1467 | return iod; |
b60503ba | 1468 | |
eca18b23 MW |
1469 | free_iod: |
1470 | kfree(iod); | |
7fc3cdab MW |
1471 | put_pages: |
1472 | for (i = 0; i < count; i++) | |
1473 | put_page(pages[i]); | |
1474 | kfree(pages); | |
eca18b23 | 1475 | return ERR_PTR(err); |
7fc3cdab | 1476 | } |
b60503ba | 1477 | |
5d0f6131 | 1478 | void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1c2ad9fa | 1479 | struct nvme_iod *iod) |
7fc3cdab | 1480 | { |
1c2ad9fa | 1481 | int i; |
b60503ba | 1482 | |
1c2ad9fa MW |
1483 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
1484 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
7fc3cdab | 1485 | |
1c2ad9fa MW |
1486 | for (i = 0; i < iod->nents; i++) |
1487 | put_page(sg_page(&iod->sg[i])); | |
7fc3cdab | 1488 | } |
b60503ba | 1489 | |
a53295b6 MW |
1490 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1491 | { | |
1492 | struct nvme_dev *dev = ns->dev; | |
a53295b6 MW |
1493 | struct nvme_user_io io; |
1494 | struct nvme_command c; | |
f410c680 KB |
1495 | unsigned length, meta_len; |
1496 | int status, i; | |
1497 | struct nvme_iod *iod, *meta_iod = NULL; | |
1498 | dma_addr_t meta_dma_addr; | |
1499 | void *meta, *uninitialized_var(meta_mem); | |
a53295b6 MW |
1500 | |
1501 | if (copy_from_user(&io, uio, sizeof(io))) | |
1502 | return -EFAULT; | |
6c7d4945 | 1503 | length = (io.nblocks + 1) << ns->lba_shift; |
f410c680 KB |
1504 | meta_len = (io.nblocks + 1) * ns->ms; |
1505 | ||
1506 | if (meta_len && ((io.metadata & 3) || !io.metadata)) | |
1507 | return -EINVAL; | |
6c7d4945 MW |
1508 | |
1509 | switch (io.opcode) { | |
1510 | case nvme_cmd_write: | |
1511 | case nvme_cmd_read: | |
6bbf1acd | 1512 | case nvme_cmd_compare: |
eca18b23 | 1513 | iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length); |
6413214c | 1514 | break; |
6c7d4945 | 1515 | default: |
6bbf1acd | 1516 | return -EINVAL; |
6c7d4945 MW |
1517 | } |
1518 | ||
eca18b23 MW |
1519 | if (IS_ERR(iod)) |
1520 | return PTR_ERR(iod); | |
a53295b6 MW |
1521 | |
1522 | memset(&c, 0, sizeof(c)); | |
1523 | c.rw.opcode = io.opcode; | |
1524 | c.rw.flags = io.flags; | |
6c7d4945 | 1525 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1526 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1527 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1528 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1529 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1530 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1531 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1532 | c.rw.appmask = cpu_to_le16(io.appmask); | |
f410c680 KB |
1533 | |
1534 | if (meta_len) { | |
1b56749e KB |
1535 | meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata, |
1536 | meta_len); | |
f410c680 KB |
1537 | if (IS_ERR(meta_iod)) { |
1538 | status = PTR_ERR(meta_iod); | |
1539 | meta_iod = NULL; | |
1540 | goto unmap; | |
1541 | } | |
1542 | ||
1543 | meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len, | |
1544 | &meta_dma_addr, GFP_KERNEL); | |
1545 | if (!meta_mem) { | |
1546 | status = -ENOMEM; | |
1547 | goto unmap; | |
1548 | } | |
1549 | ||
1550 | if (io.opcode & 1) { | |
1551 | int meta_offset = 0; | |
1552 | ||
1553 | for (i = 0; i < meta_iod->nents; i++) { | |
1554 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1555 | meta_iod->sg[i].offset; | |
1556 | memcpy(meta_mem + meta_offset, meta, | |
1557 | meta_iod->sg[i].length); | |
1558 | kunmap_atomic(meta); | |
1559 | meta_offset += meta_iod->sg[i].length; | |
1560 | } | |
1561 | } | |
1562 | ||
1563 | c.rw.metadata = cpu_to_le64(meta_dma_addr); | |
1564 | } | |
1565 | ||
eca18b23 | 1566 | length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL); |
a53295b6 | 1567 | |
b77954cb MW |
1568 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1569 | status = -ENOMEM; | |
1570 | else | |
4f5099af | 1571 | status = nvme_submit_io_cmd(dev, &c, NULL); |
a53295b6 | 1572 | |
f410c680 KB |
1573 | if (meta_len) { |
1574 | if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) { | |
1575 | int meta_offset = 0; | |
1576 | ||
1577 | for (i = 0; i < meta_iod->nents; i++) { | |
1578 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1579 | meta_iod->sg[i].offset; | |
1580 | memcpy(meta, meta_mem + meta_offset, | |
1581 | meta_iod->sg[i].length); | |
1582 | kunmap_atomic(meta); | |
1583 | meta_offset += meta_iod->sg[i].length; | |
1584 | } | |
1585 | } | |
1586 | ||
1587 | dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem, | |
1588 | meta_dma_addr); | |
1589 | } | |
1590 | ||
1591 | unmap: | |
1c2ad9fa | 1592 | nvme_unmap_user_pages(dev, io.opcode & 1, iod); |
eca18b23 | 1593 | nvme_free_iod(dev, iod); |
f410c680 KB |
1594 | |
1595 | if (meta_iod) { | |
1596 | nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod); | |
1597 | nvme_free_iod(dev, meta_iod); | |
1598 | } | |
1599 | ||
a53295b6 MW |
1600 | return status; |
1601 | } | |
1602 | ||
50af8bae | 1603 | static int nvme_user_admin_cmd(struct nvme_dev *dev, |
6bbf1acd | 1604 | struct nvme_admin_cmd __user *ucmd) |
6ee44cdc | 1605 | { |
6bbf1acd | 1606 | struct nvme_admin_cmd cmd; |
6ee44cdc | 1607 | struct nvme_command c; |
eca18b23 | 1608 | int status, length; |
c7d36ab8 | 1609 | struct nvme_iod *uninitialized_var(iod); |
94f370ca | 1610 | unsigned timeout; |
6ee44cdc | 1611 | |
6bbf1acd MW |
1612 | if (!capable(CAP_SYS_ADMIN)) |
1613 | return -EACCES; | |
1614 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1615 | return -EFAULT; |
6ee44cdc MW |
1616 | |
1617 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1618 | c.common.opcode = cmd.opcode; |
1619 | c.common.flags = cmd.flags; | |
1620 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1621 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1622 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1623 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1624 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1625 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1626 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1627 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1628 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1629 | ||
1630 | length = cmd.data_len; | |
1631 | if (cmd.data_len) { | |
49742188 MW |
1632 | iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr, |
1633 | length); | |
eca18b23 MW |
1634 | if (IS_ERR(iod)) |
1635 | return PTR_ERR(iod); | |
1636 | length = nvme_setup_prps(dev, &c.common, iod, length, | |
1637 | GFP_KERNEL); | |
6bbf1acd MW |
1638 | } |
1639 | ||
94f370ca KB |
1640 | timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) : |
1641 | ADMIN_TIMEOUT; | |
6bbf1acd | 1642 | if (length != cmd.data_len) |
b77954cb MW |
1643 | status = -ENOMEM; |
1644 | else | |
4f5099af | 1645 | status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout); |
eca18b23 | 1646 | |
6bbf1acd | 1647 | if (cmd.data_len) { |
1c2ad9fa | 1648 | nvme_unmap_user_pages(dev, cmd.opcode & 1, iod); |
eca18b23 | 1649 | nvme_free_iod(dev, iod); |
6bbf1acd | 1650 | } |
f4f117f6 | 1651 | |
cf90bc48 | 1652 | if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result, |
f4f117f6 KB |
1653 | sizeof(cmd.result))) |
1654 | status = -EFAULT; | |
1655 | ||
6ee44cdc MW |
1656 | return status; |
1657 | } | |
1658 | ||
b60503ba MW |
1659 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1660 | unsigned long arg) | |
1661 | { | |
1662 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1663 | ||
1664 | switch (cmd) { | |
6bbf1acd | 1665 | case NVME_IOCTL_ID: |
c3bfe717 | 1666 | force_successful_syscall_return(); |
6bbf1acd MW |
1667 | return ns->ns_id; |
1668 | case NVME_IOCTL_ADMIN_CMD: | |
50af8bae | 1669 | return nvme_user_admin_cmd(ns->dev, (void __user *)arg); |
a53295b6 MW |
1670 | case NVME_IOCTL_SUBMIT_IO: |
1671 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1672 | case SG_GET_VERSION_NUM: |
1673 | return nvme_sg_get_version_num((void __user *)arg); | |
1674 | case SG_IO: | |
1675 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1676 | default: |
1677 | return -ENOTTY; | |
1678 | } | |
1679 | } | |
1680 | ||
320a3827 KB |
1681 | #ifdef CONFIG_COMPAT |
1682 | static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode, | |
1683 | unsigned int cmd, unsigned long arg) | |
1684 | { | |
1685 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1686 | ||
1687 | switch (cmd) { | |
1688 | case SG_IO: | |
1689 | return nvme_sg_io32(ns, arg); | |
1690 | } | |
1691 | return nvme_ioctl(bdev, mode, cmd, arg); | |
1692 | } | |
1693 | #else | |
1694 | #define nvme_compat_ioctl NULL | |
1695 | #endif | |
1696 | ||
9ac27090 KB |
1697 | static int nvme_open(struct block_device *bdev, fmode_t mode) |
1698 | { | |
1699 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1700 | struct nvme_dev *dev = ns->dev; | |
1701 | ||
1702 | kref_get(&dev->kref); | |
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | static void nvme_free_dev(struct kref *kref); | |
1707 | ||
1708 | static void nvme_release(struct gendisk *disk, fmode_t mode) | |
1709 | { | |
1710 | struct nvme_ns *ns = disk->private_data; | |
1711 | struct nvme_dev *dev = ns->dev; | |
1712 | ||
1713 | kref_put(&dev->kref, nvme_free_dev); | |
1714 | } | |
1715 | ||
b60503ba MW |
1716 | static const struct block_device_operations nvme_fops = { |
1717 | .owner = THIS_MODULE, | |
1718 | .ioctl = nvme_ioctl, | |
320a3827 | 1719 | .compat_ioctl = nvme_compat_ioctl, |
9ac27090 KB |
1720 | .open = nvme_open, |
1721 | .release = nvme_release, | |
b60503ba MW |
1722 | }; |
1723 | ||
1fa6aead MW |
1724 | static void nvme_resubmit_bios(struct nvme_queue *nvmeq) |
1725 | { | |
1726 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1727 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1728 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
427e9708 KB |
1729 | |
1730 | if (bio_list_empty(&nvmeq->sq_cong)) | |
1731 | remove_wait_queue(&nvmeq->sq_full, | |
1732 | &nvmeq->sq_cong_wait); | |
1fa6aead | 1733 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { |
427e9708 KB |
1734 | if (bio_list_empty(&nvmeq->sq_cong)) |
1735 | add_wait_queue(&nvmeq->sq_full, | |
1736 | &nvmeq->sq_cong_wait); | |
1fa6aead MW |
1737 | bio_list_add_head(&nvmeq->sq_cong, bio); |
1738 | break; | |
1739 | } | |
1740 | } | |
1741 | } | |
1742 | ||
1743 | static int nvme_kthread(void *data) | |
1744 | { | |
d4b4ff8e | 1745 | struct nvme_dev *dev, *next; |
1fa6aead MW |
1746 | |
1747 | while (!kthread_should_stop()) { | |
564a232c | 1748 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 1749 | spin_lock(&dev_list_lock); |
d4b4ff8e | 1750 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 1751 | int i; |
d4b4ff8e KB |
1752 | if (readl(&dev->bar->csts) & NVME_CSTS_CFS && |
1753 | dev->initialized) { | |
1754 | if (work_busy(&dev->reset_work)) | |
1755 | continue; | |
1756 | list_del_init(&dev->node); | |
1757 | dev_warn(&dev->pci_dev->dev, | |
1758 | "Failed status, reset controller\n"); | |
bdfd70fd | 1759 | PREPARE_WORK(&dev->reset_work, |
d4b4ff8e KB |
1760 | nvme_reset_failed_dev); |
1761 | queue_work(nvme_workq, &dev->reset_work); | |
1762 | continue; | |
1763 | } | |
5a92e700 | 1764 | rcu_read_lock(); |
1fa6aead | 1765 | for (i = 0; i < dev->queue_count; i++) { |
5a92e700 KB |
1766 | struct nvme_queue *nvmeq = |
1767 | rcu_dereference(dev->queues[i]); | |
740216fc MW |
1768 | if (!nvmeq) |
1769 | continue; | |
1fa6aead | 1770 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1771 | if (nvmeq->q_suspended) |
1772 | goto unlock; | |
bc57a0f7 | 1773 | nvme_process_cq(nvmeq); |
a09115b2 | 1774 | nvme_cancel_ios(nvmeq, true); |
1fa6aead | 1775 | nvme_resubmit_bios(nvmeq); |
22404274 | 1776 | unlock: |
1fa6aead MW |
1777 | spin_unlock_irq(&nvmeq->q_lock); |
1778 | } | |
5a92e700 | 1779 | rcu_read_unlock(); |
1fa6aead MW |
1780 | } |
1781 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 1782 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
1783 | } |
1784 | return 0; | |
1785 | } | |
1786 | ||
0e5e4f0e KB |
1787 | static void nvme_config_discard(struct nvme_ns *ns) |
1788 | { | |
1789 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1790 | ns->queue->limits.discard_zeroes_data = 0; | |
1791 | ns->queue->limits.discard_alignment = logical_block_size; | |
1792 | ns->queue->limits.discard_granularity = logical_block_size; | |
1793 | ns->queue->limits.max_discard_sectors = 0xffffffff; | |
1794 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); | |
1795 | } | |
1796 | ||
c3bfe717 | 1797 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid, |
b60503ba MW |
1798 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) |
1799 | { | |
1800 | struct nvme_ns *ns; | |
1801 | struct gendisk *disk; | |
1802 | int lbaf; | |
1803 | ||
1804 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1805 | return NULL; | |
1806 | ||
1807 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1808 | if (!ns) | |
1809 | return NULL; | |
1810 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1811 | if (!ns->queue) | |
1812 | goto out_free_ns; | |
4eeb9215 MW |
1813 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT; |
1814 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); | |
1815 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
b60503ba MW |
1816 | blk_queue_make_request(ns->queue, nvme_make_request); |
1817 | ns->dev = dev; | |
1818 | ns->queue->queuedata = ns; | |
1819 | ||
469071a3 | 1820 | disk = alloc_disk(0); |
b60503ba MW |
1821 | if (!disk) |
1822 | goto out_free_queue; | |
5aff9382 | 1823 | ns->ns_id = nsid; |
b60503ba MW |
1824 | ns->disk = disk; |
1825 | lbaf = id->flbas & 0xf; | |
1826 | ns->lba_shift = id->lbaf[lbaf].ds; | |
f410c680 | 1827 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
e9ef4636 | 1828 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
1829 | if (dev->max_hw_sectors) |
1830 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
b60503ba MW |
1831 | |
1832 | disk->major = nvme_major; | |
469071a3 | 1833 | disk->first_minor = 0; |
b60503ba MW |
1834 | disk->fops = &nvme_fops; |
1835 | disk->private_data = ns; | |
1836 | disk->queue = ns->queue; | |
388f037f | 1837 | disk->driverfs_dev = &dev->pci_dev->dev; |
469071a3 | 1838 | disk->flags = GENHD_FL_EXT_DEVT; |
5aff9382 | 1839 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba MW |
1840 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); |
1841 | ||
0e5e4f0e KB |
1842 | if (dev->oncs & NVME_CTRL_ONCS_DSM) |
1843 | nvme_config_discard(ns); | |
1844 | ||
b60503ba MW |
1845 | return ns; |
1846 | ||
1847 | out_free_queue: | |
1848 | blk_cleanup_queue(ns->queue); | |
1849 | out_free_ns: | |
1850 | kfree(ns); | |
1851 | return NULL; | |
1852 | } | |
1853 | ||
42f61420 KB |
1854 | static int nvme_find_closest_node(int node) |
1855 | { | |
1856 | int n, val, min_val = INT_MAX, best_node = node; | |
1857 | ||
1858 | for_each_online_node(n) { | |
1859 | if (n == node) | |
1860 | continue; | |
1861 | val = node_distance(node, n); | |
1862 | if (val < min_val) { | |
1863 | min_val = val; | |
1864 | best_node = n; | |
1865 | } | |
1866 | } | |
1867 | return best_node; | |
1868 | } | |
1869 | ||
1870 | static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq, | |
1871 | int count) | |
1872 | { | |
1873 | int cpu; | |
1874 | for_each_cpu(cpu, qmask) { | |
1875 | if (cpumask_weight(nvmeq->cpu_mask) >= count) | |
1876 | break; | |
1877 | if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask)) | |
1878 | *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid; | |
1879 | } | |
1880 | } | |
1881 | ||
1882 | static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus, | |
1883 | const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue) | |
1884 | { | |
1885 | int next_cpu; | |
1886 | for_each_cpu(next_cpu, new_mask) { | |
1887 | cpumask_or(mask, mask, get_cpu_mask(next_cpu)); | |
1888 | cpumask_or(mask, mask, topology_thread_cpumask(next_cpu)); | |
1889 | cpumask_and(mask, mask, unassigned_cpus); | |
1890 | nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue); | |
1891 | } | |
1892 | } | |
1893 | ||
1894 | static void nvme_create_io_queues(struct nvme_dev *dev) | |
1895 | { | |
1896 | unsigned i, max; | |
1897 | ||
1898 | max = min(dev->max_qid, num_online_cpus()); | |
1899 | for (i = dev->queue_count; i <= max; i++) | |
1900 | if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1)) | |
1901 | break; | |
1902 | ||
1903 | max = min(dev->queue_count - 1, num_online_cpus()); | |
1904 | for (i = dev->online_queues; i <= max; i++) | |
1905 | if (nvme_create_queue(raw_nvmeq(dev, i), i)) | |
1906 | break; | |
1907 | } | |
1908 | ||
1909 | /* | |
1910 | * If there are fewer queues than online cpus, this will try to optimally | |
1911 | * assign a queue to multiple cpus by grouping cpus that are "close" together: | |
1912 | * thread siblings, core, socket, closest node, then whatever else is | |
1913 | * available. | |
1914 | */ | |
1915 | static void nvme_assign_io_queues(struct nvme_dev *dev) | |
1916 | { | |
1917 | unsigned cpu, cpus_per_queue, queues, remainder, i; | |
1918 | cpumask_var_t unassigned_cpus; | |
1919 | ||
1920 | nvme_create_io_queues(dev); | |
1921 | ||
1922 | queues = min(dev->online_queues - 1, num_online_cpus()); | |
1923 | if (!queues) | |
1924 | return; | |
1925 | ||
1926 | cpus_per_queue = num_online_cpus() / queues; | |
1927 | remainder = queues - (num_online_cpus() - queues * cpus_per_queue); | |
1928 | ||
1929 | if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL)) | |
1930 | return; | |
1931 | ||
1932 | cpumask_copy(unassigned_cpus, cpu_online_mask); | |
1933 | cpu = cpumask_first(unassigned_cpus); | |
1934 | for (i = 1; i <= queues; i++) { | |
1935 | struct nvme_queue *nvmeq = lock_nvmeq(dev, i); | |
1936 | cpumask_t mask; | |
1937 | ||
1938 | cpumask_clear(nvmeq->cpu_mask); | |
1939 | if (!cpumask_weight(unassigned_cpus)) { | |
1940 | unlock_nvmeq(nvmeq); | |
1941 | break; | |
1942 | } | |
1943 | ||
1944 | mask = *get_cpu_mask(cpu); | |
1945 | nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue); | |
1946 | if (cpus_weight(mask) < cpus_per_queue) | |
1947 | nvme_add_cpus(&mask, unassigned_cpus, | |
1948 | topology_thread_cpumask(cpu), | |
1949 | nvmeq, cpus_per_queue); | |
1950 | if (cpus_weight(mask) < cpus_per_queue) | |
1951 | nvme_add_cpus(&mask, unassigned_cpus, | |
1952 | topology_core_cpumask(cpu), | |
1953 | nvmeq, cpus_per_queue); | |
1954 | if (cpus_weight(mask) < cpus_per_queue) | |
1955 | nvme_add_cpus(&mask, unassigned_cpus, | |
1956 | cpumask_of_node(cpu_to_node(cpu)), | |
1957 | nvmeq, cpus_per_queue); | |
1958 | if (cpus_weight(mask) < cpus_per_queue) | |
1959 | nvme_add_cpus(&mask, unassigned_cpus, | |
1960 | cpumask_of_node( | |
1961 | nvme_find_closest_node( | |
1962 | cpu_to_node(cpu))), | |
1963 | nvmeq, cpus_per_queue); | |
1964 | if (cpus_weight(mask) < cpus_per_queue) | |
1965 | nvme_add_cpus(&mask, unassigned_cpus, | |
1966 | unassigned_cpus, | |
1967 | nvmeq, cpus_per_queue); | |
1968 | ||
1969 | WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue, | |
1970 | "nvme%d qid:%d mis-matched queue-to-cpu assignment\n", | |
1971 | dev->instance, i); | |
1972 | ||
1973 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
1974 | nvmeq->cpu_mask); | |
1975 | cpumask_andnot(unassigned_cpus, unassigned_cpus, | |
1976 | nvmeq->cpu_mask); | |
1977 | cpu = cpumask_next(cpu, unassigned_cpus); | |
1978 | if (remainder && !--remainder) | |
1979 | cpus_per_queue++; | |
1980 | unlock_nvmeq(nvmeq); | |
1981 | } | |
1982 | WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n", | |
1983 | dev->instance); | |
1984 | i = 0; | |
1985 | cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask); | |
1986 | for_each_cpu(cpu, unassigned_cpus) | |
1987 | *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1; | |
1988 | free_cpumask_var(unassigned_cpus); | |
1989 | } | |
1990 | ||
b3b06812 | 1991 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1992 | { |
1993 | int status; | |
1994 | u32 result; | |
b3b06812 | 1995 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 1996 | |
df348139 | 1997 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 1998 | &result); |
b60503ba | 1999 | if (status) |
7e03b124 | 2000 | return status < 0 ? -EIO : -EBUSY; |
b60503ba MW |
2001 | return min(result & 0xffff, result >> 16) + 1; |
2002 | } | |
2003 | ||
9d713c2b KB |
2004 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
2005 | { | |
b80d5ccc | 2006 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
2007 | } |
2008 | ||
33b1e95c KB |
2009 | static int nvme_cpu_notify(struct notifier_block *self, |
2010 | unsigned long action, void *hcpu) | |
2011 | { | |
2012 | struct nvme_dev *dev = container_of(self, struct nvme_dev, nb); | |
2013 | switch (action) { | |
2014 | case CPU_ONLINE: | |
2015 | case CPU_DEAD: | |
2016 | nvme_assign_io_queues(dev); | |
2017 | break; | |
2018 | } | |
2019 | return NOTIFY_OK; | |
2020 | } | |
2021 | ||
8d85fce7 | 2022 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2023 | { |
5a92e700 | 2024 | struct nvme_queue *adminq = raw_nvmeq(dev, 0); |
fa08a396 | 2025 | struct pci_dev *pdev = dev->pci_dev; |
42f61420 | 2026 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 2027 | |
42f61420 | 2028 | nr_io_queues = num_possible_cpus(); |
b348b7d5 | 2029 | result = set_queue_count(dev, nr_io_queues); |
1b23484b MW |
2030 | if (result < 0) |
2031 | return result; | |
b348b7d5 MW |
2032 | if (result < nr_io_queues) |
2033 | nr_io_queues = result; | |
b60503ba | 2034 | |
9d713c2b KB |
2035 | size = db_bar_size(dev, nr_io_queues); |
2036 | if (size > 8192) { | |
f1938f6e | 2037 | iounmap(dev->bar); |
9d713c2b KB |
2038 | do { |
2039 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
2040 | if (dev->bar) | |
2041 | break; | |
2042 | if (!--nr_io_queues) | |
2043 | return -ENOMEM; | |
2044 | size = db_bar_size(dev, nr_io_queues); | |
2045 | } while (1); | |
f1938f6e | 2046 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
5a92e700 | 2047 | adminq->q_db = dev->dbs; |
f1938f6e MW |
2048 | } |
2049 | ||
9d713c2b | 2050 | /* Deregister the admin queue's interrupt */ |
3193f07b | 2051 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 2052 | |
063a8096 MW |
2053 | vecs = nr_io_queues; |
2054 | for (i = 0; i < vecs; i++) | |
1b23484b MW |
2055 | dev->entry[i].entry = i; |
2056 | for (;;) { | |
063a8096 MW |
2057 | result = pci_enable_msix(pdev, dev->entry, vecs); |
2058 | if (result <= 0) | |
1b23484b | 2059 | break; |
063a8096 | 2060 | vecs = result; |
1b23484b MW |
2061 | } |
2062 | ||
063a8096 MW |
2063 | if (result < 0) { |
2064 | vecs = nr_io_queues; | |
2065 | if (vecs > 32) | |
2066 | vecs = 32; | |
fa08a396 | 2067 | for (;;) { |
063a8096 | 2068 | result = pci_enable_msi_block(pdev, vecs); |
fa08a396 | 2069 | if (result == 0) { |
063a8096 | 2070 | for (i = 0; i < vecs; i++) |
fa08a396 RRG |
2071 | dev->entry[i].vector = i + pdev->irq; |
2072 | break; | |
063a8096 MW |
2073 | } else if (result < 0) { |
2074 | vecs = 1; | |
fa08a396 RRG |
2075 | break; |
2076 | } | |
063a8096 | 2077 | vecs = result; |
fa08a396 RRG |
2078 | } |
2079 | } | |
2080 | ||
063a8096 MW |
2081 | /* |
2082 | * Should investigate if there's a performance win from allocating | |
2083 | * more queues than interrupt vectors; it might allow the submission | |
2084 | * path to scale better, even if the receive path is limited by the | |
2085 | * number of interrupts. | |
2086 | */ | |
2087 | nr_io_queues = vecs; | |
42f61420 | 2088 | dev->max_qid = nr_io_queues; |
063a8096 | 2089 | |
3193f07b | 2090 | result = queue_request_irq(dev, adminq, adminq->irqname); |
9d713c2b | 2091 | if (result) { |
3193f07b | 2092 | adminq->q_suspended = 1; |
22404274 | 2093 | goto free_queues; |
9d713c2b | 2094 | } |
1b23484b | 2095 | |
cd638946 | 2096 | /* Free previously allocated queues that are no longer usable */ |
42f61420 KB |
2097 | nvme_free_queues(dev, nr_io_queues + 1); |
2098 | nvme_assign_io_queues(dev); | |
b60503ba | 2099 | |
33b1e95c KB |
2100 | dev->nb.notifier_call = &nvme_cpu_notify; |
2101 | result = register_hotcpu_notifier(&dev->nb); | |
2102 | if (result) | |
2103 | goto free_queues; | |
2104 | ||
22404274 | 2105 | return 0; |
b60503ba | 2106 | |
22404274 | 2107 | free_queues: |
a1a5ef99 | 2108 | nvme_free_queues(dev, 1); |
22404274 | 2109 | return result; |
b60503ba MW |
2110 | } |
2111 | ||
422ef0c7 MW |
2112 | /* |
2113 | * Return: error value if an error occurred setting up the queues or calling | |
2114 | * Identify Device. 0 if these succeeded, even if adding some of the | |
2115 | * namespaces failed. At the moment, these failures are silent. TBD which | |
2116 | * failures should be reported. | |
2117 | */ | |
8d85fce7 | 2118 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2119 | { |
68608c26 | 2120 | struct pci_dev *pdev = dev->pci_dev; |
c3bfe717 MW |
2121 | int res; |
2122 | unsigned nn, i; | |
cbb6218f | 2123 | struct nvme_ns *ns; |
51814232 | 2124 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 MW |
2125 | struct nvme_id_ns *id_ns; |
2126 | void *mem; | |
b60503ba | 2127 | dma_addr_t dma_addr; |
159b67d7 | 2128 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; |
b60503ba | 2129 | |
68608c26 | 2130 | mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL); |
a9ef4343 KB |
2131 | if (!mem) |
2132 | return -ENOMEM; | |
b60503ba | 2133 | |
bc5fc7e4 | 2134 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba MW |
2135 | if (res) { |
2136 | res = -EIO; | |
cbb6218f | 2137 | goto out; |
b60503ba MW |
2138 | } |
2139 | ||
bc5fc7e4 | 2140 | ctrl = mem; |
51814232 | 2141 | nn = le32_to_cpup(&ctrl->nn); |
0e5e4f0e | 2142 | dev->oncs = le16_to_cpup(&ctrl->oncs); |
c30341dc | 2143 | dev->abort_limit = ctrl->acl + 1; |
51814232 MW |
2144 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
2145 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
2146 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 2147 | if (ctrl->mdts) |
8fc23e03 | 2148 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
68608c26 MW |
2149 | if ((pdev->vendor == PCI_VENDOR_ID_INTEL) && |
2150 | (pdev->device == 0x0953) && ctrl->vs[3]) | |
159b67d7 | 2151 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); |
b60503ba | 2152 | |
bc5fc7e4 | 2153 | id_ns = mem; |
2b2c1896 | 2154 | for (i = 1; i <= nn; i++) { |
bc5fc7e4 | 2155 | res = nvme_identify(dev, i, 0, dma_addr); |
b60503ba MW |
2156 | if (res) |
2157 | continue; | |
2158 | ||
bc5fc7e4 | 2159 | if (id_ns->ncap == 0) |
b60503ba MW |
2160 | continue; |
2161 | ||
bc5fc7e4 | 2162 | res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i, |
08df1e05 | 2163 | dma_addr + 4096, NULL); |
b60503ba | 2164 | if (res) |
12209036 | 2165 | memset(mem + 4096, 0, 4096); |
b60503ba | 2166 | |
bc5fc7e4 | 2167 | ns = nvme_alloc_ns(dev, i, mem, mem + 4096); |
b60503ba MW |
2168 | if (ns) |
2169 | list_add_tail(&ns->list, &dev->namespaces); | |
2170 | } | |
2171 | list_for_each_entry(ns, &dev->namespaces, list) | |
2172 | add_disk(ns->disk); | |
422ef0c7 | 2173 | res = 0; |
b60503ba | 2174 | |
bc5fc7e4 | 2175 | out: |
684f5c20 | 2176 | dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr); |
b60503ba MW |
2177 | return res; |
2178 | } | |
2179 | ||
0877cb0d KB |
2180 | static int nvme_dev_map(struct nvme_dev *dev) |
2181 | { | |
42f61420 | 2182 | u64 cap; |
0877cb0d KB |
2183 | int bars, result = -ENOMEM; |
2184 | struct pci_dev *pdev = dev->pci_dev; | |
2185 | ||
2186 | if (pci_enable_device_mem(pdev)) | |
2187 | return result; | |
2188 | ||
2189 | dev->entry[0].vector = pdev->irq; | |
2190 | pci_set_master(pdev); | |
2191 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
2192 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
2193 | goto disable_pci; | |
2194 | ||
052d0efa RK |
2195 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) && |
2196 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) | |
2197 | goto disable; | |
0877cb0d | 2198 | |
0877cb0d KB |
2199 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
2200 | if (!dev->bar) | |
2201 | goto disable; | |
0e53d180 KB |
2202 | if (readl(&dev->bar->csts) == -1) { |
2203 | result = -ENODEV; | |
2204 | goto unmap; | |
2205 | } | |
42f61420 KB |
2206 | cap = readq(&dev->bar->cap); |
2207 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); | |
2208 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
0877cb0d KB |
2209 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
2210 | ||
2211 | return 0; | |
2212 | ||
0e53d180 KB |
2213 | unmap: |
2214 | iounmap(dev->bar); | |
2215 | dev->bar = NULL; | |
0877cb0d KB |
2216 | disable: |
2217 | pci_release_regions(pdev); | |
2218 | disable_pci: | |
2219 | pci_disable_device(pdev); | |
2220 | return result; | |
2221 | } | |
2222 | ||
2223 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
2224 | { | |
2225 | if (dev->pci_dev->msi_enabled) | |
2226 | pci_disable_msi(dev->pci_dev); | |
2227 | else if (dev->pci_dev->msix_enabled) | |
2228 | pci_disable_msix(dev->pci_dev); | |
2229 | ||
2230 | if (dev->bar) { | |
2231 | iounmap(dev->bar); | |
2232 | dev->bar = NULL; | |
9a6b9458 | 2233 | pci_release_regions(dev->pci_dev); |
0877cb0d KB |
2234 | } |
2235 | ||
0877cb0d KB |
2236 | if (pci_is_enabled(dev->pci_dev)) |
2237 | pci_disable_device(dev->pci_dev); | |
2238 | } | |
2239 | ||
4d115420 KB |
2240 | struct nvme_delq_ctx { |
2241 | struct task_struct *waiter; | |
2242 | struct kthread_worker *worker; | |
2243 | atomic_t refcount; | |
2244 | }; | |
2245 | ||
2246 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
2247 | { | |
2248 | dq->waiter = current; | |
2249 | mb(); | |
2250 | ||
2251 | for (;;) { | |
2252 | set_current_state(TASK_KILLABLE); | |
2253 | if (!atomic_read(&dq->refcount)) | |
2254 | break; | |
2255 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
2256 | fatal_signal_pending(current)) { | |
2257 | set_current_state(TASK_RUNNING); | |
2258 | ||
2259 | nvme_disable_ctrl(dev, readq(&dev->bar->cap)); | |
2260 | nvme_disable_queue(dev, 0); | |
2261 | ||
2262 | send_sig(SIGKILL, dq->worker->task, 1); | |
2263 | flush_kthread_worker(dq->worker); | |
2264 | return; | |
2265 | } | |
2266 | } | |
2267 | set_current_state(TASK_RUNNING); | |
2268 | } | |
2269 | ||
2270 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
2271 | { | |
2272 | atomic_dec(&dq->refcount); | |
2273 | if (dq->waiter) | |
2274 | wake_up_process(dq->waiter); | |
2275 | } | |
2276 | ||
2277 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
2278 | { | |
2279 | atomic_inc(&dq->refcount); | |
2280 | return dq; | |
2281 | } | |
2282 | ||
2283 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
2284 | { | |
2285 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
2286 | ||
2287 | nvme_clear_queue(nvmeq); | |
2288 | nvme_put_dq(dq); | |
2289 | } | |
2290 | ||
2291 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
2292 | kthread_work_func_t fn) | |
2293 | { | |
2294 | struct nvme_command c; | |
2295 | ||
2296 | memset(&c, 0, sizeof(c)); | |
2297 | c.delete_queue.opcode = opcode; | |
2298 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
2299 | ||
2300 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
2301 | return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo); | |
2302 | } | |
2303 | ||
2304 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
2305 | { | |
2306 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2307 | cmdinfo.work); | |
2308 | nvme_del_queue_end(nvmeq); | |
2309 | } | |
2310 | ||
2311 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
2312 | { | |
2313 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
2314 | nvme_del_cq_work_handler); | |
2315 | } | |
2316 | ||
2317 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
2318 | { | |
2319 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2320 | cmdinfo.work); | |
2321 | int status = nvmeq->cmdinfo.status; | |
2322 | ||
2323 | if (!status) | |
2324 | status = nvme_delete_cq(nvmeq); | |
2325 | if (status) | |
2326 | nvme_del_queue_end(nvmeq); | |
2327 | } | |
2328 | ||
2329 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
2330 | { | |
2331 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
2332 | nvme_del_sq_work_handler); | |
2333 | } | |
2334 | ||
2335 | static void nvme_del_queue_start(struct kthread_work *work) | |
2336 | { | |
2337 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2338 | cmdinfo.work); | |
2339 | allow_signal(SIGKILL); | |
2340 | if (nvme_delete_sq(nvmeq)) | |
2341 | nvme_del_queue_end(nvmeq); | |
2342 | } | |
2343 | ||
2344 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
2345 | { | |
2346 | int i; | |
2347 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
2348 | struct nvme_delq_ctx dq; | |
2349 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
2350 | &worker, "nvme%d", dev->instance); | |
2351 | ||
2352 | if (IS_ERR(kworker_task)) { | |
2353 | dev_err(&dev->pci_dev->dev, | |
2354 | "Failed to create queue del task\n"); | |
2355 | for (i = dev->queue_count - 1; i > 0; i--) | |
2356 | nvme_disable_queue(dev, i); | |
2357 | return; | |
2358 | } | |
2359 | ||
2360 | dq.waiter = NULL; | |
2361 | atomic_set(&dq.refcount, 0); | |
2362 | dq.worker = &worker; | |
2363 | for (i = dev->queue_count - 1; i > 0; i--) { | |
5a92e700 | 2364 | struct nvme_queue *nvmeq = raw_nvmeq(dev, i); |
4d115420 KB |
2365 | |
2366 | if (nvme_suspend_queue(nvmeq)) | |
2367 | continue; | |
2368 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
2369 | nvmeq->cmdinfo.worker = dq.worker; | |
2370 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
2371 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
2372 | } | |
2373 | nvme_wait_dq(&dq, dev); | |
2374 | kthread_stop(kworker_task); | |
2375 | } | |
2376 | ||
f0b50732 | 2377 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2378 | { |
22404274 KB |
2379 | int i; |
2380 | ||
d4b4ff8e | 2381 | dev->initialized = 0; |
33b1e95c | 2382 | unregister_hotcpu_notifier(&dev->nb); |
b60503ba | 2383 | |
1fa6aead | 2384 | spin_lock(&dev_list_lock); |
f0b50732 | 2385 | list_del_init(&dev->node); |
1fa6aead MW |
2386 | spin_unlock(&dev_list_lock); |
2387 | ||
4d115420 KB |
2388 | if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) { |
2389 | for (i = dev->queue_count - 1; i >= 0; i--) { | |
5a92e700 | 2390 | struct nvme_queue *nvmeq = raw_nvmeq(dev, i); |
4d115420 KB |
2391 | nvme_suspend_queue(nvmeq); |
2392 | nvme_clear_queue(nvmeq); | |
2393 | } | |
2394 | } else { | |
2395 | nvme_disable_io_queues(dev); | |
1894d8f1 | 2396 | nvme_shutdown_ctrl(dev); |
4d115420 KB |
2397 | nvme_disable_queue(dev, 0); |
2398 | } | |
f0b50732 KB |
2399 | nvme_dev_unmap(dev); |
2400 | } | |
2401 | ||
2402 | static void nvme_dev_remove(struct nvme_dev *dev) | |
2403 | { | |
9ac27090 | 2404 | struct nvme_ns *ns; |
f0b50732 | 2405 | |
9ac27090 KB |
2406 | list_for_each_entry(ns, &dev->namespaces, list) { |
2407 | if (ns->disk->flags & GENHD_FL_UP) | |
2408 | del_gendisk(ns->disk); | |
2409 | if (!blk_queue_dying(ns->queue)) | |
2410 | blk_cleanup_queue(ns->queue); | |
b60503ba | 2411 | } |
b60503ba MW |
2412 | } |
2413 | ||
091b6092 MW |
2414 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2415 | { | |
2416 | struct device *dmadev = &dev->pci_dev->dev; | |
2417 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
2418 | PAGE_SIZE, PAGE_SIZE, 0); | |
2419 | if (!dev->prp_page_pool) | |
2420 | return -ENOMEM; | |
2421 | ||
99802a7a MW |
2422 | /* Optimisation for I/Os between 4k and 128k */ |
2423 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
2424 | 256, 256, 0); | |
2425 | if (!dev->prp_small_pool) { | |
2426 | dma_pool_destroy(dev->prp_page_pool); | |
2427 | return -ENOMEM; | |
2428 | } | |
091b6092 MW |
2429 | return 0; |
2430 | } | |
2431 | ||
2432 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2433 | { | |
2434 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2435 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2436 | } |
2437 | ||
cd58ad7d QSA |
2438 | static DEFINE_IDA(nvme_instance_ida); |
2439 | ||
2440 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2441 | { |
cd58ad7d QSA |
2442 | int instance, error; |
2443 | ||
2444 | do { | |
2445 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2446 | return -ENODEV; | |
2447 | ||
2448 | spin_lock(&dev_list_lock); | |
2449 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2450 | spin_unlock(&dev_list_lock); | |
2451 | } while (error == -EAGAIN); | |
2452 | ||
2453 | if (error) | |
2454 | return -ENODEV; | |
2455 | ||
2456 | dev->instance = instance; | |
2457 | return 0; | |
b60503ba MW |
2458 | } |
2459 | ||
2460 | static void nvme_release_instance(struct nvme_dev *dev) | |
2461 | { | |
cd58ad7d QSA |
2462 | spin_lock(&dev_list_lock); |
2463 | ida_remove(&nvme_instance_ida, dev->instance); | |
2464 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
2465 | } |
2466 | ||
9ac27090 KB |
2467 | static void nvme_free_namespaces(struct nvme_dev *dev) |
2468 | { | |
2469 | struct nvme_ns *ns, *next; | |
2470 | ||
2471 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
2472 | list_del(&ns->list); | |
2473 | put_disk(ns->disk); | |
2474 | kfree(ns); | |
2475 | } | |
2476 | } | |
2477 | ||
5e82e952 KB |
2478 | static void nvme_free_dev(struct kref *kref) |
2479 | { | |
2480 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
9ac27090 KB |
2481 | |
2482 | nvme_free_namespaces(dev); | |
42f61420 | 2483 | free_percpu(dev->io_queue); |
5e82e952 KB |
2484 | kfree(dev->queues); |
2485 | kfree(dev->entry); | |
2486 | kfree(dev); | |
2487 | } | |
2488 | ||
2489 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2490 | { | |
2491 | struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev, | |
2492 | miscdev); | |
2493 | kref_get(&dev->kref); | |
2494 | f->private_data = dev; | |
2495 | return 0; | |
2496 | } | |
2497 | ||
2498 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2499 | { | |
2500 | struct nvme_dev *dev = f->private_data; | |
2501 | kref_put(&dev->kref, nvme_free_dev); | |
2502 | return 0; | |
2503 | } | |
2504 | ||
2505 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2506 | { | |
2507 | struct nvme_dev *dev = f->private_data; | |
2508 | switch (cmd) { | |
2509 | case NVME_IOCTL_ADMIN_CMD: | |
2510 | return nvme_user_admin_cmd(dev, (void __user *)arg); | |
2511 | default: | |
2512 | return -ENOTTY; | |
2513 | } | |
2514 | } | |
2515 | ||
2516 | static const struct file_operations nvme_dev_fops = { | |
2517 | .owner = THIS_MODULE, | |
2518 | .open = nvme_dev_open, | |
2519 | .release = nvme_dev_release, | |
2520 | .unlocked_ioctl = nvme_dev_ioctl, | |
2521 | .compat_ioctl = nvme_dev_ioctl, | |
2522 | }; | |
2523 | ||
f0b50732 KB |
2524 | static int nvme_dev_start(struct nvme_dev *dev) |
2525 | { | |
2526 | int result; | |
2527 | ||
2528 | result = nvme_dev_map(dev); | |
2529 | if (result) | |
2530 | return result; | |
2531 | ||
2532 | result = nvme_configure_admin_queue(dev); | |
2533 | if (result) | |
2534 | goto unmap; | |
2535 | ||
2536 | spin_lock(&dev_list_lock); | |
2537 | list_add(&dev->node, &dev_list); | |
2538 | spin_unlock(&dev_list_lock); | |
2539 | ||
2540 | result = nvme_setup_io_queues(dev); | |
d82e8bfd | 2541 | if (result && result != -EBUSY) |
f0b50732 KB |
2542 | goto disable; |
2543 | ||
d82e8bfd | 2544 | return result; |
f0b50732 KB |
2545 | |
2546 | disable: | |
a1a5ef99 | 2547 | nvme_disable_queue(dev, 0); |
f0b50732 KB |
2548 | spin_lock(&dev_list_lock); |
2549 | list_del_init(&dev->node); | |
2550 | spin_unlock(&dev_list_lock); | |
2551 | unmap: | |
2552 | nvme_dev_unmap(dev); | |
2553 | return result; | |
2554 | } | |
2555 | ||
9a6b9458 KB |
2556 | static int nvme_remove_dead_ctrl(void *arg) |
2557 | { | |
2558 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
2559 | struct pci_dev *pdev = dev->pci_dev; | |
2560 | ||
2561 | if (pci_get_drvdata(pdev)) | |
2562 | pci_stop_and_remove_bus_device(pdev); | |
2563 | kref_put(&dev->kref, nvme_free_dev); | |
2564 | return 0; | |
2565 | } | |
2566 | ||
2567 | static void nvme_remove_disks(struct work_struct *ws) | |
2568 | { | |
9a6b9458 KB |
2569 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
2570 | ||
2571 | nvme_dev_remove(dev); | |
5a92e700 | 2572 | nvme_free_queues(dev, 1); |
9a6b9458 KB |
2573 | } |
2574 | ||
2575 | static int nvme_dev_resume(struct nvme_dev *dev) | |
2576 | { | |
2577 | int ret; | |
2578 | ||
2579 | ret = nvme_dev_start(dev); | |
2580 | if (ret && ret != -EBUSY) | |
2581 | return ret; | |
2582 | if (ret == -EBUSY) { | |
2583 | spin_lock(&dev_list_lock); | |
bdfd70fd | 2584 | PREPARE_WORK(&dev->reset_work, nvme_remove_disks); |
9a6b9458 KB |
2585 | queue_work(nvme_workq, &dev->reset_work); |
2586 | spin_unlock(&dev_list_lock); | |
2587 | } | |
d4b4ff8e | 2588 | dev->initialized = 1; |
9a6b9458 KB |
2589 | return 0; |
2590 | } | |
2591 | ||
2592 | static void nvme_dev_reset(struct nvme_dev *dev) | |
2593 | { | |
2594 | nvme_dev_shutdown(dev); | |
2595 | if (nvme_dev_resume(dev)) { | |
2596 | dev_err(&dev->pci_dev->dev, "Device failed to resume\n"); | |
2597 | kref_get(&dev->kref); | |
2598 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", | |
2599 | dev->instance))) { | |
2600 | dev_err(&dev->pci_dev->dev, | |
2601 | "Failed to start controller remove task\n"); | |
2602 | kref_put(&dev->kref, nvme_free_dev); | |
2603 | } | |
2604 | } | |
2605 | } | |
2606 | ||
2607 | static void nvme_reset_failed_dev(struct work_struct *ws) | |
2608 | { | |
2609 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); | |
2610 | nvme_dev_reset(dev); | |
2611 | } | |
2612 | ||
8d85fce7 | 2613 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2614 | { |
0877cb0d | 2615 | int result = -ENOMEM; |
b60503ba MW |
2616 | struct nvme_dev *dev; |
2617 | ||
2618 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
2619 | if (!dev) | |
2620 | return -ENOMEM; | |
2621 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
2622 | GFP_KERNEL); | |
2623 | if (!dev->entry) | |
2624 | goto free; | |
1b23484b MW |
2625 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
2626 | GFP_KERNEL); | |
b60503ba MW |
2627 | if (!dev->queues) |
2628 | goto free; | |
42f61420 KB |
2629 | dev->io_queue = alloc_percpu(unsigned short); |
2630 | if (!dev->io_queue) | |
2631 | goto free; | |
b60503ba MW |
2632 | |
2633 | INIT_LIST_HEAD(&dev->namespaces); | |
bdfd70fd | 2634 | INIT_WORK(&dev->reset_work, nvme_reset_failed_dev); |
b60503ba | 2635 | dev->pci_dev = pdev; |
9a6b9458 | 2636 | pci_set_drvdata(pdev, dev); |
cd58ad7d QSA |
2637 | result = nvme_set_instance(dev); |
2638 | if (result) | |
0877cb0d | 2639 | goto free; |
b60503ba | 2640 | |
091b6092 MW |
2641 | result = nvme_setup_prp_pools(dev); |
2642 | if (result) | |
0877cb0d | 2643 | goto release; |
091b6092 | 2644 | |
fb35e914 | 2645 | kref_init(&dev->kref); |
f0b50732 | 2646 | result = nvme_dev_start(dev); |
d82e8bfd KB |
2647 | if (result) { |
2648 | if (result == -EBUSY) | |
2649 | goto create_cdev; | |
0877cb0d | 2650 | goto release_pools; |
d82e8bfd | 2651 | } |
b60503ba | 2652 | |
740216fc | 2653 | result = nvme_dev_add(dev); |
d82e8bfd | 2654 | if (result) |
f0b50732 | 2655 | goto shutdown; |
740216fc | 2656 | |
d82e8bfd | 2657 | create_cdev: |
5e82e952 KB |
2658 | scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance); |
2659 | dev->miscdev.minor = MISC_DYNAMIC_MINOR; | |
2660 | dev->miscdev.parent = &pdev->dev; | |
2661 | dev->miscdev.name = dev->name; | |
2662 | dev->miscdev.fops = &nvme_dev_fops; | |
2663 | result = misc_register(&dev->miscdev); | |
2664 | if (result) | |
2665 | goto remove; | |
2666 | ||
d4b4ff8e | 2667 | dev->initialized = 1; |
b60503ba MW |
2668 | return 0; |
2669 | ||
5e82e952 KB |
2670 | remove: |
2671 | nvme_dev_remove(dev); | |
9ac27090 | 2672 | nvme_free_namespaces(dev); |
f0b50732 KB |
2673 | shutdown: |
2674 | nvme_dev_shutdown(dev); | |
0877cb0d | 2675 | release_pools: |
a1a5ef99 | 2676 | nvme_free_queues(dev, 0); |
091b6092 | 2677 | nvme_release_prp_pools(dev); |
0877cb0d KB |
2678 | release: |
2679 | nvme_release_instance(dev); | |
b60503ba | 2680 | free: |
42f61420 | 2681 | free_percpu(dev->io_queue); |
b60503ba MW |
2682 | kfree(dev->queues); |
2683 | kfree(dev->entry); | |
2684 | kfree(dev); | |
2685 | return result; | |
2686 | } | |
2687 | ||
09ece142 KB |
2688 | static void nvme_shutdown(struct pci_dev *pdev) |
2689 | { | |
2690 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2691 | nvme_dev_shutdown(dev); | |
2692 | } | |
2693 | ||
8d85fce7 | 2694 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2695 | { |
2696 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
2697 | |
2698 | spin_lock(&dev_list_lock); | |
2699 | list_del_init(&dev->node); | |
2700 | spin_unlock(&dev_list_lock); | |
2701 | ||
2702 | pci_set_drvdata(pdev, NULL); | |
2703 | flush_work(&dev->reset_work); | |
5e82e952 | 2704 | misc_deregister(&dev->miscdev); |
9a6b9458 KB |
2705 | nvme_dev_remove(dev); |
2706 | nvme_dev_shutdown(dev); | |
a1a5ef99 | 2707 | nvme_free_queues(dev, 0); |
5a92e700 | 2708 | rcu_barrier(); |
9a6b9458 KB |
2709 | nvme_release_instance(dev); |
2710 | nvme_release_prp_pools(dev); | |
5e82e952 | 2711 | kref_put(&dev->kref, nvme_free_dev); |
b60503ba MW |
2712 | } |
2713 | ||
2714 | /* These functions are yet to be implemented */ | |
2715 | #define nvme_error_detected NULL | |
2716 | #define nvme_dump_registers NULL | |
2717 | #define nvme_link_reset NULL | |
2718 | #define nvme_slot_reset NULL | |
2719 | #define nvme_error_resume NULL | |
cd638946 | 2720 | |
671a6018 | 2721 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2722 | static int nvme_suspend(struct device *dev) |
2723 | { | |
2724 | struct pci_dev *pdev = to_pci_dev(dev); | |
2725 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2726 | ||
2727 | nvme_dev_shutdown(ndev); | |
2728 | return 0; | |
2729 | } | |
2730 | ||
2731 | static int nvme_resume(struct device *dev) | |
2732 | { | |
2733 | struct pci_dev *pdev = to_pci_dev(dev); | |
2734 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2735 | |
9a6b9458 | 2736 | if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) { |
bdfd70fd | 2737 | PREPARE_WORK(&ndev->reset_work, nvme_reset_failed_dev); |
9a6b9458 KB |
2738 | queue_work(nvme_workq, &ndev->reset_work); |
2739 | } | |
2740 | return 0; | |
cd638946 | 2741 | } |
671a6018 | 2742 | #endif |
cd638946 KB |
2743 | |
2744 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2745 | |
1d352035 | 2746 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
2747 | .error_detected = nvme_error_detected, |
2748 | .mmio_enabled = nvme_dump_registers, | |
2749 | .link_reset = nvme_link_reset, | |
2750 | .slot_reset = nvme_slot_reset, | |
2751 | .resume = nvme_error_resume, | |
2752 | }; | |
2753 | ||
2754 | /* Move to pci_ids.h later */ | |
2755 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
2756 | ||
6eb0d698 | 2757 | static const struct pci_device_id nvme_id_table[] = { |
b60503ba MW |
2758 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
2759 | { 0, } | |
2760 | }; | |
2761 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2762 | ||
2763 | static struct pci_driver nvme_driver = { | |
2764 | .name = "nvme", | |
2765 | .id_table = nvme_id_table, | |
2766 | .probe = nvme_probe, | |
8d85fce7 | 2767 | .remove = nvme_remove, |
09ece142 | 2768 | .shutdown = nvme_shutdown, |
cd638946 KB |
2769 | .driver = { |
2770 | .pm = &nvme_dev_pm_ops, | |
2771 | }, | |
b60503ba MW |
2772 | .err_handler = &nvme_err_handler, |
2773 | }; | |
2774 | ||
2775 | static int __init nvme_init(void) | |
2776 | { | |
0ac13140 | 2777 | int result; |
1fa6aead MW |
2778 | |
2779 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
2780 | if (IS_ERR(nvme_thread)) | |
2781 | return PTR_ERR(nvme_thread); | |
b60503ba | 2782 | |
9a6b9458 KB |
2783 | result = -ENOMEM; |
2784 | nvme_workq = create_singlethread_workqueue("nvme"); | |
2785 | if (!nvme_workq) | |
2786 | goto kill_kthread; | |
2787 | ||
5c42ea16 KB |
2788 | result = register_blkdev(nvme_major, "nvme"); |
2789 | if (result < 0) | |
9a6b9458 | 2790 | goto kill_workq; |
5c42ea16 | 2791 | else if (result > 0) |
0ac13140 | 2792 | nvme_major = result; |
b60503ba MW |
2793 | |
2794 | result = pci_register_driver(&nvme_driver); | |
1fa6aead MW |
2795 | if (result) |
2796 | goto unregister_blkdev; | |
2797 | return 0; | |
b60503ba | 2798 | |
1fa6aead | 2799 | unregister_blkdev: |
b60503ba | 2800 | unregister_blkdev(nvme_major, "nvme"); |
9a6b9458 KB |
2801 | kill_workq: |
2802 | destroy_workqueue(nvme_workq); | |
1fa6aead MW |
2803 | kill_kthread: |
2804 | kthread_stop(nvme_thread); | |
b60503ba MW |
2805 | return result; |
2806 | } | |
2807 | ||
2808 | static void __exit nvme_exit(void) | |
2809 | { | |
2810 | pci_unregister_driver(&nvme_driver); | |
2811 | unregister_blkdev(nvme_major, "nvme"); | |
9a6b9458 | 2812 | destroy_workqueue(nvme_workq); |
1fa6aead | 2813 | kthread_stop(nvme_thread); |
b60503ba MW |
2814 | } |
2815 | ||
2816 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2817 | MODULE_LICENSE("GPL"); | |
6eb0d698 | 2818 | MODULE_VERSION("0.9"); |
b60503ba MW |
2819 | module_init(nvme_init); |
2820 | module_exit(nvme_exit); |