Commit | Line | Data |
---|---|---|
b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
8de05535 | 21 | #include <linux/bitops.h> |
b60503ba | 22 | #include <linux/blkdev.h> |
fd63e9ce | 23 | #include <linux/delay.h> |
b60503ba MW |
24 | #include <linux/errno.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/genhd.h> | |
5aff9382 | 27 | #include <linux/idr.h> |
b60503ba MW |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kdev_t.h> | |
1fa6aead | 32 | #include <linux/kthread.h> |
b60503ba MW |
33 | #include <linux/kernel.h> |
34 | #include <linux/mm.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/pci.h> | |
be7b6275 | 38 | #include <linux/poison.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/version.h> | |
43 | ||
44 | #define NVME_Q_DEPTH 1024 | |
45 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
46 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
47 | #define NVME_MINORS 64 | |
e85248e5 MW |
48 | #define IO_TIMEOUT (5 * HZ) |
49 | #define ADMIN_TIMEOUT (60 * HZ) | |
b60503ba MW |
50 | |
51 | static int nvme_major; | |
52 | module_param(nvme_major, int, 0); | |
53 | ||
58ffacb5 MW |
54 | static int use_threaded_interrupts; |
55 | module_param(use_threaded_interrupts, int, 0); | |
56 | ||
1fa6aead MW |
57 | static DEFINE_SPINLOCK(dev_list_lock); |
58 | static LIST_HEAD(dev_list); | |
59 | static struct task_struct *nvme_thread; | |
60 | ||
b60503ba MW |
61 | /* |
62 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
63 | */ | |
64 | struct nvme_dev { | |
1fa6aead | 65 | struct list_head node; |
b60503ba MW |
66 | struct nvme_queue **queues; |
67 | u32 __iomem *dbs; | |
68 | struct pci_dev *pci_dev; | |
091b6092 | 69 | struct dma_pool *prp_page_pool; |
99802a7a | 70 | struct dma_pool *prp_small_pool; |
b60503ba MW |
71 | int instance; |
72 | int queue_count; | |
73 | u32 ctrl_config; | |
74 | struct msix_entry *entry; | |
75 | struct nvme_bar __iomem *bar; | |
76 | struct list_head namespaces; | |
51814232 MW |
77 | char serial[20]; |
78 | char model[40]; | |
79 | char firmware_rev[8]; | |
b60503ba MW |
80 | }; |
81 | ||
82 | /* | |
83 | * An NVM Express namespace is equivalent to a SCSI LUN | |
84 | */ | |
85 | struct nvme_ns { | |
86 | struct list_head list; | |
87 | ||
88 | struct nvme_dev *dev; | |
89 | struct request_queue *queue; | |
90 | struct gendisk *disk; | |
91 | ||
92 | int ns_id; | |
93 | int lba_shift; | |
94 | }; | |
95 | ||
96 | /* | |
97 | * An NVM Express queue. Each device has at least two (one for admin | |
98 | * commands and one for I/O commands). | |
99 | */ | |
100 | struct nvme_queue { | |
101 | struct device *q_dmadev; | |
091b6092 | 102 | struct nvme_dev *dev; |
b60503ba MW |
103 | spinlock_t q_lock; |
104 | struct nvme_command *sq_cmds; | |
105 | volatile struct nvme_completion *cqes; | |
106 | dma_addr_t sq_dma_addr; | |
107 | dma_addr_t cq_dma_addr; | |
108 | wait_queue_head_t sq_full; | |
1fa6aead | 109 | wait_queue_t sq_cong_wait; |
b60503ba MW |
110 | struct bio_list sq_cong; |
111 | u32 __iomem *q_db; | |
112 | u16 q_depth; | |
113 | u16 cq_vector; | |
114 | u16 sq_head; | |
115 | u16 sq_tail; | |
116 | u16 cq_head; | |
82123460 | 117 | u16 cq_phase; |
b60503ba MW |
118 | unsigned long cmdid_data[]; |
119 | }; | |
120 | ||
121 | /* | |
122 | * Check we didin't inadvertently grow the command struct | |
123 | */ | |
124 | static inline void _nvme_check_size(void) | |
125 | { | |
126 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
127 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
128 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
129 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
130 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
131 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
132 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
133 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
134 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
135 | } | |
136 | ||
e85248e5 MW |
137 | struct nvme_cmd_info { |
138 | unsigned long ctx; | |
139 | unsigned long timeout; | |
140 | }; | |
141 | ||
142 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
143 | { | |
144 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
145 | } | |
146 | ||
b60503ba | 147 | /** |
714a7a22 MW |
148 | * alloc_cmdid() - Allocate a Command ID |
149 | * @nvmeq: The queue that will be used for this command | |
150 | * @ctx: A pointer that will be passed to the handler | |
151 | * @handler: The ID of the handler to call | |
b60503ba MW |
152 | * |
153 | * Allocate a Command ID for a queue. The data passed in will | |
154 | * be passed to the completion handler. This is implemented by using | |
155 | * the bottom two bits of the ctx pointer to store the handler ID. | |
156 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
157 | * We can change this if it becomes a problem. | |
184d2944 MW |
158 | * |
159 | * May be called with local interrupts disabled and the q_lock held, | |
160 | * or with interrupts enabled and no locks held. | |
b60503ba | 161 | */ |
e85248e5 MW |
162 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler, |
163 | unsigned timeout) | |
b60503ba | 164 | { |
e6d15f79 | 165 | int depth = nvmeq->q_depth - 1; |
e85248e5 | 166 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
167 | int cmdid; |
168 | ||
169 | BUG_ON((unsigned long)ctx & 3); | |
170 | ||
171 | do { | |
172 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
173 | if (cmdid >= depth) | |
174 | return -EBUSY; | |
175 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
176 | ||
e85248e5 MW |
177 | info[cmdid].ctx = (unsigned long)ctx | handler; |
178 | info[cmdid].timeout = jiffies + timeout; | |
b60503ba MW |
179 | return cmdid; |
180 | } | |
181 | ||
182 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
e85248e5 | 183 | int handler, unsigned timeout) |
b60503ba MW |
184 | { |
185 | int cmdid; | |
186 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 187 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
188 | return (cmdid < 0) ? -EINTR : cmdid; |
189 | } | |
190 | ||
fa922821 MW |
191 | /* |
192 | * If you need more than four handlers, you'll need to change how | |
be7b6275 MW |
193 | * alloc_cmdid and nvme_process_cq work. Consider using a special |
194 | * CMD_CTX value instead, if that works for your situation. | |
b60503ba MW |
195 | */ |
196 | enum { | |
197 | sync_completion_id = 0, | |
198 | bio_completion_id, | |
199 | }; | |
200 | ||
00df5cb4 | 201 | /* Special values must be a multiple of 4, and less than 0x1000 */ |
be7b6275 | 202 | #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id) |
d2d87034 MW |
203 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
204 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
205 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
00df5cb4 | 206 | #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE) |
be7b6275 | 207 | |
184d2944 MW |
208 | /* |
209 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
210 | */ | |
b60503ba MW |
211 | static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid) |
212 | { | |
213 | unsigned long data; | |
e85248e5 | 214 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 215 | |
e85248e5 | 216 | if (cmdid >= nvmeq->q_depth) |
48e3d398 | 217 | return CMD_CTX_INVALID; |
e85248e5 MW |
218 | data = info[cmdid].ctx; |
219 | info[cmdid].ctx = CMD_CTX_COMPLETED; | |
b60503ba MW |
220 | clear_bit(cmdid, nvmeq->cmdid_data); |
221 | wake_up(&nvmeq->sq_full); | |
222 | return data; | |
223 | } | |
224 | ||
21075bde | 225 | static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid) |
3c0cf138 | 226 | { |
21075bde | 227 | unsigned long data; |
e85248e5 | 228 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
21075bde | 229 | data = info[cmdid].ctx; |
e85248e5 | 230 | info[cmdid].ctx = CMD_CTX_CANCELLED; |
21075bde | 231 | return data; |
3c0cf138 MW |
232 | } |
233 | ||
b60503ba MW |
234 | static struct nvme_queue *get_nvmeq(struct nvme_ns *ns) |
235 | { | |
9ecdc946 | 236 | return ns->dev->queues[get_cpu() + 1]; |
b60503ba MW |
237 | } |
238 | ||
239 | static void put_nvmeq(struct nvme_queue *nvmeq) | |
240 | { | |
1b23484b | 241 | put_cpu(); |
b60503ba MW |
242 | } |
243 | ||
244 | /** | |
714a7a22 | 245 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
246 | * @nvmeq: The queue to use |
247 | * @cmd: The command to send | |
248 | * | |
249 | * Safe to use from interrupt context | |
250 | */ | |
251 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
252 | { | |
253 | unsigned long flags; | |
254 | u16 tail; | |
b60503ba MW |
255 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
256 | tail = nvmeq->sq_tail; | |
257 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
b60503ba MW |
258 | if (++tail == nvmeq->q_depth) |
259 | tail = 0; | |
7547881d | 260 | writel(tail, nvmeq->q_db); |
b60503ba MW |
261 | nvmeq->sq_tail = tail; |
262 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
e025344c SMM |
267 | struct nvme_prps { |
268 | int npages; | |
269 | dma_addr_t first_dma; | |
270 | __le64 *list[0]; | |
271 | }; | |
272 | ||
d567760c | 273 | static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps) |
e025344c SMM |
274 | { |
275 | const int last_prp = PAGE_SIZE / 8 - 1; | |
276 | int i; | |
277 | dma_addr_t prp_dma; | |
278 | ||
279 | if (!prps) | |
280 | return; | |
281 | ||
282 | prp_dma = prps->first_dma; | |
99802a7a MW |
283 | |
284 | if (prps->npages == 0) | |
285 | dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma); | |
e025344c SMM |
286 | for (i = 0; i < prps->npages; i++) { |
287 | __le64 *prp_list = prps->list[i]; | |
288 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
091b6092 | 289 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); |
e025344c SMM |
290 | prp_dma = next_prp_dma; |
291 | } | |
292 | kfree(prps); | |
293 | } | |
294 | ||
d534df3c | 295 | struct nvme_bio { |
b60503ba MW |
296 | struct bio *bio; |
297 | int nents; | |
e025344c | 298 | struct nvme_prps *prps; |
b60503ba MW |
299 | struct scatterlist sg[0]; |
300 | }; | |
301 | ||
302 | /* XXX: use a mempool */ | |
d534df3c | 303 | static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp) |
b60503ba | 304 | { |
d534df3c | 305 | return kzalloc(sizeof(struct nvme_bio) + |
b60503ba MW |
306 | sizeof(struct scatterlist) * nseg, gfp); |
307 | } | |
308 | ||
d534df3c | 309 | static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio) |
b60503ba | 310 | { |
d567760c | 311 | nvme_free_prps(nvmeq->dev, nbio->prps); |
d534df3c | 312 | kfree(nbio); |
b60503ba MW |
313 | } |
314 | ||
315 | static void bio_completion(struct nvme_queue *nvmeq, void *ctx, | |
316 | struct nvme_completion *cqe) | |
317 | { | |
d534df3c MW |
318 | struct nvme_bio *nbio = ctx; |
319 | struct bio *bio = nbio->bio; | |
b60503ba MW |
320 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
321 | ||
d534df3c | 322 | dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents, |
b60503ba | 323 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
d534df3c | 324 | free_nbio(nvmeq, nbio); |
09a58f53 | 325 | if (status) { |
1ad2f893 | 326 | bio_endio(bio, -EIO); |
09a58f53 | 327 | } else if (bio->bi_vcnt > bio->bi_idx) { |
eac623ba MW |
328 | if (bio_list_empty(&nvmeq->sq_cong)) |
329 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
1ad2f893 MW |
330 | bio_list_add(&nvmeq->sq_cong, bio); |
331 | wake_up_process(nvme_thread); | |
332 | } else { | |
333 | bio_endio(bio, 0); | |
334 | } | |
b60503ba MW |
335 | } |
336 | ||
184d2944 | 337 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
d567760c | 338 | static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev, |
e025344c | 339 | struct nvme_common_command *cmd, |
b77954cb MW |
340 | struct scatterlist *sg, int *len, |
341 | gfp_t gfp) | |
ff22b54f | 342 | { |
99802a7a | 343 | struct dma_pool *pool; |
b77954cb | 344 | int length = *len; |
ff22b54f MW |
345 | int dma_len = sg_dma_len(sg); |
346 | u64 dma_addr = sg_dma_address(sg); | |
347 | int offset = offset_in_page(dma_addr); | |
e025344c SMM |
348 | __le64 *prp_list; |
349 | dma_addr_t prp_dma; | |
350 | int nprps, npages, i, prp_page; | |
351 | struct nvme_prps *prps = NULL; | |
ff22b54f MW |
352 | |
353 | cmd->prp1 = cpu_to_le64(dma_addr); | |
354 | length -= (PAGE_SIZE - offset); | |
355 | if (length <= 0) | |
e025344c | 356 | return prps; |
ff22b54f MW |
357 | |
358 | dma_len -= (PAGE_SIZE - offset); | |
359 | if (dma_len) { | |
360 | dma_addr += (PAGE_SIZE - offset); | |
361 | } else { | |
362 | sg = sg_next(sg); | |
363 | dma_addr = sg_dma_address(sg); | |
364 | dma_len = sg_dma_len(sg); | |
365 | } | |
366 | ||
367 | if (length <= PAGE_SIZE) { | |
368 | cmd->prp2 = cpu_to_le64(dma_addr); | |
e025344c SMM |
369 | return prps; |
370 | } | |
371 | ||
372 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
373 | npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE); | |
b77954cb MW |
374 | prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, gfp); |
375 | if (!prps) { | |
376 | cmd->prp2 = cpu_to_le64(dma_addr); | |
377 | *len = (*len - length) + PAGE_SIZE; | |
378 | return prps; | |
379 | } | |
e025344c | 380 | prp_page = 0; |
99802a7a MW |
381 | if (nprps <= (256 / 8)) { |
382 | pool = dev->prp_small_pool; | |
383 | prps->npages = 0; | |
384 | } else { | |
385 | pool = dev->prp_page_pool; | |
386 | prps->npages = npages; | |
387 | } | |
388 | ||
b77954cb MW |
389 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
390 | if (!prp_list) { | |
391 | cmd->prp2 = cpu_to_le64(dma_addr); | |
392 | *len = (*len - length) + PAGE_SIZE; | |
393 | kfree(prps); | |
394 | return NULL; | |
395 | } | |
e025344c SMM |
396 | prps->list[prp_page++] = prp_list; |
397 | prps->first_dma = prp_dma; | |
398 | cmd->prp2 = cpu_to_le64(prp_dma); | |
399 | i = 0; | |
400 | for (;;) { | |
7523d834 | 401 | if (i == PAGE_SIZE / 8) { |
e025344c | 402 | __le64 *old_prp_list = prp_list; |
b77954cb MW |
403 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
404 | if (!prp_list) { | |
405 | *len = (*len - length); | |
406 | return prps; | |
407 | } | |
e025344c | 408 | prps->list[prp_page++] = prp_list; |
7523d834 MW |
409 | prp_list[0] = old_prp_list[i - 1]; |
410 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
411 | i = 1; | |
e025344c SMM |
412 | } |
413 | prp_list[i++] = cpu_to_le64(dma_addr); | |
414 | dma_len -= PAGE_SIZE; | |
415 | dma_addr += PAGE_SIZE; | |
416 | length -= PAGE_SIZE; | |
417 | if (length <= 0) | |
418 | break; | |
419 | if (dma_len > 0) | |
420 | continue; | |
421 | BUG_ON(dma_len < 0); | |
422 | sg = sg_next(sg); | |
423 | dma_addr = sg_dma_address(sg); | |
424 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
425 | } |
426 | ||
e025344c | 427 | return prps; |
ff22b54f MW |
428 | } |
429 | ||
1ad2f893 MW |
430 | /* NVMe scatterlists require no holes in the virtual address */ |
431 | #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \ | |
432 | (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE)) | |
433 | ||
d534df3c | 434 | static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio, |
b60503ba MW |
435 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
436 | { | |
76830840 MW |
437 | struct bio_vec *bvec, *bvprv = NULL; |
438 | struct scatterlist *sg = NULL; | |
1ad2f893 | 439 | int i, old_idx, length = 0, nsegs = 0; |
b60503ba | 440 | |
76830840 | 441 | sg_init_table(nbio->sg, psegs); |
1ad2f893 | 442 | old_idx = bio->bi_idx; |
b60503ba | 443 | bio_for_each_segment(bvec, bio, i) { |
76830840 MW |
444 | if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { |
445 | sg->length += bvec->bv_len; | |
446 | } else { | |
1ad2f893 MW |
447 | if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec)) |
448 | break; | |
76830840 MW |
449 | sg = sg ? sg + 1 : nbio->sg; |
450 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, | |
451 | bvec->bv_offset); | |
452 | nsegs++; | |
453 | } | |
1ad2f893 | 454 | length += bvec->bv_len; |
76830840 | 455 | bvprv = bvec; |
b60503ba | 456 | } |
1ad2f893 | 457 | bio->bi_idx = i; |
d534df3c | 458 | nbio->nents = nsegs; |
76830840 | 459 | sg_mark_end(sg); |
1ad2f893 MW |
460 | if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) { |
461 | bio->bi_idx = old_idx; | |
462 | return -ENOMEM; | |
463 | } | |
464 | return length; | |
b60503ba MW |
465 | } |
466 | ||
00df5cb4 MW |
467 | static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
468 | int cmdid) | |
469 | { | |
470 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
471 | ||
472 | memset(cmnd, 0, sizeof(*cmnd)); | |
473 | cmnd->common.opcode = nvme_cmd_flush; | |
474 | cmnd->common.command_id = cmdid; | |
475 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
476 | ||
477 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
478 | nvmeq->sq_tail = 0; | |
479 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) | |
485 | { | |
486 | int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, | |
487 | sync_completion_id, IO_TIMEOUT); | |
488 | if (unlikely(cmdid < 0)) | |
489 | return cmdid; | |
490 | ||
491 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
492 | } | |
493 | ||
184d2944 MW |
494 | /* |
495 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
496 | */ | |
b60503ba MW |
497 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
498 | struct bio *bio) | |
499 | { | |
ff22b54f | 500 | struct nvme_command *cmnd; |
d534df3c | 501 | struct nvme_bio *nbio; |
b60503ba | 502 | enum dma_data_direction dma_dir; |
1ad2f893 | 503 | int cmdid, length, result = -ENOMEM; |
b60503ba MW |
504 | u16 control; |
505 | u32 dsmgmt; | |
b60503ba MW |
506 | int psegs = bio_phys_segments(ns->queue, bio); |
507 | ||
00df5cb4 MW |
508 | if ((bio->bi_rw & REQ_FLUSH) && psegs) { |
509 | result = nvme_submit_flush_data(nvmeq, ns); | |
510 | if (result) | |
511 | return result; | |
512 | } | |
513 | ||
eeee3226 | 514 | nbio = alloc_nbio(psegs, GFP_ATOMIC); |
d534df3c | 515 | if (!nbio) |
eeee3226 | 516 | goto nomem; |
d534df3c | 517 | nbio->bio = bio; |
b60503ba | 518 | |
eeee3226 | 519 | result = -EBUSY; |
d534df3c | 520 | cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT); |
b60503ba | 521 | if (unlikely(cmdid < 0)) |
d534df3c | 522 | goto free_nbio; |
b60503ba | 523 | |
00df5cb4 MW |
524 | if ((bio->bi_rw & REQ_FLUSH) && !psegs) |
525 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
526 | ||
b60503ba MW |
527 | control = 0; |
528 | if (bio->bi_rw & REQ_FUA) | |
529 | control |= NVME_RW_FUA; | |
530 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
531 | control |= NVME_RW_LR; | |
532 | ||
533 | dsmgmt = 0; | |
534 | if (bio->bi_rw & REQ_RAHEAD) | |
535 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
536 | ||
ff22b54f | 537 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 538 | |
b8deb62c | 539 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 540 | if (bio_data_dir(bio)) { |
ff22b54f | 541 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
542 | dma_dir = DMA_TO_DEVICE; |
543 | } else { | |
ff22b54f | 544 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
545 | dma_dir = DMA_FROM_DEVICE; |
546 | } | |
547 | ||
1ad2f893 MW |
548 | result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs); |
549 | if (result < 0) | |
eeee3226 | 550 | goto free_nbio; |
1ad2f893 | 551 | length = result; |
b60503ba | 552 | |
ff22b54f MW |
553 | cmnd->rw.command_id = cmdid; |
554 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
d567760c | 555 | nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg, |
b77954cb | 556 | &length, GFP_ATOMIC); |
ff22b54f | 557 | cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9)); |
1ad2f893 | 558 | cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1); |
ff22b54f MW |
559 | cmnd->rw.control = cpu_to_le16(control); |
560 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 561 | |
d8ee9d69 MW |
562 | bio->bi_sector += length >> 9; |
563 | ||
b60503ba MW |
564 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
565 | nvmeq->sq_tail = 0; | |
7547881d | 566 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 567 | |
1974b1ae MW |
568 | return 0; |
569 | ||
d534df3c MW |
570 | free_nbio: |
571 | free_nbio(nvmeq, nbio); | |
eeee3226 MW |
572 | nomem: |
573 | return result; | |
b60503ba MW |
574 | } |
575 | ||
576 | /* | |
577 | * NB: return value of non-zero would mean that we were a stacking driver. | |
578 | * make_request must always succeed. | |
579 | */ | |
580 | static int nvme_make_request(struct request_queue *q, struct bio *bio) | |
581 | { | |
582 | struct nvme_ns *ns = q->queuedata; | |
583 | struct nvme_queue *nvmeq = get_nvmeq(ns); | |
eeee3226 MW |
584 | int result = -EBUSY; |
585 | ||
586 | spin_lock_irq(&nvmeq->q_lock); | |
587 | if (bio_list_empty(&nvmeq->sq_cong)) | |
588 | result = nvme_submit_bio_queue(nvmeq, ns, bio); | |
589 | if (unlikely(result)) { | |
590 | if (bio_list_empty(&nvmeq->sq_cong)) | |
591 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
b60503ba MW |
592 | bio_list_add(&nvmeq->sq_cong, bio); |
593 | } | |
eeee3226 MW |
594 | |
595 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
596 | put_nvmeq(nvmeq); |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | struct sync_cmd_info { | |
602 | struct task_struct *task; | |
603 | u32 result; | |
604 | int status; | |
605 | }; | |
606 | ||
607 | static void sync_completion(struct nvme_queue *nvmeq, void *ctx, | |
608 | struct nvme_completion *cqe) | |
609 | { | |
610 | struct sync_cmd_info *cmdinfo = ctx; | |
c4270559 | 611 | if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED)) |
be7b6275 | 612 | return; |
00df5cb4 MW |
613 | if ((unsigned long)cmdinfo == CMD_CTX_FLUSH) |
614 | return; | |
b36235df MW |
615 | if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) { |
616 | dev_warn(nvmeq->q_dmadev, | |
617 | "completed id %d twice on queue %d\n", | |
618 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
619 | return; | |
620 | } | |
48e3d398 MW |
621 | if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) { |
622 | dev_warn(nvmeq->q_dmadev, | |
623 | "invalid id %d completed on queue %d\n", | |
624 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
625 | return; | |
626 | } | |
b60503ba MW |
627 | cmdinfo->result = le32_to_cpup(&cqe->result); |
628 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
629 | wake_up_process(cmdinfo->task); | |
630 | } | |
631 | ||
632 | typedef void (*completion_fn)(struct nvme_queue *, void *, | |
633 | struct nvme_completion *); | |
634 | ||
8de05535 MW |
635 | static const completion_fn nvme_completions[4] = { |
636 | [sync_completion_id] = sync_completion, | |
637 | [bio_completion_id] = bio_completion, | |
638 | }; | |
639 | ||
b60503ba MW |
640 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) |
641 | { | |
82123460 | 642 | u16 head, phase; |
b60503ba | 643 | |
b60503ba | 644 | head = nvmeq->cq_head; |
82123460 | 645 | phase = nvmeq->cq_phase; |
b60503ba MW |
646 | |
647 | for (;;) { | |
648 | unsigned long data; | |
649 | void *ptr; | |
650 | unsigned char handler; | |
651 | struct nvme_completion cqe = nvmeq->cqes[head]; | |
82123460 | 652 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
653 | break; |
654 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
655 | if (++head == nvmeq->q_depth) { | |
656 | head = 0; | |
82123460 | 657 | phase = !phase; |
b60503ba MW |
658 | } |
659 | ||
660 | data = free_cmdid(nvmeq, cqe.command_id); | |
661 | handler = data & 3; | |
662 | ptr = (void *)(data & ~3UL); | |
8de05535 | 663 | nvme_completions[handler](nvmeq, ptr, &cqe); |
b60503ba MW |
664 | } |
665 | ||
666 | /* If the controller ignores the cq head doorbell and continuously | |
667 | * writes to the queue, it is theoretically possible to wrap around | |
668 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
669 | * requires that 0.1% of your interrupts are handled, so this isn't | |
670 | * a big problem. | |
671 | */ | |
82123460 | 672 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
673 | return IRQ_NONE; |
674 | ||
675 | writel(head, nvmeq->q_db + 1); | |
676 | nvmeq->cq_head = head; | |
82123460 | 677 | nvmeq->cq_phase = phase; |
b60503ba MW |
678 | |
679 | return IRQ_HANDLED; | |
680 | } | |
681 | ||
682 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
683 | { |
684 | irqreturn_t result; | |
685 | struct nvme_queue *nvmeq = data; | |
686 | spin_lock(&nvmeq->q_lock); | |
687 | result = nvme_process_cq(nvmeq); | |
688 | spin_unlock(&nvmeq->q_lock); | |
689 | return result; | |
690 | } | |
691 | ||
692 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
693 | { | |
694 | struct nvme_queue *nvmeq = data; | |
695 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
696 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
697 | return IRQ_NONE; | |
698 | return IRQ_WAKE_THREAD; | |
699 | } | |
700 | ||
3c0cf138 MW |
701 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
702 | { | |
703 | spin_lock_irq(&nvmeq->q_lock); | |
21075bde | 704 | cancel_cmdid(nvmeq, cmdid); |
3c0cf138 MW |
705 | spin_unlock_irq(&nvmeq->q_lock); |
706 | } | |
707 | ||
b60503ba MW |
708 | /* |
709 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
710 | * if the result is positive, it's an NVM Express status code | |
711 | */ | |
3c0cf138 | 712 | static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, |
e85248e5 | 713 | struct nvme_command *cmd, u32 *result, unsigned timeout) |
b60503ba MW |
714 | { |
715 | int cmdid; | |
716 | struct sync_cmd_info cmdinfo; | |
717 | ||
718 | cmdinfo.task = current; | |
719 | cmdinfo.status = -EINTR; | |
720 | ||
e85248e5 MW |
721 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id, |
722 | timeout); | |
b60503ba MW |
723 | if (cmdid < 0) |
724 | return cmdid; | |
725 | cmd->common.command_id = cmdid; | |
726 | ||
3c0cf138 MW |
727 | set_current_state(TASK_KILLABLE); |
728 | nvme_submit_cmd(nvmeq, cmd); | |
b60503ba MW |
729 | schedule(); |
730 | ||
3c0cf138 MW |
731 | if (cmdinfo.status == -EINTR) { |
732 | nvme_abort_command(nvmeq, cmdid); | |
733 | return -EINTR; | |
734 | } | |
735 | ||
b60503ba MW |
736 | if (result) |
737 | *result = cmdinfo.result; | |
738 | ||
739 | return cmdinfo.status; | |
740 | } | |
741 | ||
742 | static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
743 | u32 *result) | |
744 | { | |
e85248e5 | 745 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
746 | } |
747 | ||
748 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
749 | { | |
750 | int status; | |
751 | struct nvme_command c; | |
752 | ||
753 | memset(&c, 0, sizeof(c)); | |
754 | c.delete_queue.opcode = opcode; | |
755 | c.delete_queue.qid = cpu_to_le16(id); | |
756 | ||
757 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
758 | if (status) | |
759 | return -EIO; | |
760 | return 0; | |
761 | } | |
762 | ||
763 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
764 | struct nvme_queue *nvmeq) | |
765 | { | |
766 | int status; | |
767 | struct nvme_command c; | |
768 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
769 | ||
770 | memset(&c, 0, sizeof(c)); | |
771 | c.create_cq.opcode = nvme_admin_create_cq; | |
772 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
773 | c.create_cq.cqid = cpu_to_le16(qid); | |
774 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
775 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
776 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
777 | ||
778 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
779 | if (status) | |
780 | return -EIO; | |
781 | return 0; | |
782 | } | |
783 | ||
784 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
785 | struct nvme_queue *nvmeq) | |
786 | { | |
787 | int status; | |
788 | struct nvme_command c; | |
789 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
790 | ||
791 | memset(&c, 0, sizeof(c)); | |
792 | c.create_sq.opcode = nvme_admin_create_sq; | |
793 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
794 | c.create_sq.sqid = cpu_to_le16(qid); | |
795 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
796 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
797 | c.create_sq.cqid = cpu_to_le16(qid); | |
798 | ||
799 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
800 | if (status) | |
801 | return -EIO; | |
802 | return 0; | |
803 | } | |
804 | ||
805 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
806 | { | |
807 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
808 | } | |
809 | ||
810 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
811 | { | |
812 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
813 | } | |
814 | ||
815 | static void nvme_free_queue(struct nvme_dev *dev, int qid) | |
816 | { | |
817 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
aba2080f | 818 | int vector = dev->entry[nvmeq->cq_vector].vector; |
b60503ba | 819 | |
aba2080f MW |
820 | irq_set_affinity_hint(vector, NULL); |
821 | free_irq(vector, nvmeq); | |
b60503ba MW |
822 | |
823 | /* Don't tell the adapter to delete the admin queue */ | |
824 | if (qid) { | |
825 | adapter_delete_sq(dev, qid); | |
826 | adapter_delete_cq(dev, qid); | |
827 | } | |
828 | ||
829 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
830 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
831 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
832 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
833 | kfree(nvmeq); | |
834 | } | |
835 | ||
836 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
837 | int depth, int vector) | |
838 | { | |
839 | struct device *dmadev = &dev->pci_dev->dev; | |
e85248e5 | 840 | unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info)); |
b60503ba MW |
841 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
842 | if (!nvmeq) | |
843 | return NULL; | |
844 | ||
845 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
846 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
847 | if (!nvmeq->cqes) | |
848 | goto free_nvmeq; | |
849 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
850 | ||
851 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
852 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
853 | if (!nvmeq->sq_cmds) | |
854 | goto free_cqdma; | |
855 | ||
856 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 857 | nvmeq->dev = dev; |
b60503ba MW |
858 | spin_lock_init(&nvmeq->q_lock); |
859 | nvmeq->cq_head = 0; | |
82123460 | 860 | nvmeq->cq_phase = 1; |
b60503ba | 861 | init_waitqueue_head(&nvmeq->sq_full); |
1fa6aead | 862 | init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread); |
b60503ba MW |
863 | bio_list_init(&nvmeq->sq_cong); |
864 | nvmeq->q_db = &dev->dbs[qid * 2]; | |
865 | nvmeq->q_depth = depth; | |
866 | nvmeq->cq_vector = vector; | |
867 | ||
868 | return nvmeq; | |
869 | ||
870 | free_cqdma: | |
871 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
872 | nvmeq->cq_dma_addr); | |
873 | free_nvmeq: | |
874 | kfree(nvmeq); | |
875 | return NULL; | |
876 | } | |
877 | ||
3001082c MW |
878 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
879 | const char *name) | |
880 | { | |
58ffacb5 MW |
881 | if (use_threaded_interrupts) |
882 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 883 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
884 | IRQF_DISABLED | IRQF_SHARED, |
885 | name, nvmeq); | |
3001082c MW |
886 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
887 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
888 | } | |
889 | ||
b60503ba MW |
890 | static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, |
891 | int qid, int cq_size, int vector) | |
892 | { | |
893 | int result; | |
894 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
895 | ||
3f85d50b | 896 | if (!nvmeq) |
6f0f5449 | 897 | return ERR_PTR(-ENOMEM); |
3f85d50b | 898 | |
b60503ba MW |
899 | result = adapter_alloc_cq(dev, qid, nvmeq); |
900 | if (result < 0) | |
901 | goto free_nvmeq; | |
902 | ||
903 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
904 | if (result < 0) | |
905 | goto release_cq; | |
906 | ||
3001082c | 907 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
908 | if (result < 0) |
909 | goto release_sq; | |
910 | ||
911 | return nvmeq; | |
912 | ||
913 | release_sq: | |
914 | adapter_delete_sq(dev, qid); | |
915 | release_cq: | |
916 | adapter_delete_cq(dev, qid); | |
917 | free_nvmeq: | |
918 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
919 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
920 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
921 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
922 | kfree(nvmeq); | |
6f0f5449 | 923 | return ERR_PTR(result); |
b60503ba MW |
924 | } |
925 | ||
926 | static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) | |
927 | { | |
928 | int result; | |
929 | u32 aqa; | |
22605f96 MW |
930 | u64 cap; |
931 | unsigned long timeout; | |
b60503ba MW |
932 | struct nvme_queue *nvmeq; |
933 | ||
934 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
935 | ||
936 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
937 | if (!nvmeq) |
938 | return -ENOMEM; | |
b60503ba MW |
939 | |
940 | aqa = nvmeq->q_depth - 1; | |
941 | aqa |= aqa << 16; | |
942 | ||
943 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
944 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
945 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
7f53f9d2 | 946 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba | 947 | |
5911f200 | 948 | writel(0, &dev->bar->cc); |
b60503ba MW |
949 | writel(aqa, &dev->bar->aqa); |
950 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
951 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
952 | writel(dev->ctrl_config, &dev->bar->cc); | |
953 | ||
22605f96 MW |
954 | cap = readq(&dev->bar->cap); |
955 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
956 | ||
b60503ba MW |
957 | while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { |
958 | msleep(100); | |
959 | if (fatal_signal_pending(current)) | |
960 | return -EINTR; | |
22605f96 MW |
961 | if (time_after(jiffies, timeout)) { |
962 | dev_err(&dev->pci_dev->dev, | |
963 | "Device not ready; aborting initialisation\n"); | |
964 | return -ENODEV; | |
965 | } | |
b60503ba MW |
966 | } |
967 | ||
3001082c | 968 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
969 | dev->queues[0] = nvmeq; |
970 | return result; | |
971 | } | |
972 | ||
7fc3cdab MW |
973 | static int nvme_map_user_pages(struct nvme_dev *dev, int write, |
974 | unsigned long addr, unsigned length, | |
975 | struct scatterlist **sgp) | |
b60503ba | 976 | { |
36c14ed9 | 977 | int i, err, count, nents, offset; |
7fc3cdab MW |
978 | struct scatterlist *sg; |
979 | struct page **pages; | |
36c14ed9 MW |
980 | |
981 | if (addr & 3) | |
982 | return -EINVAL; | |
7fc3cdab MW |
983 | if (!length) |
984 | return -EINVAL; | |
985 | ||
36c14ed9 | 986 | offset = offset_in_page(addr); |
7fc3cdab MW |
987 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
988 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
36c14ed9 MW |
989 | |
990 | err = get_user_pages_fast(addr, count, 1, pages); | |
991 | if (err < count) { | |
992 | count = err; | |
993 | err = -EFAULT; | |
994 | goto put_pages; | |
995 | } | |
7fc3cdab MW |
996 | |
997 | sg = kcalloc(count, sizeof(*sg), GFP_KERNEL); | |
36c14ed9 | 998 | sg_init_table(sg, count); |
ff22b54f | 999 | sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset); |
7fc3cdab MW |
1000 | length -= (PAGE_SIZE - offset); |
1001 | for (i = 1; i < count; i++) { | |
1002 | sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0); | |
1003 | length -= PAGE_SIZE; | |
1004 | } | |
1005 | ||
1006 | err = -ENOMEM; | |
1007 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
1008 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 MW |
1009 | if (!nents) |
1010 | goto put_pages; | |
b60503ba | 1011 | |
7fc3cdab MW |
1012 | kfree(pages); |
1013 | *sgp = sg; | |
1014 | return nents; | |
b60503ba | 1015 | |
7fc3cdab MW |
1016 | put_pages: |
1017 | for (i = 0; i < count; i++) | |
1018 | put_page(pages[i]); | |
1019 | kfree(pages); | |
1020 | return err; | |
1021 | } | |
b60503ba | 1022 | |
7fc3cdab MW |
1023 | static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1024 | unsigned long addr, int length, | |
1025 | struct scatterlist *sg, int nents) | |
1026 | { | |
1027 | int i, count; | |
b60503ba | 1028 | |
7fc3cdab | 1029 | count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE); |
36c14ed9 | 1030 | dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE); |
7fc3cdab | 1031 | |
36c14ed9 | 1032 | for (i = 0; i < count; i++) |
7fc3cdab MW |
1033 | put_page(sg_page(&sg[i])); |
1034 | } | |
b60503ba | 1035 | |
7fc3cdab MW |
1036 | static int nvme_submit_user_admin_command(struct nvme_dev *dev, |
1037 | unsigned long addr, unsigned length, | |
1038 | struct nvme_command *cmd) | |
1039 | { | |
b77954cb | 1040 | int err, nents, tmplen = length; |
7fc3cdab | 1041 | struct scatterlist *sg; |
e025344c | 1042 | struct nvme_prps *prps; |
7fc3cdab MW |
1043 | |
1044 | nents = nvme_map_user_pages(dev, 0, addr, length, &sg); | |
1045 | if (nents < 0) | |
1046 | return nents; | |
b77954cb MW |
1047 | prps = nvme_setup_prps(dev, &cmd->common, sg, &tmplen, GFP_KERNEL); |
1048 | if (tmplen != length) | |
1049 | err = -ENOMEM; | |
1050 | else | |
1051 | err = nvme_submit_admin_cmd(dev, cmd, NULL); | |
7fc3cdab | 1052 | nvme_unmap_user_pages(dev, 0, addr, length, sg, nents); |
d567760c | 1053 | nvme_free_prps(dev, prps); |
7fc3cdab | 1054 | return err ? -EIO : 0; |
b60503ba MW |
1055 | } |
1056 | ||
bd38c555 | 1057 | static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns) |
b60503ba | 1058 | { |
b60503ba | 1059 | struct nvme_command c; |
b60503ba | 1060 | |
bd38c555 MW |
1061 | memset(&c, 0, sizeof(c)); |
1062 | c.identify.opcode = nvme_admin_identify; | |
1063 | c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id); | |
1064 | c.identify.cns = cpu_to_le32(cns); | |
1065 | ||
1066 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); | |
1067 | } | |
1068 | ||
1069 | static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr) | |
1070 | { | |
1071 | struct nvme_command c; | |
b60503ba MW |
1072 | |
1073 | memset(&c, 0, sizeof(c)); | |
1074 | c.features.opcode = nvme_admin_get_features; | |
1075 | c.features.nsid = cpu_to_le32(ns->ns_id); | |
b60503ba MW |
1076 | c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); |
1077 | ||
bd38c555 | 1078 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); |
b60503ba MW |
1079 | } |
1080 | ||
a53295b6 MW |
1081 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1082 | { | |
1083 | struct nvme_dev *dev = ns->dev; | |
1084 | struct nvme_queue *nvmeq; | |
1085 | struct nvme_user_io io; | |
1086 | struct nvme_command c; | |
1087 | unsigned length; | |
a53295b6 MW |
1088 | int nents, status; |
1089 | struct scatterlist *sg; | |
e025344c | 1090 | struct nvme_prps *prps; |
a53295b6 MW |
1091 | |
1092 | if (copy_from_user(&io, uio, sizeof(io))) | |
1093 | return -EFAULT; | |
6c7d4945 MW |
1094 | length = (io.nblocks + 1) << ns->lba_shift; |
1095 | ||
1096 | switch (io.opcode) { | |
1097 | case nvme_cmd_write: | |
1098 | case nvme_cmd_read: | |
1099 | nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, | |
1100 | length, &sg); | |
1101 | default: | |
1102 | return -EFAULT; | |
1103 | } | |
1104 | ||
a53295b6 MW |
1105 | if (nents < 0) |
1106 | return nents; | |
1107 | ||
1108 | memset(&c, 0, sizeof(c)); | |
1109 | c.rw.opcode = io.opcode; | |
1110 | c.rw.flags = io.flags; | |
6c7d4945 | 1111 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1112 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1113 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 MW |
1114 | c.rw.control = cpu_to_le16(io.control); |
1115 | c.rw.dsmgmt = cpu_to_le16(io.dsmgmt); | |
6c7d4945 MW |
1116 | c.rw.reftag = io.reftag; |
1117 | c.rw.apptag = io.apptag; | |
1118 | c.rw.appmask = io.appmask; | |
a53295b6 | 1119 | /* XXX: metadata */ |
b77954cb | 1120 | prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL); |
a53295b6 | 1121 | |
d567760c | 1122 | nvmeq = get_nvmeq(ns); |
fa922821 MW |
1123 | /* |
1124 | * Since nvme_submit_sync_cmd sleeps, we can't keep preemption | |
b1ad37ef MW |
1125 | * disabled. We may be preempted at any point, and be rescheduled |
1126 | * to a different CPU. That will cause cacheline bouncing, but no | |
1127 | * additional races since q_lock already protects against other CPUs. | |
1128 | */ | |
a53295b6 | 1129 | put_nvmeq(nvmeq); |
b77954cb MW |
1130 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1131 | status = -ENOMEM; | |
1132 | else | |
1133 | status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT); | |
a53295b6 MW |
1134 | |
1135 | nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents); | |
d567760c | 1136 | nvme_free_prps(dev, prps); |
a53295b6 MW |
1137 | return status; |
1138 | } | |
1139 | ||
6ee44cdc MW |
1140 | static int nvme_download_firmware(struct nvme_ns *ns, |
1141 | struct nvme_dlfw __user *udlfw) | |
1142 | { | |
1143 | struct nvme_dev *dev = ns->dev; | |
1144 | struct nvme_dlfw dlfw; | |
1145 | struct nvme_command c; | |
b77954cb | 1146 | int nents, status, length; |
6ee44cdc | 1147 | struct scatterlist *sg; |
e025344c | 1148 | struct nvme_prps *prps; |
6ee44cdc MW |
1149 | |
1150 | if (copy_from_user(&dlfw, udlfw, sizeof(dlfw))) | |
1151 | return -EFAULT; | |
1152 | if (dlfw.length >= (1 << 30)) | |
1153 | return -EINVAL; | |
b77954cb | 1154 | length = dlfw.length * 4; |
6ee44cdc | 1155 | |
b77954cb | 1156 | nents = nvme_map_user_pages(dev, 1, dlfw.addr, length, &sg); |
6ee44cdc MW |
1157 | if (nents < 0) |
1158 | return nents; | |
1159 | ||
1160 | memset(&c, 0, sizeof(c)); | |
1161 | c.dlfw.opcode = nvme_admin_download_fw; | |
1162 | c.dlfw.numd = cpu_to_le32(dlfw.length); | |
1163 | c.dlfw.offset = cpu_to_le32(dlfw.offset); | |
b77954cb MW |
1164 | prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL); |
1165 | if (length != dlfw.length * 4) | |
1166 | status = -ENOMEM; | |
1167 | else | |
1168 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
6ee44cdc | 1169 | nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents); |
d567760c | 1170 | nvme_free_prps(dev, prps); |
6ee44cdc MW |
1171 | return status; |
1172 | } | |
1173 | ||
1174 | static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg) | |
1175 | { | |
1176 | struct nvme_dev *dev = ns->dev; | |
1177 | struct nvme_command c; | |
1178 | ||
1179 | memset(&c, 0, sizeof(c)); | |
1180 | c.common.opcode = nvme_admin_activate_fw; | |
1181 | c.common.rsvd10[0] = cpu_to_le32(arg); | |
1182 | ||
1183 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
1184 | } | |
1185 | ||
b60503ba MW |
1186 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1187 | unsigned long arg) | |
1188 | { | |
1189 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1190 | ||
1191 | switch (cmd) { | |
1192 | case NVME_IOCTL_IDENTIFY_NS: | |
36c14ed9 | 1193 | return nvme_identify(ns, arg, 0); |
b60503ba | 1194 | case NVME_IOCTL_IDENTIFY_CTRL: |
36c14ed9 | 1195 | return nvme_identify(ns, arg, 1); |
b60503ba | 1196 | case NVME_IOCTL_GET_RANGE_TYPE: |
bd38c555 | 1197 | return nvme_get_range_type(ns, arg); |
a53295b6 MW |
1198 | case NVME_IOCTL_SUBMIT_IO: |
1199 | return nvme_submit_io(ns, (void __user *)arg); | |
6ee44cdc MW |
1200 | case NVME_IOCTL_DOWNLOAD_FW: |
1201 | return nvme_download_firmware(ns, (void __user *)arg); | |
1202 | case NVME_IOCTL_ACTIVATE_FW: | |
1203 | return nvme_activate_firmware(ns, arg); | |
b60503ba MW |
1204 | default: |
1205 | return -ENOTTY; | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | static const struct block_device_operations nvme_fops = { | |
1210 | .owner = THIS_MODULE, | |
1211 | .ioctl = nvme_ioctl, | |
49481682 | 1212 | .compat_ioctl = nvme_ioctl, |
b60503ba MW |
1213 | }; |
1214 | ||
8de05535 MW |
1215 | static void nvme_timeout_ios(struct nvme_queue *nvmeq) |
1216 | { | |
1217 | int depth = nvmeq->q_depth - 1; | |
1218 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
1219 | unsigned long now = jiffies; | |
1220 | int cmdid; | |
1221 | ||
1222 | for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) { | |
1223 | unsigned long data; | |
1224 | void *ptr; | |
1225 | unsigned char handler; | |
1226 | static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, }; | |
1227 | ||
1228 | if (!time_after(now, info[cmdid].timeout)) | |
1229 | continue; | |
1230 | dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid); | |
1231 | data = cancel_cmdid(nvmeq, cmdid); | |
1232 | handler = data & 3; | |
1233 | ptr = (void *)(data & ~3UL); | |
1234 | nvme_completions[handler](nvmeq, ptr, &cqe); | |
1235 | } | |
1236 | } | |
1237 | ||
1fa6aead MW |
1238 | static void nvme_resubmit_bios(struct nvme_queue *nvmeq) |
1239 | { | |
1240 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1241 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1242 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
1243 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
1244 | bio_list_add_head(&nvmeq->sq_cong, bio); | |
1245 | break; | |
1246 | } | |
3cb967c0 MW |
1247 | if (bio_list_empty(&nvmeq->sq_cong)) |
1248 | remove_wait_queue(&nvmeq->sq_full, | |
1249 | &nvmeq->sq_cong_wait); | |
1fa6aead MW |
1250 | } |
1251 | } | |
1252 | ||
1253 | static int nvme_kthread(void *data) | |
1254 | { | |
1255 | struct nvme_dev *dev; | |
1256 | ||
1257 | while (!kthread_should_stop()) { | |
1258 | __set_current_state(TASK_RUNNING); | |
1259 | spin_lock(&dev_list_lock); | |
1260 | list_for_each_entry(dev, &dev_list, node) { | |
1261 | int i; | |
1262 | for (i = 0; i < dev->queue_count; i++) { | |
1263 | struct nvme_queue *nvmeq = dev->queues[i]; | |
740216fc MW |
1264 | if (!nvmeq) |
1265 | continue; | |
1fa6aead MW |
1266 | spin_lock_irq(&nvmeq->q_lock); |
1267 | if (nvme_process_cq(nvmeq)) | |
1268 | printk("process_cq did something\n"); | |
8de05535 | 1269 | nvme_timeout_ios(nvmeq); |
1fa6aead MW |
1270 | nvme_resubmit_bios(nvmeq); |
1271 | spin_unlock_irq(&nvmeq->q_lock); | |
1272 | } | |
1273 | } | |
1274 | spin_unlock(&dev_list_lock); | |
1275 | set_current_state(TASK_INTERRUPTIBLE); | |
1276 | schedule_timeout(HZ); | |
1277 | } | |
1278 | return 0; | |
1279 | } | |
1280 | ||
5aff9382 MW |
1281 | static DEFINE_IDA(nvme_index_ida); |
1282 | ||
1283 | static int nvme_get_ns_idx(void) | |
1284 | { | |
1285 | int index, error; | |
1286 | ||
1287 | do { | |
1288 | if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL)) | |
1289 | return -1; | |
1290 | ||
1291 | spin_lock(&dev_list_lock); | |
1292 | error = ida_get_new(&nvme_index_ida, &index); | |
1293 | spin_unlock(&dev_list_lock); | |
1294 | } while (error == -EAGAIN); | |
1295 | ||
1296 | if (error) | |
1297 | index = -1; | |
1298 | return index; | |
1299 | } | |
1300 | ||
1301 | static void nvme_put_ns_idx(int index) | |
1302 | { | |
1303 | spin_lock(&dev_list_lock); | |
1304 | ida_remove(&nvme_index_ida, index); | |
1305 | spin_unlock(&dev_list_lock); | |
1306 | } | |
1307 | ||
1308 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid, | |
b60503ba MW |
1309 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) |
1310 | { | |
1311 | struct nvme_ns *ns; | |
1312 | struct gendisk *disk; | |
1313 | int lbaf; | |
1314 | ||
1315 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1316 | return NULL; | |
1317 | ||
1318 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1319 | if (!ns) | |
1320 | return NULL; | |
1321 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1322 | if (!ns->queue) | |
1323 | goto out_free_ns; | |
1324 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES | | |
1325 | QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD; | |
1326 | blk_queue_make_request(ns->queue, nvme_make_request); | |
1327 | ns->dev = dev; | |
1328 | ns->queue->queuedata = ns; | |
1329 | ||
1330 | disk = alloc_disk(NVME_MINORS); | |
1331 | if (!disk) | |
1332 | goto out_free_queue; | |
5aff9382 | 1333 | ns->ns_id = nsid; |
b60503ba MW |
1334 | ns->disk = disk; |
1335 | lbaf = id->flbas & 0xf; | |
1336 | ns->lba_shift = id->lbaf[lbaf].ds; | |
1337 | ||
1338 | disk->major = nvme_major; | |
1339 | disk->minors = NVME_MINORS; | |
5aff9382 | 1340 | disk->first_minor = NVME_MINORS * nvme_get_ns_idx(); |
b60503ba MW |
1341 | disk->fops = &nvme_fops; |
1342 | disk->private_data = ns; | |
1343 | disk->queue = ns->queue; | |
388f037f | 1344 | disk->driverfs_dev = &dev->pci_dev->dev; |
5aff9382 | 1345 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba MW |
1346 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); |
1347 | ||
1348 | return ns; | |
1349 | ||
1350 | out_free_queue: | |
1351 | blk_cleanup_queue(ns->queue); | |
1352 | out_free_ns: | |
1353 | kfree(ns); | |
1354 | return NULL; | |
1355 | } | |
1356 | ||
1357 | static void nvme_ns_free(struct nvme_ns *ns) | |
1358 | { | |
5aff9382 | 1359 | int index = ns->disk->first_minor / NVME_MINORS; |
b60503ba | 1360 | put_disk(ns->disk); |
5aff9382 | 1361 | nvme_put_ns_idx(index); |
b60503ba MW |
1362 | blk_cleanup_queue(ns->queue); |
1363 | kfree(ns); | |
1364 | } | |
1365 | ||
b3b06812 | 1366 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1367 | { |
1368 | int status; | |
1369 | u32 result; | |
1370 | struct nvme_command c; | |
b3b06812 | 1371 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba MW |
1372 | |
1373 | memset(&c, 0, sizeof(c)); | |
1374 | c.features.opcode = nvme_admin_get_features; | |
1375 | c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES); | |
1376 | c.features.dword11 = cpu_to_le32(q_count); | |
1377 | ||
1378 | status = nvme_submit_admin_cmd(dev, &c, &result); | |
1379 | if (status) | |
1380 | return -EIO; | |
1381 | return min(result & 0xffff, result >> 16) + 1; | |
1382 | } | |
1383 | ||
b60503ba MW |
1384 | static int __devinit nvme_setup_io_queues(struct nvme_dev *dev) |
1385 | { | |
b348b7d5 | 1386 | int result, cpu, i, nr_io_queues; |
b60503ba | 1387 | |
b348b7d5 MW |
1388 | nr_io_queues = num_online_cpus(); |
1389 | result = set_queue_count(dev, nr_io_queues); | |
1b23484b MW |
1390 | if (result < 0) |
1391 | return result; | |
b348b7d5 MW |
1392 | if (result < nr_io_queues) |
1393 | nr_io_queues = result; | |
b60503ba | 1394 | |
1b23484b MW |
1395 | /* Deregister the admin queue's interrupt */ |
1396 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1397 | ||
b348b7d5 | 1398 | for (i = 0; i < nr_io_queues; i++) |
1b23484b MW |
1399 | dev->entry[i].entry = i; |
1400 | for (;;) { | |
b348b7d5 MW |
1401 | result = pci_enable_msix(dev->pci_dev, dev->entry, |
1402 | nr_io_queues); | |
1b23484b MW |
1403 | if (result == 0) { |
1404 | break; | |
1405 | } else if (result > 0) { | |
b348b7d5 | 1406 | nr_io_queues = result; |
1b23484b MW |
1407 | continue; |
1408 | } else { | |
b348b7d5 | 1409 | nr_io_queues = 1; |
1b23484b MW |
1410 | break; |
1411 | } | |
1412 | } | |
1413 | ||
1414 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
1415 | /* XXX: handle failure here */ | |
1416 | ||
1417 | cpu = cpumask_first(cpu_online_mask); | |
b348b7d5 | 1418 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1419 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); |
1420 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1421 | } | |
1422 | ||
b348b7d5 | 1423 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1424 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, |
1425 | NVME_Q_DEPTH, i); | |
6f0f5449 MW |
1426 | if (IS_ERR(dev->queues[i + 1])) |
1427 | return PTR_ERR(dev->queues[i + 1]); | |
1b23484b MW |
1428 | dev->queue_count++; |
1429 | } | |
b60503ba | 1430 | |
9ecdc946 MW |
1431 | for (; i < num_possible_cpus(); i++) { |
1432 | int target = i % rounddown_pow_of_two(dev->queue_count - 1); | |
1433 | dev->queues[i + 1] = dev->queues[target + 1]; | |
1434 | } | |
1435 | ||
b60503ba MW |
1436 | return 0; |
1437 | } | |
1438 | ||
1439 | static void nvme_free_queues(struct nvme_dev *dev) | |
1440 | { | |
1441 | int i; | |
1442 | ||
1443 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1444 | nvme_free_queue(dev, i); | |
1445 | } | |
1446 | ||
1447 | static int __devinit nvme_dev_add(struct nvme_dev *dev) | |
1448 | { | |
1449 | int res, nn, i; | |
1450 | struct nvme_ns *ns, *next; | |
51814232 | 1451 | struct nvme_id_ctrl *ctrl; |
b60503ba MW |
1452 | void *id; |
1453 | dma_addr_t dma_addr; | |
1454 | struct nvme_command cid, crt; | |
1455 | ||
1456 | res = nvme_setup_io_queues(dev); | |
1457 | if (res) | |
1458 | return res; | |
1459 | ||
1460 | /* XXX: Switch to a SG list once prp2 works */ | |
1461 | id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, | |
1462 | GFP_KERNEL); | |
1463 | ||
1464 | memset(&cid, 0, sizeof(cid)); | |
1465 | cid.identify.opcode = nvme_admin_identify; | |
1466 | cid.identify.nsid = 0; | |
1467 | cid.identify.prp1 = cpu_to_le64(dma_addr); | |
1468 | cid.identify.cns = cpu_to_le32(1); | |
1469 | ||
1470 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1471 | if (res) { | |
1472 | res = -EIO; | |
1473 | goto out_free; | |
1474 | } | |
1475 | ||
51814232 MW |
1476 | ctrl = id; |
1477 | nn = le32_to_cpup(&ctrl->nn); | |
1478 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); | |
1479 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1480 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
b60503ba MW |
1481 | |
1482 | cid.identify.cns = 0; | |
1483 | memset(&crt, 0, sizeof(crt)); | |
1484 | crt.features.opcode = nvme_admin_get_features; | |
1485 | crt.features.prp1 = cpu_to_le64(dma_addr + 4096); | |
1486 | crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); | |
1487 | ||
ac88c36a | 1488 | for (i = 0; i <= nn; i++) { |
b60503ba MW |
1489 | cid.identify.nsid = cpu_to_le32(i); |
1490 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1491 | if (res) | |
1492 | continue; | |
1493 | ||
1494 | if (((struct nvme_id_ns *)id)->ncap == 0) | |
1495 | continue; | |
1496 | ||
1497 | crt.features.nsid = cpu_to_le32(i); | |
1498 | res = nvme_submit_admin_cmd(dev, &crt, NULL); | |
1499 | if (res) | |
1500 | continue; | |
1501 | ||
1502 | ns = nvme_alloc_ns(dev, i, id, id + 4096); | |
1503 | if (ns) | |
1504 | list_add_tail(&ns->list, &dev->namespaces); | |
1505 | } | |
1506 | list_for_each_entry(ns, &dev->namespaces, list) | |
1507 | add_disk(ns->disk); | |
1508 | ||
1509 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1510 | return 0; | |
1511 | ||
1512 | out_free: | |
1513 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1514 | list_del(&ns->list); | |
1515 | nvme_ns_free(ns); | |
1516 | } | |
1517 | ||
1518 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1519 | return res; | |
1520 | } | |
1521 | ||
1522 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1523 | { | |
1524 | struct nvme_ns *ns, *next; | |
1525 | ||
1fa6aead MW |
1526 | spin_lock(&dev_list_lock); |
1527 | list_del(&dev->node); | |
1528 | spin_unlock(&dev_list_lock); | |
1529 | ||
b60503ba MW |
1530 | /* TODO: wait all I/O finished or cancel them */ |
1531 | ||
1532 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1533 | list_del(&ns->list); | |
1534 | del_gendisk(ns->disk); | |
1535 | nvme_ns_free(ns); | |
1536 | } | |
1537 | ||
1538 | nvme_free_queues(dev); | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
091b6092 MW |
1543 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1544 | { | |
1545 | struct device *dmadev = &dev->pci_dev->dev; | |
1546 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
1547 | PAGE_SIZE, PAGE_SIZE, 0); | |
1548 | if (!dev->prp_page_pool) | |
1549 | return -ENOMEM; | |
1550 | ||
99802a7a MW |
1551 | /* Optimisation for I/Os between 4k and 128k */ |
1552 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
1553 | 256, 256, 0); | |
1554 | if (!dev->prp_small_pool) { | |
1555 | dma_pool_destroy(dev->prp_page_pool); | |
1556 | return -ENOMEM; | |
1557 | } | |
091b6092 MW |
1558 | return 0; |
1559 | } | |
1560 | ||
1561 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1562 | { | |
1563 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1564 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1565 | } |
1566 | ||
b60503ba MW |
1567 | /* XXX: Use an ida or something to let remove / add work correctly */ |
1568 | static void nvme_set_instance(struct nvme_dev *dev) | |
1569 | { | |
1570 | static int instance; | |
1571 | dev->instance = instance++; | |
1572 | } | |
1573 | ||
1574 | static void nvme_release_instance(struct nvme_dev *dev) | |
1575 | { | |
1576 | } | |
1577 | ||
1578 | static int __devinit nvme_probe(struct pci_dev *pdev, | |
1579 | const struct pci_device_id *id) | |
1580 | { | |
574e8b95 | 1581 | int bars, result = -ENOMEM; |
b60503ba MW |
1582 | struct nvme_dev *dev; |
1583 | ||
1584 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1585 | if (!dev) | |
1586 | return -ENOMEM; | |
1587 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1588 | GFP_KERNEL); | |
1589 | if (!dev->entry) | |
1590 | goto free; | |
1b23484b MW |
1591 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1592 | GFP_KERNEL); | |
b60503ba MW |
1593 | if (!dev->queues) |
1594 | goto free; | |
1595 | ||
0ee5a7d7 SMM |
1596 | if (pci_enable_device_mem(pdev)) |
1597 | goto free; | |
f64d3365 | 1598 | pci_set_master(pdev); |
574e8b95 MW |
1599 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1600 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1601 | goto disable; | |
0ee5a7d7 | 1602 | |
b60503ba MW |
1603 | INIT_LIST_HEAD(&dev->namespaces); |
1604 | dev->pci_dev = pdev; | |
1605 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1606 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1607 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
b60503ba | 1608 | nvme_set_instance(dev); |
53c9577e | 1609 | dev->entry[0].vector = pdev->irq; |
b60503ba | 1610 | |
091b6092 MW |
1611 | result = nvme_setup_prp_pools(dev); |
1612 | if (result) | |
1613 | goto disable_msix; | |
1614 | ||
b60503ba MW |
1615 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1616 | if (!dev->bar) { | |
1617 | result = -ENOMEM; | |
574e8b95 | 1618 | goto disable_msix; |
b60503ba MW |
1619 | } |
1620 | ||
1621 | result = nvme_configure_admin_queue(dev); | |
1622 | if (result) | |
1623 | goto unmap; | |
1624 | dev->queue_count++; | |
1625 | ||
1fa6aead MW |
1626 | spin_lock(&dev_list_lock); |
1627 | list_add(&dev->node, &dev_list); | |
1628 | spin_unlock(&dev_list_lock); | |
1629 | ||
740216fc MW |
1630 | result = nvme_dev_add(dev); |
1631 | if (result) | |
1632 | goto delete; | |
1633 | ||
b60503ba MW |
1634 | return 0; |
1635 | ||
1636 | delete: | |
740216fc MW |
1637 | spin_lock(&dev_list_lock); |
1638 | list_del(&dev->node); | |
1639 | spin_unlock(&dev_list_lock); | |
1640 | ||
b60503ba MW |
1641 | nvme_free_queues(dev); |
1642 | unmap: | |
1643 | iounmap(dev->bar); | |
574e8b95 | 1644 | disable_msix: |
b60503ba MW |
1645 | pci_disable_msix(pdev); |
1646 | nvme_release_instance(dev); | |
091b6092 | 1647 | nvme_release_prp_pools(dev); |
574e8b95 | 1648 | disable: |
0ee5a7d7 | 1649 | pci_disable_device(pdev); |
574e8b95 | 1650 | pci_release_regions(pdev); |
b60503ba MW |
1651 | free: |
1652 | kfree(dev->queues); | |
1653 | kfree(dev->entry); | |
1654 | kfree(dev); | |
1655 | return result; | |
1656 | } | |
1657 | ||
1658 | static void __devexit nvme_remove(struct pci_dev *pdev) | |
1659 | { | |
1660 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1661 | nvme_dev_remove(dev); | |
1662 | pci_disable_msix(pdev); | |
1663 | iounmap(dev->bar); | |
1664 | nvme_release_instance(dev); | |
091b6092 | 1665 | nvme_release_prp_pools(dev); |
0ee5a7d7 | 1666 | pci_disable_device(pdev); |
574e8b95 | 1667 | pci_release_regions(pdev); |
b60503ba MW |
1668 | kfree(dev->queues); |
1669 | kfree(dev->entry); | |
1670 | kfree(dev); | |
1671 | } | |
1672 | ||
1673 | /* These functions are yet to be implemented */ | |
1674 | #define nvme_error_detected NULL | |
1675 | #define nvme_dump_registers NULL | |
1676 | #define nvme_link_reset NULL | |
1677 | #define nvme_slot_reset NULL | |
1678 | #define nvme_error_resume NULL | |
1679 | #define nvme_suspend NULL | |
1680 | #define nvme_resume NULL | |
1681 | ||
1682 | static struct pci_error_handlers nvme_err_handler = { | |
1683 | .error_detected = nvme_error_detected, | |
1684 | .mmio_enabled = nvme_dump_registers, | |
1685 | .link_reset = nvme_link_reset, | |
1686 | .slot_reset = nvme_slot_reset, | |
1687 | .resume = nvme_error_resume, | |
1688 | }; | |
1689 | ||
1690 | /* Move to pci_ids.h later */ | |
1691 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1692 | ||
1693 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1694 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1695 | { 0, } | |
1696 | }; | |
1697 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1698 | ||
1699 | static struct pci_driver nvme_driver = { | |
1700 | .name = "nvme", | |
1701 | .id_table = nvme_id_table, | |
1702 | .probe = nvme_probe, | |
1703 | .remove = __devexit_p(nvme_remove), | |
1704 | .suspend = nvme_suspend, | |
1705 | .resume = nvme_resume, | |
1706 | .err_handler = &nvme_err_handler, | |
1707 | }; | |
1708 | ||
1709 | static int __init nvme_init(void) | |
1710 | { | |
1fa6aead MW |
1711 | int result = -EBUSY; |
1712 | ||
1713 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1714 | if (IS_ERR(nvme_thread)) | |
1715 | return PTR_ERR(nvme_thread); | |
b60503ba MW |
1716 | |
1717 | nvme_major = register_blkdev(nvme_major, "nvme"); | |
1718 | if (nvme_major <= 0) | |
1fa6aead | 1719 | goto kill_kthread; |
b60503ba MW |
1720 | |
1721 | result = pci_register_driver(&nvme_driver); | |
1fa6aead MW |
1722 | if (result) |
1723 | goto unregister_blkdev; | |
1724 | return 0; | |
b60503ba | 1725 | |
1fa6aead | 1726 | unregister_blkdev: |
b60503ba | 1727 | unregister_blkdev(nvme_major, "nvme"); |
1fa6aead MW |
1728 | kill_kthread: |
1729 | kthread_stop(nvme_thread); | |
b60503ba MW |
1730 | return result; |
1731 | } | |
1732 | ||
1733 | static void __exit nvme_exit(void) | |
1734 | { | |
1735 | pci_unregister_driver(&nvme_driver); | |
1736 | unregister_blkdev(nvme_major, "nvme"); | |
1fa6aead | 1737 | kthread_stop(nvme_thread); |
b60503ba MW |
1738 | } |
1739 | ||
1740 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1741 | MODULE_LICENSE("GPL"); | |
be5e0948 | 1742 | MODULE_VERSION("0.6"); |
b60503ba MW |
1743 | module_init(nvme_init); |
1744 | module_exit(nvme_exit); |