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74489a91 GL |
1 | /* |
2 | * Xilinx SystemACE device driver | |
3 | * | |
4 | * Copyright 2007 Secret Lab Technologies Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * The SystemACE chip is designed to configure FPGAs by loading an FPGA | |
13 | * bitstream from a file on a CF card and squirting it into FPGAs connected | |
14 | * to the SystemACE JTAG chain. It also has the advantage of providing an | |
15 | * MPU interface which can be used to control the FPGA configuration process | |
16 | * and to use the attached CF card for general purpose storage. | |
17 | * | |
18 | * This driver is a block device driver for the SystemACE. | |
19 | * | |
20 | * Initialization: | |
21 | * The driver registers itself as a platform_device driver at module | |
22 | * load time. The platform bus will take care of calling the | |
23 | * ace_probe() method for all SystemACE instances in the system. Any | |
24 | * number of SystemACE instances are supported. ace_probe() calls | |
25 | * ace_setup() which initialized all data structures, reads the CF | |
26 | * id structure and registers the device. | |
27 | * | |
28 | * Processing: | |
29 | * Just about all of the heavy lifting in this driver is performed by | |
30 | * a Finite State Machine (FSM). The driver needs to wait on a number | |
31 | * of events; some raised by interrupts, some which need to be polled | |
32 | * for. Describing all of the behaviour in a FSM seems to be the | |
33 | * easiest way to keep the complexity low and make it easy to | |
34 | * understand what the driver is doing. If the block ops or the | |
35 | * request function need to interact with the hardware, then they | |
36 | * simply need to flag the request and kick of FSM processing. | |
37 | * | |
38 | * The FSM itself is atomic-safe code which can be run from any | |
39 | * context. The general process flow is: | |
40 | * 1. obtain the ace->lock spinlock. | |
41 | * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is | |
42 | * cleared. | |
43 | * 3. release the lock. | |
44 | * | |
45 | * Individual states do not sleep in any way. If a condition needs to | |
46 | * be waited for then the state much clear the fsm_continue flag and | |
47 | * either schedule the FSM to be run again at a later time, or expect | |
48 | * an interrupt to call the FSM when the desired condition is met. | |
49 | * | |
50 | * In normal operation, the FSM is processed at interrupt context | |
51 | * either when the driver's tasklet is scheduled, or when an irq is | |
52 | * raised by the hardware. The tasklet can be scheduled at any time. | |
53 | * The request method in particular schedules the tasklet when a new | |
54 | * request has been indicated by the block layer. Once started, the | |
55 | * FSM proceeds as far as it can processing the request until it | |
56 | * needs on a hardware event. At this point, it must yield execution. | |
57 | * | |
58 | * A state has two options when yielding execution: | |
59 | * 1. ace_fsm_yield() | |
60 | * - Call if need to poll for event. | |
61 | * - clears the fsm_continue flag to exit the processing loop | |
62 | * - reschedules the tasklet to run again as soon as possible | |
63 | * 2. ace_fsm_yieldirq() | |
64 | * - Call if an irq is expected from the HW | |
65 | * - clears the fsm_continue flag to exit the processing loop | |
66 | * - does not reschedule the tasklet so the FSM will not be processed | |
67 | * again until an irq is received. | |
68 | * After calling a yield function, the state must return control back | |
69 | * to the FSM main loop. | |
70 | * | |
71 | * Additionally, the driver maintains a kernel timer which can process | |
72 | * the FSM. If the FSM gets stalled, typically due to a missed | |
73 | * interrupt, then the kernel timer will expire and the driver can | |
74 | * continue where it left off. | |
75 | * | |
76 | * To Do: | |
77 | * - Add FPGA configuration control interface. | |
78 | * - Request major number from lanana | |
79 | */ | |
80 | ||
81 | #undef DEBUG | |
82 | ||
83 | #include <linux/module.h> | |
84 | #include <linux/ctype.h> | |
85 | #include <linux/init.h> | |
86 | #include <linux/interrupt.h> | |
87 | #include <linux/errno.h> | |
88 | #include <linux/kernel.h> | |
89 | #include <linux/delay.h> | |
90 | #include <linux/slab.h> | |
91 | #include <linux/blkdev.h> | |
92 | #include <linux/hdreg.h> | |
93 | #include <linux/platform_device.h> | |
94 | ||
95 | MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); | |
96 | MODULE_DESCRIPTION("Xilinx SystemACE device driver"); | |
97 | MODULE_LICENSE("GPL"); | |
98 | ||
99 | /* SystemACE register definitions */ | |
100 | #define ACE_BUSMODE (0x00) | |
101 | ||
102 | #define ACE_STATUS (0x04) | |
103 | #define ACE_STATUS_CFGLOCK (0x00000001) | |
104 | #define ACE_STATUS_MPULOCK (0x00000002) | |
105 | #define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */ | |
106 | #define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */ | |
107 | #define ACE_STATUS_CFDETECT (0x00000010) | |
108 | #define ACE_STATUS_DATABUFRDY (0x00000020) | |
109 | #define ACE_STATUS_DATABUFMODE (0x00000040) | |
110 | #define ACE_STATUS_CFGDONE (0x00000080) | |
111 | #define ACE_STATUS_RDYFORCFCMD (0x00000100) | |
112 | #define ACE_STATUS_CFGMODEPIN (0x00000200) | |
113 | #define ACE_STATUS_CFGADDR_MASK (0x0000e000) | |
114 | #define ACE_STATUS_CFBSY (0x00020000) | |
115 | #define ACE_STATUS_CFRDY (0x00040000) | |
116 | #define ACE_STATUS_CFDWF (0x00080000) | |
117 | #define ACE_STATUS_CFDSC (0x00100000) | |
118 | #define ACE_STATUS_CFDRQ (0x00200000) | |
119 | #define ACE_STATUS_CFCORR (0x00400000) | |
120 | #define ACE_STATUS_CFERR (0x00800000) | |
121 | ||
122 | #define ACE_ERROR (0x08) | |
123 | #define ACE_CFGLBA (0x0c) | |
124 | #define ACE_MPULBA (0x10) | |
125 | ||
126 | #define ACE_SECCNTCMD (0x14) | |
127 | #define ACE_SECCNTCMD_RESET (0x0100) | |
128 | #define ACE_SECCNTCMD_IDENTIFY (0x0200) | |
129 | #define ACE_SECCNTCMD_READ_DATA (0x0300) | |
130 | #define ACE_SECCNTCMD_WRITE_DATA (0x0400) | |
131 | #define ACE_SECCNTCMD_ABORT (0x0600) | |
132 | ||
133 | #define ACE_VERSION (0x16) | |
134 | #define ACE_VERSION_REVISION_MASK (0x00FF) | |
135 | #define ACE_VERSION_MINOR_MASK (0x0F00) | |
136 | #define ACE_VERSION_MAJOR_MASK (0xF000) | |
137 | ||
138 | #define ACE_CTRL (0x18) | |
139 | #define ACE_CTRL_FORCELOCKREQ (0x0001) | |
140 | #define ACE_CTRL_LOCKREQ (0x0002) | |
141 | #define ACE_CTRL_FORCECFGADDR (0x0004) | |
142 | #define ACE_CTRL_FORCECFGMODE (0x0008) | |
143 | #define ACE_CTRL_CFGMODE (0x0010) | |
144 | #define ACE_CTRL_CFGSTART (0x0020) | |
145 | #define ACE_CTRL_CFGSEL (0x0040) | |
146 | #define ACE_CTRL_CFGRESET (0x0080) | |
147 | #define ACE_CTRL_DATABUFRDYIRQ (0x0100) | |
148 | #define ACE_CTRL_ERRORIRQ (0x0200) | |
149 | #define ACE_CTRL_CFGDONEIRQ (0x0400) | |
150 | #define ACE_CTRL_RESETIRQ (0x0800) | |
151 | #define ACE_CTRL_CFGPROG (0x1000) | |
152 | #define ACE_CTRL_CFGADDR_MASK (0xe000) | |
153 | ||
154 | #define ACE_FATSTAT (0x1c) | |
155 | ||
156 | #define ACE_NUM_MINORS 16 | |
157 | #define ACE_SECTOR_SIZE (512) | |
158 | #define ACE_FIFO_SIZE (32) | |
159 | #define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE) | |
160 | ||
4a24d861 GL |
161 | #define ACE_BUS_WIDTH_8 0 |
162 | #define ACE_BUS_WIDTH_16 1 | |
163 | ||
74489a91 GL |
164 | struct ace_reg_ops; |
165 | ||
166 | struct ace_device { | |
167 | /* driver state data */ | |
168 | int id; | |
169 | int media_change; | |
170 | int users; | |
171 | struct list_head list; | |
172 | ||
173 | /* finite state machine data */ | |
174 | struct tasklet_struct fsm_tasklet; | |
175 | uint fsm_task; /* Current activity (ACE_TASK_*) */ | |
176 | uint fsm_state; /* Current state (ACE_FSM_STATE_*) */ | |
177 | uint fsm_continue_flag; /* cleared to exit FSM mainloop */ | |
178 | uint fsm_iter_num; | |
179 | struct timer_list stall_timer; | |
180 | ||
181 | /* Transfer state/result, use for both id and block request */ | |
182 | struct request *req; /* request being processed */ | |
183 | void *data_ptr; /* pointer to I/O buffer */ | |
184 | int data_count; /* number of buffers remaining */ | |
185 | int data_result; /* Result of transfer; 0 := success */ | |
186 | ||
187 | int id_req_count; /* count of id requests */ | |
188 | int id_result; | |
189 | struct completion id_completion; /* used when id req finishes */ | |
190 | int in_irq; | |
191 | ||
192 | /* Details of hardware device */ | |
193 | unsigned long physaddr; | |
194 | void *baseaddr; | |
195 | int irq; | |
196 | int bus_width; /* 0 := 8 bit; 1 := 16 bit */ | |
197 | struct ace_reg_ops *reg_ops; | |
198 | int lock_count; | |
199 | ||
200 | /* Block device data structures */ | |
201 | spinlock_t lock; | |
202 | struct device *dev; | |
203 | struct request_queue *queue; | |
204 | struct gendisk *gd; | |
205 | ||
206 | /* Inserted CF card parameters */ | |
207 | struct hd_driveid cf_id; | |
208 | }; | |
209 | ||
210 | static int ace_major; | |
211 | ||
212 | /* --------------------------------------------------------------------- | |
213 | * Low level register access | |
214 | */ | |
215 | ||
216 | struct ace_reg_ops { | |
217 | u16(*in) (struct ace_device * ace, int reg); | |
218 | void (*out) (struct ace_device * ace, int reg, u16 val); | |
219 | void (*datain) (struct ace_device * ace); | |
220 | void (*dataout) (struct ace_device * ace); | |
221 | }; | |
222 | ||
223 | /* 8 Bit bus width */ | |
224 | static u16 ace_in_8(struct ace_device *ace, int reg) | |
225 | { | |
226 | void *r = ace->baseaddr + reg; | |
227 | return in_8(r) | (in_8(r + 1) << 8); | |
228 | } | |
229 | ||
230 | static void ace_out_8(struct ace_device *ace, int reg, u16 val) | |
231 | { | |
232 | void *r = ace->baseaddr + reg; | |
233 | out_8(r, val); | |
234 | out_8(r + 1, val >> 8); | |
235 | } | |
236 | ||
237 | static void ace_datain_8(struct ace_device *ace) | |
238 | { | |
239 | void *r = ace->baseaddr + 0x40; | |
240 | u8 *dst = ace->data_ptr; | |
241 | int i = ACE_FIFO_SIZE; | |
242 | while (i--) | |
243 | *dst++ = in_8(r++); | |
244 | ace->data_ptr = dst; | |
245 | } | |
246 | ||
247 | static void ace_dataout_8(struct ace_device *ace) | |
248 | { | |
249 | void *r = ace->baseaddr + 0x40; | |
250 | u8 *src = ace->data_ptr; | |
251 | int i = ACE_FIFO_SIZE; | |
252 | while (i--) | |
253 | out_8(r++, *src++); | |
254 | ace->data_ptr = src; | |
255 | } | |
256 | ||
257 | static struct ace_reg_ops ace_reg_8_ops = { | |
258 | .in = ace_in_8, | |
259 | .out = ace_out_8, | |
260 | .datain = ace_datain_8, | |
261 | .dataout = ace_dataout_8, | |
262 | }; | |
263 | ||
264 | /* 16 bit big endian bus attachment */ | |
265 | static u16 ace_in_be16(struct ace_device *ace, int reg) | |
266 | { | |
267 | return in_be16(ace->baseaddr + reg); | |
268 | } | |
269 | ||
270 | static void ace_out_be16(struct ace_device *ace, int reg, u16 val) | |
271 | { | |
272 | out_be16(ace->baseaddr + reg, val); | |
273 | } | |
274 | ||
275 | static void ace_datain_be16(struct ace_device *ace) | |
276 | { | |
277 | int i = ACE_FIFO_SIZE / 2; | |
278 | u16 *dst = ace->data_ptr; | |
279 | while (i--) | |
280 | *dst++ = in_le16(ace->baseaddr + 0x40); | |
281 | ace->data_ptr = dst; | |
282 | } | |
283 | ||
284 | static void ace_dataout_be16(struct ace_device *ace) | |
285 | { | |
286 | int i = ACE_FIFO_SIZE / 2; | |
287 | u16 *src = ace->data_ptr; | |
288 | while (i--) | |
289 | out_le16(ace->baseaddr + 0x40, *src++); | |
290 | ace->data_ptr = src; | |
291 | } | |
292 | ||
293 | /* 16 bit little endian bus attachment */ | |
294 | static u16 ace_in_le16(struct ace_device *ace, int reg) | |
295 | { | |
296 | return in_le16(ace->baseaddr + reg); | |
297 | } | |
298 | ||
299 | static void ace_out_le16(struct ace_device *ace, int reg, u16 val) | |
300 | { | |
301 | out_le16(ace->baseaddr + reg, val); | |
302 | } | |
303 | ||
304 | static void ace_datain_le16(struct ace_device *ace) | |
305 | { | |
306 | int i = ACE_FIFO_SIZE / 2; | |
307 | u16 *dst = ace->data_ptr; | |
308 | while (i--) | |
309 | *dst++ = in_be16(ace->baseaddr + 0x40); | |
310 | ace->data_ptr = dst; | |
311 | } | |
312 | ||
313 | static void ace_dataout_le16(struct ace_device *ace) | |
314 | { | |
315 | int i = ACE_FIFO_SIZE / 2; | |
316 | u16 *src = ace->data_ptr; | |
317 | while (i--) | |
318 | out_be16(ace->baseaddr + 0x40, *src++); | |
319 | ace->data_ptr = src; | |
320 | } | |
321 | ||
322 | static struct ace_reg_ops ace_reg_be16_ops = { | |
323 | .in = ace_in_be16, | |
324 | .out = ace_out_be16, | |
325 | .datain = ace_datain_be16, | |
326 | .dataout = ace_dataout_be16, | |
327 | }; | |
328 | ||
329 | static struct ace_reg_ops ace_reg_le16_ops = { | |
330 | .in = ace_in_le16, | |
331 | .out = ace_out_le16, | |
332 | .datain = ace_datain_le16, | |
333 | .dataout = ace_dataout_le16, | |
334 | }; | |
335 | ||
336 | static inline u16 ace_in(struct ace_device *ace, int reg) | |
337 | { | |
338 | return ace->reg_ops->in(ace, reg); | |
339 | } | |
340 | ||
341 | static inline u32 ace_in32(struct ace_device *ace, int reg) | |
342 | { | |
343 | return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16); | |
344 | } | |
345 | ||
346 | static inline void ace_out(struct ace_device *ace, int reg, u16 val) | |
347 | { | |
348 | ace->reg_ops->out(ace, reg, val); | |
349 | } | |
350 | ||
351 | static inline void ace_out32(struct ace_device *ace, int reg, u32 val) | |
352 | { | |
353 | ace_out(ace, reg, val); | |
354 | ace_out(ace, reg + 2, val >> 16); | |
355 | } | |
356 | ||
357 | /* --------------------------------------------------------------------- | |
358 | * Debug support functions | |
359 | */ | |
360 | ||
361 | #if defined(DEBUG) | |
362 | static void ace_dump_mem(void *base, int len) | |
363 | { | |
364 | const char *ptr = base; | |
365 | int i, j; | |
366 | ||
367 | for (i = 0; i < len; i += 16) { | |
368 | printk(KERN_INFO "%.8x:", i); | |
369 | for (j = 0; j < 16; j++) { | |
370 | if (!(j % 4)) | |
371 | printk(" "); | |
372 | printk("%.2x", ptr[i + j]); | |
373 | } | |
374 | printk(" "); | |
375 | for (j = 0; j < 16; j++) | |
376 | printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.'); | |
377 | printk("\n"); | |
378 | } | |
379 | } | |
380 | #else | |
381 | static inline void ace_dump_mem(void *base, int len) | |
382 | { | |
383 | } | |
384 | #endif | |
385 | ||
386 | static void ace_dump_regs(struct ace_device *ace) | |
387 | { | |
388 | dev_info(ace->dev, " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n" | |
389 | " status:%.8x mpu_lba:%.8x busmode:%4x\n" | |
390 | " error: %.8x cfg_lba:%.8x fatstat:%.4x\n", | |
391 | ace_in32(ace, ACE_CTRL), | |
392 | ace_in(ace, ACE_SECCNTCMD), | |
393 | ace_in(ace, ACE_VERSION), | |
394 | ace_in32(ace, ACE_STATUS), | |
395 | ace_in32(ace, ACE_MPULBA), | |
396 | ace_in(ace, ACE_BUSMODE), | |
397 | ace_in32(ace, ACE_ERROR), | |
398 | ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT)); | |
399 | } | |
400 | ||
401 | void ace_fix_driveid(struct hd_driveid *id) | |
402 | { | |
403 | #if defined(__BIG_ENDIAN) | |
404 | u16 *buf = (void *)id; | |
405 | int i; | |
406 | ||
407 | /* All half words have wrong byte order; swap the bytes */ | |
408 | for (i = 0; i < sizeof(struct hd_driveid); i += 2, buf++) | |
409 | *buf = le16_to_cpu(*buf); | |
410 | ||
411 | /* Some of the data values are 32bit; swap the half words */ | |
412 | id->lba_capacity = ((id->lba_capacity >> 16) & 0x0000FFFF) | | |
413 | ((id->lba_capacity << 16) & 0xFFFF0000); | |
414 | id->spg = ((id->spg >> 16) & 0x0000FFFF) | | |
415 | ((id->spg << 16) & 0xFFFF0000); | |
416 | #endif | |
417 | } | |
418 | ||
419 | /* --------------------------------------------------------------------- | |
420 | * Finite State Machine (FSM) implementation | |
421 | */ | |
422 | ||
423 | /* FSM tasks; used to direct state transitions */ | |
424 | #define ACE_TASK_IDLE 0 | |
425 | #define ACE_TASK_IDENTIFY 1 | |
426 | #define ACE_TASK_READ 2 | |
427 | #define ACE_TASK_WRITE 3 | |
428 | #define ACE_FSM_NUM_TASKS 4 | |
429 | ||
430 | /* FSM state definitions */ | |
431 | #define ACE_FSM_STATE_IDLE 0 | |
432 | #define ACE_FSM_STATE_REQ_LOCK 1 | |
433 | #define ACE_FSM_STATE_WAIT_LOCK 2 | |
434 | #define ACE_FSM_STATE_WAIT_CFREADY 3 | |
435 | #define ACE_FSM_STATE_IDENTIFY_PREPARE 4 | |
436 | #define ACE_FSM_STATE_IDENTIFY_TRANSFER 5 | |
437 | #define ACE_FSM_STATE_IDENTIFY_COMPLETE 6 | |
438 | #define ACE_FSM_STATE_REQ_PREPARE 7 | |
439 | #define ACE_FSM_STATE_REQ_TRANSFER 8 | |
440 | #define ACE_FSM_STATE_REQ_COMPLETE 9 | |
441 | #define ACE_FSM_STATE_ERROR 10 | |
442 | #define ACE_FSM_NUM_STATES 11 | |
443 | ||
444 | /* Set flag to exit FSM loop and reschedule tasklet */ | |
445 | static inline void ace_fsm_yield(struct ace_device *ace) | |
446 | { | |
447 | dev_dbg(ace->dev, "ace_fsm_yield()\n"); | |
448 | tasklet_schedule(&ace->fsm_tasklet); | |
449 | ace->fsm_continue_flag = 0; | |
450 | } | |
451 | ||
452 | /* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */ | |
453 | static inline void ace_fsm_yieldirq(struct ace_device *ace) | |
454 | { | |
455 | dev_dbg(ace->dev, "ace_fsm_yieldirq()\n"); | |
456 | ||
457 | if (ace->irq == NO_IRQ) | |
458 | /* No IRQ assigned, so need to poll */ | |
459 | tasklet_schedule(&ace->fsm_tasklet); | |
460 | ace->fsm_continue_flag = 0; | |
461 | } | |
462 | ||
463 | /* Get the next read/write request; ending requests that we don't handle */ | |
165125e1 | 464 | struct request *ace_get_next_request(struct request_queue * q) |
74489a91 GL |
465 | { |
466 | struct request *req; | |
467 | ||
468 | while ((req = elv_next_request(q)) != NULL) { | |
469 | if (blk_fs_request(req)) | |
470 | break; | |
471 | end_request(req, 0); | |
472 | } | |
473 | return req; | |
474 | } | |
475 | ||
476 | static void ace_fsm_dostate(struct ace_device *ace) | |
477 | { | |
478 | struct request *req; | |
479 | u32 status; | |
480 | u16 val; | |
481 | int count; | |
482 | int i; | |
483 | ||
484 | #if defined(DEBUG) | |
485 | dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n", | |
486 | ace->fsm_state, ace->id_req_count); | |
487 | #endif | |
488 | ||
489 | switch (ace->fsm_state) { | |
490 | case ACE_FSM_STATE_IDLE: | |
491 | /* See if there is anything to do */ | |
492 | if (ace->id_req_count || ace_get_next_request(ace->queue)) { | |
493 | ace->fsm_iter_num++; | |
494 | ace->fsm_state = ACE_FSM_STATE_REQ_LOCK; | |
495 | mod_timer(&ace->stall_timer, jiffies + HZ); | |
496 | if (!timer_pending(&ace->stall_timer)) | |
497 | add_timer(&ace->stall_timer); | |
498 | break; | |
499 | } | |
500 | del_timer(&ace->stall_timer); | |
501 | ace->fsm_continue_flag = 0; | |
502 | break; | |
503 | ||
504 | case ACE_FSM_STATE_REQ_LOCK: | |
505 | if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { | |
506 | /* Already have the lock, jump to next state */ | |
507 | ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; | |
508 | break; | |
509 | } | |
510 | ||
511 | /* Request the lock */ | |
512 | val = ace_in(ace, ACE_CTRL); | |
513 | ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ); | |
514 | ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK; | |
515 | break; | |
516 | ||
517 | case ACE_FSM_STATE_WAIT_LOCK: | |
518 | if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { | |
519 | /* got the lock; move to next state */ | |
520 | ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; | |
521 | break; | |
522 | } | |
523 | ||
524 | /* wait a bit for the lock */ | |
525 | ace_fsm_yield(ace); | |
526 | break; | |
527 | ||
528 | case ACE_FSM_STATE_WAIT_CFREADY: | |
529 | status = ace_in32(ace, ACE_STATUS); | |
530 | if (!(status & ACE_STATUS_RDYFORCFCMD) || | |
531 | (status & ACE_STATUS_CFBSY)) { | |
532 | /* CF card isn't ready; it needs to be polled */ | |
533 | ace_fsm_yield(ace); | |
534 | break; | |
535 | } | |
536 | ||
537 | /* Device is ready for command; determine what to do next */ | |
538 | if (ace->id_req_count) | |
539 | ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE; | |
540 | else | |
541 | ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE; | |
542 | break; | |
543 | ||
544 | case ACE_FSM_STATE_IDENTIFY_PREPARE: | |
545 | /* Send identify command */ | |
546 | ace->fsm_task = ACE_TASK_IDENTIFY; | |
547 | ace->data_ptr = &ace->cf_id; | |
548 | ace->data_count = ACE_BUF_PER_SECTOR; | |
549 | ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY); | |
550 | ||
551 | /* As per datasheet, put config controller in reset */ | |
552 | val = ace_in(ace, ACE_CTRL); | |
553 | ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); | |
554 | ||
555 | /* irq handler takes over from this point; wait for the | |
556 | * transfer to complete */ | |
557 | ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER; | |
558 | ace_fsm_yieldirq(ace); | |
559 | break; | |
560 | ||
561 | case ACE_FSM_STATE_IDENTIFY_TRANSFER: | |
562 | /* Check that the sysace is ready to receive data */ | |
563 | status = ace_in32(ace, ACE_STATUS); | |
564 | if (status & ACE_STATUS_CFBSY) { | |
565 | dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n", | |
566 | ace->fsm_task, ace->fsm_iter_num, | |
567 | ace->data_count); | |
568 | ace_fsm_yield(ace); | |
569 | break; | |
570 | } | |
571 | if (!(status & ACE_STATUS_DATABUFRDY)) { | |
572 | ace_fsm_yield(ace); | |
573 | break; | |
574 | } | |
575 | ||
576 | /* Transfer the next buffer */ | |
577 | ace->reg_ops->datain(ace); | |
578 | ace->data_count--; | |
579 | ||
580 | /* If there are still buffers to be transfers; jump out here */ | |
581 | if (ace->data_count != 0) { | |
582 | ace_fsm_yieldirq(ace); | |
583 | break; | |
584 | } | |
585 | ||
586 | /* transfer finished; kick state machine */ | |
587 | dev_dbg(ace->dev, "identify finished\n"); | |
588 | ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE; | |
589 | break; | |
590 | ||
591 | case ACE_FSM_STATE_IDENTIFY_COMPLETE: | |
592 | ace_fix_driveid(&ace->cf_id); | |
593 | ace_dump_mem(&ace->cf_id, 512); /* Debug: Dump out disk ID */ | |
594 | ||
595 | if (ace->data_result) { | |
596 | /* Error occured, disable the disk */ | |
597 | ace->media_change = 1; | |
598 | set_capacity(ace->gd, 0); | |
599 | dev_err(ace->dev, "error fetching CF id (%i)\n", | |
600 | ace->data_result); | |
601 | } else { | |
602 | ace->media_change = 0; | |
603 | ||
604 | /* Record disk parameters */ | |
605 | set_capacity(ace->gd, ace->cf_id.lba_capacity); | |
606 | dev_info(ace->dev, "capacity: %i sectors\n", | |
607 | ace->cf_id.lba_capacity); | |
608 | } | |
609 | ||
610 | /* We're done, drop to IDLE state and notify waiters */ | |
611 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
612 | ace->id_result = ace->data_result; | |
613 | while (ace->id_req_count) { | |
614 | complete(&ace->id_completion); | |
615 | ace->id_req_count--; | |
616 | } | |
617 | break; | |
618 | ||
619 | case ACE_FSM_STATE_REQ_PREPARE: | |
620 | req = ace_get_next_request(ace->queue); | |
621 | if (!req) { | |
622 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
623 | break; | |
624 | } | |
625 | ||
626 | /* Okay, it's a data request, set it up for transfer */ | |
627 | dev_dbg(ace->dev, | |
628 | "request: sec=%lx hcnt=%lx, ccnt=%x, dir=%i\n", | |
629 | req->sector, req->hard_nr_sectors, | |
630 | req->current_nr_sectors, rq_data_dir(req)); | |
631 | ||
632 | ace->req = req; | |
633 | ace->data_ptr = req->buffer; | |
634 | ace->data_count = req->current_nr_sectors * ACE_BUF_PER_SECTOR; | |
635 | ace_out32(ace, ACE_MPULBA, req->sector & 0x0FFFFFFF); | |
636 | ||
637 | count = req->hard_nr_sectors; | |
638 | if (rq_data_dir(req)) { | |
639 | /* Kick off write request */ | |
640 | dev_dbg(ace->dev, "write data\n"); | |
641 | ace->fsm_task = ACE_TASK_WRITE; | |
642 | ace_out(ace, ACE_SECCNTCMD, | |
643 | count | ACE_SECCNTCMD_WRITE_DATA); | |
644 | } else { | |
645 | /* Kick off read request */ | |
646 | dev_dbg(ace->dev, "read data\n"); | |
647 | ace->fsm_task = ACE_TASK_READ; | |
648 | ace_out(ace, ACE_SECCNTCMD, | |
649 | count | ACE_SECCNTCMD_READ_DATA); | |
650 | } | |
651 | ||
652 | /* As per datasheet, put config controller in reset */ | |
653 | val = ace_in(ace, ACE_CTRL); | |
654 | ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); | |
655 | ||
656 | /* Move to the transfer state. The systemace will raise | |
657 | * an interrupt once there is something to do | |
658 | */ | |
659 | ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER; | |
660 | if (ace->fsm_task == ACE_TASK_READ) | |
661 | ace_fsm_yieldirq(ace); /* wait for data ready */ | |
662 | break; | |
663 | ||
664 | case ACE_FSM_STATE_REQ_TRANSFER: | |
665 | /* Check that the sysace is ready to receive data */ | |
666 | status = ace_in32(ace, ACE_STATUS); | |
667 | if (status & ACE_STATUS_CFBSY) { | |
668 | dev_dbg(ace->dev, | |
669 | "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n", | |
670 | ace->fsm_task, ace->fsm_iter_num, | |
671 | ace->req->current_nr_sectors * 16, | |
672 | ace->data_count, ace->in_irq); | |
673 | ace_fsm_yield(ace); /* need to poll CFBSY bit */ | |
674 | break; | |
675 | } | |
676 | if (!(status & ACE_STATUS_DATABUFRDY)) { | |
677 | dev_dbg(ace->dev, | |
678 | "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n", | |
679 | ace->fsm_task, ace->fsm_iter_num, | |
680 | ace->req->current_nr_sectors * 16, | |
681 | ace->data_count, ace->in_irq); | |
682 | ace_fsm_yieldirq(ace); | |
683 | break; | |
684 | } | |
685 | ||
686 | /* Transfer the next buffer */ | |
687 | i = 16; | |
688 | if (ace->fsm_task == ACE_TASK_WRITE) | |
689 | ace->reg_ops->dataout(ace); | |
690 | else | |
691 | ace->reg_ops->datain(ace); | |
692 | ace->data_count--; | |
693 | ||
694 | /* If there are still buffers to be transfers; jump out here */ | |
695 | if (ace->data_count != 0) { | |
696 | ace_fsm_yieldirq(ace); | |
697 | break; | |
698 | } | |
699 | ||
700 | /* bio finished; is there another one? */ | |
701 | i = ace->req->current_nr_sectors; | |
702 | if (end_that_request_first(ace->req, 1, i)) { | |
703 | /* dev_dbg(ace->dev, "next block; h=%li c=%i\n", | |
704 | * ace->req->hard_nr_sectors, | |
705 | * ace->req->current_nr_sectors); | |
706 | */ | |
707 | ace->data_ptr = ace->req->buffer; | |
708 | ace->data_count = ace->req->current_nr_sectors * 16; | |
709 | ace_fsm_yieldirq(ace); | |
710 | break; | |
711 | } | |
712 | ||
713 | ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE; | |
714 | break; | |
715 | ||
716 | case ACE_FSM_STATE_REQ_COMPLETE: | |
717 | /* Complete the block request */ | |
718 | blkdev_dequeue_request(ace->req); | |
719 | end_that_request_last(ace->req, 1); | |
720 | ace->req = NULL; | |
721 | ||
722 | /* Finished request; go to idle state */ | |
723 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
724 | break; | |
725 | ||
726 | default: | |
727 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
728 | break; | |
729 | } | |
730 | } | |
731 | ||
732 | static void ace_fsm_tasklet(unsigned long data) | |
733 | { | |
734 | struct ace_device *ace = (void *)data; | |
735 | unsigned long flags; | |
736 | ||
737 | spin_lock_irqsave(&ace->lock, flags); | |
738 | ||
739 | /* Loop over state machine until told to stop */ | |
740 | ace->fsm_continue_flag = 1; | |
741 | while (ace->fsm_continue_flag) | |
742 | ace_fsm_dostate(ace); | |
743 | ||
744 | spin_unlock_irqrestore(&ace->lock, flags); | |
745 | } | |
746 | ||
747 | static void ace_stall_timer(unsigned long data) | |
748 | { | |
749 | struct ace_device *ace = (void *)data; | |
750 | unsigned long flags; | |
751 | ||
752 | dev_warn(ace->dev, | |
753 | "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n", | |
754 | ace->fsm_state, ace->fsm_task, ace->fsm_iter_num, | |
755 | ace->data_count); | |
756 | spin_lock_irqsave(&ace->lock, flags); | |
757 | ||
758 | /* Rearm the stall timer *before* entering FSM (which may then | |
759 | * delete the timer) */ | |
760 | mod_timer(&ace->stall_timer, jiffies + HZ); | |
761 | ||
762 | /* Loop over state machine until told to stop */ | |
763 | ace->fsm_continue_flag = 1; | |
764 | while (ace->fsm_continue_flag) | |
765 | ace_fsm_dostate(ace); | |
766 | ||
767 | spin_unlock_irqrestore(&ace->lock, flags); | |
768 | } | |
769 | ||
770 | /* --------------------------------------------------------------------- | |
771 | * Interrupt handling routines | |
772 | */ | |
773 | static int ace_interrupt_checkstate(struct ace_device *ace) | |
774 | { | |
775 | u32 sreg = ace_in32(ace, ACE_STATUS); | |
776 | u16 creg = ace_in(ace, ACE_CTRL); | |
777 | ||
778 | /* Check for error occurance */ | |
779 | if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) && | |
780 | (creg & ACE_CTRL_ERRORIRQ)) { | |
781 | dev_err(ace->dev, "transfer failure\n"); | |
782 | ace_dump_regs(ace); | |
783 | return -EIO; | |
784 | } | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static irqreturn_t ace_interrupt(int irq, void *dev_id) | |
790 | { | |
791 | u16 creg; | |
792 | struct ace_device *ace = dev_id; | |
793 | ||
794 | /* be safe and get the lock */ | |
795 | spin_lock(&ace->lock); | |
796 | ace->in_irq = 1; | |
797 | ||
798 | /* clear the interrupt */ | |
799 | creg = ace_in(ace, ACE_CTRL); | |
800 | ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ); | |
801 | ace_out(ace, ACE_CTRL, creg); | |
802 | ||
803 | /* check for IO failures */ | |
804 | if (ace_interrupt_checkstate(ace)) | |
805 | ace->data_result = -EIO; | |
806 | ||
807 | if (ace->fsm_task == 0) { | |
808 | dev_err(ace->dev, | |
809 | "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n", | |
810 | ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL), | |
811 | ace_in(ace, ACE_SECCNTCMD)); | |
812 | dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n", | |
813 | ace->fsm_task, ace->fsm_state, ace->data_count); | |
814 | } | |
815 | ||
816 | /* Loop over state machine until told to stop */ | |
817 | ace->fsm_continue_flag = 1; | |
818 | while (ace->fsm_continue_flag) | |
819 | ace_fsm_dostate(ace); | |
820 | ||
821 | /* done with interrupt; drop the lock */ | |
822 | ace->in_irq = 0; | |
823 | spin_unlock(&ace->lock); | |
824 | ||
825 | return IRQ_HANDLED; | |
826 | } | |
827 | ||
828 | /* --------------------------------------------------------------------- | |
829 | * Block ops | |
830 | */ | |
165125e1 | 831 | static void ace_request(struct request_queue * q) |
74489a91 GL |
832 | { |
833 | struct request *req; | |
834 | struct ace_device *ace; | |
835 | ||
836 | req = ace_get_next_request(q); | |
837 | ||
838 | if (req) { | |
839 | ace = req->rq_disk->private_data; | |
840 | tasklet_schedule(&ace->fsm_tasklet); | |
841 | } | |
842 | } | |
843 | ||
844 | static int ace_media_changed(struct gendisk *gd) | |
845 | { | |
846 | struct ace_device *ace = gd->private_data; | |
847 | dev_dbg(ace->dev, "ace_media_changed(): %i\n", ace->media_change); | |
848 | ||
849 | return ace->media_change; | |
850 | } | |
851 | ||
852 | static int ace_revalidate_disk(struct gendisk *gd) | |
853 | { | |
854 | struct ace_device *ace = gd->private_data; | |
855 | unsigned long flags; | |
856 | ||
857 | dev_dbg(ace->dev, "ace_revalidate_disk()\n"); | |
858 | ||
859 | if (ace->media_change) { | |
860 | dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n"); | |
861 | ||
862 | spin_lock_irqsave(&ace->lock, flags); | |
863 | ace->id_req_count++; | |
864 | spin_unlock_irqrestore(&ace->lock, flags); | |
865 | ||
866 | tasklet_schedule(&ace->fsm_tasklet); | |
867 | wait_for_completion(&ace->id_completion); | |
868 | } | |
869 | ||
870 | dev_dbg(ace->dev, "revalidate complete\n"); | |
871 | return ace->id_result; | |
872 | } | |
873 | ||
874 | static int ace_open(struct inode *inode, struct file *filp) | |
875 | { | |
876 | struct ace_device *ace = inode->i_bdev->bd_disk->private_data; | |
877 | unsigned long flags; | |
878 | ||
879 | dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1); | |
880 | ||
881 | filp->private_data = ace; | |
882 | spin_lock_irqsave(&ace->lock, flags); | |
883 | ace->users++; | |
884 | spin_unlock_irqrestore(&ace->lock, flags); | |
885 | ||
886 | check_disk_change(inode->i_bdev); | |
887 | return 0; | |
888 | } | |
889 | ||
890 | static int ace_release(struct inode *inode, struct file *filp) | |
891 | { | |
892 | struct ace_device *ace = inode->i_bdev->bd_disk->private_data; | |
893 | unsigned long flags; | |
894 | u16 val; | |
895 | ||
896 | dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1); | |
897 | ||
898 | spin_lock_irqsave(&ace->lock, flags); | |
899 | ace->users--; | |
900 | if (ace->users == 0) { | |
901 | val = ace_in(ace, ACE_CTRL); | |
902 | ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ); | |
903 | } | |
904 | spin_unlock_irqrestore(&ace->lock, flags); | |
905 | return 0; | |
906 | } | |
907 | ||
a6b3a93e | 908 | static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo) |
74489a91 | 909 | { |
a6b3a93e | 910 | struct ace_device *ace = bdev->bd_disk->private_data; |
74489a91 | 911 | |
a6b3a93e CH |
912 | dev_dbg(ace->dev, "ace_getgeo()\n"); |
913 | ||
914 | geo->heads = ace->cf_id.heads; | |
915 | geo->sectors = ace->cf_id.sectors; | |
916 | geo->cylinders = ace->cf_id.cyls; | |
917 | ||
918 | return 0; | |
74489a91 GL |
919 | } |
920 | ||
921 | static struct block_device_operations ace_fops = { | |
922 | .owner = THIS_MODULE, | |
923 | .open = ace_open, | |
924 | .release = ace_release, | |
925 | .media_changed = ace_media_changed, | |
926 | .revalidate_disk = ace_revalidate_disk, | |
a6b3a93e | 927 | .getgeo = ace_getgeo, |
74489a91 GL |
928 | }; |
929 | ||
930 | /* -------------------------------------------------------------------- | |
931 | * SystemACE device setup/teardown code | |
932 | */ | |
933 | static int __devinit ace_setup(struct ace_device *ace) | |
934 | { | |
935 | u16 version; | |
936 | u16 val; | |
74489a91 GL |
937 | int rc; |
938 | ||
4a24d861 GL |
939 | dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace); |
940 | dev_dbg(ace->dev, "physaddr=0x%lx irq=%i\n", ace->physaddr, ace->irq); | |
941 | ||
74489a91 GL |
942 | spin_lock_init(&ace->lock); |
943 | init_completion(&ace->id_completion); | |
944 | ||
945 | /* | |
946 | * Map the device | |
947 | */ | |
948 | ace->baseaddr = ioremap(ace->physaddr, 0x80); | |
949 | if (!ace->baseaddr) | |
950 | goto err_ioremap; | |
951 | ||
74489a91 GL |
952 | /* |
953 | * Initialize the state machine tasklet and stall timer | |
954 | */ | |
955 | tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace); | |
956 | setup_timer(&ace->stall_timer, ace_stall_timer, (unsigned long)ace); | |
957 | ||
958 | /* | |
959 | * Initialize the request queue | |
960 | */ | |
961 | ace->queue = blk_init_queue(ace_request, &ace->lock); | |
962 | if (ace->queue == NULL) | |
963 | goto err_blk_initq; | |
964 | blk_queue_hardsect_size(ace->queue, 512); | |
965 | ||
966 | /* | |
967 | * Allocate and initialize GD structure | |
968 | */ | |
969 | ace->gd = alloc_disk(ACE_NUM_MINORS); | |
970 | if (!ace->gd) | |
971 | goto err_alloc_disk; | |
972 | ||
973 | ace->gd->major = ace_major; | |
974 | ace->gd->first_minor = ace->id * ACE_NUM_MINORS; | |
975 | ace->gd->fops = &ace_fops; | |
976 | ace->gd->queue = ace->queue; | |
977 | ace->gd->private_data = ace; | |
978 | snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a'); | |
979 | ||
980 | /* set bus width */ | |
4a24d861 | 981 | if (ace->bus_width == ACE_BUS_WIDTH_16) { |
74489a91 GL |
982 | /* 0x0101 should work regardless of endianess */ |
983 | ace_out_le16(ace, ACE_BUSMODE, 0x0101); | |
984 | ||
985 | /* read it back to determine endianess */ | |
986 | if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001) | |
987 | ace->reg_ops = &ace_reg_le16_ops; | |
988 | else | |
989 | ace->reg_ops = &ace_reg_be16_ops; | |
990 | } else { | |
991 | ace_out_8(ace, ACE_BUSMODE, 0x00); | |
992 | ace->reg_ops = &ace_reg_8_ops; | |
993 | } | |
994 | ||
995 | /* Make sure version register is sane */ | |
996 | version = ace_in(ace, ACE_VERSION); | |
997 | if ((version == 0) || (version == 0xFFFF)) | |
998 | goto err_read; | |
999 | ||
1000 | /* Put sysace in a sane state by clearing most control reg bits */ | |
1001 | ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE | | |
1002 | ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ); | |
1003 | ||
1004 | /* Enable interrupts */ | |
1005 | val = ace_in(ace, ACE_CTRL); | |
1006 | val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ; | |
1007 | ace_out(ace, ACE_CTRL, val); | |
1008 | ||
32f6fff4 GL |
1009 | /* Now we can hook up the irq handler */ |
1010 | if (ace->irq != NO_IRQ) { | |
1011 | rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace); | |
1012 | if (rc) { | |
1013 | /* Failure - fall back to polled mode */ | |
1014 | dev_err(ace->dev, "request_irq failed\n"); | |
1015 | ace->irq = NO_IRQ; | |
1016 | } | |
1017 | } | |
1018 | ||
74489a91 GL |
1019 | /* Print the identification */ |
1020 | dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n", | |
1021 | (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff); | |
1022 | dev_dbg(ace->dev, "physaddr 0x%lx, mapped to 0x%p, irq=%i\n", | |
1023 | ace->physaddr, ace->baseaddr, ace->irq); | |
1024 | ||
1025 | ace->media_change = 1; | |
1026 | ace_revalidate_disk(ace->gd); | |
1027 | ||
1028 | /* Make the sysace device 'live' */ | |
1029 | add_disk(ace->gd); | |
1030 | ||
1031 | return 0; | |
1032 | ||
1033 | err_read: | |
1034 | put_disk(ace->gd); | |
1035 | err_alloc_disk: | |
1036 | blk_cleanup_queue(ace->queue); | |
1037 | err_blk_initq: | |
1038 | iounmap(ace->baseaddr); | |
74489a91 | 1039 | err_ioremap: |
1b455466 | 1040 | dev_info(ace->dev, "xsysace: error initializing device at 0x%lx\n", |
74489a91 GL |
1041 | ace->physaddr); |
1042 | return -ENOMEM; | |
1043 | } | |
1044 | ||
1045 | static void __devexit ace_teardown(struct ace_device *ace) | |
1046 | { | |
1047 | if (ace->gd) { | |
1048 | del_gendisk(ace->gd); | |
1049 | put_disk(ace->gd); | |
1050 | } | |
1051 | ||
1052 | if (ace->queue) | |
1053 | blk_cleanup_queue(ace->queue); | |
1054 | ||
1055 | tasklet_kill(&ace->fsm_tasklet); | |
1056 | ||
1057 | if (ace->irq != NO_IRQ) | |
1058 | free_irq(ace->irq, ace); | |
1059 | ||
1060 | iounmap(ace->baseaddr); | |
1061 | } | |
1062 | ||
1b455466 GL |
1063 | static int __devinit |
1064 | ace_alloc(struct device *dev, int id, unsigned long physaddr, | |
1065 | int irq, int bus_width) | |
74489a91 | 1066 | { |
74489a91 | 1067 | struct ace_device *ace; |
1b455466 GL |
1068 | int rc; |
1069 | dev_dbg(dev, "ace_alloc(%p)\n", dev); | |
74489a91 | 1070 | |
1b455466 GL |
1071 | if (!physaddr) { |
1072 | rc = -ENODEV; | |
1073 | goto err_noreg; | |
1074 | } | |
74489a91 | 1075 | |
1b455466 | 1076 | /* Allocate and initialize the ace device structure */ |
74489a91 | 1077 | ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL); |
1b455466 GL |
1078 | if (!ace) { |
1079 | rc = -ENOMEM; | |
74489a91 | 1080 | goto err_alloc; |
74489a91 GL |
1081 | } |
1082 | ||
1b455466 GL |
1083 | ace->dev = dev; |
1084 | ace->id = id; | |
1085 | ace->physaddr = physaddr; | |
1086 | ace->irq = irq; | |
1087 | ace->bus_width = bus_width; | |
74489a91 | 1088 | |
1b455466 GL |
1089 | /* Call the setup code */ |
1090 | if ((rc = ace_setup(ace)) != 0) | |
74489a91 GL |
1091 | goto err_setup; |
1092 | ||
1b455466 | 1093 | dev_set_drvdata(dev, ace); |
74489a91 GL |
1094 | return 0; |
1095 | ||
1096 | err_setup: | |
1b455466 | 1097 | dev_set_drvdata(dev, NULL); |
74489a91 GL |
1098 | kfree(ace); |
1099 | err_alloc: | |
1b455466 GL |
1100 | err_noreg: |
1101 | dev_err(dev, "could not initialize device, err=%i\n", rc); | |
1102 | return rc; | |
74489a91 GL |
1103 | } |
1104 | ||
1b455466 | 1105 | static void __devexit ace_free(struct device *dev) |
74489a91 | 1106 | { |
1b455466 GL |
1107 | struct ace_device *ace = dev_get_drvdata(dev); |
1108 | dev_dbg(dev, "ace_free(%p)\n", dev); | |
74489a91 GL |
1109 | |
1110 | if (ace) { | |
1111 | ace_teardown(ace); | |
1b455466 | 1112 | dev_set_drvdata(dev, NULL); |
74489a91 GL |
1113 | kfree(ace); |
1114 | } | |
1b455466 GL |
1115 | } |
1116 | ||
1117 | /* --------------------------------------------------------------------- | |
1118 | * Platform Bus Support | |
1119 | */ | |
1120 | ||
1121 | static int __devinit ace_probe(struct platform_device *dev) | |
1122 | { | |
1123 | unsigned long physaddr = 0; | |
4a24d861 | 1124 | int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */ |
1b455466 GL |
1125 | int id = dev->id; |
1126 | int irq = NO_IRQ; | |
1127 | int i; | |
1128 | ||
1129 | dev_dbg(&dev->dev, "ace_probe(%p)\n", dev); | |
1130 | ||
1131 | for (i = 0; i < dev->num_resources; i++) { | |
1132 | if (dev->resource[i].flags & IORESOURCE_MEM) | |
1133 | physaddr = dev->resource[i].start; | |
1134 | if (dev->resource[i].flags & IORESOURCE_IRQ) | |
1135 | irq = dev->resource[i].start; | |
1136 | } | |
1137 | ||
1138 | /* Call the bus-independant setup code */ | |
1139 | return ace_alloc(&dev->dev, id, physaddr, irq, bus_width); | |
1140 | } | |
74489a91 | 1141 | |
1b455466 GL |
1142 | /* |
1143 | * Platform bus remove() method | |
1144 | */ | |
1145 | static int __devexit ace_remove(struct platform_device *dev) | |
1146 | { | |
1147 | ace_free(&dev->dev); | |
74489a91 GL |
1148 | return 0; |
1149 | } | |
1150 | ||
edec4961 | 1151 | static struct platform_driver ace_platform_driver = { |
74489a91 GL |
1152 | .probe = ace_probe, |
1153 | .remove = __devexit_p(ace_remove), | |
edec4961 GL |
1154 | .driver = { |
1155 | .owner = THIS_MODULE, | |
1156 | .name = "xsysace", | |
1157 | }, | |
74489a91 GL |
1158 | }; |
1159 | ||
1160 | /* --------------------------------------------------------------------- | |
1161 | * Module init/exit routines | |
1162 | */ | |
1163 | static int __init ace_init(void) | |
1164 | { | |
edec4961 GL |
1165 | int rc; |
1166 | ||
74489a91 GL |
1167 | ace_major = register_blkdev(ace_major, "xsysace"); |
1168 | if (ace_major <= 0) { | |
edec4961 GL |
1169 | rc = -ENOMEM; |
1170 | goto err_blk; | |
74489a91 GL |
1171 | } |
1172 | ||
4a24d861 | 1173 | pr_debug("xsysace: registering platform binding\n"); |
edec4961 GL |
1174 | if ((rc = platform_driver_register(&ace_platform_driver)) != 0) |
1175 | goto err_plat; | |
1176 | ||
1177 | pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major); | |
1178 | return 0; | |
1179 | ||
1180 | err_plat: | |
1181 | unregister_blkdev(ace_major, "xsysace"); | |
1182 | err_blk: | |
1183 | printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc); | |
1184 | return rc; | |
74489a91 GL |
1185 | } |
1186 | ||
1187 | static void __exit ace_exit(void) | |
1188 | { | |
1189 | pr_debug("Unregistering Xilinx SystemACE driver\n"); | |
edec4961 | 1190 | platform_driver_unregister(&ace_platform_driver); |
c6d4d634 | 1191 | unregister_blkdev(ace_major, "xsysace"); |
74489a91 GL |
1192 | } |
1193 | ||
1194 | module_init(ace_init); | |
1195 | module_exit(ace_exit); |