projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 26a84b3e KVA |
1 | # |
| 2 | # Bus Devices | |
| 3 | # | |
| 4 | ||
| 5 | menu "Bus devices" | |
| 6 | ||
| 13fbf3c8 | 7 | config ARM_CCI |
| 47f36e49 OJ |
8 | bool |
| 9 | ||
| f4d58938 SP |
10 | config ARM_CCI_PMU |
| 11 | bool | |
| 12 | select ARM_CCI | |
| 13 | ||
| 47f36e49 OJ |
14 | config ARM_CCI400_COMMON |
| 15 | bool | |
| 16 | select ARM_CCI | |
| 17 | ||
| 18 | config ARM_CCI400_PMU | |
| 19 | bool "ARM CCI400 PMU support" | |
| 85bbba70 SP |
20 | depends on (ARM && CPU_V7) || ARM64 |
| 21 | depends on PERF_EVENTS | |
| 47f36e49 | 22 | select ARM_CCI400_COMMON |
| f4d58938 | 23 | select ARM_CCI_PMU |
| 47f36e49 | 24 | help |
| 85bbba70 SP |
25 | Support for PMU events monitoring on the ARM CCI-400 (cache coherent |
| 26 | interconnect). CCI-400 supports counting events related to the | |
| 27 | connected slave/master interfaces. | |
| 47f36e49 OJ |
28 | |
| 29 | config ARM_CCI400_PORT_CTRL | |
| 30 | bool | |
| 13fbf3c8 | 31 | depends on ARM && OF && CPU_V7 |
| 47f36e49 | 32 | select ARM_CCI400_COMMON |
| 13fbf3c8 | 33 | help |
| 47f36e49 OJ |
34 | Low level power management driver for CCI400 cache coherent |
| 35 | interconnect for ARM platforms. | |
| 13fbf3c8 | 36 | |
| a95791ef SP |
37 | config ARM_CCI500_PMU |
| 38 | bool "ARM CCI500 PMU support" | |
| 39 | default y | |
| 40 | depends on (ARM && CPU_V7) || ARM64 | |
| 41 | depends on PERF_EVENTS | |
| 42 | select ARM_CCI_PMU | |
| 43 | help | |
| 44 | Support for PMU events monitoring on the ARM CCI-500 cache coherent | |
| 45 | interconnect. CCI-500 provides 8 independent event counters, which | |
| 46 | can count events pertaining to the slave/master interfaces as well | |
| 47 | as the internal events to the CCI. | |
| 48 | ||
| 49 | If unsure, say Y | |
| 50 | ||
| 13fbf3c8 GU |
51 | config ARM_CCN |
| 52 | bool "ARM CCN driver support" | |
| 53 | depends on ARM || ARM64 | |
| 54 | depends on PERF_EVENTS | |
| 55 | help | |
| 56 | PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) | |
| 57 | interconnect. | |
| 58 | ||
| 44127b77 FF |
59 | config BRCMSTB_GISB_ARB |
| 60 | bool "Broadcom STB GISB bus arbiter" | |
| dd1d78a1 | 61 | depends on ARM || MIPS |
| 44127b77 FF |
62 | help |
| 63 | Driver for the Broadcom Set Top Box System-on-a-chip internal bus | |
| 64 | arbiter. This driver provides timeout and target abort error handling | |
| 65 | and internal bus master decoding. | |
| 66 | ||
| 85bf6d4e HS |
67 | config IMX_WEIM |
| 68 | bool "Freescale EIM DRIVER" | |
| 69 | depends on ARCH_MXC | |
| 70 | help | |
| 3f98b6ba | 71 | Driver for i.MX WEIM controller. |
| 85bf6d4e HS |
72 | The WEIM(Wireless External Interface Module) works like a bus. |
| 73 | You can attach many different devices on it, such as NOR, onenand. | |
| 85bf6d4e | 74 | |
| 8286ae03 JH |
75 | config MIPS_CDMM |
| 76 | bool "MIPS Common Device Memory Map (CDMM) Driver" | |
| 77 | depends on CPU_MIPSR2 | |
| 78 | help | |
| 79 | Driver needed for the MIPS Common Device Memory Map bus in MIPS | |
| 80 | cores. This bus is for per-CPU tightly coupled devices such as the | |
| 81 | Fast Debug Channel (FDC). | |
| 82 | ||
| 83 | For this to work, either your bootloader needs to enable the CDMM | |
| 84 | region at an unused physical address on the boot CPU, or else your | |
| 85 | platform code needs to implement mips_cdmm_phys_base() (see | |
| 86 | asm/cdmm.h). | |
| 87 | ||
| fddddb52 TP |
88 | config MVEBU_MBUS |
| 89 | bool | |
| 90 | depends on PLAT_ORION | |
| 91 | help | |
| 92 | Driver needed for the MBus configuration on Marvell EBU SoCs | |
| 93 | (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP). | |
| 94 | ||
| 0ee7261c SS |
95 | config OMAP_INTERCONNECT |
| 96 | tristate "OMAP INTERCONNECT DRIVER" | |
| 97 | depends on ARCH_OMAP2PLUS | |
| 98 | ||
| 99 | help | |
| 100 | Driver to enable OMAP interconnect error handling driver. | |
| ed69bdd8 | 101 | |
| 13fbf3c8 GU |
102 | config OMAP_OCP2SCP |
| 103 | tristate "OMAP OCP2SCP DRIVER" | |
| 104 | depends on ARCH_OMAP2PLUS | |
| ed69bdd8 | 105 | help |
| 13fbf3c8 GU |
106 | Driver to enable ocp2scp module which transforms ocp interface |
| 107 | protocol to scp protocol. In OMAP4, USB PHY is connected via | |
| 108 | OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via | |
| 109 | OCP2SCP. | |
| 3b9334ac | 110 | |
| 89d463ea GU |
111 | config SIMPLE_PM_BUS |
| 112 | bool "Simple Power-Managed Bus Driver" | |
| 113 | depends on OF && PM | |
| 114 | depends on ARCH_SHMOBILE || COMPILE_TEST | |
| a33b0daa | 115 | help |
| 89d463ea GU |
116 | Driver for transparent busses that don't need a real driver, but |
| 117 | where the bus controller is part of a PM domain, or under the control | |
| 118 | of a functional clock, and thus relies on runtime PM for managing | |
| 119 | this PM domain and/or clock. | |
| 120 | An example of such a bus controller is the Renesas Bus State | |
| 121 | Controller (BSC, sometimes called "LBSC within Bus Bridge", or | |
| 122 | "External Bus Interface") as found on several Renesas ARM SoCs. | |
| a33b0daa | 123 | |
| 3b9334ac PM |
124 | config VEXPRESS_CONFIG |
| 125 | bool "Versatile Express configuration bus" | |
| 126 | default y if ARCH_VEXPRESS | |
| 127 | depends on ARM || ARM64 | |
| b33cdd28 | 128 | depends on OF |
| 3b9334ac PM |
129 | select REGMAP |
| 130 | help | |
| 131 | Platform configuration infrastructure for the ARM Ltd. | |
| 132 | Versatile Express. | |
| 26a84b3e | 133 | endmenu |