Commit | Line | Data |
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2722e56d | 1 | /* |
ed0e3520 | 2 | * OMAP4XXX L3 Interconnect error handling driver |
3 | * | |
4 | * Copyright (C) 2011 Texas Corporation | |
5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
6 | * Sricharan <r.sricharan@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
21 | * USA | |
22 | */ | |
d4fc7eb5 | 23 | #include <linux/module.h> |
2722e56d SS |
24 | #include <linux/init.h> |
25 | #include <linux/io.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/slab.h> | |
30 | ||
31 | #include "omap_l3_noc.h" | |
32 | ||
33 | /* | |
34 | * Interrupt Handler for L3 error detection. | |
35 | * 1) Identify the L3 clockdomain partition to which the error belongs to. | |
36 | * 2) Identify the slave where the error information is logged | |
37 | * 3) Print the logged information. | |
38 | * 4) Add dump stack to provide kernel trace. | |
39 | * | |
40 | * Two Types of errors : | |
41 | * 1) Custom errors in L3 : | |
42 | * Target like DMM/FW/EMIF generates SRESP=ERR error | |
43 | * 2) Standard L3 error: | |
44 | * - Unsupported CMD. | |
45 | * L3 tries to access target while it is idle | |
46 | * - OCP disconnect. | |
47 | * - Address hole error: | |
48 | * If DSS/ISS/FDIF/USBHOSTFS access a target where they | |
49 | * do not have connectivity, the error is logged in | |
50 | * their default target which is DMM2. | |
51 | * | |
52 | * On High Secure devices, firewall errors are possible and those | |
53 | * can be trapped as well. But the trapping is implemented as part | |
54 | * secure software and hence need not be implemented here. | |
55 | */ | |
56 | static irqreturn_t l3_interrupt_handler(int irq, void *_l3) | |
57 | { | |
58 | ||
ed0e3520 | 59 | struct omap4_l3 *l3 = _l3; |
551a9fa9 | 60 | int inttype, i, k; |
2722e56d | 61 | int err_src = 0; |
551a9fa9 | 62 | u32 std_err_main, err_reg, clear, masterid; |
6616aac6 | 63 | void __iomem *base, *l3_targ_base; |
551a9fa9 | 64 | char *target_name, *master_name = "UN IDENTIFIED"; |
2722e56d SS |
65 | |
66 | /* Get the Type of interrupt */ | |
35f7b961 | 67 | inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; |
2722e56d SS |
68 | |
69 | for (i = 0; i < L3_MODULES; i++) { | |
70 | /* | |
71 | * Read the regerr register of the clock domain | |
72 | * to determine the source | |
73 | */ | |
6616aac6 | 74 | base = l3->l3_base[i]; |
75 | err_reg = __raw_readl(base + l3_flagmux[i] + | |
342fd144 | 76 | + L3_FLAGMUX_REGERR0 + (inttype << 3)); |
2722e56d SS |
77 | |
78 | /* Get the corresponding error and analyse */ | |
79 | if (err_reg) { | |
80 | /* Identify the source from control status register */ | |
342fd144 | 81 | err_src = __ffs(err_reg); |
2722e56d | 82 | |
2722e56d | 83 | /* Read the stderrlog_main_source from clk domain */ |
342fd144 | 84 | l3_targ_base = base + *(l3_targ[i] + err_src); |
6616aac6 | 85 | std_err_main = __raw_readl(l3_targ_base + |
342fd144 | 86 | L3_TARG_STDERRLOG_MAIN); |
551a9fa9 | 87 | masterid = __raw_readl(l3_targ_base + |
88 | L3_TARG_STDERRLOG_MSTADDR); | |
2722e56d | 89 | |
35f7b961 | 90 | switch (std_err_main & CUSTOM_ERROR) { |
2722e56d | 91 | case STANDARD_ERROR: |
551a9fa9 | 92 | target_name = |
342fd144 | 93 | l3_targ_inst_name[i][err_src]; |
551a9fa9 | 94 | WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n", |
95 | target_name, | |
6616aac6 | 96 | __raw_readl(l3_targ_base + |
342fd144 | 97 | L3_TARG_STDERRLOG_SLVOFSLSB)); |
2722e56d SS |
98 | /* clear the std error log*/ |
99 | clear = std_err_main | CLEAR_STDERR_LOG; | |
342fd144 TP |
100 | writel(clear, l3_targ_base + |
101 | L3_TARG_STDERRLOG_MAIN); | |
2722e56d SS |
102 | break; |
103 | ||
104 | case CUSTOM_ERROR: | |
551a9fa9 | 105 | target_name = |
342fd144 | 106 | l3_targ_inst_name[i][err_src]; |
551a9fa9 | 107 | for (k = 0; k < NUM_OF_L3_MASTERS; k++) { |
108 | if (masterid == l3_masters[k].id) | |
109 | master_name = | |
110 | l3_masters[k].name; | |
111 | } | |
112 | WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n", | |
113 | master_name, target_name); | |
2722e56d SS |
114 | /* clear the std error log*/ |
115 | clear = std_err_main | CLEAR_STDERR_LOG; | |
342fd144 TP |
116 | writel(clear, l3_targ_base + |
117 | L3_TARG_STDERRLOG_MAIN); | |
2722e56d SS |
118 | break; |
119 | ||
120 | default: | |
121 | /* Nothing to be handled here as of now */ | |
122 | break; | |
123 | } | |
124 | /* Error found so break the for loop */ | |
125 | break; | |
126 | } | |
127 | } | |
128 | return IRQ_HANDLED; | |
129 | } | |
130 | ||
0fe763c5 | 131 | static int omap4_l3_probe(struct platform_device *pdev) |
2722e56d | 132 | { |
ed0e3520 | 133 | static struct omap4_l3 *l3; |
56c4a022 | 134 | int ret, i; |
2722e56d | 135 | |
bae74510 | 136 | l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL); |
2722e56d | 137 | if (!l3) |
7529b703 | 138 | return -ENOMEM; |
2722e56d SS |
139 | |
140 | platform_set_drvdata(pdev, l3); | |
2722e56d | 141 | |
56c4a022 PU |
142 | /* Get mem resources */ |
143 | for (i = 0; i < L3_MODULES; i++) { | |
144 | struct resource *res = platform_get_resource(pdev, | |
145 | IORESOURCE_MEM, i); | |
2722e56d | 146 | |
56c4a022 PU |
147 | l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res); |
148 | if (IS_ERR(l3->l3_base[i])) { | |
149 | dev_err(&pdev->dev, "ioremap %d failed\n", i); | |
150 | return PTR_ERR(l3->l3_base[i]); | |
151 | } | |
2722e56d SS |
152 | } |
153 | ||
154 | /* | |
155 | * Setup interrupt Handlers | |
156 | */ | |
c1df2dcc | 157 | l3->debug_irq = platform_get_irq(pdev, 0); |
a0ef78f3 PU |
158 | ret = devm_request_irq(&pdev->dev, l3->debug_irq, l3_interrupt_handler, |
159 | IRQF_DISABLED, "l3-dbg-irq", l3); | |
2722e56d SS |
160 | if (ret) { |
161 | pr_crit("L3: request_irq failed to register for 0x%x\n", | |
2c2d1674 | 162 | l3->debug_irq); |
56c4a022 | 163 | return ret; |
2722e56d | 164 | } |
2722e56d | 165 | |
c1df2dcc | 166 | l3->app_irq = platform_get_irq(pdev, 1); |
a0ef78f3 PU |
167 | ret = devm_request_irq(&pdev->dev, l3->app_irq, l3_interrupt_handler, |
168 | IRQF_DISABLED, "l3-app-irq", l3); | |
169 | if (ret) | |
2722e56d | 170 | pr_crit("L3: request_irq failed to register for 0x%x\n", |
2c2d1674 | 171 | l3->app_irq); |
7529b703 | 172 | |
2722e56d SS |
173 | return ret; |
174 | } | |
175 | ||
d039c5b9 BC |
176 | #if defined(CONFIG_OF) |
177 | static const struct of_device_id l3_noc_match[] = { | |
178 | {.compatible = "ti,omap4-l3-noc", }, | |
179 | {}, | |
8770b07c | 180 | }; |
d039c5b9 BC |
181 | MODULE_DEVICE_TABLE(of, l3_noc_match); |
182 | #else | |
183 | #define l3_noc_match NULL | |
184 | #endif | |
185 | ||
2722e56d | 186 | static struct platform_driver omap4_l3_driver = { |
d039c5b9 | 187 | .probe = omap4_l3_probe, |
d039c5b9 BC |
188 | .driver = { |
189 | .name = "omap_l3_noc", | |
190 | .owner = THIS_MODULE, | |
191 | .of_match_table = l3_noc_match, | |
2722e56d SS |
192 | }, |
193 | }; | |
194 | ||
195 | static int __init omap4_l3_init(void) | |
196 | { | |
d039c5b9 | 197 | return platform_driver_register(&omap4_l3_driver); |
2722e56d SS |
198 | } |
199 | postcore_initcall_sync(omap4_l3_init); | |
200 | ||
201 | static void __exit omap4_l3_exit(void) | |
202 | { | |
203 | platform_driver_unregister(&omap4_l3_driver); | |
204 | } | |
205 | module_exit(omap4_l3_exit); |