[deliverable/linux.git] / drivers / bus / omap_l3_noc.c

/*
 * OMAP L3 Interconnect error handling driver
 *
 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *	Sricharan <r.sricharan@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "omap_l3_noc.h"

/*
 * Interrupt Handler for L3 error detection.
 *	1) Identify the L3 clockdomain partition to which the error belongs to.
 *	2) Identify the slave where the error information is logged
 *	3) Print the logged information.
 *	4) Add dump stack to provide kernel trace.
 *
 * Two Types of errors :
 *	1) Custom errors in L3 :
 *		Target like DMM/FW/EMIF generates SRESP=ERR error
 *	2) Standard L3 error:
 *		- Unsupported CMD.
 *			L3 tries to access target while it is idle
 *		- OCP disconnect.
 *		- Address hole error:
 *			If DSS/ISS/FDIF/USBHOSTFS access a target where they
 *			do not have connectivity, the error is logged in
 *			their default target which is DMM2.
 *
 *	On High Secure devices, firewall errors are possible and those
 *	can be trapped as well. But the trapping is implemented as part
 *	secure software and hence need not be implemented here.
 */
static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
{

	struct omap_l3 *l3 = _l3;
	int inttype, i, k;
	int err_src = 0;
	u32 std_err_main, err_reg, clear, masterid;
	void __iomem *base, *l3_targ_base;
	void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
	char *target_name, *master_name = "UN IDENTIFIED";
	struct l3_target_data *l3_targ_inst;
	struct l3_flagmux_data *flag_mux;
	struct l3_masters_data *master;

	/* Get the Type of interrupt */
	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;

	for (i = 0; i < l3->num_modules; i++) {
		/*
		 * Read the regerr register of the clock domain
		 * to determine the source
		 */
		base = l3->l3_base[i];
		flag_mux = l3->l3_flagmux[i];
		err_reg = readl_relaxed(base + flag_mux->offset +
					L3_FLAGMUX_REGERR0 + (inttype << 3));

		/* Get the corresponding error and analyse */
		if (err_reg) {
			/* Identify the source from control status register */
			err_src = __ffs(err_reg);

			/* We DONOT expect err_src to go out of bounds */
			BUG_ON(err_src > MAX_CLKDM_TARGETS);

			if (err_src < flag_mux->num_targ_data) {
				l3_targ_inst = &flag_mux->l3_targ[err_src];
				target_name = l3_targ_inst->name;
				l3_targ_base = base + l3_targ_inst->offset;
			} else {
				target_name = L3_TARGET_NOT_SUPPORTED;
			}

			/*
			 * If we do not know of a register offset to decode
			 * and clear, then mask.
			 */
			if (target_name == L3_TARGET_NOT_SUPPORTED) {
				u32 mask_val;
				void __iomem *mask_reg;

				/*
				 * Certain plaforms may have "undocumented"
				 * status pending on boot.. So dont generate
				 * a severe warning here.
				 */
				dev_err(l3->dev,
					"L3 %s error: target %d mod:%d %s\n",
					inttype ? "debug" : "application",
					err_src, i, "(unclearable)");

				mask_reg = base + flag_mux->offset +
					   L3_FLAGMUX_MASK0 + (inttype << 3);
				mask_val = readl_relaxed(mask_reg);
				mask_val &= ~(1 << err_src);
				writel_relaxed(mask_val, mask_reg);

				break;
			}

			/* Read the stderrlog_main_source from clk domain */
			l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
			l3_targ_slvofslsb = l3_targ_base +
					    L3_TARG_STDERRLOG_SLVOFSLSB;
			l3_targ_mstaddr = l3_targ_base +
					  L3_TARG_STDERRLOG_MSTADDR;

			std_err_main = readl_relaxed(l3_targ_stderr);

			/* STDERRLOG_MSTADDR Stores the NTTP master address. */
			masterid = (readl_relaxed(l3_targ_mstaddr) &
				    l3->mst_addr_mask) >>
					__ffs(l3->mst_addr_mask);

			switch (std_err_main & CUSTOM_ERROR) {
			case STANDARD_ERROR:
				WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
					target_name,
					readl_relaxed(l3_targ_slvofslsb));
				/* clear the std error log*/
				clear = std_err_main | CLEAR_STDERR_LOG;
				writel_relaxed(clear, l3_targ_stderr);
				break;

			case CUSTOM_ERROR:
				for (k = 0, master = l3->l3_masters;
				     k < l3->num_masters; k++, master++) {
					if (masterid == master->id) {
						master_name = master->name;
						break;
					}
				}
				WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
					master_name, target_name);
				/* clear the std error log*/
				clear = std_err_main | CLEAR_STDERR_LOG;
				writel_relaxed(clear, l3_targ_stderr);
				break;

			default:
				/* Nothing to be handled here as of now */
				break;
			}
		/* Error found so break the for loop */
		break;
		}
	}
	return IRQ_HANDLED;
}

static const struct of_device_id l3_noc_match[] = {
	{.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
	{},
};
MODULE_DEVICE_TABLE(of, l3_noc_match);

static int omap_l3_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	static struct omap_l3 *l3;
	int ret, i;

	of_id = of_match_device(l3_noc_match, &pdev->dev);
	if (!of_id) {
		dev_err(&pdev->dev, "OF data missing\n");
		return -EINVAL;
	}

	l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
	if (!l3)
		return -ENOMEM;

	memcpy(l3, of_id->data, sizeof(*l3));
	l3->dev = &pdev->dev;
	platform_set_drvdata(pdev, l3);

	/* Get mem resources */
	for (i = 0; i < l3->num_modules; i++) {
		struct resource	*res = platform_get_resource(pdev,
							     IORESOURCE_MEM, i);

		l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(l3->l3_base[i])) {
			dev_err(l3->dev, "ioremap %d failed\n", i);
			return PTR_ERR(l3->l3_base[i]);
		}
	}

	/*
	 * Setup interrupt Handlers
	 */
	l3->debug_irq = platform_get_irq(pdev, 0);
	ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
			       IRQF_DISABLED, "l3-dbg-irq", l3);
	if (ret) {
		dev_err(l3->dev, "request_irq failed for %d\n",
			l3->debug_irq);
		return ret;
	}

	l3->app_irq = platform_get_irq(pdev, 1);
	ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
			       IRQF_DISABLED, "l3-app-irq", l3);
	if (ret)
		dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);

	return ret;
}

static struct platform_driver omap_l3_driver = {
	.probe		= omap_l3_probe,
	.driver		= {
		.name		= "omap_l3_noc",
		.owner		= THIS_MODULE,
		.of_match_table = of_match_ptr(l3_noc_match),
	},
};

static int __init omap_l3_init(void)
{
	return platform_driver_register(&omap_l3_driver);
}
postcore_initcall_sync(omap_l3_init);

static void __exit omap_l3_exit(void)
{
	platform_driver_unregister(&omap_l3_driver);
}
module_exit(omap_l3_exit);
Commit	Line	Data
2722e56d	1	/*
c10d5c9e	2	* OMAP L3 Interconnect error handling driver
ed0e3520	3	*
c5f2aea0	4	* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
ed0e3520	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Sricharan <r.sricharan@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
c5f2aea0 NM	9	* it under the terms of the GNU General Public License version 2 as
c5f2aea0 NM	10	* published by the Free Software Foundation.
ed0e3520	11	*
c5f2aea0 NM	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ed0e3520	15	* GNU General Public License for more details.
ed0e3520	16	*/
2722e56d	17	#include <linux/init.h>
2722e56d	18	#include <linux/interrupt.h>
0659452d	19	#include <linux/io.h>
2722e56d	20	#include <linux/kernel.h>
0659452d S	21	#include <linux/module.h>
	22	#include <linux/of_device.h>
	23	#include <linux/of.h>
	24	#include <linux/platform_device.h>
2722e56d SS	25	#include <linux/slab.h>
	26
	27	#include "omap_l3_noc.h"
	28
	29	/*
	30	* Interrupt Handler for L3 error detection.
	31	* 1) Identify the L3 clockdomain partition to which the error belongs to.
	32	* 2) Identify the slave where the error information is logged
	33	* 3) Print the logged information.
	34	* 4) Add dump stack to provide kernel trace.
	35	*
	36	* Two Types of errors :
	37	* 1) Custom errors in L3 :
	38	* Target like DMM/FW/EMIF generates SRESP=ERR error
	39	* 2) Standard L3 error:
	40	* - Unsupported CMD.
	41	* L3 tries to access target while it is idle
	42	* - OCP disconnect.
	43	* - Address hole error:
	44	* If DSS/ISS/FDIF/USBHOSTFS access a target where they
	45	* do not have connectivity, the error is logged in
	46	* their default target which is DMM2.
	47	*
	48	* On High Secure devices, firewall errors are possible and those
	49	* can be trapped as well. But the trapping is implemented as part
	50	* secure software and hence need not be implemented here.
	51	*/
	52	static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
	53	{
	54
c10d5c9e	55	struct omap_l3 *l3 = _l3;
551a9fa9	56	int inttype, i, k;
2722e56d	57	int err_src = 0;
551a9fa9	58	u32 std_err_main, err_reg, clear, masterid;
6616aac6	59	void __iomem base, l3_targ_base;
9e224c8f	60	void __iomem l3_targ_stderr, l3_targ_slvofslsb, *l3_targ_mstaddr;
551a9fa9	61	char target_name, master_name = "UN IDENTIFIED";
3ae9af7c	62	struct l3_target_data *l3_targ_inst;
97708c08	63	struct l3_flagmux_data *flag_mux;
0659452d	64	struct l3_masters_data *master;
2722e56d SS	65
2722e56d SS	66	/* Get the Type of interrupt */
35f7b961	67	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
2722e56d	68
0659452d	69	for (i = 0; i < l3->num_modules; i++) {
2722e56d SS	70	/*
	71	* Read the regerr register of the clock domain
	72	* to determine the source
	73	*/
6616aac6	74	base = l3->l3_base[i];
97708c08 NM	75	flag_mux = l3->l3_flagmux[i];
97708c08 NM	76	err_reg = readl_relaxed(base + flag_mux->offset +
9e224c8f	77	L3_FLAGMUX_REGERR0 + (inttype << 3));
2722e56d SS	78
	79	/* Get the corresponding error and analyse */
	80	if (err_reg) {
	81	/* Identify the source from control status register */
342fd144	82	err_src = __ffs(err_reg);
3340d739 RN	83
	84	/* We DONOT expect err_src to go out of bounds */
	85	BUG_ON(err_src > MAX_CLKDM_TARGETS);
	86
97708c08 NM	87	if (err_src < flag_mux->num_targ_data) {
	88	l3_targ_inst = &flag_mux->l3_targ[err_src];
	89	target_name = l3_targ_inst->name;
	90	l3_targ_base = base + l3_targ_inst->offset;
	91	} else {
	92	target_name = L3_TARGET_NOT_SUPPORTED;
	93	}
2722e56d	94
3340d739 RN	95	/*
	96	* If we do not know of a register offset to decode
	97	* and clear, then mask.
	98	*/
	99	if (target_name == L3_TARGET_NOT_SUPPORTED) {
	100	u32 mask_val;
	101	void __iomem *mask_reg;
	102
	103	/*
	104	* Certain plaforms may have "undocumented"
	105	* status pending on boot.. So dont generate
	106	* a severe warning here.
	107	*/
	108	dev_err(l3->dev,
	109	"L3 %s error: target %d mod:%d %s\n",
	110	inttype ? "debug" : "application",
	111	err_src, i, "(unclearable)");
	112
97708c08	113	mask_reg = base + flag_mux->offset +
3340d739 RN	114	L3_FLAGMUX_MASK0 + (inttype << 3);
	115	mask_val = readl_relaxed(mask_reg);
	116	mask_val &= ~(1 << err_src);
	117	writel_relaxed(mask_val, mask_reg);
	118
	119	break;
	120	}
	121
2722e56d	122	/* Read the stderrlog_main_source from clk domain */
9e224c8f NM	123	l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
	124	l3_targ_slvofslsb = l3_targ_base +
	125	L3_TARG_STDERRLOG_SLVOFSLSB;
	126	l3_targ_mstaddr = l3_targ_base +
	127	L3_TARG_STDERRLOG_MSTADDR;
	128
	129	std_err_main = readl_relaxed(l3_targ_stderr);
d4d8819e NM	130
	131	/* STDERRLOG_MSTADDR Stores the NTTP master address. */
	132	masterid = (readl_relaxed(l3_targ_mstaddr) &
	133	l3->mst_addr_mask) >>
	134	__ffs(l3->mst_addr_mask);
2722e56d	135
35f7b961	136	switch (std_err_main & CUSTOM_ERROR) {
2722e56d	137	case STANDARD_ERROR:
551a9fa9	138	WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
551a9fa9	139	target_name,
9e224c8f	140	readl_relaxed(l3_targ_slvofslsb));
2722e56d SS	141	/* clear the std error log*/
2722e56d SS	142	clear = std_err_main \| CLEAR_STDERR_LOG;
9e224c8f	143	writel_relaxed(clear, l3_targ_stderr);
2722e56d SS	144	break;
	145
	146	case CUSTOM_ERROR:
0659452d S	147	for (k = 0, master = l3->l3_masters;
	148	k < l3->num_masters; k++, master++) {
	149	if (masterid == master->id) {
	150	master_name = master->name;
	151	break;
	152	}
551a9fa9	153	}
	154	WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
	155	master_name, target_name);
2722e56d SS	156	/* clear the std error log*/
2722e56d SS	157	clear = std_err_main \| CLEAR_STDERR_LOG;
9e224c8f	158	writel_relaxed(clear, l3_targ_stderr);
2722e56d SS	159	break;
	160
	161	default:
	162	/* Nothing to be handled here as of now */
	163	break;
	164	}
	165	/* Error found so break the for loop */
	166	break;
	167	}
	168	}
	169	return IRQ_HANDLED;
	170	}
	171
0659452d S	172	static const struct of_device_id l3_noc_match[] = {
	173	{.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
	174	{},
	175	};
	176	MODULE_DEVICE_TABLE(of, l3_noc_match);
	177
c10d5c9e	178	static int omap_l3_probe(struct platform_device *pdev)
2722e56d	179	{
0659452d	180	const struct of_device_id *of_id;
c10d5c9e	181	static struct omap_l3 *l3;
56c4a022	182	int ret, i;
2722e56d	183
0659452d S	184	of_id = of_match_device(l3_noc_match, &pdev->dev);
	185	if (!of_id) {
	186	dev_err(&pdev->dev, "OF data missing\n");
	187	return -EINVAL;
	188	}
	189
bae74510	190	l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
2722e56d	191	if (!l3)
7529b703	192	return -ENOMEM;
2722e56d	193
0659452d	194	memcpy(l3, of_id->data, sizeof(*l3));
ca6a3493	195	l3->dev = &pdev->dev;
2722e56d	196	platform_set_drvdata(pdev, l3);
2722e56d	197
56c4a022	198	/* Get mem resources */
0659452d	199	for (i = 0; i < l3->num_modules; i++) {
56c4a022 PU	200	struct resource *res = platform_get_resource(pdev,
56c4a022 PU	201	IORESOURCE_MEM, i);
2722e56d	202
56c4a022 PU	203	l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
56c4a022 PU	204	if (IS_ERR(l3->l3_base[i])) {
ca6a3493	205	dev_err(l3->dev, "ioremap %d failed\n", i);
56c4a022 PU	206	return PTR_ERR(l3->l3_base[i]);
56c4a022 PU	207	}
2722e56d SS	208	}
	209
	210	/*
	211	* Setup interrupt Handlers
	212	*/
c1df2dcc	213	l3->debug_irq = platform_get_irq(pdev, 0);
ca6a3493	214	ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
a0ef78f3	215	IRQF_DISABLED, "l3-dbg-irq", l3);
2722e56d	216	if (ret) {
ca6a3493	217	dev_err(l3->dev, "request_irq failed for %d\n",
ae22598a	218	l3->debug_irq);
56c4a022	219	return ret;
2722e56d	220	}
2722e56d	221
c1df2dcc	222	l3->app_irq = platform_get_irq(pdev, 1);
ca6a3493	223	ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
a0ef78f3 PU	224	IRQF_DISABLED, "l3-app-irq", l3);
a0ef78f3 PU	225	if (ret)
ca6a3493	226	dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
7529b703	227
2722e56d SS	228	return ret;
	229	}
	230
c10d5c9e S	231	static struct platform_driver omap_l3_driver = {
c10d5c9e S	232	.probe = omap_l3_probe,
d039c5b9 BC	233	.driver = {
	234	.name = "omap_l3_noc",
	235	.owner = THIS_MODULE,
0659452d	236	.of_match_table = of_match_ptr(l3_noc_match),
2722e56d SS	237	},
	238	};
	239
c10d5c9e	240	static int __init omap_l3_init(void)
2722e56d	241	{
c10d5c9e	242	return platform_driver_register(&omap_l3_driver);
2722e56d	243	}
c10d5c9e	244	postcore_initcall_sync(omap_l3_init);
2722e56d	245
c10d5c9e	246	static void __exit omap_l3_exit(void)
2722e56d	247	{
c10d5c9e	248	platform_driver_unregister(&omap_l3_driver);
2722e56d	249	}
c10d5c9e	250	module_exit(omap_l3_exit);