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e329113c BG |
1 | /* |
2 | * AMD CS5535/CS5536 GPIO driver. | |
3 | * Allows a user space process to play with the GPIO pins. | |
4 | * | |
5 | * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the smems of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | */ | |
11 | ||
12 | #include <linux/fs.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/cdev.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/pci.h> | |
20 | #include <asm/uaccess.h> | |
21 | #include <asm/io.h> | |
22 | ||
23 | ||
24 | #define NAME "cs5535_gpio" | |
25 | ||
26 | MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>"); | |
27 | MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO Pin Driver"); | |
28 | MODULE_LICENSE("GPL"); | |
29 | ||
30 | static int major; | |
31 | module_param(major, int, 0); | |
32 | MODULE_PARM_DESC(major, "Major device number"); | |
33 | ||
34 | static ulong mask; | |
35 | module_param(mask, ulong, 0); | |
36 | MODULE_PARM_DESC(mask, "GPIO channel mask"); | |
37 | ||
38 | #define MSR_LBAR_GPIO 0x5140000C | |
39 | ||
40 | static u32 gpio_base; | |
41 | ||
42 | static struct pci_device_id divil_pci[] = { | |
43 | { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) }, | |
44 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) }, | |
45 | { } /* NULL entry */ | |
46 | }; | |
47 | ||
48 | static struct cdev cs5535_gpio_cdev; | |
49 | ||
50 | /* reserve 32 entries even though some aren't usable */ | |
51 | #define CS5535_GPIO_COUNT 32 | |
52 | ||
53 | /* IO block size */ | |
54 | #define CS5535_GPIO_SIZE 256 | |
55 | ||
56 | struct gpio_regmap { | |
57 | u32 rd_offset; | |
58 | u32 wr_offset; | |
59 | char on; | |
60 | char off; | |
61 | }; | |
62 | static struct gpio_regmap rm[] = | |
63 | { | |
64 | { 0x30, 0x00, '1', '0' }, /* GPIOx_READ_BACK / GPIOx_OUT_VAL */ | |
65 | { 0x20, 0x20, 'I', 'i' }, /* GPIOx_IN_EN */ | |
66 | { 0x04, 0x04, 'O', 'o' }, /* GPIOx_OUT_EN */ | |
67 | { 0x08, 0x08, 't', 'T' }, /* GPIOx_OUT_OD_EN */ | |
68 | { 0x18, 0x18, 'P', 'p' }, /* GPIOx_OUT_PU_EN */ | |
69 | { 0x1c, 0x1c, 'D', 'd' }, /* GPIOx_OUT_PD_EN */ | |
70 | }; | |
71 | ||
72 | ||
73 | /** | |
74 | * Gets the register offset for the GPIO bank. | |
75 | * Low (0-15) starts at 0x00, high (16-31) starts at 0x80 | |
76 | */ | |
77 | static inline u32 cs5535_lowhigh_base(int reg) | |
78 | { | |
79 | return (reg & 0x10) << 3; | |
80 | } | |
81 | ||
82 | static ssize_t cs5535_gpio_write(struct file *file, const char __user *data, | |
83 | size_t len, loff_t *ppos) | |
84 | { | |
85 | u32 m = iminor(file->f_dentry->d_inode); | |
86 | int i, j; | |
87 | u32 base = gpio_base + cs5535_lowhigh_base(m); | |
88 | u32 m0, m1; | |
89 | char c; | |
90 | ||
91 | /** | |
92 | * Creates the mask for atomic bit programming. | |
93 | * The high 16 bits and the low 16 bits are used to set the mask. | |
94 | * For example, GPIO 15 maps to 31,15: 0,1 => On; 1,0=> Off | |
95 | */ | |
96 | m1 = 1 << (m & 0x0F); | |
97 | m0 = m1 << 16; | |
98 | ||
99 | for (i = 0; i < len; ++i) { | |
100 | if (get_user(c, data+i)) | |
101 | return -EFAULT; | |
102 | ||
103 | for (j = 0; j < ARRAY_SIZE(rm); j++) { | |
104 | if (c == rm[j].on) { | |
105 | outl(m1, base + rm[j].wr_offset); | |
106 | break; | |
107 | } else if (c == rm[j].off) { | |
108 | outl(m0, base + rm[j].wr_offset); | |
109 | break; | |
110 | } | |
111 | } | |
112 | } | |
113 | *ppos = 0; | |
114 | return len; | |
115 | } | |
116 | ||
117 | static ssize_t cs5535_gpio_read(struct file *file, char __user *buf, | |
118 | size_t len, loff_t *ppos) | |
119 | { | |
120 | u32 m = iminor(file->f_dentry->d_inode); | |
121 | u32 base = gpio_base + cs5535_lowhigh_base(m); | |
122 | int rd_bit = 1 << (m & 0x0f); | |
123 | int i; | |
124 | char ch; | |
125 | ssize_t count = 0; | |
126 | ||
127 | if (*ppos >= ARRAY_SIZE(rm)) | |
128 | return 0; | |
129 | ||
130 | for (i = *ppos; (i < (*ppos + len)) && (i < ARRAY_SIZE(rm)); i++) { | |
131 | ch = (inl(base + rm[i].rd_offset) & rd_bit) ? | |
132 | rm[i].on : rm[i].off; | |
133 | ||
134 | if (put_user(ch, buf+count)) | |
135 | return -EFAULT; | |
136 | ||
137 | count++; | |
138 | } | |
139 | ||
140 | /* add a line-feed if there is room */ | |
141 | if ((i == ARRAY_SIZE(rm)) && (count < len)) { | |
142 | put_user('\n', buf + count); | |
143 | count++; | |
144 | } | |
145 | ||
146 | *ppos += count; | |
147 | return count; | |
148 | } | |
149 | ||
150 | static int cs5535_gpio_open(struct inode *inode, struct file *file) | |
151 | { | |
152 | u32 m = iminor(inode); | |
153 | ||
154 | /* the mask says which pins are usable by this driver */ | |
155 | if ((mask & (1 << m)) == 0) | |
156 | return -EINVAL; | |
157 | ||
158 | return nonseekable_open(inode, file); | |
159 | } | |
160 | ||
62322d25 | 161 | static const struct file_operations cs5535_gpio_fops = { |
e329113c BG |
162 | .owner = THIS_MODULE, |
163 | .write = cs5535_gpio_write, | |
164 | .read = cs5535_gpio_read, | |
165 | .open = cs5535_gpio_open | |
166 | }; | |
167 | ||
168 | static int __init cs5535_gpio_init(void) | |
169 | { | |
170 | dev_t dev_id; | |
171 | u32 low, hi; | |
172 | int retval; | |
173 | ||
174 | if (pci_dev_present(divil_pci) == 0) { | |
175 | printk(KERN_WARNING NAME ": DIVIL not found\n"); | |
176 | return -ENODEV; | |
177 | } | |
178 | ||
179 | /* Grab the GPIO I/O range */ | |
180 | rdmsr(MSR_LBAR_GPIO, low, hi); | |
181 | ||
182 | /* Check the mask and whether GPIO is enabled (sanity check) */ | |
183 | if (hi != 0x0000f001) { | |
184 | printk(KERN_WARNING NAME ": GPIO not enabled\n"); | |
185 | return -ENODEV; | |
186 | } | |
187 | ||
188 | /* Mask off the IO base address */ | |
189 | gpio_base = low & 0x0000ff00; | |
190 | ||
191 | /** | |
192 | * Some GPIO pins | |
193 | * 31-29,23 : reserved (always mask out) | |
194 | * 28 : Power Button | |
195 | * 26 : PME# | |
196 | * 22-16 : LPC | |
197 | * 14,15 : SMBus | |
198 | * 9,8 : UART1 | |
199 | * 7 : PCI INTB | |
200 | * 3,4 : UART2/DDC | |
201 | * 2 : IDE_IRQ0 | |
202 | * 0 : PCI INTA | |
203 | * | |
204 | * If a mask was not specified, be conservative and only allow: | |
205 | * 1,2,5,6,10-13,24,25,27 | |
206 | */ | |
207 | if (mask != 0) | |
208 | mask &= 0x1f7fffff; | |
209 | else | |
210 | mask = 0x0b003c66; | |
211 | ||
212 | if (request_region(gpio_base, CS5535_GPIO_SIZE, NAME) == 0) { | |
213 | printk(KERN_ERR NAME ": can't allocate I/O for GPIO\n"); | |
214 | return -ENODEV; | |
215 | } | |
216 | ||
217 | if (major) { | |
218 | dev_id = MKDEV(major, 0); | |
219 | retval = register_chrdev_region(dev_id, CS5535_GPIO_COUNT, | |
220 | NAME); | |
221 | } else { | |
222 | retval = alloc_chrdev_region(&dev_id, 0, CS5535_GPIO_COUNT, | |
223 | NAME); | |
224 | major = MAJOR(dev_id); | |
225 | } | |
226 | ||
227 | if (retval) { | |
228 | release_region(gpio_base, CS5535_GPIO_SIZE); | |
229 | return -1; | |
230 | } | |
231 | ||
232 | printk(KERN_DEBUG NAME ": base=%#x mask=%#lx major=%d\n", | |
233 | gpio_base, mask, major); | |
234 | ||
235 | cdev_init(&cs5535_gpio_cdev, &cs5535_gpio_fops); | |
236 | cdev_add(&cs5535_gpio_cdev, dev_id, CS5535_GPIO_COUNT); | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
241 | static void __exit cs5535_gpio_cleanup(void) | |
242 | { | |
243 | dev_t dev_id = MKDEV(major, 0); | |
03246800 TS |
244 | |
245 | cdev_del(&cs5535_gpio_cdev); | |
e329113c | 246 | unregister_chrdev_region(dev_id, CS5535_GPIO_COUNT); |
03246800 | 247 | release_region(gpio_base, CS5535_GPIO_SIZE); |
e329113c BG |
248 | } |
249 | ||
250 | module_init(cs5535_gpio_init); | |
251 | module_exit(cs5535_gpio_cleanup); |