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drm: some minor cleanups and changes to make memory manager merging easier.
[deliverable/linux.git] / drivers / char / drm / mga_drv.h
CommitLineData
1da177e4
LT		 1/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __MGA_DRV_H__
32#define __MGA_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
38
39#define DRIVER_NAME "mga"
40#define DRIVER_DESC "Matrox G200/G400"
7ccf800e 41#define DRIVER_DATE "20051102"
1da177e4
LT		 42
43#define DRIVER_MAJOR 3
6795c985 44#define DRIVER_MINOR 2
7ccf800e 45#define DRIVER_PATCHLEVEL 1
1da177e4
LT		 46
47typedef struct drm_mga_primary_buffer {
48 u8 *start;
49 u8 *end;
50 int size;
51
52 u32 tail;
53 int space;
54 volatile long wrapped;
55
56 volatile u32 *status;
57
58 u32 last_flush;
59 u32 last_wrap;
60
61 u32 high_mark;
62} drm_mga_primary_buffer_t;
63
64typedef struct drm_mga_freelist {
b5e89ed5
DA		 65 struct drm_mga_freelist *next;
66 struct drm_mga_freelist *prev;
1da177e4 67 drm_mga_age_t age;
056219e2 68 struct drm_buf *buf;
1da177e4
LT		 69} drm_mga_freelist_t;
70
71typedef struct {
b5e89ed5 72 drm_mga_freelist_t *list_entry;
1da177e4
LT		 73 int discard;
74 int dispatched;
75} drm_mga_buf_priv_t;
76
77typedef struct drm_mga_private {
78 drm_mga_primary_buffer_t prim;
79 drm_mga_sarea_t *sarea_priv;
80
b5e89ed5
DA		 81 drm_mga_freelist_t *head;
82 drm_mga_freelist_t *tail;
1da177e4
LT		 83
84 unsigned int warp_pipe;
85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
86
87 int chipset;
88 int usec_timeout;
89
6795c985
DA		 90 /**
91 * If set, the new DMA initialization sequence was used. This is
92 * primarilly used to select how the driver should uninitialized its
93 * internal DMA structures.
94 */
95 int used_new_dma_init;
96
97 /**
98 * If AGP memory is used for DMA buffers, this will be the value
99 * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer).
100 */
101 u32 dma_access;
102
103 /**
104 * If AGP memory is used for DMA buffers, this will be the value
105 * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI
106 * transfer).
107 */
108 u32 wagp_enable;
109
110 /**
111 * \name MMIO region parameters.
b5e89ed5 112 *
6795c985
DA		 113 * \sa drm_mga_private_t::mmio
114 */
b5e89ed5
DA		 115 /*@{ */
116 u32 mmio_base; /**< Bus address of base of MMIO. */
117 u32 mmio_size; /**< Size of the MMIO region. */
118 /*@} */
6795c985 119
1da177e4
LT		 120 u32 clear_cmd;
121 u32 maccess;
122
6795c985
DA		 123 wait_queue_head_t fence_queue;
124 atomic_t last_fence_retired;
125 u32 next_fence_to_post;
126
1da177e4
LT		 127 unsigned int fb_cpp;
128 unsigned int front_offset;
129 unsigned int front_pitch;
130 unsigned int back_offset;
131 unsigned int back_pitch;
132
133 unsigned int depth_cpp;
134 unsigned int depth_offset;
135 unsigned int depth_pitch;
136
137 unsigned int texture_offset;
138 unsigned int texture_size;
139
140 drm_local_map_t *sarea;
141 drm_local_map_t *mmio;
142 drm_local_map_t *status;
143 drm_local_map_t *warp;
144 drm_local_map_t *primary;
1da177e4 145 drm_local_map_t *agp_textures;
b5e89ed5 146
7ccf800e
DA		 147 unsigned long agp_handle;
148 unsigned int agp_size;
1da177e4
LT		 149} drm_mga_private_t;
150
c153f45f 151extern struct drm_ioctl_desc mga_ioctls[];
b3a83639
DA		 152extern int mga_max_ioctl;
153
1da177e4 154 /* mga_dma.c */
c153f45f
EA		 155extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
156 struct drm_file *file_priv);
157extern int mga_dma_init(struct drm_device *dev, void *data,
158 struct drm_file *file_priv);
159extern int mga_dma_flush(struct drm_device *dev, void *data,
160 struct drm_file *file_priv);
161extern int mga_dma_reset(struct drm_device *dev, void *data,
162 struct drm_file *file_priv);
163extern int mga_dma_buffers(struct drm_device *dev, void *data,
164 struct drm_file *file_priv);
eddca551
DA		 165extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
166extern int mga_driver_unload(struct drm_device * dev);
167extern void mga_driver_lastclose(struct drm_device * dev);
168extern int mga_driver_dma_quiescent(struct drm_device * dev);
6795c985
DA		 169
170extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv);
171
172extern void mga_do_dma_flush(drm_mga_private_t * dev_priv);
173extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv);
174extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
1da177e4 175
056219e2 176extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf);
1da177e4
LT		 177
178 /* mga_warp.c */
6795c985
DA		 179extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv);
180extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
181extern int mga_warp_init(drm_mga_private_t * dev_priv);
182
183 /* mga_irq.c */
eddca551
DA		 184extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence);
185extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
6795c985 186extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
eddca551
DA		 187extern void mga_driver_irq_preinstall(struct drm_device * dev);
188extern void mga_driver_irq_postinstall(struct drm_device * dev);
189extern void mga_driver_irq_uninstall(struct drm_device * dev);
8ca7c1df
DA		 190extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
191 unsigned long arg);
1da177e4
LT		 192
193#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
194
195#if defined(__linux__) && defined(__alpha__)
196#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
197#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
198
199#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
200#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
201
202#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
203#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
204#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
205#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
206
b5e89ed5 207static inline u32 _MGA_READ(u32 * addr)
1da177e4
LT		 208{
209 DRM_MEMORYBARRIER();
210 return *(volatile u32 *)addr;
211}
212#else
213#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
214#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
215#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
216#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
217#endif
218
219#define DWGREG0 0x1c00
220#define DWGREG0_END 0x1dff
221#define DWGREG1 0x2c00
222#define DWGREG1_END 0x2dff
223
224#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
225#define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
226#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
227#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
228
1da177e4
LT		 229/* ================================================================
230 * Helper macross...
231 */
232
233#define MGA_EMIT_STATE( dev_priv, dirty ) \
234do { \
235 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
e29971f9 236 if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) { \
1da177e4
LT		 237 mga_g400_emit_state( dev_priv ); \
238 } else { \
239 mga_g200_emit_state( dev_priv ); \
240 } \
241 } \
242} while (0)
243
244#define WRAP_TEST_WITH_RETURN( dev_priv ) \
245do { \
246 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
247 if ( mga_is_idle( dev_priv ) ) { \
248 mga_do_dma_wrap_end( dev_priv ); \
249 } else if ( dev_priv->prim.space < \
250 dev_priv->prim.high_mark ) { \
251 if ( MGA_DMA_DEBUG ) \
252 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
20caafa6 253 return -EBUSY; \
1da177e4
LT		 254 } \
255 } \
256} while (0)
257
258#define WRAP_WAIT_WITH_RETURN( dev_priv ) \
259do { \
260 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
261 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
262 if ( MGA_DMA_DEBUG ) \
263 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
20caafa6 264 return -EBUSY; \
1da177e4
LT		 265 } \
266 mga_do_dma_wrap_end( dev_priv ); \
267 } \
268} while (0)
269
1da177e4
LT		 270/* ================================================================
271 * Primary DMA command stream
272 */
273
274#define MGA_VERBOSE 0
275
276#define DMA_LOCALS unsigned int write; volatile u8 *prim;
277
278#define DMA_BLOCK_SIZE (5 * sizeof(u32))
279
280#define BEGIN_DMA( n ) \
281do { \
282 if ( MGA_VERBOSE ) { \
283 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
284 (n), __FUNCTION__ ); \
285 DRM_INFO( " space=0x%x req=0x%Zx\n", \
286 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
287 } \
288 prim = dev_priv->prim.start; \
289 write = dev_priv->prim.tail; \
290} while (0)
291
292#define BEGIN_DMA_WRAP() \
293do { \
294 if ( MGA_VERBOSE ) { \
295 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
296 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
297 } \
298 prim = dev_priv->prim.start; \
299 write = dev_priv->prim.tail; \
300} while (0)
301
302#define ADVANCE_DMA() \
303do { \
304 dev_priv->prim.tail = write; \
305 if ( MGA_VERBOSE ) { \
306 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
307 write, dev_priv->prim.space ); \
308 } \
309} while (0)
310
311#define FLUSH_DMA() \
312do { \
313 if ( 0 ) { \
314 DRM_INFO( "%s:\n", __FUNCTION__ ); \
315 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
316 dev_priv->prim.tail, \
317 MGA_READ( MGA_PRIMADDRESS ) - \
318 dev_priv->primary->offset ); \
319 } \
320 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
321 if ( dev_priv->prim.space < \
322 dev_priv->prim.high_mark ) { \
323 mga_do_dma_wrap_start( dev_priv ); \
324 } else { \
325 mga_do_dma_flush( dev_priv ); \
326 } \
327 } \
328} while (0)
329
330/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
331 */
332#define DMA_WRITE( offset, val ) \
333do { \
334 if ( MGA_VERBOSE ) { \
335 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
336 (u32)(val), write + (offset) * sizeof(u32) ); \
337 } \
338 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
339} while (0)
340
341#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
342do { \
343 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
344 (DMAREG( reg1 ) << 8) | \
345 (DMAREG( reg2 ) << 16) | \
346 (DMAREG( reg3 ) << 24)) ); \
347 DMA_WRITE( 1, val0 ); \
348 DMA_WRITE( 2, val1 ); \
349 DMA_WRITE( 3, val2 ); \
350 DMA_WRITE( 4, val3 ); \
351 write += DMA_BLOCK_SIZE; \
352} while (0)
353
1da177e4
LT		 354/* Buffer aging via primary DMA stream head pointer.
355 */
356
357#define SET_AGE( age, h, w ) \
358do { \
359 (age)->head = h; \
360 (age)->wrap = w; \
361} while (0)
362
363#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
364 ( (age)->wrap == w && \
365 (age)->head < h ) )
366
367#define AGE_BUFFER( buf_priv ) \
368do { \
369 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
370 if ( (buf_priv)->dispatched ) { \
371 entry->age.head = (dev_priv->prim.tail + \
372 dev_priv->primary->offset); \
373 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
374 } else { \
375 entry->age.head = 0; \
376 entry->age.wrap = 0; \
377 } \
378} while (0)
379
1da177e4
LT		 380#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
381 MGA_DWGENGSTS | \
382 MGA_ENDPRDMASTS)
383#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
384 MGA_ENDPRDMASTS)
385
386#define MGA_DMA_DEBUG 0
387
1da177e4
LT		 388/* A reduced set of the mga registers.
389 */
390#define MGA_CRTC_INDEX 0x1fd4
391#define MGA_CRTC_DATA 0x1fd5
392
393/* CRTC11 */
394#define MGA_VINTCLR (1 << 4)
395#define MGA_VINTEN (1 << 5)
396
397#define MGA_ALPHACTRL 0x2c7c
398#define MGA_AR0 0x1c60
399#define MGA_AR1 0x1c64
400#define MGA_AR2 0x1c68
401#define MGA_AR3 0x1c6c
402#define MGA_AR4 0x1c70
403#define MGA_AR5 0x1c74
404#define MGA_AR6 0x1c78
405
406#define MGA_CXBNDRY 0x1c80
407#define MGA_CXLEFT 0x1ca0
408#define MGA_CXRIGHT 0x1ca4
409
410#define MGA_DMAPAD 0x1c54
411#define MGA_DSTORG 0x2cb8
412#define MGA_DWGCTL 0x1c00
413# define MGA_OPCOD_MASK (15 << 0)
414# define MGA_OPCOD_TRAP (4 << 0)
415# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
416# define MGA_OPCOD_BITBLT (8 << 0)
417# define MGA_OPCOD_ILOAD (9 << 0)
418# define MGA_ATYPE_MASK (7 << 4)
419# define MGA_ATYPE_RPL (0 << 4)
420# define MGA_ATYPE_RSTR (1 << 4)
421# define MGA_ATYPE_ZI (3 << 4)
422# define MGA_ATYPE_BLK (4 << 4)
423# define MGA_ATYPE_I (7 << 4)
424# define MGA_LINEAR (1 << 7)
425# define MGA_ZMODE_MASK (7 << 8)
426# define MGA_ZMODE_NOZCMP (0 << 8)
427# define MGA_ZMODE_ZE (2 << 8)
428# define MGA_ZMODE_ZNE (3 << 8)
429# define MGA_ZMODE_ZLT (4 << 8)
430# define MGA_ZMODE_ZLTE (5 << 8)
431# define MGA_ZMODE_ZGT (6 << 8)
432# define MGA_ZMODE_ZGTE (7 << 8)
433# define MGA_SOLID (1 << 11)
434# define MGA_ARZERO (1 << 12)
435# define MGA_SGNZERO (1 << 13)
436# define MGA_SHIFTZERO (1 << 14)
437# define MGA_BOP_MASK (15 << 16)
438# define MGA_BOP_ZERO (0 << 16)
439# define MGA_BOP_DST (10 << 16)
440# define MGA_BOP_SRC (12 << 16)
441# define MGA_BOP_ONE (15 << 16)
442# define MGA_TRANS_SHIFT 20
443# define MGA_TRANS_MASK (15 << 20)
444# define MGA_BLTMOD_MASK (15 << 25)
445# define MGA_BLTMOD_BMONOLEF (0 << 25)
446# define MGA_BLTMOD_BMONOWF (4 << 25)
447# define MGA_BLTMOD_PLAN (1 << 25)
448# define MGA_BLTMOD_BFCOL (2 << 25)
449# define MGA_BLTMOD_BU32BGR (3 << 25)
450# define MGA_BLTMOD_BU32RGB (7 << 25)
451# define MGA_BLTMOD_BU24BGR (11 << 25)
452# define MGA_BLTMOD_BU24RGB (15 << 25)
453# define MGA_PATTERN (1 << 29)
454# define MGA_TRANSC (1 << 30)
455# define MGA_CLIPDIS (1 << 31)
456#define MGA_DWGSYNC 0x2c4c
457
458#define MGA_FCOL 0x1c24
459#define MGA_FIFOSTATUS 0x1e10
460#define MGA_FOGCOL 0x1cf4
461#define MGA_FXBNDRY 0x1c84
462#define MGA_FXLEFT 0x1ca8
463#define MGA_FXRIGHT 0x1cac
464
465#define MGA_ICLEAR 0x1e18
466# define MGA_SOFTRAPICLR (1 << 0)
467# define MGA_VLINEICLR (1 << 5)
468#define MGA_IEN 0x1e1c
469# define MGA_SOFTRAPIEN (1 << 0)
470# define MGA_VLINEIEN (1 << 5)
471
472#define MGA_LEN 0x1c5c
473
474#define MGA_MACCESS 0x1c04
475
476#define MGA_PITCH 0x1c8c
477#define MGA_PLNWT 0x1c1c
478#define MGA_PRIMADDRESS 0x1e58
479# define MGA_DMA_GENERAL (0 << 0)
480# define MGA_DMA_BLIT (1 << 0)
481# define MGA_DMA_VECTOR (2 << 0)
482# define MGA_DMA_VERTEX (3 << 0)
483#define MGA_PRIMEND 0x1e5c
484# define MGA_PRIMNOSTART (1 << 0)
485# define MGA_PAGPXFER (1 << 1)
486#define MGA_PRIMPTR 0x1e50
487# define MGA_PRIMPTREN0 (1 << 0)
488# define MGA_PRIMPTREN1 (1 << 1)
489
490#define MGA_RST 0x1e40
491# define MGA_SOFTRESET (1 << 0)
492# define MGA_SOFTEXTRST (1 << 1)
493
494#define MGA_SECADDRESS 0x2c40
495#define MGA_SECEND 0x2c44
496#define MGA_SETUPADDRESS 0x2cd0
497#define MGA_SETUPEND 0x2cd4
498#define MGA_SGN 0x1c58
499#define MGA_SOFTRAP 0x2c48
500#define MGA_SRCORG 0x2cb4
501# define MGA_SRMMAP_MASK (1 << 0)
502# define MGA_SRCMAP_FB (0 << 0)
503# define MGA_SRCMAP_SYSMEM (1 << 0)
504# define MGA_SRCACC_MASK (1 << 1)
505# define MGA_SRCACC_PCI (0 << 1)
506# define MGA_SRCACC_AGP (1 << 1)
507#define MGA_STATUS 0x1e14
508# define MGA_SOFTRAPEN (1 << 0)
509# define MGA_VSYNCPEN (1 << 4)
510# define MGA_VLINEPEN (1 << 5)
511# define MGA_DWGENGSTS (1 << 16)
512# define MGA_ENDPRDMASTS (1 << 17)
513#define MGA_STENCIL 0x2cc8
514#define MGA_STENCILCTL 0x2ccc
515
516#define MGA_TDUALSTAGE0 0x2cf8
517#define MGA_TDUALSTAGE1 0x2cfc
518#define MGA_TEXBORDERCOL 0x2c5c
519#define MGA_TEXCTL 0x2c30
520#define MGA_TEXCTL2 0x2c3c
521# define MGA_DUALTEX (1 << 7)
522# define MGA_G400_TC2_MAGIC (1 << 15)
523# define MGA_MAP1_ENABLE (1 << 31)
524#define MGA_TEXFILTER 0x2c58
525#define MGA_TEXHEIGHT 0x2c2c
526#define MGA_TEXORG 0x2c24
527# define MGA_TEXORGMAP_MASK (1 << 0)
528# define MGA_TEXORGMAP_FB (0 << 0)
529# define MGA_TEXORGMAP_SYSMEM (1 << 0)
530# define MGA_TEXORGACC_MASK (1 << 1)
531# define MGA_TEXORGACC_PCI (0 << 1)
532# define MGA_TEXORGACC_AGP (1 << 1)
533#define MGA_TEXORG1 0x2ca4
534#define MGA_TEXORG2 0x2ca8
535#define MGA_TEXORG3 0x2cac
536#define MGA_TEXORG4 0x2cb0
537#define MGA_TEXTRANS 0x2c34
538#define MGA_TEXTRANSHIGH 0x2c38
539#define MGA_TEXWIDTH 0x2c28
540
541#define MGA_WACCEPTSEQ 0x1dd4
542#define MGA_WCODEADDR 0x1e6c
543#define MGA_WFLAG 0x1dc4
544#define MGA_WFLAG1 0x1de0
545#define MGA_WFLAGNB 0x1e64
546#define MGA_WFLAGNB1 0x1e08
547#define MGA_WGETMSB 0x1dc8
548#define MGA_WIADDR 0x1dc0
549#define MGA_WIADDR2 0x1dd8
550# define MGA_WMODE_SUSPEND (0 << 0)
551# define MGA_WMODE_RESUME (1 << 0)
552# define MGA_WMODE_JUMP (2 << 0)
553# define MGA_WMODE_START (3 << 0)
554# define MGA_WAGP_ENABLE (1 << 2)
555#define MGA_WMISC 0x1e70
556# define MGA_WUCODECACHE_ENABLE (1 << 0)
557# define MGA_WMASTER_ENABLE (1 << 1)
558# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
559#define MGA_WVRTXSZ 0x1dcc
560
561#define MGA_YBOT 0x1c9c
562#define MGA_YDST 0x1c90
563#define MGA_YDSTLEN 0x1c88
564#define MGA_YDSTORG 0x1c94
565#define MGA_YTOP 0x1c98
566
567#define MGA_ZORG 0x1c0c
568
569/* This finishes the current batch of commands
570 */
571#define MGA_EXEC 0x0100
572
6795c985
DA		 573/* AGP PLL encoding (for G200 only).
574 */
575#define MGA_AGP_PLL 0x1e4c
576# define MGA_AGP2XPLL_DISABLE (0 << 0)
577# define MGA_AGP2XPLL_ENABLE (1 << 0)
578
1da177e4
LT		 579/* Warp registers
580 */
581#define MGA_WR0 0x2d00
582#define MGA_WR1 0x2d04
583#define MGA_WR2 0x2d08
584#define MGA_WR3 0x2d0c
585#define MGA_WR4 0x2d10
586#define MGA_WR5 0x2d14
587#define MGA_WR6 0x2d18
588#define MGA_WR7 0x2d1c
589#define MGA_WR8 0x2d20
590#define MGA_WR9 0x2d24
591#define MGA_WR10 0x2d28
592#define MGA_WR11 0x2d2c
593#define MGA_WR12 0x2d30
594#define MGA_WR13 0x2d34
595#define MGA_WR14 0x2d38
596#define MGA_WR15 0x2d3c
597#define MGA_WR16 0x2d40
598#define MGA_WR17 0x2d44
599#define MGA_WR18 0x2d48
600#define MGA_WR19 0x2d4c
601#define MGA_WR20 0x2d50
602#define MGA_WR21 0x2d54
603#define MGA_WR22 0x2d58
604#define MGA_WR23 0x2d5c
605#define MGA_WR24 0x2d60
606#define MGA_WR25 0x2d64
607#define MGA_WR26 0x2d68
608#define MGA_WR27 0x2d6c
609#define MGA_WR28 0x2d70
610#define MGA_WR29 0x2d74
611#define MGA_WR30 0x2d78
612#define MGA_WR31 0x2d7c
613#define MGA_WR32 0x2d80
614#define MGA_WR33 0x2d84
615#define MGA_WR34 0x2d88
616#define MGA_WR35 0x2d8c
617#define MGA_WR36 0x2d90
618#define MGA_WR37 0x2d94
619#define MGA_WR38 0x2d98
620#define MGA_WR39 0x2d9c
621#define MGA_WR40 0x2da0
622#define MGA_WR41 0x2da4
623#define MGA_WR42 0x2da8
624#define MGA_WR43 0x2dac
625#define MGA_WR44 0x2db0
626#define MGA_WR45 0x2db4
627#define MGA_WR46 0x2db8
628#define MGA_WR47 0x2dbc
629#define MGA_WR48 0x2dc0
630#define MGA_WR49 0x2dc4
631#define MGA_WR50 0x2dc8
632#define MGA_WR51 0x2dcc
633#define MGA_WR52 0x2dd0
634#define MGA_WR53 0x2dd4
635#define MGA_WR54 0x2dd8
636#define MGA_WR55 0x2ddc
637#define MGA_WR56 0x2de0
638#define MGA_WR57 0x2de4
639#define MGA_WR58 0x2de8
640#define MGA_WR59 0x2dec
641#define MGA_WR60 0x2df0
642#define MGA_WR61 0x2df4
643#define MGA_WR62 0x2df8
644#define MGA_WR63 0x2dfc
645# define MGA_G400_WR_MAGIC (1 << 6)
646# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
647
1da177e4
LT		 648#define MGA_ILOAD_ALIGN 64
649#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
650
651#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
652 MGA_ATYPE_I | \
653 MGA_ZMODE_NOZCMP | \
654 MGA_ARZERO | \
655 MGA_SGNZERO | \
656 MGA_BOP_SRC | \
657 (15 << MGA_TRANS_SHIFT))
658
659#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
660 MGA_ZMODE_NOZCMP | \
661 MGA_SOLID | \
662 MGA_ARZERO | \
663 MGA_SGNZERO | \
664 MGA_SHIFTZERO | \
665 MGA_BOP_SRC | \
666 (0 << MGA_TRANS_SHIFT) | \
667 MGA_BLTMOD_BMONOLEF | \
668 MGA_TRANSC | \
669 MGA_CLIPDIS)
670
671#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
672 MGA_ATYPE_RPL | \
673 MGA_SGNZERO | \
674 MGA_SHIFTZERO | \
675 MGA_BOP_SRC | \
676 (0 << MGA_TRANS_SHIFT) | \
677 MGA_BLTMOD_BFCOL | \
678 MGA_CLIPDIS)
679
680/* Simple idle test.
681 */
b5e89ed5 682static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv)
1da177e4 683{
b5e89ed5
DA		 684 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
685 return (status == MGA_ENDPRDMASTS);
1da177e4
LT		 686}
687
688#endif
Linux kernel - Deliverables
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