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1da177e4 LT |
1 | /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- |
2 | * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com | |
3 | * | |
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
6 | * All rights reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
25 | * OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | */ | |
30 | ||
31 | #ifndef __MGA_DRV_H__ | |
32 | #define __MGA_DRV_H__ | |
33 | ||
34 | /* General customization: | |
35 | */ | |
36 | ||
37 | #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." | |
38 | ||
39 | #define DRIVER_NAME "mga" | |
40 | #define DRIVER_DESC "Matrox G200/G400" | |
7ccf800e | 41 | #define DRIVER_DATE "20051102" |
1da177e4 LT |
42 | |
43 | #define DRIVER_MAJOR 3 | |
6795c985 | 44 | #define DRIVER_MINOR 2 |
7ccf800e | 45 | #define DRIVER_PATCHLEVEL 1 |
1da177e4 LT |
46 | |
47 | typedef struct drm_mga_primary_buffer { | |
48 | u8 *start; | |
49 | u8 *end; | |
50 | int size; | |
51 | ||
52 | u32 tail; | |
53 | int space; | |
54 | volatile long wrapped; | |
55 | ||
56 | volatile u32 *status; | |
57 | ||
58 | u32 last_flush; | |
59 | u32 last_wrap; | |
60 | ||
61 | u32 high_mark; | |
62 | } drm_mga_primary_buffer_t; | |
63 | ||
64 | typedef struct drm_mga_freelist { | |
b5e89ed5 DA |
65 | struct drm_mga_freelist *next; |
66 | struct drm_mga_freelist *prev; | |
1da177e4 | 67 | drm_mga_age_t age; |
056219e2 | 68 | struct drm_buf *buf; |
1da177e4 LT |
69 | } drm_mga_freelist_t; |
70 | ||
71 | typedef struct { | |
b5e89ed5 | 72 | drm_mga_freelist_t *list_entry; |
1da177e4 LT |
73 | int discard; |
74 | int dispatched; | |
75 | } drm_mga_buf_priv_t; | |
76 | ||
77 | typedef struct drm_mga_private { | |
78 | drm_mga_primary_buffer_t prim; | |
79 | drm_mga_sarea_t *sarea_priv; | |
80 | ||
b5e89ed5 DA |
81 | drm_mga_freelist_t *head; |
82 | drm_mga_freelist_t *tail; | |
1da177e4 LT |
83 | |
84 | unsigned int warp_pipe; | |
85 | unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; | |
86 | ||
87 | int chipset; | |
88 | int usec_timeout; | |
89 | ||
6795c985 DA |
90 | /** |
91 | * If set, the new DMA initialization sequence was used. This is | |
92 | * primarilly used to select how the driver should uninitialized its | |
93 | * internal DMA structures. | |
94 | */ | |
95 | int used_new_dma_init; | |
96 | ||
97 | /** | |
98 | * If AGP memory is used for DMA buffers, this will be the value | |
99 | * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer). | |
100 | */ | |
101 | u32 dma_access; | |
102 | ||
103 | /** | |
104 | * If AGP memory is used for DMA buffers, this will be the value | |
105 | * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI | |
106 | * transfer). | |
107 | */ | |
108 | u32 wagp_enable; | |
109 | ||
110 | /** | |
111 | * \name MMIO region parameters. | |
b5e89ed5 | 112 | * |
6795c985 DA |
113 | * \sa drm_mga_private_t::mmio |
114 | */ | |
b5e89ed5 DA |
115 | /*@{ */ |
116 | u32 mmio_base; /**< Bus address of base of MMIO. */ | |
117 | u32 mmio_size; /**< Size of the MMIO region. */ | |
118 | /*@} */ | |
6795c985 | 119 | |
1da177e4 LT |
120 | u32 clear_cmd; |
121 | u32 maccess; | |
122 | ||
6795c985 DA |
123 | wait_queue_head_t fence_queue; |
124 | atomic_t last_fence_retired; | |
125 | u32 next_fence_to_post; | |
126 | ||
1da177e4 LT |
127 | unsigned int fb_cpp; |
128 | unsigned int front_offset; | |
129 | unsigned int front_pitch; | |
130 | unsigned int back_offset; | |
131 | unsigned int back_pitch; | |
132 | ||
133 | unsigned int depth_cpp; | |
134 | unsigned int depth_offset; | |
135 | unsigned int depth_pitch; | |
136 | ||
137 | unsigned int texture_offset; | |
138 | unsigned int texture_size; | |
139 | ||
140 | drm_local_map_t *sarea; | |
141 | drm_local_map_t *mmio; | |
142 | drm_local_map_t *status; | |
143 | drm_local_map_t *warp; | |
144 | drm_local_map_t *primary; | |
1da177e4 | 145 | drm_local_map_t *agp_textures; |
b5e89ed5 | 146 | |
7ccf800e DA |
147 | unsigned long agp_handle; |
148 | unsigned int agp_size; | |
1da177e4 LT |
149 | } drm_mga_private_t; |
150 | ||
b3a83639 DA |
151 | extern drm_ioctl_desc_t mga_ioctls[]; |
152 | extern int mga_max_ioctl; | |
153 | ||
1da177e4 | 154 | /* mga_dma.c */ |
6795c985 DA |
155 | extern int mga_dma_bootstrap(DRM_IOCTL_ARGS); |
156 | extern int mga_dma_init(DRM_IOCTL_ARGS); | |
157 | extern int mga_dma_flush(DRM_IOCTL_ARGS); | |
158 | extern int mga_dma_reset(DRM_IOCTL_ARGS); | |
159 | extern int mga_dma_buffers(DRM_IOCTL_ARGS); | |
eddca551 DA |
160 | extern int mga_driver_load(struct drm_device *dev, unsigned long flags); |
161 | extern int mga_driver_unload(struct drm_device * dev); | |
162 | extern void mga_driver_lastclose(struct drm_device * dev); | |
163 | extern int mga_driver_dma_quiescent(struct drm_device * dev); | |
6795c985 DA |
164 | |
165 | extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv); | |
166 | ||
167 | extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); | |
168 | extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); | |
169 | extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); | |
1da177e4 | 170 | |
056219e2 | 171 | extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf); |
1da177e4 LT |
172 | |
173 | /* mga_warp.c */ | |
6795c985 DA |
174 | extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); |
175 | extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); | |
176 | extern int mga_warp_init(drm_mga_private_t * dev_priv); | |
177 | ||
178 | /* mga_irq.c */ | |
eddca551 DA |
179 | extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence); |
180 | extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence); | |
6795c985 | 181 | extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS); |
eddca551 DA |
182 | extern void mga_driver_irq_preinstall(struct drm_device * dev); |
183 | extern void mga_driver_irq_postinstall(struct drm_device * dev); | |
184 | extern void mga_driver_irq_uninstall(struct drm_device * dev); | |
8ca7c1df DA |
185 | extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, |
186 | unsigned long arg); | |
1da177e4 LT |
187 | |
188 | #define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() | |
189 | ||
190 | #if defined(__linux__) && defined(__alpha__) | |
191 | #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) | |
192 | #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) | |
193 | ||
194 | #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) | |
195 | #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) | |
196 | ||
197 | #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) | |
198 | #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) | |
199 | #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) | |
200 | #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) | |
201 | ||
b5e89ed5 | 202 | static inline u32 _MGA_READ(u32 * addr) |
1da177e4 LT |
203 | { |
204 | DRM_MEMORYBARRIER(); | |
205 | return *(volatile u32 *)addr; | |
206 | } | |
207 | #else | |
208 | #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) | |
209 | #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) | |
210 | #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) | |
211 | #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) | |
212 | #endif | |
213 | ||
214 | #define DWGREG0 0x1c00 | |
215 | #define DWGREG0_END 0x1dff | |
216 | #define DWGREG1 0x2c00 | |
217 | #define DWGREG1_END 0x2dff | |
218 | ||
219 | #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) | |
220 | #define DMAREG0(r) (u8)((r - DWGREG0) >> 2) | |
221 | #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) | |
222 | #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) | |
223 | ||
1da177e4 LT |
224 | /* ================================================================ |
225 | * Helper macross... | |
226 | */ | |
227 | ||
228 | #define MGA_EMIT_STATE( dev_priv, dirty ) \ | |
229 | do { \ | |
230 | if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ | |
e29971f9 | 231 | if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) { \ |
1da177e4 LT |
232 | mga_g400_emit_state( dev_priv ); \ |
233 | } else { \ | |
234 | mga_g200_emit_state( dev_priv ); \ | |
235 | } \ | |
236 | } \ | |
237 | } while (0) | |
238 | ||
239 | #define WRAP_TEST_WITH_RETURN( dev_priv ) \ | |
240 | do { \ | |
241 | if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ | |
242 | if ( mga_is_idle( dev_priv ) ) { \ | |
243 | mga_do_dma_wrap_end( dev_priv ); \ | |
244 | } else if ( dev_priv->prim.space < \ | |
245 | dev_priv->prim.high_mark ) { \ | |
246 | if ( MGA_DMA_DEBUG ) \ | |
247 | DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ | |
20caafa6 | 248 | return -EBUSY; \ |
1da177e4 LT |
249 | } \ |
250 | } \ | |
251 | } while (0) | |
252 | ||
253 | #define WRAP_WAIT_WITH_RETURN( dev_priv ) \ | |
254 | do { \ | |
255 | if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ | |
256 | if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ | |
257 | if ( MGA_DMA_DEBUG ) \ | |
258 | DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ | |
20caafa6 | 259 | return -EBUSY; \ |
1da177e4 LT |
260 | } \ |
261 | mga_do_dma_wrap_end( dev_priv ); \ | |
262 | } \ | |
263 | } while (0) | |
264 | ||
1da177e4 LT |
265 | /* ================================================================ |
266 | * Primary DMA command stream | |
267 | */ | |
268 | ||
269 | #define MGA_VERBOSE 0 | |
270 | ||
271 | #define DMA_LOCALS unsigned int write; volatile u8 *prim; | |
272 | ||
273 | #define DMA_BLOCK_SIZE (5 * sizeof(u32)) | |
274 | ||
275 | #define BEGIN_DMA( n ) \ | |
276 | do { \ | |
277 | if ( MGA_VERBOSE ) { \ | |
278 | DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ | |
279 | (n), __FUNCTION__ ); \ | |
280 | DRM_INFO( " space=0x%x req=0x%Zx\n", \ | |
281 | dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ | |
282 | } \ | |
283 | prim = dev_priv->prim.start; \ | |
284 | write = dev_priv->prim.tail; \ | |
285 | } while (0) | |
286 | ||
287 | #define BEGIN_DMA_WRAP() \ | |
288 | do { \ | |
289 | if ( MGA_VERBOSE ) { \ | |
290 | DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ | |
291 | DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ | |
292 | } \ | |
293 | prim = dev_priv->prim.start; \ | |
294 | write = dev_priv->prim.tail; \ | |
295 | } while (0) | |
296 | ||
297 | #define ADVANCE_DMA() \ | |
298 | do { \ | |
299 | dev_priv->prim.tail = write; \ | |
300 | if ( MGA_VERBOSE ) { \ | |
301 | DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ | |
302 | write, dev_priv->prim.space ); \ | |
303 | } \ | |
304 | } while (0) | |
305 | ||
306 | #define FLUSH_DMA() \ | |
307 | do { \ | |
308 | if ( 0 ) { \ | |
309 | DRM_INFO( "%s:\n", __FUNCTION__ ); \ | |
310 | DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ | |
311 | dev_priv->prim.tail, \ | |
312 | MGA_READ( MGA_PRIMADDRESS ) - \ | |
313 | dev_priv->primary->offset ); \ | |
314 | } \ | |
315 | if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ | |
316 | if ( dev_priv->prim.space < \ | |
317 | dev_priv->prim.high_mark ) { \ | |
318 | mga_do_dma_wrap_start( dev_priv ); \ | |
319 | } else { \ | |
320 | mga_do_dma_flush( dev_priv ); \ | |
321 | } \ | |
322 | } \ | |
323 | } while (0) | |
324 | ||
325 | /* Never use this, always use DMA_BLOCK(...) for primary DMA output. | |
326 | */ | |
327 | #define DMA_WRITE( offset, val ) \ | |
328 | do { \ | |
329 | if ( MGA_VERBOSE ) { \ | |
330 | DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ | |
331 | (u32)(val), write + (offset) * sizeof(u32) ); \ | |
332 | } \ | |
333 | *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ | |
334 | } while (0) | |
335 | ||
336 | #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ | |
337 | do { \ | |
338 | DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ | |
339 | (DMAREG( reg1 ) << 8) | \ | |
340 | (DMAREG( reg2 ) << 16) | \ | |
341 | (DMAREG( reg3 ) << 24)) ); \ | |
342 | DMA_WRITE( 1, val0 ); \ | |
343 | DMA_WRITE( 2, val1 ); \ | |
344 | DMA_WRITE( 3, val2 ); \ | |
345 | DMA_WRITE( 4, val3 ); \ | |
346 | write += DMA_BLOCK_SIZE; \ | |
347 | } while (0) | |
348 | ||
1da177e4 LT |
349 | /* Buffer aging via primary DMA stream head pointer. |
350 | */ | |
351 | ||
352 | #define SET_AGE( age, h, w ) \ | |
353 | do { \ | |
354 | (age)->head = h; \ | |
355 | (age)->wrap = w; \ | |
356 | } while (0) | |
357 | ||
358 | #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ | |
359 | ( (age)->wrap == w && \ | |
360 | (age)->head < h ) ) | |
361 | ||
362 | #define AGE_BUFFER( buf_priv ) \ | |
363 | do { \ | |
364 | drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ | |
365 | if ( (buf_priv)->dispatched ) { \ | |
366 | entry->age.head = (dev_priv->prim.tail + \ | |
367 | dev_priv->primary->offset); \ | |
368 | entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ | |
369 | } else { \ | |
370 | entry->age.head = 0; \ | |
371 | entry->age.wrap = 0; \ | |
372 | } \ | |
373 | } while (0) | |
374 | ||
1da177e4 LT |
375 | #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ |
376 | MGA_DWGENGSTS | \ | |
377 | MGA_ENDPRDMASTS) | |
378 | #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ | |
379 | MGA_ENDPRDMASTS) | |
380 | ||
381 | #define MGA_DMA_DEBUG 0 | |
382 | ||
1da177e4 LT |
383 | /* A reduced set of the mga registers. |
384 | */ | |
385 | #define MGA_CRTC_INDEX 0x1fd4 | |
386 | #define MGA_CRTC_DATA 0x1fd5 | |
387 | ||
388 | /* CRTC11 */ | |
389 | #define MGA_VINTCLR (1 << 4) | |
390 | #define MGA_VINTEN (1 << 5) | |
391 | ||
392 | #define MGA_ALPHACTRL 0x2c7c | |
393 | #define MGA_AR0 0x1c60 | |
394 | #define MGA_AR1 0x1c64 | |
395 | #define MGA_AR2 0x1c68 | |
396 | #define MGA_AR3 0x1c6c | |
397 | #define MGA_AR4 0x1c70 | |
398 | #define MGA_AR5 0x1c74 | |
399 | #define MGA_AR6 0x1c78 | |
400 | ||
401 | #define MGA_CXBNDRY 0x1c80 | |
402 | #define MGA_CXLEFT 0x1ca0 | |
403 | #define MGA_CXRIGHT 0x1ca4 | |
404 | ||
405 | #define MGA_DMAPAD 0x1c54 | |
406 | #define MGA_DSTORG 0x2cb8 | |
407 | #define MGA_DWGCTL 0x1c00 | |
408 | # define MGA_OPCOD_MASK (15 << 0) | |
409 | # define MGA_OPCOD_TRAP (4 << 0) | |
410 | # define MGA_OPCOD_TEXTURE_TRAP (6 << 0) | |
411 | # define MGA_OPCOD_BITBLT (8 << 0) | |
412 | # define MGA_OPCOD_ILOAD (9 << 0) | |
413 | # define MGA_ATYPE_MASK (7 << 4) | |
414 | # define MGA_ATYPE_RPL (0 << 4) | |
415 | # define MGA_ATYPE_RSTR (1 << 4) | |
416 | # define MGA_ATYPE_ZI (3 << 4) | |
417 | # define MGA_ATYPE_BLK (4 << 4) | |
418 | # define MGA_ATYPE_I (7 << 4) | |
419 | # define MGA_LINEAR (1 << 7) | |
420 | # define MGA_ZMODE_MASK (7 << 8) | |
421 | # define MGA_ZMODE_NOZCMP (0 << 8) | |
422 | # define MGA_ZMODE_ZE (2 << 8) | |
423 | # define MGA_ZMODE_ZNE (3 << 8) | |
424 | # define MGA_ZMODE_ZLT (4 << 8) | |
425 | # define MGA_ZMODE_ZLTE (5 << 8) | |
426 | # define MGA_ZMODE_ZGT (6 << 8) | |
427 | # define MGA_ZMODE_ZGTE (7 << 8) | |
428 | # define MGA_SOLID (1 << 11) | |
429 | # define MGA_ARZERO (1 << 12) | |
430 | # define MGA_SGNZERO (1 << 13) | |
431 | # define MGA_SHIFTZERO (1 << 14) | |
432 | # define MGA_BOP_MASK (15 << 16) | |
433 | # define MGA_BOP_ZERO (0 << 16) | |
434 | # define MGA_BOP_DST (10 << 16) | |
435 | # define MGA_BOP_SRC (12 << 16) | |
436 | # define MGA_BOP_ONE (15 << 16) | |
437 | # define MGA_TRANS_SHIFT 20 | |
438 | # define MGA_TRANS_MASK (15 << 20) | |
439 | # define MGA_BLTMOD_MASK (15 << 25) | |
440 | # define MGA_BLTMOD_BMONOLEF (0 << 25) | |
441 | # define MGA_BLTMOD_BMONOWF (4 << 25) | |
442 | # define MGA_BLTMOD_PLAN (1 << 25) | |
443 | # define MGA_BLTMOD_BFCOL (2 << 25) | |
444 | # define MGA_BLTMOD_BU32BGR (3 << 25) | |
445 | # define MGA_BLTMOD_BU32RGB (7 << 25) | |
446 | # define MGA_BLTMOD_BU24BGR (11 << 25) | |
447 | # define MGA_BLTMOD_BU24RGB (15 << 25) | |
448 | # define MGA_PATTERN (1 << 29) | |
449 | # define MGA_TRANSC (1 << 30) | |
450 | # define MGA_CLIPDIS (1 << 31) | |
451 | #define MGA_DWGSYNC 0x2c4c | |
452 | ||
453 | #define MGA_FCOL 0x1c24 | |
454 | #define MGA_FIFOSTATUS 0x1e10 | |
455 | #define MGA_FOGCOL 0x1cf4 | |
456 | #define MGA_FXBNDRY 0x1c84 | |
457 | #define MGA_FXLEFT 0x1ca8 | |
458 | #define MGA_FXRIGHT 0x1cac | |
459 | ||
460 | #define MGA_ICLEAR 0x1e18 | |
461 | # define MGA_SOFTRAPICLR (1 << 0) | |
462 | # define MGA_VLINEICLR (1 << 5) | |
463 | #define MGA_IEN 0x1e1c | |
464 | # define MGA_SOFTRAPIEN (1 << 0) | |
465 | # define MGA_VLINEIEN (1 << 5) | |
466 | ||
467 | #define MGA_LEN 0x1c5c | |
468 | ||
469 | #define MGA_MACCESS 0x1c04 | |
470 | ||
471 | #define MGA_PITCH 0x1c8c | |
472 | #define MGA_PLNWT 0x1c1c | |
473 | #define MGA_PRIMADDRESS 0x1e58 | |
474 | # define MGA_DMA_GENERAL (0 << 0) | |
475 | # define MGA_DMA_BLIT (1 << 0) | |
476 | # define MGA_DMA_VECTOR (2 << 0) | |
477 | # define MGA_DMA_VERTEX (3 << 0) | |
478 | #define MGA_PRIMEND 0x1e5c | |
479 | # define MGA_PRIMNOSTART (1 << 0) | |
480 | # define MGA_PAGPXFER (1 << 1) | |
481 | #define MGA_PRIMPTR 0x1e50 | |
482 | # define MGA_PRIMPTREN0 (1 << 0) | |
483 | # define MGA_PRIMPTREN1 (1 << 1) | |
484 | ||
485 | #define MGA_RST 0x1e40 | |
486 | # define MGA_SOFTRESET (1 << 0) | |
487 | # define MGA_SOFTEXTRST (1 << 1) | |
488 | ||
489 | #define MGA_SECADDRESS 0x2c40 | |
490 | #define MGA_SECEND 0x2c44 | |
491 | #define MGA_SETUPADDRESS 0x2cd0 | |
492 | #define MGA_SETUPEND 0x2cd4 | |
493 | #define MGA_SGN 0x1c58 | |
494 | #define MGA_SOFTRAP 0x2c48 | |
495 | #define MGA_SRCORG 0x2cb4 | |
496 | # define MGA_SRMMAP_MASK (1 << 0) | |
497 | # define MGA_SRCMAP_FB (0 << 0) | |
498 | # define MGA_SRCMAP_SYSMEM (1 << 0) | |
499 | # define MGA_SRCACC_MASK (1 << 1) | |
500 | # define MGA_SRCACC_PCI (0 << 1) | |
501 | # define MGA_SRCACC_AGP (1 << 1) | |
502 | #define MGA_STATUS 0x1e14 | |
503 | # define MGA_SOFTRAPEN (1 << 0) | |
504 | # define MGA_VSYNCPEN (1 << 4) | |
505 | # define MGA_VLINEPEN (1 << 5) | |
506 | # define MGA_DWGENGSTS (1 << 16) | |
507 | # define MGA_ENDPRDMASTS (1 << 17) | |
508 | #define MGA_STENCIL 0x2cc8 | |
509 | #define MGA_STENCILCTL 0x2ccc | |
510 | ||
511 | #define MGA_TDUALSTAGE0 0x2cf8 | |
512 | #define MGA_TDUALSTAGE1 0x2cfc | |
513 | #define MGA_TEXBORDERCOL 0x2c5c | |
514 | #define MGA_TEXCTL 0x2c30 | |
515 | #define MGA_TEXCTL2 0x2c3c | |
516 | # define MGA_DUALTEX (1 << 7) | |
517 | # define MGA_G400_TC2_MAGIC (1 << 15) | |
518 | # define MGA_MAP1_ENABLE (1 << 31) | |
519 | #define MGA_TEXFILTER 0x2c58 | |
520 | #define MGA_TEXHEIGHT 0x2c2c | |
521 | #define MGA_TEXORG 0x2c24 | |
522 | # define MGA_TEXORGMAP_MASK (1 << 0) | |
523 | # define MGA_TEXORGMAP_FB (0 << 0) | |
524 | # define MGA_TEXORGMAP_SYSMEM (1 << 0) | |
525 | # define MGA_TEXORGACC_MASK (1 << 1) | |
526 | # define MGA_TEXORGACC_PCI (0 << 1) | |
527 | # define MGA_TEXORGACC_AGP (1 << 1) | |
528 | #define MGA_TEXORG1 0x2ca4 | |
529 | #define MGA_TEXORG2 0x2ca8 | |
530 | #define MGA_TEXORG3 0x2cac | |
531 | #define MGA_TEXORG4 0x2cb0 | |
532 | #define MGA_TEXTRANS 0x2c34 | |
533 | #define MGA_TEXTRANSHIGH 0x2c38 | |
534 | #define MGA_TEXWIDTH 0x2c28 | |
535 | ||
536 | #define MGA_WACCEPTSEQ 0x1dd4 | |
537 | #define MGA_WCODEADDR 0x1e6c | |
538 | #define MGA_WFLAG 0x1dc4 | |
539 | #define MGA_WFLAG1 0x1de0 | |
540 | #define MGA_WFLAGNB 0x1e64 | |
541 | #define MGA_WFLAGNB1 0x1e08 | |
542 | #define MGA_WGETMSB 0x1dc8 | |
543 | #define MGA_WIADDR 0x1dc0 | |
544 | #define MGA_WIADDR2 0x1dd8 | |
545 | # define MGA_WMODE_SUSPEND (0 << 0) | |
546 | # define MGA_WMODE_RESUME (1 << 0) | |
547 | # define MGA_WMODE_JUMP (2 << 0) | |
548 | # define MGA_WMODE_START (3 << 0) | |
549 | # define MGA_WAGP_ENABLE (1 << 2) | |
550 | #define MGA_WMISC 0x1e70 | |
551 | # define MGA_WUCODECACHE_ENABLE (1 << 0) | |
552 | # define MGA_WMASTER_ENABLE (1 << 1) | |
553 | # define MGA_WCACHEFLUSH_ENABLE (1 << 3) | |
554 | #define MGA_WVRTXSZ 0x1dcc | |
555 | ||
556 | #define MGA_YBOT 0x1c9c | |
557 | #define MGA_YDST 0x1c90 | |
558 | #define MGA_YDSTLEN 0x1c88 | |
559 | #define MGA_YDSTORG 0x1c94 | |
560 | #define MGA_YTOP 0x1c98 | |
561 | ||
562 | #define MGA_ZORG 0x1c0c | |
563 | ||
564 | /* This finishes the current batch of commands | |
565 | */ | |
566 | #define MGA_EXEC 0x0100 | |
567 | ||
6795c985 DA |
568 | /* AGP PLL encoding (for G200 only). |
569 | */ | |
570 | #define MGA_AGP_PLL 0x1e4c | |
571 | # define MGA_AGP2XPLL_DISABLE (0 << 0) | |
572 | # define MGA_AGP2XPLL_ENABLE (1 << 0) | |
573 | ||
1da177e4 LT |
574 | /* Warp registers |
575 | */ | |
576 | #define MGA_WR0 0x2d00 | |
577 | #define MGA_WR1 0x2d04 | |
578 | #define MGA_WR2 0x2d08 | |
579 | #define MGA_WR3 0x2d0c | |
580 | #define MGA_WR4 0x2d10 | |
581 | #define MGA_WR5 0x2d14 | |
582 | #define MGA_WR6 0x2d18 | |
583 | #define MGA_WR7 0x2d1c | |
584 | #define MGA_WR8 0x2d20 | |
585 | #define MGA_WR9 0x2d24 | |
586 | #define MGA_WR10 0x2d28 | |
587 | #define MGA_WR11 0x2d2c | |
588 | #define MGA_WR12 0x2d30 | |
589 | #define MGA_WR13 0x2d34 | |
590 | #define MGA_WR14 0x2d38 | |
591 | #define MGA_WR15 0x2d3c | |
592 | #define MGA_WR16 0x2d40 | |
593 | #define MGA_WR17 0x2d44 | |
594 | #define MGA_WR18 0x2d48 | |
595 | #define MGA_WR19 0x2d4c | |
596 | #define MGA_WR20 0x2d50 | |
597 | #define MGA_WR21 0x2d54 | |
598 | #define MGA_WR22 0x2d58 | |
599 | #define MGA_WR23 0x2d5c | |
600 | #define MGA_WR24 0x2d60 | |
601 | #define MGA_WR25 0x2d64 | |
602 | #define MGA_WR26 0x2d68 | |
603 | #define MGA_WR27 0x2d6c | |
604 | #define MGA_WR28 0x2d70 | |
605 | #define MGA_WR29 0x2d74 | |
606 | #define MGA_WR30 0x2d78 | |
607 | #define MGA_WR31 0x2d7c | |
608 | #define MGA_WR32 0x2d80 | |
609 | #define MGA_WR33 0x2d84 | |
610 | #define MGA_WR34 0x2d88 | |
611 | #define MGA_WR35 0x2d8c | |
612 | #define MGA_WR36 0x2d90 | |
613 | #define MGA_WR37 0x2d94 | |
614 | #define MGA_WR38 0x2d98 | |
615 | #define MGA_WR39 0x2d9c | |
616 | #define MGA_WR40 0x2da0 | |
617 | #define MGA_WR41 0x2da4 | |
618 | #define MGA_WR42 0x2da8 | |
619 | #define MGA_WR43 0x2dac | |
620 | #define MGA_WR44 0x2db0 | |
621 | #define MGA_WR45 0x2db4 | |
622 | #define MGA_WR46 0x2db8 | |
623 | #define MGA_WR47 0x2dbc | |
624 | #define MGA_WR48 0x2dc0 | |
625 | #define MGA_WR49 0x2dc4 | |
626 | #define MGA_WR50 0x2dc8 | |
627 | #define MGA_WR51 0x2dcc | |
628 | #define MGA_WR52 0x2dd0 | |
629 | #define MGA_WR53 0x2dd4 | |
630 | #define MGA_WR54 0x2dd8 | |
631 | #define MGA_WR55 0x2ddc | |
632 | #define MGA_WR56 0x2de0 | |
633 | #define MGA_WR57 0x2de4 | |
634 | #define MGA_WR58 0x2de8 | |
635 | #define MGA_WR59 0x2dec | |
636 | #define MGA_WR60 0x2df0 | |
637 | #define MGA_WR61 0x2df4 | |
638 | #define MGA_WR62 0x2df8 | |
639 | #define MGA_WR63 0x2dfc | |
640 | # define MGA_G400_WR_MAGIC (1 << 6) | |
641 | # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ | |
642 | ||
1da177e4 LT |
643 | #define MGA_ILOAD_ALIGN 64 |
644 | #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) | |
645 | ||
646 | #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ | |
647 | MGA_ATYPE_I | \ | |
648 | MGA_ZMODE_NOZCMP | \ | |
649 | MGA_ARZERO | \ | |
650 | MGA_SGNZERO | \ | |
651 | MGA_BOP_SRC | \ | |
652 | (15 << MGA_TRANS_SHIFT)) | |
653 | ||
654 | #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ | |
655 | MGA_ZMODE_NOZCMP | \ | |
656 | MGA_SOLID | \ | |
657 | MGA_ARZERO | \ | |
658 | MGA_SGNZERO | \ | |
659 | MGA_SHIFTZERO | \ | |
660 | MGA_BOP_SRC | \ | |
661 | (0 << MGA_TRANS_SHIFT) | \ | |
662 | MGA_BLTMOD_BMONOLEF | \ | |
663 | MGA_TRANSC | \ | |
664 | MGA_CLIPDIS) | |
665 | ||
666 | #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ | |
667 | MGA_ATYPE_RPL | \ | |
668 | MGA_SGNZERO | \ | |
669 | MGA_SHIFTZERO | \ | |
670 | MGA_BOP_SRC | \ | |
671 | (0 << MGA_TRANS_SHIFT) | \ | |
672 | MGA_BLTMOD_BFCOL | \ | |
673 | MGA_CLIPDIS) | |
674 | ||
675 | /* Simple idle test. | |
676 | */ | |
b5e89ed5 | 677 | static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv) |
1da177e4 | 678 | { |
b5e89ed5 DA |
679 | u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; |
680 | return (status == MGA_ENDPRDMASTS); | |
1da177e4 LT |
681 | } |
682 | ||
683 | #endif |