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f26c473c | 1 | /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- |
1da177e4 | 2 | * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com |
f26c473c DA |
3 | */ |
4 | /* | |
1da177e4 LT |
5 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
6 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
7 | * All Rights Reserved. | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a | |
10 | * copy of this software and associated documentation files (the "Software"), | |
11 | * to deal in the Software without restriction, including without limitation | |
12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
13 | * and/or sell copies of the Software, and to permit persons to whom the | |
14 | * Software is furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the next | |
17 | * paragraph) shall be included in all copies or substantial portions of the | |
18 | * Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
26 | * DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Gareth Hughes <gareth@valinux.com> | |
30 | */ | |
31 | ||
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "r128_drm.h" | |
35 | #include "r128_drv.h" | |
36 | ||
37 | #define R128_FIFO_DEBUG 0 | |
38 | ||
39 | /* CCE microcode (from ATI) */ | |
40 | static u32 r128_cce_microcode[] = { | |
41 | 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, | |
42 | 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, | |
43 | 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, | |
44 | 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, | |
45 | 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, | |
46 | 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, | |
47 | 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, | |
48 | 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, | |
49 | 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, | |
50 | 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, | |
51 | 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, | |
52 | 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, | |
53 | 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, | |
54 | 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, | |
55 | 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, | |
56 | 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, | |
57 | 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, | |
58 | 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, | |
59 | 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, | |
60 | 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, | |
61 | 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, | |
62 | 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, | |
63 | 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, | |
64 | 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, | |
65 | 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, | |
66 | 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, | |
67 | 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, | |
68 | 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, | |
69 | 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, | |
70 | 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, | |
71 | 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, | |
72 | 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, | |
73 | 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, | |
74 | 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, | |
75 | 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
76 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
77 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
78 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
79 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
80 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
81 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
82 | }; | |
83 | ||
b5e89ed5 | 84 | static int R128_READ_PLL(drm_device_t * dev, int addr) |
1da177e4 LT |
85 | { |
86 | drm_r128_private_t *dev_priv = dev->dev_private; | |
87 | ||
88 | R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); | |
89 | return R128_READ(R128_CLOCK_CNTL_DATA); | |
90 | } | |
91 | ||
92 | #if R128_FIFO_DEBUG | |
b5e89ed5 | 93 | static void r128_status(drm_r128_private_t * dev_priv) |
1da177e4 | 94 | { |
b5e89ed5 DA |
95 | printk("GUI_STAT = 0x%08x\n", |
96 | (unsigned int)R128_READ(R128_GUI_STAT)); | |
97 | printk("PM4_STAT = 0x%08x\n", | |
98 | (unsigned int)R128_READ(R128_PM4_STAT)); | |
99 | printk("PM4_BUFFER_DL_WPTR = 0x%08x\n", | |
100 | (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR)); | |
101 | printk("PM4_BUFFER_DL_RPTR = 0x%08x\n", | |
102 | (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR)); | |
103 | printk("PM4_MICRO_CNTL = 0x%08x\n", | |
104 | (unsigned int)R128_READ(R128_PM4_MICRO_CNTL)); | |
105 | printk("PM4_BUFFER_CNTL = 0x%08x\n", | |
106 | (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL)); | |
1da177e4 LT |
107 | } |
108 | #endif | |
109 | ||
1da177e4 LT |
110 | /* ================================================================ |
111 | * Engine, FIFO control | |
112 | */ | |
113 | ||
b5e89ed5 | 114 | static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) |
1da177e4 LT |
115 | { |
116 | u32 tmp; | |
117 | int i; | |
118 | ||
b5e89ed5 DA |
119 | tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL; |
120 | R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp); | |
1da177e4 | 121 | |
b5e89ed5 DA |
122 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
123 | if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) { | |
1da177e4 LT |
124 | return 0; |
125 | } | |
b5e89ed5 | 126 | DRM_UDELAY(1); |
1da177e4 LT |
127 | } |
128 | ||
129 | #if R128_FIFO_DEBUG | |
b5e89ed5 | 130 | DRM_ERROR("failed!\n"); |
1da177e4 LT |
131 | #endif |
132 | return DRM_ERR(EBUSY); | |
133 | } | |
134 | ||
b5e89ed5 | 135 | static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) |
1da177e4 LT |
136 | { |
137 | int i; | |
138 | ||
b5e89ed5 DA |
139 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
140 | int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK; | |
141 | if (slots >= entries) | |
142 | return 0; | |
143 | DRM_UDELAY(1); | |
1da177e4 LT |
144 | } |
145 | ||
146 | #if R128_FIFO_DEBUG | |
b5e89ed5 | 147 | DRM_ERROR("failed!\n"); |
1da177e4 LT |
148 | #endif |
149 | return DRM_ERR(EBUSY); | |
150 | } | |
151 | ||
b5e89ed5 | 152 | static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) |
1da177e4 LT |
153 | { |
154 | int i, ret; | |
155 | ||
b5e89ed5 DA |
156 | ret = r128_do_wait_for_fifo(dev_priv, 64); |
157 | if (ret) | |
158 | return ret; | |
1da177e4 | 159 | |
b5e89ed5 DA |
160 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
161 | if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) { | |
162 | r128_do_pixcache_flush(dev_priv); | |
1da177e4 LT |
163 | return 0; |
164 | } | |
b5e89ed5 | 165 | DRM_UDELAY(1); |
1da177e4 LT |
166 | } |
167 | ||
168 | #if R128_FIFO_DEBUG | |
b5e89ed5 | 169 | DRM_ERROR("failed!\n"); |
1da177e4 LT |
170 | #endif |
171 | return DRM_ERR(EBUSY); | |
172 | } | |
173 | ||
1da177e4 LT |
174 | /* ================================================================ |
175 | * CCE control, initialization | |
176 | */ | |
177 | ||
178 | /* Load the microcode for the CCE */ | |
b5e89ed5 | 179 | static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) |
1da177e4 LT |
180 | { |
181 | int i; | |
182 | ||
b5e89ed5 | 183 | DRM_DEBUG("\n"); |
1da177e4 | 184 | |
b5e89ed5 | 185 | r128_do_wait_for_idle(dev_priv); |
1da177e4 | 186 | |
b5e89ed5 DA |
187 | R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); |
188 | for (i = 0; i < 256; i++) { | |
189 | R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); | |
190 | R128_WRITE(R128_PM4_MICROCODE_DATAL, | |
191 | r128_cce_microcode[i * 2 + 1]); | |
1da177e4 LT |
192 | } |
193 | } | |
194 | ||
195 | /* Flush any pending commands to the CCE. This should only be used just | |
196 | * prior to a wait for idle, as it informs the engine that the command | |
197 | * stream is ending. | |
198 | */ | |
b5e89ed5 | 199 | static void r128_do_cce_flush(drm_r128_private_t * dev_priv) |
1da177e4 LT |
200 | { |
201 | u32 tmp; | |
202 | ||
b5e89ed5 DA |
203 | tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE; |
204 | R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp); | |
1da177e4 LT |
205 | } |
206 | ||
207 | /* Wait for the CCE to go idle. | |
208 | */ | |
b5e89ed5 | 209 | int r128_do_cce_idle(drm_r128_private_t * dev_priv) |
1da177e4 LT |
210 | { |
211 | int i; | |
212 | ||
b5e89ed5 DA |
213 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
214 | if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { | |
215 | int pm4stat = R128_READ(R128_PM4_STAT); | |
216 | if (((pm4stat & R128_PM4_FIFOCNT_MASK) >= | |
217 | dev_priv->cce_fifo_size) && | |
218 | !(pm4stat & (R128_PM4_BUSY | | |
219 | R128_PM4_GUI_ACTIVE))) { | |
220 | return r128_do_pixcache_flush(dev_priv); | |
1da177e4 LT |
221 | } |
222 | } | |
b5e89ed5 | 223 | DRM_UDELAY(1); |
1da177e4 LT |
224 | } |
225 | ||
226 | #if R128_FIFO_DEBUG | |
b5e89ed5 DA |
227 | DRM_ERROR("failed!\n"); |
228 | r128_status(dev_priv); | |
1da177e4 LT |
229 | #endif |
230 | return DRM_ERR(EBUSY); | |
231 | } | |
232 | ||
233 | /* Start the Concurrent Command Engine. | |
234 | */ | |
b5e89ed5 | 235 | static void r128_do_cce_start(drm_r128_private_t * dev_priv) |
1da177e4 | 236 | { |
b5e89ed5 | 237 | r128_do_wait_for_idle(dev_priv); |
1da177e4 | 238 | |
b5e89ed5 DA |
239 | R128_WRITE(R128_PM4_BUFFER_CNTL, |
240 | dev_priv->cce_mode | dev_priv->ring.size_l2qw | |
241 | | R128_PM4_BUFFER_CNTL_NOUPDATE); | |
242 | R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */ | |
243 | R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN); | |
1da177e4 LT |
244 | |
245 | dev_priv->cce_running = 1; | |
246 | } | |
247 | ||
248 | /* Reset the Concurrent Command Engine. This will not flush any pending | |
249 | * commands, so you must wait for the CCE command stream to complete | |
250 | * before calling this routine. | |
251 | */ | |
b5e89ed5 | 252 | static void r128_do_cce_reset(drm_r128_private_t * dev_priv) |
1da177e4 | 253 | { |
b5e89ed5 DA |
254 | R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); |
255 | R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); | |
1da177e4 LT |
256 | dev_priv->ring.tail = 0; |
257 | } | |
258 | ||
259 | /* Stop the Concurrent Command Engine. This will not flush any pending | |
260 | * commands, so you must flush the command stream and wait for the CCE | |
261 | * to go idle before calling this routine. | |
262 | */ | |
b5e89ed5 | 263 | static void r128_do_cce_stop(drm_r128_private_t * dev_priv) |
1da177e4 | 264 | { |
b5e89ed5 DA |
265 | R128_WRITE(R128_PM4_MICRO_CNTL, 0); |
266 | R128_WRITE(R128_PM4_BUFFER_CNTL, | |
267 | R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE); | |
1da177e4 LT |
268 | |
269 | dev_priv->cce_running = 0; | |
270 | } | |
271 | ||
272 | /* Reset the engine. This will stop the CCE if it is running. | |
273 | */ | |
b5e89ed5 | 274 | static int r128_do_engine_reset(drm_device_t * dev) |
1da177e4 LT |
275 | { |
276 | drm_r128_private_t *dev_priv = dev->dev_private; | |
277 | u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; | |
278 | ||
b5e89ed5 | 279 | r128_do_pixcache_flush(dev_priv); |
1da177e4 | 280 | |
b5e89ed5 DA |
281 | clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX); |
282 | mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL); | |
1da177e4 | 283 | |
b5e89ed5 DA |
284 | R128_WRITE_PLL(R128_MCLK_CNTL, |
285 | mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP); | |
1da177e4 | 286 | |
b5e89ed5 | 287 | gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL); |
1da177e4 LT |
288 | |
289 | /* Taken from the sample code - do not change */ | |
b5e89ed5 DA |
290 | R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI); |
291 | R128_READ(R128_GEN_RESET_CNTL); | |
292 | R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI); | |
293 | R128_READ(R128_GEN_RESET_CNTL); | |
1da177e4 | 294 | |
b5e89ed5 DA |
295 | R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl); |
296 | R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index); | |
297 | R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl); | |
1da177e4 LT |
298 | |
299 | /* Reset the CCE ring */ | |
b5e89ed5 | 300 | r128_do_cce_reset(dev_priv); |
1da177e4 LT |
301 | |
302 | /* The CCE is no longer running after an engine reset */ | |
303 | dev_priv->cce_running = 0; | |
304 | ||
305 | /* Reset any pending vertex, indirect buffers */ | |
b5e89ed5 | 306 | r128_freelist_reset(dev); |
1da177e4 LT |
307 | |
308 | return 0; | |
309 | } | |
310 | ||
b5e89ed5 DA |
311 | static void r128_cce_init_ring_buffer(drm_device_t * dev, |
312 | drm_r128_private_t * dev_priv) | |
1da177e4 LT |
313 | { |
314 | u32 ring_start; | |
315 | u32 tmp; | |
316 | ||
b5e89ed5 | 317 | DRM_DEBUG("\n"); |
1da177e4 LT |
318 | |
319 | /* The manual (p. 2) says this address is in "VM space". This | |
320 | * means it's an offset from the start of AGP space. | |
321 | */ | |
322 | #if __OS_HAS_AGP | |
b5e89ed5 | 323 | if (!dev_priv->is_pci) |
1da177e4 LT |
324 | ring_start = dev_priv->cce_ring->offset - dev->agp->base; |
325 | else | |
326 | #endif | |
b5e89ed5 DA |
327 | ring_start = dev_priv->cce_ring->offset - |
328 | (unsigned long)dev->sg->virtual; | |
1da177e4 | 329 | |
b5e89ed5 | 330 | R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET); |
1da177e4 | 331 | |
b5e89ed5 DA |
332 | R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); |
333 | R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); | |
1da177e4 LT |
334 | |
335 | /* Set watermark control */ | |
b5e89ed5 DA |
336 | R128_WRITE(R128_PM4_BUFFER_WM_CNTL, |
337 | ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT) | |
338 | | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT) | |
339 | | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT) | |
340 | | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT)); | |
1da177e4 LT |
341 | |
342 | /* Force read. Why? Because it's in the examples... */ | |
b5e89ed5 | 343 | R128_READ(R128_PM4_BUFFER_ADDR); |
1da177e4 LT |
344 | |
345 | /* Turn on bus mastering */ | |
b5e89ed5 DA |
346 | tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS; |
347 | R128_WRITE(R128_BUS_CNTL, tmp); | |
1da177e4 LT |
348 | } |
349 | ||
b5e89ed5 | 350 | static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init) |
1da177e4 LT |
351 | { |
352 | drm_r128_private_t *dev_priv; | |
353 | ||
b5e89ed5 | 354 | DRM_DEBUG("\n"); |
1da177e4 | 355 | |
b5e89ed5 DA |
356 | dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER); |
357 | if (dev_priv == NULL) | |
1da177e4 LT |
358 | return DRM_ERR(ENOMEM); |
359 | ||
b5e89ed5 | 360 | memset(dev_priv, 0, sizeof(drm_r128_private_t)); |
1da177e4 LT |
361 | |
362 | dev_priv->is_pci = init->is_pci; | |
363 | ||
b5e89ed5 DA |
364 | if (dev_priv->is_pci && !dev->sg) { |
365 | DRM_ERROR("PCI GART memory not allocated!\n"); | |
1da177e4 | 366 | dev->dev_private = (void *)dev_priv; |
b5e89ed5 | 367 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
368 | return DRM_ERR(EINVAL); |
369 | } | |
370 | ||
371 | dev_priv->usec_timeout = init->usec_timeout; | |
b5e89ed5 DA |
372 | if (dev_priv->usec_timeout < 1 || |
373 | dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) { | |
374 | DRM_DEBUG("TIMEOUT problem!\n"); | |
1da177e4 | 375 | dev->dev_private = (void *)dev_priv; |
b5e89ed5 | 376 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
377 | return DRM_ERR(EINVAL); |
378 | } | |
379 | ||
380 | dev_priv->cce_mode = init->cce_mode; | |
381 | ||
382 | /* GH: Simple idle check. | |
383 | */ | |
b5e89ed5 | 384 | atomic_set(&dev_priv->idle_count, 0); |
1da177e4 LT |
385 | |
386 | /* We don't support anything other than bus-mastering ring mode, | |
387 | * but the ring can be in either AGP or PCI space for the ring | |
388 | * read pointer. | |
389 | */ | |
b5e89ed5 DA |
390 | if ((init->cce_mode != R128_PM4_192BM) && |
391 | (init->cce_mode != R128_PM4_128BM_64INDBM) && | |
392 | (init->cce_mode != R128_PM4_64BM_128INDBM) && | |
393 | (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) { | |
394 | DRM_DEBUG("Bad cce_mode!\n"); | |
1da177e4 | 395 | dev->dev_private = (void *)dev_priv; |
b5e89ed5 | 396 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
397 | return DRM_ERR(EINVAL); |
398 | } | |
399 | ||
b5e89ed5 | 400 | switch (init->cce_mode) { |
1da177e4 LT |
401 | case R128_PM4_NONPM4: |
402 | dev_priv->cce_fifo_size = 0; | |
403 | break; | |
404 | case R128_PM4_192PIO: | |
405 | case R128_PM4_192BM: | |
406 | dev_priv->cce_fifo_size = 192; | |
407 | break; | |
408 | case R128_PM4_128PIO_64INDBM: | |
409 | case R128_PM4_128BM_64INDBM: | |
410 | dev_priv->cce_fifo_size = 128; | |
411 | break; | |
412 | case R128_PM4_64PIO_128INDBM: | |
413 | case R128_PM4_64BM_128INDBM: | |
414 | case R128_PM4_64PIO_64VCBM_64INDBM: | |
415 | case R128_PM4_64BM_64VCBM_64INDBM: | |
416 | case R128_PM4_64PIO_64VCPIO_64INDPIO: | |
417 | dev_priv->cce_fifo_size = 64; | |
418 | break; | |
419 | } | |
420 | ||
b5e89ed5 | 421 | switch (init->fb_bpp) { |
1da177e4 LT |
422 | case 16: |
423 | dev_priv->color_fmt = R128_DATATYPE_RGB565; | |
424 | break; | |
425 | case 32: | |
426 | default: | |
427 | dev_priv->color_fmt = R128_DATATYPE_ARGB8888; | |
428 | break; | |
429 | } | |
b5e89ed5 DA |
430 | dev_priv->front_offset = init->front_offset; |
431 | dev_priv->front_pitch = init->front_pitch; | |
432 | dev_priv->back_offset = init->back_offset; | |
433 | dev_priv->back_pitch = init->back_pitch; | |
1da177e4 | 434 | |
b5e89ed5 | 435 | switch (init->depth_bpp) { |
1da177e4 LT |
436 | case 16: |
437 | dev_priv->depth_fmt = R128_DATATYPE_RGB565; | |
438 | break; | |
439 | case 24: | |
440 | case 32: | |
441 | default: | |
442 | dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; | |
443 | break; | |
444 | } | |
b5e89ed5 DA |
445 | dev_priv->depth_offset = init->depth_offset; |
446 | dev_priv->depth_pitch = init->depth_pitch; | |
447 | dev_priv->span_offset = init->span_offset; | |
1da177e4 | 448 | |
b5e89ed5 | 449 | dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | |
1da177e4 | 450 | (dev_priv->front_offset >> 5)); |
b5e89ed5 | 451 | dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | |
1da177e4 | 452 | (dev_priv->back_offset >> 5)); |
b5e89ed5 | 453 | dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | |
1da177e4 LT |
454 | (dev_priv->depth_offset >> 5) | |
455 | R128_DST_TILE); | |
b5e89ed5 | 456 | dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | |
1da177e4 LT |
457 | (dev_priv->span_offset >> 5)); |
458 | ||
459 | DRM_GETSAREA(); | |
b5e89ed5 DA |
460 | |
461 | if (!dev_priv->sarea) { | |
1da177e4 LT |
462 | DRM_ERROR("could not find sarea!\n"); |
463 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 | 464 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
465 | return DRM_ERR(EINVAL); |
466 | } | |
467 | ||
468 | dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); | |
b5e89ed5 | 469 | if (!dev_priv->mmio) { |
1da177e4 LT |
470 | DRM_ERROR("could not find mmio region!\n"); |
471 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 | 472 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
473 | return DRM_ERR(EINVAL); |
474 | } | |
475 | dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); | |
b5e89ed5 | 476 | if (!dev_priv->cce_ring) { |
1da177e4 LT |
477 | DRM_ERROR("could not find cce ring region!\n"); |
478 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 | 479 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
480 | return DRM_ERR(EINVAL); |
481 | } | |
482 | dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); | |
b5e89ed5 | 483 | if (!dev_priv->ring_rptr) { |
1da177e4 LT |
484 | DRM_ERROR("could not find ring read pointer!\n"); |
485 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 | 486 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
487 | return DRM_ERR(EINVAL); |
488 | } | |
d1f2b55a | 489 | dev->agp_buffer_token = init->buffers_offset; |
1da177e4 | 490 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); |
b5e89ed5 | 491 | if (!dev->agp_buffer_map) { |
1da177e4 LT |
492 | DRM_ERROR("could not find dma buffer region!\n"); |
493 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 | 494 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
495 | return DRM_ERR(EINVAL); |
496 | } | |
497 | ||
b5e89ed5 DA |
498 | if (!dev_priv->is_pci) { |
499 | dev_priv->agp_textures = | |
500 | drm_core_findmap(dev, init->agp_textures_offset); | |
501 | if (!dev_priv->agp_textures) { | |
1da177e4 LT |
502 | DRM_ERROR("could not find agp texture region!\n"); |
503 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 | 504 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
505 | return DRM_ERR(EINVAL); |
506 | } | |
507 | } | |
508 | ||
509 | dev_priv->sarea_priv = | |
b5e89ed5 DA |
510 | (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle + |
511 | init->sarea_priv_offset); | |
1da177e4 LT |
512 | |
513 | #if __OS_HAS_AGP | |
b5e89ed5 DA |
514 | if (!dev_priv->is_pci) { |
515 | drm_core_ioremap(dev_priv->cce_ring, dev); | |
516 | drm_core_ioremap(dev_priv->ring_rptr, dev); | |
517 | drm_core_ioremap(dev->agp_buffer_map, dev); | |
518 | if (!dev_priv->cce_ring->handle || | |
519 | !dev_priv->ring_rptr->handle || | |
520 | !dev->agp_buffer_map->handle) { | |
1da177e4 LT |
521 | DRM_ERROR("Could not ioremap agp regions!\n"); |
522 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 | 523 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
524 | return DRM_ERR(ENOMEM); |
525 | } | |
526 | } else | |
527 | #endif | |
528 | { | |
b5e89ed5 | 529 | dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset; |
1da177e4 | 530 | dev_priv->ring_rptr->handle = |
b5e89ed5 DA |
531 | (void *)dev_priv->ring_rptr->offset; |
532 | dev->agp_buffer_map->handle = | |
533 | (void *)dev->agp_buffer_map->offset; | |
1da177e4 LT |
534 | } |
535 | ||
536 | #if __OS_HAS_AGP | |
b5e89ed5 | 537 | if (!dev_priv->is_pci) |
1da177e4 LT |
538 | dev_priv->cce_buffers_offset = dev->agp->base; |
539 | else | |
540 | #endif | |
d1f2b55a | 541 | dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual; |
1da177e4 | 542 | |
b5e89ed5 DA |
543 | dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; |
544 | dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle | |
1da177e4 LT |
545 | + init->ring_size / sizeof(u32)); |
546 | dev_priv->ring.size = init->ring_size; | |
b5e89ed5 | 547 | dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); |
1da177e4 | 548 | |
b5e89ed5 | 549 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; |
1da177e4 LT |
550 | |
551 | dev_priv->ring.high_mark = 128; | |
552 | ||
553 | dev_priv->sarea_priv->last_frame = 0; | |
b5e89ed5 | 554 | R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); |
1da177e4 LT |
555 | |
556 | dev_priv->sarea_priv->last_dispatch = 0; | |
b5e89ed5 | 557 | R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); |
1da177e4 LT |
558 | |
559 | #if __OS_HAS_AGP | |
b5e89ed5 | 560 | if (dev_priv->is_pci) { |
1da177e4 | 561 | #endif |
ea98a92f | 562 | dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; |
f26c473c DA |
563 | dev_priv->gart_info.addr = NULL; |
564 | dev_priv->gart_info.bus_addr = 0; | |
b5e89ed5 | 565 | dev_priv->gart_info.is_pcie = 0; |
ea98a92f | 566 | if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { |
b5e89ed5 | 567 | DRM_ERROR("failed to init PCI GART!\n"); |
1da177e4 | 568 | dev->dev_private = (void *)dev_priv; |
b5e89ed5 | 569 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
570 | return DRM_ERR(ENOMEM); |
571 | } | |
ea98a92f | 572 | R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); |
1da177e4 LT |
573 | #if __OS_HAS_AGP |
574 | } | |
575 | #endif | |
576 | ||
b5e89ed5 DA |
577 | r128_cce_init_ring_buffer(dev, dev_priv); |
578 | r128_cce_load_microcode(dev_priv); | |
1da177e4 LT |
579 | |
580 | dev->dev_private = (void *)dev_priv; | |
581 | ||
b5e89ed5 | 582 | r128_do_engine_reset(dev); |
1da177e4 LT |
583 | |
584 | return 0; | |
585 | } | |
586 | ||
b5e89ed5 | 587 | int r128_do_cleanup_cce(drm_device_t * dev) |
1da177e4 LT |
588 | { |
589 | ||
590 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
591 | * may not have been called from userspace and after dev_private | |
592 | * is freed, it's too late. | |
593 | */ | |
b5e89ed5 DA |
594 | if (dev->irq_enabled) |
595 | drm_irq_uninstall(dev); | |
1da177e4 | 596 | |
b5e89ed5 | 597 | if (dev->dev_private) { |
1da177e4 LT |
598 | drm_r128_private_t *dev_priv = dev->dev_private; |
599 | ||
600 | #if __OS_HAS_AGP | |
b5e89ed5 DA |
601 | if (!dev_priv->is_pci) { |
602 | if (dev_priv->cce_ring != NULL) | |
603 | drm_core_ioremapfree(dev_priv->cce_ring, dev); | |
604 | if (dev_priv->ring_rptr != NULL) | |
605 | drm_core_ioremapfree(dev_priv->ring_rptr, dev); | |
f26c473c | 606 | if (dev->agp_buffer_map != NULL) { |
b5e89ed5 | 607 | drm_core_ioremapfree(dev->agp_buffer_map, dev); |
f26c473c DA |
608 | dev->agp_buffer_map = NULL; |
609 | } | |
1da177e4 LT |
610 | } else |
611 | #endif | |
612 | { | |
b5e89ed5 DA |
613 | if (dev_priv->gart_info.bus_addr) |
614 | if (!drm_ati_pcigart_cleanup(dev, | |
f26c473c | 615 | &dev_priv->gart_info)) |
b5e89ed5 DA |
616 | DRM_ERROR |
617 | ("failed to cleanup PCI GART!\n"); | |
1da177e4 LT |
618 | } |
619 | ||
b5e89ed5 DA |
620 | drm_free(dev->dev_private, sizeof(drm_r128_private_t), |
621 | DRM_MEM_DRIVER); | |
1da177e4 LT |
622 | dev->dev_private = NULL; |
623 | } | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
b5e89ed5 | 628 | int r128_cce_init(DRM_IOCTL_ARGS) |
1da177e4 LT |
629 | { |
630 | DRM_DEVICE; | |
631 | drm_r128_init_t init; | |
632 | ||
b5e89ed5 | 633 | DRM_DEBUG("\n"); |
1da177e4 | 634 | |
b5e89ed5 | 635 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 636 | |
b5e89ed5 DA |
637 | DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data, |
638 | sizeof(init)); | |
1da177e4 | 639 | |
b5e89ed5 | 640 | switch (init.func) { |
1da177e4 | 641 | case R128_INIT_CCE: |
b5e89ed5 | 642 | return r128_do_init_cce(dev, &init); |
1da177e4 | 643 | case R128_CLEANUP_CCE: |
b5e89ed5 | 644 | return r128_do_cleanup_cce(dev); |
1da177e4 LT |
645 | } |
646 | ||
647 | return DRM_ERR(EINVAL); | |
648 | } | |
649 | ||
b5e89ed5 | 650 | int r128_cce_start(DRM_IOCTL_ARGS) |
1da177e4 LT |
651 | { |
652 | DRM_DEVICE; | |
653 | drm_r128_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 654 | DRM_DEBUG("\n"); |
1da177e4 | 655 | |
b5e89ed5 | 656 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 657 | |
b5e89ed5 DA |
658 | if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { |
659 | DRM_DEBUG("%s while CCE running\n", __FUNCTION__); | |
1da177e4 LT |
660 | return 0; |
661 | } | |
662 | ||
b5e89ed5 | 663 | r128_do_cce_start(dev_priv); |
1da177e4 LT |
664 | |
665 | return 0; | |
666 | } | |
667 | ||
668 | /* Stop the CCE. The engine must have been idled before calling this | |
669 | * routine. | |
670 | */ | |
b5e89ed5 | 671 | int r128_cce_stop(DRM_IOCTL_ARGS) |
1da177e4 LT |
672 | { |
673 | DRM_DEVICE; | |
674 | drm_r128_private_t *dev_priv = dev->dev_private; | |
675 | drm_r128_cce_stop_t stop; | |
676 | int ret; | |
b5e89ed5 | 677 | DRM_DEBUG("\n"); |
1da177e4 | 678 | |
b5e89ed5 | 679 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 680 | |
b5e89ed5 DA |
681 | DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data, |
682 | sizeof(stop)); | |
1da177e4 LT |
683 | |
684 | /* Flush any pending CCE commands. This ensures any outstanding | |
685 | * commands are exectuted by the engine before we turn it off. | |
686 | */ | |
b5e89ed5 DA |
687 | if (stop.flush) { |
688 | r128_do_cce_flush(dev_priv); | |
1da177e4 LT |
689 | } |
690 | ||
691 | /* If we fail to make the engine go idle, we return an error | |
692 | * code so that the DRM ioctl wrapper can try again. | |
693 | */ | |
b5e89ed5 DA |
694 | if (stop.idle) { |
695 | ret = r128_do_cce_idle(dev_priv); | |
696 | if (ret) | |
697 | return ret; | |
1da177e4 LT |
698 | } |
699 | ||
700 | /* Finally, we can turn off the CCE. If the engine isn't idle, | |
701 | * we will get some dropped triangles as they won't be fully | |
702 | * rendered before the CCE is shut down. | |
703 | */ | |
b5e89ed5 | 704 | r128_do_cce_stop(dev_priv); |
1da177e4 LT |
705 | |
706 | /* Reset the engine */ | |
b5e89ed5 | 707 | r128_do_engine_reset(dev); |
1da177e4 LT |
708 | |
709 | return 0; | |
710 | } | |
711 | ||
712 | /* Just reset the CCE ring. Called as part of an X Server engine reset. | |
713 | */ | |
b5e89ed5 | 714 | int r128_cce_reset(DRM_IOCTL_ARGS) |
1da177e4 LT |
715 | { |
716 | DRM_DEVICE; | |
717 | drm_r128_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 718 | DRM_DEBUG("\n"); |
1da177e4 | 719 | |
b5e89ed5 | 720 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 721 | |
b5e89ed5 DA |
722 | if (!dev_priv) { |
723 | DRM_DEBUG("%s called before init done\n", __FUNCTION__); | |
1da177e4 LT |
724 | return DRM_ERR(EINVAL); |
725 | } | |
726 | ||
b5e89ed5 | 727 | r128_do_cce_reset(dev_priv); |
1da177e4 LT |
728 | |
729 | /* The CCE is no longer running after an engine reset */ | |
730 | dev_priv->cce_running = 0; | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
b5e89ed5 | 735 | int r128_cce_idle(DRM_IOCTL_ARGS) |
1da177e4 LT |
736 | { |
737 | DRM_DEVICE; | |
738 | drm_r128_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 739 | DRM_DEBUG("\n"); |
1da177e4 | 740 | |
b5e89ed5 | 741 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 742 | |
b5e89ed5 DA |
743 | if (dev_priv->cce_running) { |
744 | r128_do_cce_flush(dev_priv); | |
1da177e4 LT |
745 | } |
746 | ||
b5e89ed5 | 747 | return r128_do_cce_idle(dev_priv); |
1da177e4 LT |
748 | } |
749 | ||
b5e89ed5 | 750 | int r128_engine_reset(DRM_IOCTL_ARGS) |
1da177e4 LT |
751 | { |
752 | DRM_DEVICE; | |
b5e89ed5 | 753 | DRM_DEBUG("\n"); |
1da177e4 | 754 | |
b5e89ed5 | 755 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 756 | |
b5e89ed5 | 757 | return r128_do_engine_reset(dev); |
1da177e4 LT |
758 | } |
759 | ||
b5e89ed5 | 760 | int r128_fullscreen(DRM_IOCTL_ARGS) |
1da177e4 LT |
761 | { |
762 | return DRM_ERR(EINVAL); | |
763 | } | |
764 | ||
1da177e4 LT |
765 | /* ================================================================ |
766 | * Freelist management | |
767 | */ | |
768 | #define R128_BUFFER_USED 0xffffffff | |
769 | #define R128_BUFFER_FREE 0 | |
770 | ||
771 | #if 0 | |
b5e89ed5 | 772 | static int r128_freelist_init(drm_device_t * dev) |
1da177e4 LT |
773 | { |
774 | drm_device_dma_t *dma = dev->dma; | |
775 | drm_r128_private_t *dev_priv = dev->dev_private; | |
776 | drm_buf_t *buf; | |
777 | drm_r128_buf_priv_t *buf_priv; | |
778 | drm_r128_freelist_t *entry; | |
779 | int i; | |
780 | ||
b5e89ed5 DA |
781 | dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); |
782 | if (dev_priv->head == NULL) | |
1da177e4 LT |
783 | return DRM_ERR(ENOMEM); |
784 | ||
b5e89ed5 | 785 | memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t)); |
1da177e4 LT |
786 | dev_priv->head->age = R128_BUFFER_USED; |
787 | ||
b5e89ed5 | 788 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 LT |
789 | buf = dma->buflist[i]; |
790 | buf_priv = buf->dev_private; | |
791 | ||
b5e89ed5 DA |
792 | entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); |
793 | if (!entry) | |
794 | return DRM_ERR(ENOMEM); | |
1da177e4 LT |
795 | |
796 | entry->age = R128_BUFFER_FREE; | |
797 | entry->buf = buf; | |
798 | entry->prev = dev_priv->head; | |
799 | entry->next = dev_priv->head->next; | |
b5e89ed5 | 800 | if (!entry->next) |
1da177e4 LT |
801 | dev_priv->tail = entry; |
802 | ||
803 | buf_priv->discard = 0; | |
804 | buf_priv->dispatched = 0; | |
805 | buf_priv->list_entry = entry; | |
806 | ||
807 | dev_priv->head->next = entry; | |
808 | ||
b5e89ed5 | 809 | if (dev_priv->head->next) |
1da177e4 LT |
810 | dev_priv->head->next->prev = entry; |
811 | } | |
812 | ||
813 | return 0; | |
814 | ||
815 | } | |
816 | #endif | |
817 | ||
b5e89ed5 | 818 | static drm_buf_t *r128_freelist_get(drm_device_t * dev) |
1da177e4 LT |
819 | { |
820 | drm_device_dma_t *dma = dev->dma; | |
821 | drm_r128_private_t *dev_priv = dev->dev_private; | |
822 | drm_r128_buf_priv_t *buf_priv; | |
823 | drm_buf_t *buf; | |
824 | int i, t; | |
825 | ||
826 | /* FIXME: Optimize -- use freelist code */ | |
827 | ||
b5e89ed5 | 828 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 LT |
829 | buf = dma->buflist[i]; |
830 | buf_priv = buf->dev_private; | |
b5e89ed5 | 831 | if (buf->filp == 0) |
1da177e4 LT |
832 | return buf; |
833 | } | |
834 | ||
b5e89ed5 DA |
835 | for (t = 0; t < dev_priv->usec_timeout; t++) { |
836 | u32 done_age = R128_READ(R128_LAST_DISPATCH_REG); | |
1da177e4 | 837 | |
b5e89ed5 | 838 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 LT |
839 | buf = dma->buflist[i]; |
840 | buf_priv = buf->dev_private; | |
b5e89ed5 | 841 | if (buf->pending && buf_priv->age <= done_age) { |
1da177e4 LT |
842 | /* The buffer has been processed, so it |
843 | * can now be used. | |
844 | */ | |
845 | buf->pending = 0; | |
846 | return buf; | |
847 | } | |
848 | } | |
b5e89ed5 | 849 | DRM_UDELAY(1); |
1da177e4 LT |
850 | } |
851 | ||
b5e89ed5 | 852 | DRM_DEBUG("returning NULL!\n"); |
1da177e4 LT |
853 | return NULL; |
854 | } | |
855 | ||
b5e89ed5 | 856 | void r128_freelist_reset(drm_device_t * dev) |
1da177e4 LT |
857 | { |
858 | drm_device_dma_t *dma = dev->dma; | |
859 | int i; | |
860 | ||
b5e89ed5 | 861 | for (i = 0; i < dma->buf_count; i++) { |
1da177e4 LT |
862 | drm_buf_t *buf = dma->buflist[i]; |
863 | drm_r128_buf_priv_t *buf_priv = buf->dev_private; | |
864 | buf_priv->age = 0; | |
865 | } | |
866 | } | |
867 | ||
1da177e4 LT |
868 | /* ================================================================ |
869 | * CCE command submission | |
870 | */ | |
871 | ||
b5e89ed5 | 872 | int r128_wait_ring(drm_r128_private_t * dev_priv, int n) |
1da177e4 LT |
873 | { |
874 | drm_r128_ring_buffer_t *ring = &dev_priv->ring; | |
875 | int i; | |
876 | ||
b5e89ed5 DA |
877 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
878 | r128_update_ring_snapshot(dev_priv); | |
879 | if (ring->space >= n) | |
1da177e4 | 880 | return 0; |
b5e89ed5 | 881 | DRM_UDELAY(1); |
1da177e4 LT |
882 | } |
883 | ||
884 | /* FIXME: This is being ignored... */ | |
b5e89ed5 | 885 | DRM_ERROR("failed!\n"); |
1da177e4 LT |
886 | return DRM_ERR(EBUSY); |
887 | } | |
888 | ||
b5e89ed5 | 889 | static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) |
1da177e4 LT |
890 | { |
891 | int i; | |
892 | drm_buf_t *buf; | |
893 | ||
b5e89ed5 DA |
894 | for (i = d->granted_count; i < d->request_count; i++) { |
895 | buf = r128_freelist_get(dev); | |
896 | if (!buf) | |
897 | return DRM_ERR(EAGAIN); | |
1da177e4 LT |
898 | |
899 | buf->filp = filp; | |
900 | ||
b5e89ed5 DA |
901 | if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, |
902 | sizeof(buf->idx))) | |
1da177e4 | 903 | return DRM_ERR(EFAULT); |
b5e89ed5 DA |
904 | if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, |
905 | sizeof(buf->total))) | |
1da177e4 LT |
906 | return DRM_ERR(EFAULT); |
907 | ||
908 | d->granted_count++; | |
909 | } | |
910 | return 0; | |
911 | } | |
912 | ||
b5e89ed5 | 913 | int r128_cce_buffers(DRM_IOCTL_ARGS) |
1da177e4 LT |
914 | { |
915 | DRM_DEVICE; | |
916 | drm_device_dma_t *dma = dev->dma; | |
917 | int ret = 0; | |
918 | drm_dma_t __user *argp = (void __user *)data; | |
919 | drm_dma_t d; | |
920 | ||
b5e89ed5 | 921 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 922 | |
b5e89ed5 | 923 | DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); |
1da177e4 LT |
924 | |
925 | /* Please don't send us buffers. | |
926 | */ | |
b5e89ed5 DA |
927 | if (d.send_count != 0) { |
928 | DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", | |
929 | DRM_CURRENTPID, d.send_count); | |
1da177e4 LT |
930 | return DRM_ERR(EINVAL); |
931 | } | |
932 | ||
933 | /* We'll send you buffers. | |
934 | */ | |
b5e89ed5 DA |
935 | if (d.request_count < 0 || d.request_count > dma->buf_count) { |
936 | DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", | |
937 | DRM_CURRENTPID, d.request_count, dma->buf_count); | |
1da177e4 LT |
938 | return DRM_ERR(EINVAL); |
939 | } | |
940 | ||
941 | d.granted_count = 0; | |
942 | ||
b5e89ed5 DA |
943 | if (d.request_count) { |
944 | ret = r128_cce_get_buffers(filp, dev, &d); | |
1da177e4 LT |
945 | } |
946 | ||
b5e89ed5 | 947 | DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); |
1da177e4 LT |
948 | |
949 | return ret; | |
950 | } |