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[PATCH] fix typo in acpi video brightness changes.
[deliverable/linux.git] / drivers / char / drm / radeon_drv.h
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1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
d5ea702f 41#define DRIVER_DATE "20060225"
1da177e4
LT		 42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
b5e89ed5 71 * clients use to tell the DRM where they think the framebuffer is
1da177e4
LT		 72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
d985c108 76 * (No 3D support yet - just microcode loading).
1da177e4
LT		 77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
414ed537 85 * 1.17- Add initial support for R300 (3D).
9d17601c
DA		 86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
ea98a92f 90 * 1.19- Add support for gart table in FB memory and PCIE r300
d985c108
DA		 91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
4e5e2e25 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
d5ea702f 94 * 1.23- Add new radeon memory map work from benh
ee4621f0 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
1da177e4
LT		 96 */
97#define DRIVER_MAJOR 1
ee4621f0 98#define DRIVER_MINOR 24
1da177e4
LT		 99#define DRIVER_PATCHLEVEL 0
100
1da177e4
LT		 101/*
102 * Radeon chip families
103 */
104enum radeon_family {
105 CHIP_R100,
1da177e4 106 CHIP_RV100,
dfab1154 107 CHIP_RS100,
1da177e4
LT		 108 CHIP_RV200,
109 CHIP_RS200,
dfab1154 110 CHIP_R200,
1da177e4 111 CHIP_RV250,
dfab1154 112 CHIP_RS300,
1da177e4
LT		 113 CHIP_RV280,
114 CHIP_R300,
414ed537 115 CHIP_R350,
1da177e4 116 CHIP_RV350,
dfab1154 117 CHIP_RV380,
414ed537 118 CHIP_R420,
dfab1154
DA		 119 CHIP_RV410,
120 CHIP_RS400,
1da177e4
LT		 121 CHIP_LAST,
122};
123
124enum radeon_cp_microcode_version {
125 UCODE_R100,
126 UCODE_R200,
127 UCODE_R300,
128};
129
130/*
131 * Chip flags
132 */
133enum radeon_chip_flags {
134 CHIP_FAMILY_MASK = 0x0000ffffUL,
135 CHIP_FLAGS_MASK = 0xffff0000UL,
136 CHIP_IS_MOBILITY = 0x00010000UL,
137 CHIP_IS_IGP = 0x00020000UL,
138 CHIP_SINGLE_CRTC = 0x00040000UL,
139 CHIP_IS_AGP = 0x00080000UL,
b5e89ed5 140 CHIP_HAS_HIERZ = 0x00100000UL,
ea98a92f 141 CHIP_IS_PCIE = 0x00200000UL,
f3dd5c37 142 CHIP_NEW_MEMMAP = 0x00400000UL,
1da177e4
LT		 143};
144
d5ea702f
DA		 145#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
146 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
d985c108
DA		 147#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
148
1da177e4 149typedef struct drm_radeon_freelist {
b5e89ed5
DA		 150 unsigned int age;
151 drm_buf_t *buf;
152 struct drm_radeon_freelist *next;
153 struct drm_radeon_freelist *prev;
1da177e4
LT		 154} drm_radeon_freelist_t;
155
156typedef struct drm_radeon_ring_buffer {
157 u32 *start;
158 u32 *end;
159 int size;
160 int size_l2qw;
161
162 u32 tail;
163 u32 tail_mask;
164 int space;
165
166 int high_mark;
167} drm_radeon_ring_buffer_t;
168
169typedef struct drm_radeon_depth_clear_t {
170 u32 rb3d_cntl;
171 u32 rb3d_zstencilcntl;
172 u32 se_cntl;
173} drm_radeon_depth_clear_t;
174
175struct drm_radeon_driver_file_fields {
176 int64_t radeon_fb_delta;
177};
178
179struct mem_block {
180 struct mem_block *next;
181 struct mem_block *prev;
182 int start;
183 int size;
184 DRMFILE filp; /* 0: free, -1: heap, other: real files */
185};
186
187struct radeon_surface {
188 int refcount;
189 u32 lower;
190 u32 upper;
191 u32 flags;
192};
193
194struct radeon_virt_surface {
195 int surface_index;
196 u32 lower;
197 u32 upper;
198 u32 flags;
199 DRMFILE filp;
200};
201
202typedef struct drm_radeon_private {
203 drm_radeon_ring_buffer_t ring;
204 drm_radeon_sarea_t *sarea_priv;
205
206 u32 fb_location;
d5ea702f
DA		 207 u32 fb_size;
208 int new_memmap;
1da177e4
LT		 209
210 int gart_size;
211 u32 gart_vm_start;
212 unsigned long gart_buffers_offset;
213
214 int cp_mode;
215 int cp_running;
216
b5e89ed5
DA		 217 drm_radeon_freelist_t *head;
218 drm_radeon_freelist_t *tail;
1da177e4
LT		 219 int last_buf;
220 volatile u32 *scratch;
221 int writeback_works;
222
223 int usec_timeout;
224
225 int microcode_version;
226
1da177e4
LT		 227 struct {
228 u32 boxes;
229 int freelist_timeouts;
230 int freelist_loops;
231 int requested_bufs;
232 int last_frame_reads;
233 int last_clear_reads;
234 int clears;
235 int texture_uploads;
236 } stats;
237
238 int do_boxes;
239 int page_flipping;
240 int current_page;
241
242 u32 color_fmt;
243 unsigned int front_offset;
244 unsigned int front_pitch;
245 unsigned int back_offset;
246 unsigned int back_pitch;
247
248 u32 depth_fmt;
249 unsigned int depth_offset;
250 unsigned int depth_pitch;
251
252 u32 front_pitch_offset;
253 u32 back_pitch_offset;
254 u32 depth_pitch_offset;
255
256 drm_radeon_depth_clear_t depth_clear;
b5e89ed5 257
1da177e4
LT		 258 unsigned long ring_offset;
259 unsigned long ring_rptr_offset;
260 unsigned long buffers_offset;
261 unsigned long gart_textures_offset;
262
263 drm_local_map_t *sarea;
264 drm_local_map_t *mmio;
265 drm_local_map_t *cp_ring;
266 drm_local_map_t *ring_rptr;
267 drm_local_map_t *gart_textures;
268
269 struct mem_block *gart_heap;
270 struct mem_block *fb_heap;
271
272 /* SW interrupt */
b5e89ed5
DA		 273 wait_queue_head_t swi_queue;
274 atomic_t swi_emitted;
1da177e4
LT		 275
276 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
b5e89ed5 277 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
1da177e4 278
b5e89ed5
DA		 279 unsigned long pcigart_offset;
280 drm_ati_pcigart_info gart_info;
ea98a92f 281
ee4621f0
DA		 282 u32 scratch_ages[5];
283
1da177e4
LT		 284 /* starting from here on, data is preserved accross an open */
285 uint32_t flags; /* see radeon_chip_flags */
286} drm_radeon_private_t;
287
288typedef struct drm_radeon_buf_priv {
289 u32 age;
290} drm_radeon_buf_priv_t;
291
b3a83639
DA		 292typedef struct drm_radeon_kcmd_buffer {
293 int bufsz;
294 char *buf;
295 int nbox;
296 drm_clip_rect_t __user *boxes;
297} drm_radeon_kcmd_buffer_t;
298
689b9d74 299extern int radeon_no_wb;
b3a83639
DA		 300extern drm_ioctl_desc_t radeon_ioctls[];
301extern int radeon_max_ioctl;
302
1da177e4 303 /* radeon_cp.c */
b5e89ed5
DA		 304extern int radeon_cp_init(DRM_IOCTL_ARGS);
305extern int radeon_cp_start(DRM_IOCTL_ARGS);
306extern int radeon_cp_stop(DRM_IOCTL_ARGS);
307extern int radeon_cp_reset(DRM_IOCTL_ARGS);
308extern int radeon_cp_idle(DRM_IOCTL_ARGS);
309extern int radeon_cp_resume(DRM_IOCTL_ARGS);
310extern int radeon_engine_reset(DRM_IOCTL_ARGS);
311extern int radeon_fullscreen(DRM_IOCTL_ARGS);
312extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
1da177e4 313
b5e89ed5
DA		 314extern void radeon_freelist_reset(drm_device_t * dev);
315extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
1da177e4 316
b5e89ed5 317extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
1da177e4 318
b5e89ed5 319extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
1da177e4
LT		 320
321extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 322extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 323extern int radeon_driver_postcleanup(struct drm_device *dev);
324
b5e89ed5
DA		 325extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
326extern int radeon_mem_free(DRM_IOCTL_ARGS);
327extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
328extern void radeon_mem_takedown(struct mem_block **heap);
329extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
1da177e4
LT		 330
331 /* radeon_irq.c */
b5e89ed5
DA		 332extern int radeon_irq_emit(DRM_IOCTL_ARGS);
333extern int radeon_irq_wait(DRM_IOCTL_ARGS);
334
335extern void radeon_do_release(drm_device_t * dev);
336extern int radeon_driver_vblank_wait(drm_device_t * dev,
337 unsigned int *sequence);
338extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
339extern void radeon_driver_irq_preinstall(drm_device_t * dev);
340extern void radeon_driver_irq_postinstall(drm_device_t * dev);
341extern void radeon_driver_irq_uninstall(drm_device_t * dev);
1da177e4 342
22eae947
DA		 343extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
344extern int radeon_driver_unload(struct drm_device *dev);
345extern int radeon_driver_firstopen(struct drm_device *dev);
346extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp);
347extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp);
348extern void radeon_driver_lastclose(drm_device_t * dev);
349extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv);
9a186645
DA		 350extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
351 unsigned long arg);
352
414ed537
DA		 353/* r300_cmdbuf.c */
354extern void r300_init_reg_flags(void);
355
b5e89ed5
DA		 356extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
357 drm_file_t * filp_priv,
b3a83639 358 drm_radeon_kcmd_buffer_t * cmdbuf);
414ed537 359
1da177e4
LT		 360/* Flags for stats.boxes
361 */
362#define RADEON_BOX_DMA_IDLE 0x1
363#define RADEON_BOX_RING_FULL 0x2
364#define RADEON_BOX_FLIP 0x4
365#define RADEON_BOX_WAIT_IDLE 0x8
366#define RADEON_BOX_TEXTURE_LOAD 0x10
367
1da177e4
LT		 368/* Register definitions, register access macros and drmAddMap constants
369 * for Radeon kernel driver.
370 */
371
372#define RADEON_AGP_COMMAND 0x0f60
d985c108
DA		 373#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
374# define RADEON_AGP_ENABLE (1<<8)
1da177e4
LT		 375#define RADEON_AUX_SCISSOR_CNTL 0x26f0
376# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
377# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
378# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
379# define RADEON_SCISSOR_0_ENABLE (1 << 28)
380# define RADEON_SCISSOR_1_ENABLE (1 << 29)
381# define RADEON_SCISSOR_2_ENABLE (1 << 30)
382
383#define RADEON_BUS_CNTL 0x0030
384# define RADEON_BUS_MASTER_DIS (1 << 6)
385
386#define RADEON_CLOCK_CNTL_DATA 0x000c
387# define RADEON_PLL_WR_EN (1 << 7)
388#define RADEON_CLOCK_CNTL_INDEX 0x0008
389#define RADEON_CONFIG_APER_SIZE 0x0108
d985c108 390#define RADEON_CONFIG_MEMSIZE 0x00f8
1da177e4
LT		 391#define RADEON_CRTC_OFFSET 0x0224
392#define RADEON_CRTC_OFFSET_CNTL 0x0228
393# define RADEON_CRTC_TILE_EN (1 << 15)
394# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
395#define RADEON_CRTC2_OFFSET 0x0324
396#define RADEON_CRTC2_OFFSET_CNTL 0x0328
397
ea98a92f
DA		 398#define RADEON_PCIE_INDEX 0x0030
399#define RADEON_PCIE_DATA 0x0034
400#define RADEON_PCIE_TX_GART_CNTL 0x10
401# define RADEON_PCIE_TX_GART_EN (1 << 0)
402# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
403# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
404# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
405# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
406# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
407# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
408# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
409#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
410#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
411#define RADEON_PCIE_TX_GART_BASE 0x13
412#define RADEON_PCIE_TX_GART_START_LO 0x14
413#define RADEON_PCIE_TX_GART_START_HI 0x15
414#define RADEON_PCIE_TX_GART_END_LO 0x16
415#define RADEON_PCIE_TX_GART_END_HI 0x17
416
414ed537
DA		 417#define RADEON_MPP_TB_CONFIG 0x01c0
418#define RADEON_MEM_CNTL 0x0140
419#define RADEON_MEM_SDRAM_MODE_REG 0x0158
420#define RADEON_AGP_BASE 0x0170
421
1da177e4
LT		 422#define RADEON_RB3D_COLOROFFSET 0x1c40
423#define RADEON_RB3D_COLORPITCH 0x1c48
424
425#define RADEON_DP_GUI_MASTER_CNTL 0x146c
426# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
427# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
428# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
429# define RADEON_GMC_BRUSH_NONE (15 << 4)
430# define RADEON_GMC_DST_16BPP (4 << 8)
431# define RADEON_GMC_DST_24BPP (5 << 8)
432# define RADEON_GMC_DST_32BPP (6 << 8)
433# define RADEON_GMC_DST_DATATYPE_SHIFT 8
434# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
435# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
436# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
437# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
438# define RADEON_GMC_WR_MSK_DIS (1 << 30)
439# define RADEON_ROP3_S 0x00cc0000
440# define RADEON_ROP3_P 0x00f00000
441#define RADEON_DP_WRITE_MASK 0x16cc
442#define RADEON_DST_PITCH_OFFSET 0x142c
443#define RADEON_DST_PITCH_OFFSET_C 0x1c80
444# define RADEON_DST_TILE_LINEAR (0 << 30)
445# define RADEON_DST_TILE_MACRO (1 << 30)
446# define RADEON_DST_TILE_MICRO (2 << 30)
447# define RADEON_DST_TILE_BOTH (3 << 30)
448
449#define RADEON_SCRATCH_REG0 0x15e0
450#define RADEON_SCRATCH_REG1 0x15e4
451#define RADEON_SCRATCH_REG2 0x15e8
452#define RADEON_SCRATCH_REG3 0x15ec
453#define RADEON_SCRATCH_REG4 0x15f0
454#define RADEON_SCRATCH_REG5 0x15f4
455#define RADEON_SCRATCH_UMSK 0x0770
456#define RADEON_SCRATCH_ADDR 0x0774
457
458#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
459
460#define GET_SCRATCH( x ) (dev_priv->writeback_works \
461 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
462 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
463
1da177e4
LT		 464#define RADEON_GEN_INT_CNTL 0x0040
465# define RADEON_CRTC_VBLANK_MASK (1 << 0)
466# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
467# define RADEON_SW_INT_ENABLE (1 << 25)
468
469#define RADEON_GEN_INT_STATUS 0x0044
470# define RADEON_CRTC_VBLANK_STAT (1 << 0)
471# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
472# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
473# define RADEON_SW_INT_TEST (1 << 25)
474# define RADEON_SW_INT_TEST_ACK (1 << 25)
475# define RADEON_SW_INT_FIRE (1 << 26)
476
477#define RADEON_HOST_PATH_CNTL 0x0130
478# define RADEON_HDP_SOFT_RESET (1 << 26)
479# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
480# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
481
482#define RADEON_ISYNC_CNTL 0x1724
483# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
484# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
485# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
486# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
487# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
488# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
489
490#define RADEON_RBBM_GUICNTL 0x172c
491# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
492# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
493# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
494# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
495
496#define RADEON_MC_AGP_LOCATION 0x014c
497#define RADEON_MC_FB_LOCATION 0x0148
498#define RADEON_MCLK_CNTL 0x0012
499# define RADEON_FORCEON_MCLKA (1 << 16)
500# define RADEON_FORCEON_MCLKB (1 << 17)
501# define RADEON_FORCEON_YCLKA (1 << 18)
502# define RADEON_FORCEON_YCLKB (1 << 19)
503# define RADEON_FORCEON_MC (1 << 20)
504# define RADEON_FORCEON_AIC (1 << 21)
505
506#define RADEON_PP_BORDER_COLOR_0 0x1d40
507#define RADEON_PP_BORDER_COLOR_1 0x1d44
508#define RADEON_PP_BORDER_COLOR_2 0x1d48
509#define RADEON_PP_CNTL 0x1c38
510# define RADEON_SCISSOR_ENABLE (1 << 1)
511#define RADEON_PP_LUM_MATRIX 0x1d00
512#define RADEON_PP_MISC 0x1c14
513#define RADEON_PP_ROT_MATRIX_0 0x1d58
514#define RADEON_PP_TXFILTER_0 0x1c54
515#define RADEON_PP_TXOFFSET_0 0x1c5c
516#define RADEON_PP_TXFILTER_1 0x1c6c
517#define RADEON_PP_TXFILTER_2 0x1c84
518
519#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
520# define RADEON_RB2D_DC_FLUSH (3 << 0)
521# define RADEON_RB2D_DC_FREE (3 << 2)
522# define RADEON_RB2D_DC_FLUSH_ALL 0xf
523# define RADEON_RB2D_DC_BUSY (1 << 31)
524#define RADEON_RB3D_CNTL 0x1c3c
525# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
526# define RADEON_PLANE_MASK_ENABLE (1 << 1)
527# define RADEON_DITHER_ENABLE (1 << 2)
528# define RADEON_ROUND_ENABLE (1 << 3)
529# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
530# define RADEON_DITHER_INIT (1 << 5)
531# define RADEON_ROP_ENABLE (1 << 6)
532# define RADEON_STENCIL_ENABLE (1 << 7)
533# define RADEON_Z_ENABLE (1 << 8)
534# define RADEON_ZBLOCK16 (1 << 15)
535#define RADEON_RB3D_DEPTHOFFSET 0x1c24
536#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
537#define RADEON_RB3D_DEPTHPITCH 0x1c28
538#define RADEON_RB3D_PLANEMASK 0x1d84
539#define RADEON_RB3D_STENCILREFMASK 0x1d7c
540#define RADEON_RB3D_ZCACHE_MODE 0x3250
541#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
542# define RADEON_RB3D_ZC_FLUSH (1 << 0)
543# define RADEON_RB3D_ZC_FREE (1 << 2)
544# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
545# define RADEON_RB3D_ZC_BUSY (1 << 31)
546#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
547# define RADEON_Z_TEST_MASK (7 << 4)
548# define RADEON_Z_TEST_ALWAYS (7 << 4)
549# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
550# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
551# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
552# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
553# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
554# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
555# define RADEON_FORCE_Z_DIRTY (1 << 29)
556# define RADEON_Z_WRITE_ENABLE (1 << 30)
557# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
558#define RADEON_RBBM_SOFT_RESET 0x00f0
559# define RADEON_SOFT_RESET_CP (1 << 0)
560# define RADEON_SOFT_RESET_HI (1 << 1)
561# define RADEON_SOFT_RESET_SE (1 << 2)
562# define RADEON_SOFT_RESET_RE (1 << 3)
563# define RADEON_SOFT_RESET_PP (1 << 4)
564# define RADEON_SOFT_RESET_E2 (1 << 5)
565# define RADEON_SOFT_RESET_RB (1 << 6)
566# define RADEON_SOFT_RESET_HDP (1 << 7)
567#define RADEON_RBBM_STATUS 0x0e40
568# define RADEON_RBBM_FIFOCNT_MASK 0x007f
569# define RADEON_RBBM_ACTIVE (1 << 31)
570#define RADEON_RE_LINE_PATTERN 0x1cd0
571#define RADEON_RE_MISC 0x26c4
572#define RADEON_RE_TOP_LEFT 0x26c0
573#define RADEON_RE_WIDTH_HEIGHT 0x1c44
574#define RADEON_RE_STIPPLE_ADDR 0x1cc8
575#define RADEON_RE_STIPPLE_DATA 0x1ccc
576
577#define RADEON_SCISSOR_TL_0 0x1cd8
578#define RADEON_SCISSOR_BR_0 0x1cdc
579#define RADEON_SCISSOR_TL_1 0x1ce0
580#define RADEON_SCISSOR_BR_1 0x1ce4
581#define RADEON_SCISSOR_TL_2 0x1ce8
582#define RADEON_SCISSOR_BR_2 0x1cec
583#define RADEON_SE_COORD_FMT 0x1c50
584#define RADEON_SE_CNTL 0x1c4c
585# define RADEON_FFACE_CULL_CW (0 << 0)
586# define RADEON_BFACE_SOLID (3 << 1)
587# define RADEON_FFACE_SOLID (3 << 3)
588# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
589# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
590# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
591# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
592# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
593# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
594# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
595# define RADEON_FOG_SHADE_FLAT (1 << 14)
596# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
597# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
598# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
599# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
600# define RADEON_ROUND_MODE_TRUNC (0 << 28)
601# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
602#define RADEON_SE_CNTL_STATUS 0x2140
603#define RADEON_SE_LINE_WIDTH 0x1db8
604#define RADEON_SE_VPORT_XSCALE 0x1d98
605#define RADEON_SE_ZBIAS_FACTOR 0x1db0
606#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
607#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
608#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
609# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
610# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
611#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
612#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
613# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
614#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
615#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
616#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
617#define RADEON_SURFACE_CNTL 0x0b00
618# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
619# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
620# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
621# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
622# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
623# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
624# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
625# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
626# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
627#define RADEON_SURFACE0_INFO 0x0b0c
628# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
629# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
630# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
631# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
632# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
633# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
634#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
635#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
636# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
637#define RADEON_SURFACE1_INFO 0x0b1c
638#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
639#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
640#define RADEON_SURFACE2_INFO 0x0b2c
641#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
642#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
643#define RADEON_SURFACE3_INFO 0x0b3c
644#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
645#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
646#define RADEON_SURFACE4_INFO 0x0b4c
647#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
648#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
649#define RADEON_SURFACE5_INFO 0x0b5c
650#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
651#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
652#define RADEON_SURFACE6_INFO 0x0b6c
653#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
654#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
655#define RADEON_SURFACE7_INFO 0x0b7c
656#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
657#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
658#define RADEON_SW_SEMAPHORE 0x013c
659
660#define RADEON_WAIT_UNTIL 0x1720
661# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
d985c108
DA		 662# define RADEON_WAIT_2D_IDLE (1 << 14)
663# define RADEON_WAIT_3D_IDLE (1 << 15)
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LT		 664# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
665# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
666# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
667
668#define RADEON_RB3D_ZMASKOFFSET 0x3234
669#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
670# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
671# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
672
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LT		 673/* CP registers */
674#define RADEON_CP_ME_RAM_ADDR 0x07d4
675#define RADEON_CP_ME_RAM_RADDR 0x07d8
676#define RADEON_CP_ME_RAM_DATAH 0x07dc
677#define RADEON_CP_ME_RAM_DATAL 0x07e0
678
679#define RADEON_CP_RB_BASE 0x0700
680#define RADEON_CP_RB_CNTL 0x0704
681# define RADEON_BUF_SWAP_32BIT (2 << 16)
682#define RADEON_CP_RB_RPTR_ADDR 0x070c
683#define RADEON_CP_RB_RPTR 0x0710
684#define RADEON_CP_RB_WPTR 0x0714
685
686#define RADEON_CP_RB_WPTR_DELAY 0x0718
687# define RADEON_PRE_WRITE_TIMER_SHIFT 0
688# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
689
690#define RADEON_CP_IB_BASE 0x0738
691
692#define RADEON_CP_CSQ_CNTL 0x0740
693# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
694# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
695# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
696# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
697# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
698# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
699# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
700
701#define RADEON_AIC_CNTL 0x01d0
702# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
703#define RADEON_AIC_STAT 0x01d4
704#define RADEON_AIC_PT_BASE 0x01d8
705#define RADEON_AIC_LO_ADDR 0x01dc
706#define RADEON_AIC_HI_ADDR 0x01e0
707#define RADEON_AIC_TLB_ADDR 0x01e4
708#define RADEON_AIC_TLB_DATA 0x01e8
709
710/* CP command packets */
711#define RADEON_CP_PACKET0 0x00000000
712# define RADEON_ONE_REG_WR (1 << 15)
713#define RADEON_CP_PACKET1 0x40000000
714#define RADEON_CP_PACKET2 0x80000000
715#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 716# define RADEON_CP_NOP 0x00001000
717# define RADEON_CP_NEXT_CHAR 0x00001900
718# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
719# define RADEON_CP_SET_SCISSORS 0x00001E00
b5e89ed5 720 /* GEN_INDX_PRIM is unsupported starting with R300 */
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LT		 721# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
722# define RADEON_WAIT_FOR_IDLE 0x00002600
723# define RADEON_3D_DRAW_VBUF 0x00002800
724# define RADEON_3D_DRAW_IMMD 0x00002900
725# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 726# define RADEON_CP_LOAD_PALETTE 0x00002C00
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LT		 727# define RADEON_3D_LOAD_VBPNTR 0x00002F00
728# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
729# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
730# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 731# define RADEON_CP_INDX_BUFFER 0x00003300
732# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
733# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
734# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 735# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 736# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
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LT		 737# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
738# define RADEON_CNTL_PAINT_MULTI 0x00009A00
739# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
740# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
741
742#define RADEON_CP_PACKET_MASK 0xC0000000
743#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
744#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
745#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
746#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
747
748#define RADEON_VTX_Z_PRESENT (1 << 31)
749#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
750
751#define RADEON_PRIM_TYPE_NONE (0 << 0)
752#define RADEON_PRIM_TYPE_POINT (1 << 0)
753#define RADEON_PRIM_TYPE_LINE (2 << 0)
754#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
755#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
756#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
757#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
758#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
759#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
760#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
761#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
762#define RADEON_PRIM_TYPE_MASK 0xf
763#define RADEON_PRIM_WALK_IND (1 << 4)
764#define RADEON_PRIM_WALK_LIST (2 << 4)
765#define RADEON_PRIM_WALK_RING (3 << 4)
766#define RADEON_COLOR_ORDER_BGRA (0 << 6)
767#define RADEON_COLOR_ORDER_RGBA (1 << 6)
768#define RADEON_MAOS_ENABLE (1 << 7)
769#define RADEON_VTX_FMT_R128_MODE (0 << 8)
770#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
771#define RADEON_NUM_VERTICES_SHIFT 16
772
773#define RADEON_COLOR_FORMAT_CI8 2
774#define RADEON_COLOR_FORMAT_ARGB1555 3
775#define RADEON_COLOR_FORMAT_RGB565 4
776#define RADEON_COLOR_FORMAT_ARGB8888 6
777#define RADEON_COLOR_FORMAT_RGB332 7
778#define RADEON_COLOR_FORMAT_RGB8 9
779#define RADEON_COLOR_FORMAT_ARGB4444 15
780
781#define RADEON_TXFORMAT_I8 0
782#define RADEON_TXFORMAT_AI88 1
783#define RADEON_TXFORMAT_RGB332 2
784#define RADEON_TXFORMAT_ARGB1555 3
785#define RADEON_TXFORMAT_RGB565 4
786#define RADEON_TXFORMAT_ARGB4444 5
787#define RADEON_TXFORMAT_ARGB8888 6
788#define RADEON_TXFORMAT_RGBA8888 7
789#define RADEON_TXFORMAT_Y8 8
790#define RADEON_TXFORMAT_VYUY422 10
791#define RADEON_TXFORMAT_YVYU422 11
792#define RADEON_TXFORMAT_DXT1 12
793#define RADEON_TXFORMAT_DXT23 14
794#define RADEON_TXFORMAT_DXT45 15
795
796#define R200_PP_TXCBLEND_0 0x2f00
797#define R200_PP_TXCBLEND_1 0x2f10
798#define R200_PP_TXCBLEND_2 0x2f20
799#define R200_PP_TXCBLEND_3 0x2f30
800#define R200_PP_TXCBLEND_4 0x2f40
801#define R200_PP_TXCBLEND_5 0x2f50
802#define R200_PP_TXCBLEND_6 0x2f60
803#define R200_PP_TXCBLEND_7 0x2f70
b5e89ed5 804#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1da177e4
LT		 805#define R200_PP_TFACTOR_0 0x2ee0
806#define R200_SE_VTX_FMT_0 0x2088
807#define R200_SE_VAP_CNTL 0x2080
808#define R200_SE_TCL_MATRIX_SEL_0 0x2230
b5e89ed5
DA		 809#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
810#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
811#define R200_PP_TXFILTER_5 0x2ca0
812#define R200_PP_TXFILTER_4 0x2c80
813#define R200_PP_TXFILTER_3 0x2c60
814#define R200_PP_TXFILTER_2 0x2c40
815#define R200_PP_TXFILTER_1 0x2c20
816#define R200_PP_TXFILTER_0 0x2c00
1da177e4
LT		 817#define R200_PP_TXOFFSET_5 0x2d78
818#define R200_PP_TXOFFSET_4 0x2d60
819#define R200_PP_TXOFFSET_3 0x2d48
820#define R200_PP_TXOFFSET_2 0x2d30
821#define R200_PP_TXOFFSET_1 0x2d18
822#define R200_PP_TXOFFSET_0 0x2d00
823
824#define R200_PP_CUBIC_FACES_0 0x2c18
825#define R200_PP_CUBIC_FACES_1 0x2c38
826#define R200_PP_CUBIC_FACES_2 0x2c58
827#define R200_PP_CUBIC_FACES_3 0x2c78
828#define R200_PP_CUBIC_FACES_4 0x2c98
829#define R200_PP_CUBIC_FACES_5 0x2cb8
830#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
831#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
832#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
833#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
834#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
835#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
836#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
837#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
838#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
839#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
840#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
841#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
842#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
843#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
844#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
845#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
846#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
847#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
848#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
849#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
850#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
851#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
852#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
853#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
854#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
855#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
856#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
857#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
858#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
859#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
860
861#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
862#define R200_SE_VTE_CNTL 0x20b0
863#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
864#define R200_PP_TAM_DEBUG3 0x2d9c
865#define R200_PP_CNTL_X 0x2cc4
866#define R200_SE_VAP_CNTL_STATUS 0x2140
867#define R200_RE_SCISSOR_TL_0 0x1cd8
868#define R200_RE_SCISSOR_TL_1 0x1ce0
869#define R200_RE_SCISSOR_TL_2 0x1ce8
b5e89ed5 870#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1da177e4
LT		 871#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
872#define R200_SE_VTX_STATE_CNTL 0x2180
873#define R200_RE_POINTSIZE 0x2648
874#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
875
b5e89ed5 876#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1da177e4
LT		 877#define RADEON_PP_TEX_SIZE_1 0x1d0c
878#define RADEON_PP_TEX_SIZE_2 0x1d14
879
880#define RADEON_PP_CUBIC_FACES_0 0x1d24
881#define RADEON_PP_CUBIC_FACES_1 0x1d28
882#define RADEON_PP_CUBIC_FACES_2 0x1d2c
883#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
884#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
885#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
886
887#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
888#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
889#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
890#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
891#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
892#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
893#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
894#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
895#define R200_3D_DRAW_IMMD_2 0xC0003500
896#define R200_SE_VTX_FMT_1 0x208c
b5e89ed5 897#define R200_RE_CNTL 0x1c50
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LT		 898
899#define R200_RB3D_BLENDCOLOR 0x3218
900
901#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
902
903#define R200_PP_TRI_PERF 0x2cf8
904
9d17601c 905#define R200_PP_AFS_0 0x2f80
b5e89ed5 906#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
9d17601c 907
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LT		 908/* Constants */
909#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
910
911#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
912#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
913#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
914#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
915#define RADEON_LAST_DISPATCH 1
916
917#define RADEON_MAX_VB_AGE 0x7fffffff
918#define RADEON_MAX_VB_VERTS (0xffff)
919
920#define RADEON_RING_HIGH_MARK 128
921
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DA		 922#define RADEON_PCIGART_TABLE_SIZE (32*1024)
923
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LT		 924#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
925#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
926#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
927#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
928
929#define RADEON_WRITE_PLL( addr, val ) \
930do { \
931 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
932 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
933 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
934} while (0)
935
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DA		 936#define RADEON_WRITE_PCIE( addr, val ) \
937do { \
938 RADEON_WRITE8( RADEON_PCIE_INDEX, \
939 ((addr) & 0xff)); \
940 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
941} while (0)
942
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LT		 943#define CP_PACKET0( reg, n ) \
944 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
945#define CP_PACKET0_TABLE( reg, n ) \
946 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
947#define CP_PACKET1( reg0, reg1 ) \
948 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
949#define CP_PACKET2() \
950 (RADEON_CP_PACKET2)
951#define CP_PACKET3( pkt, n ) \
952 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
953
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LT		 954/* ================================================================
955 * Engine control helper macros
956 */
957
958#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
959 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
960 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
961 RADEON_WAIT_HOST_IDLECLEAN) ); \
962} while (0)
963
964#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
965 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
966 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
967 RADEON_WAIT_HOST_IDLECLEAN) ); \
968} while (0)
969
970#define RADEON_WAIT_UNTIL_IDLE() do { \
971 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
972 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
973 RADEON_WAIT_3D_IDLECLEAN | \
974 RADEON_WAIT_HOST_IDLECLEAN) ); \
975} while (0)
976
977#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
978 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
979 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
980} while (0)
981
982#define RADEON_FLUSH_CACHE() do { \
983 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
984 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
985} while (0)
986
987#define RADEON_PURGE_CACHE() do { \
988 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
989 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
990} while (0)
991
992#define RADEON_FLUSH_ZCACHE() do { \
993 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
994 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
995} while (0)
996
997#define RADEON_PURGE_ZCACHE() do { \
998 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
999 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1000} while (0)
1001
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LT		 1002/* ================================================================
1003 * Misc helper macros
1004 */
1005
b5e89ed5 1006/* Perfbox functionality only.
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LT		 1007 */
1008#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1009do { \
1010 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1011 u32 head = GET_RING_HEAD( dev_priv ); \
1012 if (head == dev_priv->ring.tail) \
1013 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1014 } \
1015} while (0)
1016
1017#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1018do { \
1019 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1020 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1021 int __ret = radeon_do_cp_idle( dev_priv ); \
1022 if ( __ret ) return __ret; \
1023 sarea_priv->last_dispatch = 0; \
1024 radeon_freelist_reset( dev ); \
1025 } \
1026} while (0)
1027
1028#define RADEON_DISPATCH_AGE( age ) do { \
1029 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1030 OUT_RING( age ); \
1031} while (0)
1032
1033#define RADEON_FRAME_AGE( age ) do { \
1034 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1035 OUT_RING( age ); \
1036} while (0)
1037
1038#define RADEON_CLEAR_AGE( age ) do { \
1039 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1040 OUT_RING( age ); \
1041} while (0)
1042
1da177e4
LT		 1043/* ================================================================
1044 * Ring control
1045 */
1046
1047#define RADEON_VERBOSE 0
1048
1049#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1050
1051#define BEGIN_RING( n ) do { \
1052 if ( RADEON_VERBOSE ) { \
1053 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1054 n, __FUNCTION__ ); \
1055 } \
1056 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1057 COMMIT_RING(); \
1058 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1059 } \
1060 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1061 ring = dev_priv->ring.start; \
1062 write = dev_priv->ring.tail; \
1063 mask = dev_priv->ring.tail_mask; \
1064} while (0)
1065
1066#define ADVANCE_RING() do { \
1067 if ( RADEON_VERBOSE ) { \
1068 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1069 write, dev_priv->ring.tail ); \
1070 } \
1071 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1072 DRM_ERROR( \
1073 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1074 ((dev_priv->ring.tail + _nr) & mask), \
1075 write, __LINE__); \
1076 } else \
1077 dev_priv->ring.tail = write; \
1078} while (0)
1079
1080#define COMMIT_RING() do { \
1081 /* Flush writes to ring */ \
1082 DRM_MEMORYBARRIER(); \
1083 GET_RING_HEAD( dev_priv ); \
1084 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1085 /* read from PCI bus to ensure correct posting */ \
1086 RADEON_READ( RADEON_CP_RB_RPTR ); \
1087} while (0)
1088
1089#define OUT_RING( x ) do { \
1090 if ( RADEON_VERBOSE ) { \
1091 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1092 (unsigned int)(x), write ); \
1093 } \
1094 ring[write++] = (x); \
1095 write &= mask; \
1096} while (0)
1097
1098#define OUT_RING_REG( reg, val ) do { \
1099 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1100 OUT_RING( val ); \
1101} while (0)
1102
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LT		 1103#define OUT_RING_TABLE( tab, sz ) do { \
1104 int _size = (sz); \
1105 int *_tab = (int *)(tab); \
1106 \
1107 if (write + _size > mask) { \
1108 int _i = (mask+1) - write; \
1109 _size -= _i; \
1110 while (_i > 0 ) { \
1111 *(int *)(ring + write) = *_tab++; \
1112 write++; \
1113 _i--; \
1114 } \
1115 write = 0; \
1116 _tab += _i; \
1117 } \
1da177e4
LT		 1118 while (_size > 0) { \
1119 *(ring + write) = *_tab++; \
1120 write++; \
1121 _size--; \
1122 } \
1123 write &= mask; \
1124} while (0)
1125
b5e89ed5 1126#endif /* __RADEON_DRV_H__ */
Linux kernel - Deliverables
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