[deliverable/linux.git] / drivers / char / hw_random / omap-rng.c

/*
 * omap-rng.c - RNG driver for TI OMAP CPU family
 *
 * Author: Deepak Saxena <dsaxena@plexity.net>
 *
 * Copyright 2005 (c) MontaVista Software, Inc.
 *
 * Mostly based on original driver:
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
 *
 * This file is licensed under  the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/random.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/hw_random.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/interrupt.h>

#include <asm/io.h>

#define RNG_REG_STATUS_RDY			(1 << 0)

#define RNG_REG_INTACK_RDY_MASK			(1 << 0)
#define RNG_REG_INTACK_SHUTDOWN_OFLO_MASK	(1 << 1)
#define RNG_SHUTDOWN_OFLO_MASK			(1 << 1)

#define RNG_CONTROL_STARTUP_CYCLES_SHIFT	16
#define RNG_CONTROL_STARTUP_CYCLES_MASK		(0xffff << 16)
#define RNG_CONTROL_ENABLE_TRNG_SHIFT		10
#define RNG_CONTROL_ENABLE_TRNG_MASK		(1 << 10)

#define RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT	16
#define RNG_CONFIG_MAX_REFIL_CYCLES_MASK	(0xffff << 16)
#define RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT	0
#define RNG_CONFIG_MIN_REFIL_CYCLES_MASK	(0xff << 0)

#define RNG_CONTROL_STARTUP_CYCLES		0xff
#define RNG_CONFIG_MIN_REFIL_CYCLES		0x21
#define RNG_CONFIG_MAX_REFIL_CYCLES		0x22

#define RNG_ALARMCNT_ALARM_TH_SHIFT		0x0
#define RNG_ALARMCNT_ALARM_TH_MASK		(0xff << 0)
#define RNG_ALARMCNT_SHUTDOWN_TH_SHIFT		16
#define RNG_ALARMCNT_SHUTDOWN_TH_MASK		(0x1f << 16)
#define RNG_ALARM_THRESHOLD			0xff
#define RNG_SHUTDOWN_THRESHOLD			0x4

#define RNG_REG_FROENABLE_MASK			0xffffff
#define RNG_REG_FRODETUNE_MASK			0xffffff

#define OMAP2_RNG_OUTPUT_SIZE			0x4
#define OMAP4_RNG_OUTPUT_SIZE			0x8

enum {
	RNG_OUTPUT_L_REG = 0,
	RNG_OUTPUT_H_REG,
	RNG_STATUS_REG,
	RNG_INTMASK_REG,
	RNG_INTACK_REG,
	RNG_CONTROL_REG,
	RNG_CONFIG_REG,
	RNG_ALARMCNT_REG,
	RNG_FROENABLE_REG,
	RNG_FRODETUNE_REG,
	RNG_ALARMMASK_REG,
	RNG_ALARMSTOP_REG,
	RNG_REV_REG,
	RNG_SYSCONFIG_REG,
};

static const u16 reg_map_omap2[] = {
	[RNG_OUTPUT_L_REG]	= 0x0,
	[RNG_STATUS_REG]	= 0x4,
	[RNG_CONFIG_REG]	= 0x28,
	[RNG_REV_REG]		= 0x3c,
	[RNG_SYSCONFIG_REG]	= 0x40,
};

static const u16 reg_map_omap4[] = {
	[RNG_OUTPUT_L_REG]	= 0x0,
	[RNG_OUTPUT_H_REG]	= 0x4,
	[RNG_STATUS_REG]	= 0x8,
	[RNG_INTMASK_REG]	= 0xc,
	[RNG_INTACK_REG]	= 0x10,
	[RNG_CONTROL_REG]	= 0x14,
	[RNG_CONFIG_REG]	= 0x18,
	[RNG_ALARMCNT_REG]	= 0x1c,
	[RNG_FROENABLE_REG]	= 0x20,
	[RNG_FRODETUNE_REG]	= 0x24,
	[RNG_ALARMMASK_REG]	= 0x28,
	[RNG_ALARMSTOP_REG]	= 0x2c,
	[RNG_REV_REG]		= 0x1FE0,
	[RNG_SYSCONFIG_REG]	= 0x1FE4,
};

struct omap_rng_dev;
/**
 * struct omap_rng_pdata - RNG IP block-specific data
 * @regs: Pointer to the register offsets structure.
 * @data_size: No. of bytes in RNG output.
 * @data_present: Callback to determine if data is available.
 * @init: Callback for IP specific initialization sequence.
 * @cleanup: Callback for IP specific cleanup sequence.
 */
struct omap_rng_pdata {
	u16	*regs;
	u32	data_size;
	u32	(*data_present)(struct omap_rng_dev *priv);
	int	(*init)(struct omap_rng_dev *priv);
	void	(*cleanup)(struct omap_rng_dev *priv);
};

struct omap_rng_dev {
	void __iomem			*base;
	struct device			*dev;
	const struct omap_rng_pdata	*pdata;
};

static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
{
	return __raw_readl(priv->base + priv->pdata->regs[reg]);
}

static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
				      u32 val)
{
	__raw_writel(val, priv->base + priv->pdata->regs[reg]);
}

static int omap_rng_data_present(struct hwrng *rng, int wait)
{
	struct omap_rng_dev *priv;
	int data, i;

	priv = (struct omap_rng_dev *)rng->priv;

	for (i = 0; i < 20; i++) {
		data = priv->pdata->data_present(priv);
		if (data || !wait)
			break;
		/* RNG produces data fast enough (2+ MBit/sec, even
		 * during "rngtest" loads, that these delays don't
		 * seem to trigger.  We *could* use the RNG IRQ, but
		 * that'd be higher overhead ... so why bother?
		 */
		udelay(10);
	}
	return data;
}

static int omap_rng_data_read(struct hwrng *rng, u32 *data)
{
	struct omap_rng_dev *priv;
	u32 data_size, i;

	priv = (struct omap_rng_dev *)rng->priv;
	data_size = priv->pdata->data_size;

	for (i = 0; i < data_size / sizeof(u32); i++)
		data[i] = omap_rng_read(priv, RNG_OUTPUT_L_REG + i);

	if (priv->pdata->regs[RNG_INTACK_REG])
		omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
	return data_size;
}

static int omap_rng_init(struct hwrng *rng)
{
	struct omap_rng_dev *priv;

	priv = (struct omap_rng_dev *)rng->priv;
	return priv->pdata->init(priv);
}

static void omap_rng_cleanup(struct hwrng *rng)
{
	struct omap_rng_dev *priv;

	priv = (struct omap_rng_dev *)rng->priv;
	priv->pdata->cleanup(priv);
}

static struct hwrng omap_rng_ops = {
	.name		= "omap",
	.data_present	= omap_rng_data_present,
	.data_read	= omap_rng_data_read,
	.init		= omap_rng_init,
	.cleanup	= omap_rng_cleanup,
};

static inline u32 omap2_rng_data_present(struct omap_rng_dev *priv)
{
	return omap_rng_read(priv, RNG_STATUS_REG) ? 0 : 1;
}

static int omap2_rng_init(struct omap_rng_dev *priv)
{
	omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x1);
	return 0;
}

static void omap2_rng_cleanup(struct omap_rng_dev *priv)
{
	omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x0);
}

static struct omap_rng_pdata omap2_rng_pdata = {
	.regs		= (u16 *)reg_map_omap2,
	.data_size	= OMAP2_RNG_OUTPUT_SIZE,
	.data_present	= omap2_rng_data_present,
	.init		= omap2_rng_init,
	.cleanup	= omap2_rng_cleanup,
};

#if defined(CONFIG_OF)
static inline u32 omap4_rng_data_present(struct omap_rng_dev *priv)
{
	return omap_rng_read(priv, RNG_STATUS_REG) & RNG_REG_STATUS_RDY;
}

static int omap4_rng_init(struct omap_rng_dev *priv)
{
	u32 val;

	/* Return if RNG is already running. */
	if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
		return 0;

	val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
	val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
	omap_rng_write(priv, RNG_CONFIG_REG, val);

	omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
	omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
	val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT;
	val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
	omap_rng_write(priv, RNG_ALARMCNT_REG, val);

	val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
	val |= RNG_CONTROL_ENABLE_TRNG_MASK;
	omap_rng_write(priv, RNG_CONTROL_REG, val);

	return 0;
}

static void omap4_rng_cleanup(struct omap_rng_dev *priv)
{
	int val;

	val = omap_rng_read(priv, RNG_CONTROL_REG);
	val &= ~RNG_CONTROL_ENABLE_TRNG_MASK;
	omap_rng_write(priv, RNG_CONTROL_REG, val);
}

static irqreturn_t omap4_rng_irq(int irq, void *dev_id)
{
	struct omap_rng_dev *priv = dev_id;
	u32 fro_detune, fro_enable;

	/*
	 * Interrupt raised by a fro shutdown threshold, do the following:
	 * 1. Clear the alarm events.
	 * 2. De tune the FROs which are shutdown.
	 * 3. Re enable the shutdown FROs.
	 */
	omap_rng_write(priv, RNG_ALARMMASK_REG, 0x0);
	omap_rng_write(priv, RNG_ALARMSTOP_REG, 0x0);

	fro_enable = omap_rng_read(priv, RNG_FROENABLE_REG);
	fro_detune = ~fro_enable & RNG_REG_FRODETUNE_MASK;
	fro_detune = fro_detune | omap_rng_read(priv, RNG_FRODETUNE_REG);
	fro_enable = RNG_REG_FROENABLE_MASK;

	omap_rng_write(priv, RNG_FRODETUNE_REG, fro_detune);
	omap_rng_write(priv, RNG_FROENABLE_REG, fro_enable);

	omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK);

	return IRQ_HANDLED;
}

static struct omap_rng_pdata omap4_rng_pdata = {
	.regs		= (u16 *)reg_map_omap4,
	.data_size	= OMAP4_RNG_OUTPUT_SIZE,
	.data_present	= omap4_rng_data_present,
	.init		= omap4_rng_init,
	.cleanup	= omap4_rng_cleanup,
};

static const struct of_device_id omap_rng_of_match[] = {
		{
			.compatible	= "ti,omap2-rng",
			.data		= &omap2_rng_pdata,
		},
		{
			.compatible	= "ti,omap4-rng",
			.data		= &omap4_rng_pdata,
		},
		{},
};
MODULE_DEVICE_TABLE(of, omap_rng_of_match);

static int of_get_omap_rng_device_details(struct omap_rng_dev *priv,
					  struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct device *dev = &pdev->dev;
	int irq, err;

	match = of_match_device(of_match_ptr(omap_rng_of_match), dev);
	if (!match) {
		dev_err(dev, "no compatible OF match\n");
		return -EINVAL;
	}
	priv->pdata = match->data;

	if (of_device_is_compatible(dev->of_node, "ti,omap4-rng")) {
		irq = platform_get_irq(pdev, 0);
		if (irq < 0) {
			dev_err(dev, "%s: error getting IRQ resource - %d\n",
				__func__, irq);
			return irq;
		}

		err = devm_request_irq(dev, irq, omap4_rng_irq,
				       IRQF_TRIGGER_NONE, dev_name(dev), priv);
		if (err) {
			dev_err(dev, "unable to request irq %d, err = %d\n",
				irq, err);
			return err;
		}
		omap_rng_write(priv, RNG_INTMASK_REG, RNG_SHUTDOWN_OFLO_MASK);
	}
	return 0;
}
#else
static int of_get_omap_rng_device_details(struct omap_rng_dev *omap_rng,
					  struct platform_device *pdev)
{
	return -EINVAL;
}
#endif

static int get_omap_rng_device_details(struct omap_rng_dev *omap_rng)
{
	/* Only OMAP2/3 can be non-DT */
	omap_rng->pdata = &omap2_rng_pdata;
	return 0;
}

static int omap_rng_probe(struct platform_device *pdev)
{
	struct omap_rng_dev *priv;
	struct resource *res;
	struct device *dev = &pdev->dev;
	int ret;

	priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	omap_rng_ops.priv = (unsigned long)priv;
	platform_set_drvdata(pdev, priv);
	priv->dev = dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->base)) {
		ret = PTR_ERR(priv->base);
		goto err_ioremap;
	}

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
				get_omap_rng_device_details(priv);
	if (ret)
		goto err_ioremap;

	ret = hwrng_register(&omap_rng_ops);
	if (ret)
		goto err_register;

	dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
		 omap_rng_read(priv, RNG_REV_REG));

	return 0;

err_register:
	priv->base = NULL;
	pm_runtime_disable(&pdev->dev);
err_ioremap:
	dev_err(dev, "initialization failed.\n");
	return ret;
}

static int omap_rng_remove(struct platform_device *pdev)
{
	struct omap_rng_dev *priv = platform_get_drvdata(pdev);

	hwrng_unregister(&omap_rng_ops);

	priv->pdata->cleanup(priv);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static int __maybe_unused omap_rng_suspend(struct device *dev)
{
	struct omap_rng_dev *priv = dev_get_drvdata(dev);

	priv->pdata->cleanup(priv);
	pm_runtime_put_sync(dev);

	return 0;
}

static int __maybe_unused omap_rng_resume(struct device *dev)
{
	struct omap_rng_dev *priv = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	priv->pdata->init(priv);

	return 0;
}

static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);

static struct platform_driver omap_rng_driver = {
	.driver = {
		.name		= "omap_rng",
		.pm		= &omap_rng_pm,
		.of_match_table = of_match_ptr(omap_rng_of_match),
	},
	.probe		= omap_rng_probe,
	.remove		= omap_rng_remove,
};

module_platform_driver(omap_rng_driver);
MODULE_ALIAS("platform:omap_rng");
MODULE_AUTHOR("Deepak Saxena (and others)");
MODULE_LICENSE("GPL");
Commit	Line	Data
ebc915ad	1	/*
c49a7f18	2	* omap-rng.c - RNG driver for TI OMAP CPU family
ebc915ad MB	3	*
	4	* Author: Deepak Saxena <dsaxena@plexity.net>
	5	*
	6	* Copyright 2005 (c) MontaVista Software, Inc.
	7	*
	8	* Mostly based on original driver:
	9	*
	10	* Copyright (C) 2005 Nokia Corporation
96de0e25	11	* Author: Juha Yrjölä <juha.yrjola@nokia.com>
ebc915ad MB	12	*
	13	* This file is licensed under the terms of the GNU General Public
	14	* License version 2. This program is licensed "as is" without any
	15	* warranty of any kind, whether express or implied.
ebc915ad MB	16	*/
	17
	18	#include <linux/module.h>
	19	#include <linux/init.h>
	20	#include <linux/random.h>
	21	#include <linux/err.h>
af2bc7d2	22	#include <linux/platform_device.h>
ebc915ad	23	#include <linux/hw_random.h>
984e976f	24	#include <linux/delay.h>
02666360	25	#include <linux/slab.h>
665d92fa	26	#include <linux/pm_runtime.h>
c903970c LV	27	#include <linux/of.h>
	28	#include <linux/of_device.h>
	29	#include <linux/of_address.h>
e83872c9	30	#include <linux/interrupt.h>
ebc915ad MB	31
ebc915ad MB	32	#include <asm/io.h>
ebc915ad	33
e83872c9 LV	34	#define RNG_REG_STATUS_RDY (1 << 0)
	35
	36	#define RNG_REG_INTACK_RDY_MASK (1 << 0)
	37	#define RNG_REG_INTACK_SHUTDOWN_OFLO_MASK (1 << 1)
	38	#define RNG_SHUTDOWN_OFLO_MASK (1 << 1)
	39
	40	#define RNG_CONTROL_STARTUP_CYCLES_SHIFT 16
	41	#define RNG_CONTROL_STARTUP_CYCLES_MASK (0xffff << 16)
	42	#define RNG_CONTROL_ENABLE_TRNG_SHIFT 10
	43	#define RNG_CONTROL_ENABLE_TRNG_MASK (1 << 10)
	44
	45	#define RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT 16
	46	#define RNG_CONFIG_MAX_REFIL_CYCLES_MASK (0xffff << 16)
	47	#define RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT 0
	48	#define RNG_CONFIG_MIN_REFIL_CYCLES_MASK (0xff << 0)
	49
	50	#define RNG_CONTROL_STARTUP_CYCLES 0xff
	51	#define RNG_CONFIG_MIN_REFIL_CYCLES 0x21
	52	#define RNG_CONFIG_MAX_REFIL_CYCLES 0x22
	53
	54	#define RNG_ALARMCNT_ALARM_TH_SHIFT 0x0
	55	#define RNG_ALARMCNT_ALARM_TH_MASK (0xff << 0)
	56	#define RNG_ALARMCNT_SHUTDOWN_TH_SHIFT 16
	57	#define RNG_ALARMCNT_SHUTDOWN_TH_MASK (0x1f << 16)
	58	#define RNG_ALARM_THRESHOLD 0xff
	59	#define RNG_SHUTDOWN_THRESHOLD 0x4
	60
	61	#define RNG_REG_FROENABLE_MASK 0xffffff
	62	#define RNG_REG_FRODETUNE_MASK 0xffffff
	63
	64	#define OMAP2_RNG_OUTPUT_SIZE 0x4
	65	#define OMAP4_RNG_OUTPUT_SIZE 0x8
	66
	67	enum {
	68	RNG_OUTPUT_L_REG = 0,
	69	RNG_OUTPUT_H_REG,
	70	RNG_STATUS_REG,
	71	RNG_INTMASK_REG,
	72	RNG_INTACK_REG,
	73	RNG_CONTROL_REG,
	74	RNG_CONFIG_REG,
	75	RNG_ALARMCNT_REG,
	76	RNG_FROENABLE_REG,
	77	RNG_FRODETUNE_REG,
	78	RNG_ALARMMASK_REG,
	79	RNG_ALARMSTOP_REG,
	80	RNG_REV_REG,
	81	RNG_SYSCONFIG_REG,
	82	};
	83
	84	static const u16 reg_map_omap2[] = {
	85	[RNG_OUTPUT_L_REG] = 0x0,
	86	[RNG_STATUS_REG] = 0x4,
	87	[RNG_CONFIG_REG] = 0x28,
	88	[RNG_REV_REG] = 0x3c,
	89	[RNG_SYSCONFIG_REG] = 0x40,
	90	};
	91
	92	static const u16 reg_map_omap4[] = {
	93	[RNG_OUTPUT_L_REG] = 0x0,
	94	[RNG_OUTPUT_H_REG] = 0x4,
	95	[RNG_STATUS_REG] = 0x8,
	96	[RNG_INTMASK_REG] = 0xc,
	97	[RNG_INTACK_REG] = 0x10,
98	[RNG_CONTROL_REG] = 0x14,
99	[RNG_CONFIG_REG] = 0x18,
100	[RNG_ALARMCNT_REG] = 0x1c,
101	[RNG_FROENABLE_REG] = 0x20,
102	[RNG_FRODETUNE_REG] = 0x24,
103	[RNG_ALARMMASK_REG] = 0x28,
104	[RNG_ALARMSTOP_REG] = 0x2c,
105	[RNG_REV_REG] = 0x1FE0,
106	[RNG_SYSCONFIG_REG] = 0x1FE4,
107	};
ebc915ad	108
e83872c9	109	struct omap_rng_dev;
02666360	110	/**
e83872c9 LV	111	* struct omap_rng_pdata - RNG IP block-specific data
	112	* @regs: Pointer to the register offsets structure.
	113	* @data_size: No. of bytes in RNG output.
	114	* @data_present: Callback to determine if data is available.
	115	* @init: Callback for IP specific initialization sequence.
	116	* @cleanup: Callback for IP specific cleanup sequence.
02666360	117	*/
e83872c9 LV	118	struct omap_rng_pdata {
	119	u16 *regs;
	120	u32 data_size;
	121	u32 (data_present)(struct omap_rng_dev priv);
	122	int (init)(struct omap_rng_dev priv);
	123	void (cleanup)(struct omap_rng_dev priv);
02666360	124	};
ebc915ad	125
e83872c9 LV	126	struct omap_rng_dev {
	127	void __iomem *base;
	128	struct device *dev;
	129	const struct omap_rng_pdata *pdata;
	130	};
	131
	132	static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
	133	{
	134	return __raw_readl(priv->base + priv->pdata->regs[reg]);
	135	}
	136
	137	static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
	138	u32 val)
ebc915ad	139	{
e83872c9	140	__raw_writel(val, priv->base + priv->pdata->regs[reg]);
ebc915ad MB	141	}
ebc915ad MB	142
984e976f	143	static int omap_rng_data_present(struct hwrng *rng, int wait)
ebc915ad	144	{
e83872c9	145	struct omap_rng_dev *priv;
984e976f PM	146	int data, i;
984e976f PM	147
e83872c9	148	priv = (struct omap_rng_dev *)rng->priv;
02666360	149
984e976f	150	for (i = 0; i < 20; i++) {
e83872c9	151	data = priv->pdata->data_present(priv);
984e976f PM	152	if (data \|\| !wait)
984e976f PM	153	break;
c49a7f18 DB	154	/* RNG produces data fast enough (2+ MBit/sec, even
	155	* during "rngtest" loads, that these delays don't
	156	* seem to trigger. We could use the RNG IRQ, but
	157	* that'd be higher overhead ... so why bother?
	158	*/
984e976f PM	159	udelay(10);
	160	}
	161	return data;
ebc915ad MB	162	}
	163
	164	static int omap_rng_data_read(struct hwrng rng, u32 data)
	165	{
e83872c9 LV	166	struct omap_rng_dev *priv;
	167	u32 data_size, i;
	168
	169	priv = (struct omap_rng_dev *)rng->priv;
	170	data_size = priv->pdata->data_size;
	171
	172	for (i = 0; i < data_size / sizeof(u32); i++)
	173	data[i] = omap_rng_read(priv, RNG_OUTPUT_L_REG + i);
	174
	175	if (priv->pdata->regs[RNG_INTACK_REG])
	176	omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
	177	return data_size;
	178	}
	179
a246968e OJ	180	static int omap_rng_init(struct hwrng *rng)
	181	{
	182	struct omap_rng_dev *priv;
	183
	184	priv = (struct omap_rng_dev *)rng->priv;
	185	return priv->pdata->init(priv);
	186	}
	187
	188	static void omap_rng_cleanup(struct hwrng *rng)
	189	{
	190	struct omap_rng_dev *priv;
	191
	192	priv = (struct omap_rng_dev *)rng->priv;
	193	priv->pdata->cleanup(priv);
	194	}
	195
	196	static struct hwrng omap_rng_ops = {
	197	.name = "omap",
	198	.data_present = omap_rng_data_present,
	199	.data_read = omap_rng_data_read,
	200	.init = omap_rng_init,
	201	.cleanup = omap_rng_cleanup,
	202	};
	203
	204	static inline u32 omap2_rng_data_present(struct omap_rng_dev *priv)
	205	{
	206	return omap_rng_read(priv, RNG_STATUS_REG) ? 0 : 1;
	207	}
	208
	209	static int omap2_rng_init(struct omap_rng_dev *priv)
	210	{
	211	omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x1);
	212	return 0;
	213	}
	214
	215	static void omap2_rng_cleanup(struct omap_rng_dev *priv)
	216	{
	217	omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x0);
	218	}
	219
	220	static struct omap_rng_pdata omap2_rng_pdata = {
	221	.regs = (u16 *)reg_map_omap2,
	222	.data_size = OMAP2_RNG_OUTPUT_SIZE,
	223	.data_present = omap2_rng_data_present,
	224	.init = omap2_rng_init,
	225	.cleanup = omap2_rng_cleanup,
	226	};
	227
	228	#if defined(CONFIG_OF)
	229	static inline u32 omap4_rng_data_present(struct omap_rng_dev *priv)
	230	{
	231	return omap_rng_read(priv, RNG_STATUS_REG) & RNG_REG_STATUS_RDY;
	232	}
	233
e83872c9 LV	234	static int omap4_rng_init(struct omap_rng_dev *priv)
	235	{
	236	u32 val;
	237
	238	/* Return if RNG is already running. */
656d7e7e	239	if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
e83872c9 LV	240	return 0;
	241
	242	val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
	243	val \|= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
	244	omap_rng_write(priv, RNG_CONFIG_REG, val);
	245
	246	omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
	247	omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
	248	val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT;
	249	val \|= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
	250	omap_rng_write(priv, RNG_ALARMCNT_REG, val);
	251
	252	val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
	253	val \|= RNG_CONTROL_ENABLE_TRNG_MASK;
	254	omap_rng_write(priv, RNG_CONTROL_REG, val);
	255
	256	return 0;
	257	}
	258
	259	static void omap4_rng_cleanup(struct omap_rng_dev *priv)
	260	{
	261	int val;
	262
	263	val = omap_rng_read(priv, RNG_CONTROL_REG);
	264	val &= ~RNG_CONTROL_ENABLE_TRNG_MASK;
1a5addfe	265	omap_rng_write(priv, RNG_CONTROL_REG, val);
e83872c9 LV	266	}
e83872c9 LV	267
e83872c9 LV	268	static irqreturn_t omap4_rng_irq(int irq, void *dev_id)
	269	{
	270	struct omap_rng_dev *priv = dev_id;
	271	u32 fro_detune, fro_enable;
	272
	273	/*
	274	* Interrupt raised by a fro shutdown threshold, do the following:
	275	* 1. Clear the alarm events.
	276	* 2. De tune the FROs which are shutdown.
	277	* 3. Re enable the shutdown FROs.
	278	*/
	279	omap_rng_write(priv, RNG_ALARMMASK_REG, 0x0);
	280	omap_rng_write(priv, RNG_ALARMSTOP_REG, 0x0);
	281
	282	fro_enable = omap_rng_read(priv, RNG_FROENABLE_REG);
	283	fro_detune = ~fro_enable & RNG_REG_FRODETUNE_MASK;
	284	fro_detune = fro_detune \| omap_rng_read(priv, RNG_FRODETUNE_REG);
	285	fro_enable = RNG_REG_FROENABLE_MASK;
02666360	286
e83872c9 LV	287	omap_rng_write(priv, RNG_FRODETUNE_REG, fro_detune);
e83872c9 LV	288	omap_rng_write(priv, RNG_FROENABLE_REG, fro_enable);
02666360	289
e83872c9	290	omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK);
ebc915ad	291
e83872c9	292	return IRQ_HANDLED;
ebc915ad MB	293	}
ebc915ad MB	294
e83872c9 LV	295	static struct omap_rng_pdata omap4_rng_pdata = {
	296	.regs = (u16 *)reg_map_omap4,
	297	.data_size = OMAP4_RNG_OUTPUT_SIZE,
	298	.data_present = omap4_rng_data_present,
	299	.init = omap4_rng_init,
	300	.cleanup = omap4_rng_cleanup,
	301	};
	302
c903970c	303	static const struct of_device_id omap_rng_of_match[] = {
e83872c9 LV	304	{
	305	.compatible = "ti,omap2-rng",
	306	.data = &omap2_rng_pdata,
	307	},
	308	{
	309	.compatible = "ti,omap4-rng",
	310	.data = &omap4_rng_pdata,
	311	},
c903970c LV	312	{},
	313	};
	314	MODULE_DEVICE_TABLE(of, omap_rng_of_match);
e83872c9 LV	315
	316	static int of_get_omap_rng_device_details(struct omap_rng_dev *priv,
	317	struct platform_device *pdev)
	318	{
	319	const struct of_device_id *match;
	320	struct device *dev = &pdev->dev;
	321	int irq, err;
	322
	323	match = of_match_device(of_match_ptr(omap_rng_of_match), dev);
	324	if (!match) {
	325	dev_err(dev, "no compatible OF match\n");
	326	return -EINVAL;
	327	}
	328	priv->pdata = match->data;
	329
	330	if (of_device_is_compatible(dev->of_node, "ti,omap4-rng")) {
	331	irq = platform_get_irq(pdev, 0);
	332	if (irq < 0) {
	333	dev_err(dev, "%s: error getting IRQ resource - %d\n",
	334	__func__, irq);
	335	return irq;
	336	}
	337
	338	err = devm_request_irq(dev, irq, omap4_rng_irq,
	339	IRQF_TRIGGER_NONE, dev_name(dev), priv);
	340	if (err) {
	341	dev_err(dev, "unable to request irq %d, err = %d\n",
	342	irq, err);
	343	return err;
	344	}
	345	omap_rng_write(priv, RNG_INTMASK_REG, RNG_SHUTDOWN_OFLO_MASK);
	346	}
	347	return 0;
	348	}
	349	#else
	350	static int of_get_omap_rng_device_details(struct omap_rng_dev *omap_rng,
	351	struct platform_device *pdev)
	352	{
	353	return -EINVAL;
	354	}
c903970c LV	355	#endif
c903970c LV	356
e83872c9 LV	357	static int get_omap_rng_device_details(struct omap_rng_dev *omap_rng)
	358	{
	359	/* Only OMAP2/3 can be non-DT */
	360	omap_rng->pdata = &omap2_rng_pdata;
	361	return 0;
	362	}
	363
bcd2982a	364	static int omap_rng_probe(struct platform_device *pdev)
ebc915ad	365	{
e83872c9 LV	366	struct omap_rng_dev *priv;
	367	struct resource *res;
	368	struct device *dev = &pdev->dev;
ebc915ad MB	369	int ret;
ebc915ad MB	370
e83872c9	371	priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
9e9026a7	372	if (!priv)
02666360	373	return -ENOMEM;
02666360 PW	374
02666360 PW	375	omap_rng_ops.priv = (unsigned long)priv;
1f539bcb	376	platform_set_drvdata(pdev, priv);
e83872c9	377	priv->dev = dev;
ebc915ad	378
e83872c9 LV	379	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
e83872c9 LV	380	priv->base = devm_ioremap_resource(dev, res);
c7c9e1c3 TR	381	if (IS_ERR(priv->base)) {
c7c9e1c3 TR	382	ret = PTR_ERR(priv->base);
55c381e4 RK	383	goto err_ioremap;
55c381e4 RK	384	}
ebc915ad	385
665d92fa PW	386	pm_runtime_enable(&pdev->dev);
	387	pm_runtime_get_sync(&pdev->dev);
	388
e83872c9 LV	389	ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
	390	get_omap_rng_device_details(priv);
	391	if (ret)
	392	goto err_ioremap;
	393
ebc915ad	394	ret = hwrng_register(&omap_rng_ops);
55c381e4 RK	395	if (ret)
55c381e4 RK	396	goto err_register;
ebc915ad	397
af2bc7d2	398	dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
e83872c9	399	omap_rng_read(priv, RNG_REV_REG));
ebc915ad MB	400
ebc915ad MB	401	return 0;
55c381e4 RK	402
55c381e4 RK	403	err_register:
02666360	404	priv->base = NULL;
665d92fa	405	pm_runtime_disable(&pdev->dev);
55c381e4	406	err_ioremap:
e83872c9	407	dev_err(dev, "initialization failed.\n");
55c381e4	408	return ret;
ebc915ad MB	409	}
ebc915ad MB	410
1ee9b5e4	411	static int omap_rng_remove(struct platform_device *pdev)
ebc915ad	412	{
e83872c9	413	struct omap_rng_dev *priv = platform_get_drvdata(pdev);
02666360	414
ebc915ad MB	415	hwrng_unregister(&omap_rng_ops);
ebc915ad MB	416
e83872c9	417	priv->pdata->cleanup(priv);
02666360	418
665d92fa PW	419	pm_runtime_put_sync(&pdev->dev);
665d92fa PW	420	pm_runtime_disable(&pdev->dev);
ebc915ad	421
ebc915ad MB	422	return 0;
	423	}
	424
a308d66f	425	static int __maybe_unused omap_rng_suspend(struct device *dev)
ebc915ad	426	{
e83872c9	427	struct omap_rng_dev *priv = dev_get_drvdata(dev);
02666360	428
e83872c9	429	priv->pdata->cleanup(priv);
665d92fa	430	pm_runtime_put_sync(dev);
02666360	431
ebc915ad MB	432	return 0;
	433	}
	434
a308d66f	435	static int __maybe_unused omap_rng_resume(struct device *dev)
ebc915ad	436	{
e83872c9	437	struct omap_rng_dev *priv = dev_get_drvdata(dev);
02666360	438
665d92fa	439	pm_runtime_get_sync(dev);
e83872c9	440	priv->pdata->init(priv);
02666360	441
af2bc7d2	442	return 0;
ebc915ad MB	443	}
ebc915ad MB	444
7650572a	445	static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
ebc915ad	446
af2bc7d2 DB	447	static struct platform_driver omap_rng_driver = {
	448	.driver = {
	449	.name = "omap_rng",
a308d66f	450	.pm = &omap_rng_pm,
c903970c	451	.of_match_table = of_match_ptr(omap_rng_of_match),
af2bc7d2	452	},
ebc915ad	453	.probe = omap_rng_probe,
1ee9b5e4	454	.remove = omap_rng_remove,
ebc915ad MB	455	};
ebc915ad MB	456
4390f77b LV	457	module_platform_driver(omap_rng_driver);
4390f77b LV	458	MODULE_ALIAS("platform:omap_rng");
ebc915ad MB	459	MODULE_AUTHOR("Deepak Saxena (and others)");
ebc915ad MB	460	MODULE_LICENSE("GPL");