Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
76832c28 | 2 | * Timer device implementation for SGI SN platforms. |
1da177e4 LT |
3 | * |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
76832c28 | 8 | * Copyright (c) 2001-2006 Silicon Graphics, Inc. All rights reserved. |
1da177e4 LT |
9 | * |
10 | * This driver exports an API that should be supportable by any HPET or IA-PC | |
11 | * multimedia timer. The code below is currently specific to the SGI Altix | |
12 | * SHub RTC, however. | |
13 | * | |
14 | * 11/01/01 - jbarnes - initial revision | |
15 | * 9/10/04 - Christoph Lameter - remove interrupt support for kernel inclusion | |
16 | * 10/1/04 - Christoph Lameter - provide posix clock CLOCK_SGI_CYCLE | |
17 | * 10/13/04 - Christoph Lameter, Dimitri Sivanich - provide timer interrupt | |
18 | * support via the posix timer interface | |
19 | */ | |
20 | ||
21 | #include <linux/types.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/ioctl.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/mm.h> | |
4e950f6f | 28 | #include <linux/fs.h> |
1da177e4 LT |
29 | #include <linux/mmtimer.h> |
30 | #include <linux/miscdevice.h> | |
31 | #include <linux/posix-timers.h> | |
32 | #include <linux/interrupt.h> | |
f8bd2258 RZ |
33 | #include <linux/time.h> |
34 | #include <linux/math64.h> | |
4cddb886 | 35 | #include <linux/smp_lock.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1da177e4 LT |
37 | |
38 | #include <asm/uaccess.h> | |
39 | #include <asm/sn/addrs.h> | |
40 | #include <asm/sn/intr.h> | |
41 | #include <asm/sn/shub_mmr.h> | |
42 | #include <asm/sn/nodepda.h> | |
43 | #include <asm/sn/shubio.h> | |
44 | ||
45 | MODULE_AUTHOR("Jesse Barnes <jbarnes@sgi.com>"); | |
46 | MODULE_DESCRIPTION("SGI Altix RTC Timer"); | |
47 | MODULE_LICENSE("GPL"); | |
48 | ||
49 | /* name of the device, usually in /dev */ | |
50 | #define MMTIMER_NAME "mmtimer" | |
51 | #define MMTIMER_DESC "SGI Altix RTC Timer" | |
76832c28 | 52 | #define MMTIMER_VERSION "2.1" |
1da177e4 LT |
53 | |
54 | #define RTC_BITS 55 /* 55 bits for this implementation */ | |
55 | ||
56 | extern unsigned long sn_rtc_cycles_per_second; | |
57 | ||
58 | #define RTC_COUNTER_ADDR ((long *)LOCAL_MMR_ADDR(SH_RTC)) | |
59 | ||
60 | #define rtc_time() (*RTC_COUNTER_ADDR) | |
61 | ||
4cddb886 AC |
62 | static long mmtimer_ioctl(struct file *file, unsigned int cmd, |
63 | unsigned long arg); | |
1da177e4 LT |
64 | static int mmtimer_mmap(struct file *file, struct vm_area_struct *vma); |
65 | ||
66 | /* | |
67 | * Period in femtoseconds (10^-15 s) | |
68 | */ | |
69 | static unsigned long mmtimer_femtoperiod = 0; | |
70 | ||
62322d25 | 71 | static const struct file_operations mmtimer_fops = { |
4cddb886 AC |
72 | .owner = THIS_MODULE, |
73 | .mmap = mmtimer_mmap, | |
74 | .unlocked_ioctl = mmtimer_ioctl, | |
1da177e4 LT |
75 | }; |
76 | ||
77 | /* | |
78 | * We only have comparison registers RTC1-4 currently available per | |
79 | * node. RTC0 is used by SAL. | |
80 | */ | |
1da177e4 | 81 | /* Check for an RTC interrupt pending */ |
cbacdd95 | 82 | static int mmtimer_int_pending(int comparator) |
1da177e4 LT |
83 | { |
84 | if (HUB_L((unsigned long *)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED)) & | |
85 | SH_EVENT_OCCURRED_RTC1_INT_MASK << comparator) | |
86 | return 1; | |
87 | else | |
88 | return 0; | |
89 | } | |
cbacdd95 | 90 | |
1da177e4 | 91 | /* Clear the RTC interrupt pending bit */ |
cbacdd95 | 92 | static void mmtimer_clr_int_pending(int comparator) |
1da177e4 LT |
93 | { |
94 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), | |
95 | SH_EVENT_OCCURRED_RTC1_INT_MASK << comparator); | |
96 | } | |
97 | ||
98 | /* Setup timer on comparator RTC1 */ | |
cbacdd95 | 99 | static void mmtimer_setup_int_0(int cpu, u64 expires) |
1da177e4 LT |
100 | { |
101 | u64 val; | |
102 | ||
103 | /* Disable interrupt */ | |
104 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC1_INT_ENABLE), 0UL); | |
105 | ||
106 | /* Initialize comparator value */ | |
107 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPB), -1L); | |
108 | ||
109 | /* Clear pending bit */ | |
110 | mmtimer_clr_int_pending(0); | |
111 | ||
112 | val = ((u64)SGI_MMTIMER_VECTOR << SH_RTC1_INT_CONFIG_IDX_SHFT) | | |
cbacdd95 | 113 | ((u64)cpu_physical_id(cpu) << |
1da177e4 LT |
114 | SH_RTC1_INT_CONFIG_PID_SHFT); |
115 | ||
116 | /* Set configuration */ | |
117 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC1_INT_CONFIG), val); | |
118 | ||
119 | /* Enable RTC interrupts */ | |
120 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC1_INT_ENABLE), 1UL); | |
121 | ||
122 | /* Initialize comparator value */ | |
123 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPB), expires); | |
124 | ||
125 | ||
126 | } | |
127 | ||
128 | /* Setup timer on comparator RTC2 */ | |
cbacdd95 | 129 | static void mmtimer_setup_int_1(int cpu, u64 expires) |
1da177e4 LT |
130 | { |
131 | u64 val; | |
132 | ||
133 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC2_INT_ENABLE), 0UL); | |
134 | ||
135 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPC), -1L); | |
136 | ||
137 | mmtimer_clr_int_pending(1); | |
138 | ||
139 | val = ((u64)SGI_MMTIMER_VECTOR << SH_RTC2_INT_CONFIG_IDX_SHFT) | | |
cbacdd95 | 140 | ((u64)cpu_physical_id(cpu) << |
1da177e4 LT |
141 | SH_RTC2_INT_CONFIG_PID_SHFT); |
142 | ||
143 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC2_INT_CONFIG), val); | |
144 | ||
145 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC2_INT_ENABLE), 1UL); | |
146 | ||
147 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPC), expires); | |
148 | } | |
149 | ||
150 | /* Setup timer on comparator RTC3 */ | |
cbacdd95 | 151 | static void mmtimer_setup_int_2(int cpu, u64 expires) |
1da177e4 LT |
152 | { |
153 | u64 val; | |
154 | ||
155 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC3_INT_ENABLE), 0UL); | |
156 | ||
157 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPD), -1L); | |
158 | ||
159 | mmtimer_clr_int_pending(2); | |
160 | ||
161 | val = ((u64)SGI_MMTIMER_VECTOR << SH_RTC3_INT_CONFIG_IDX_SHFT) | | |
cbacdd95 | 162 | ((u64)cpu_physical_id(cpu) << |
1da177e4 LT |
163 | SH_RTC3_INT_CONFIG_PID_SHFT); |
164 | ||
165 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC3_INT_CONFIG), val); | |
166 | ||
167 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC3_INT_ENABLE), 1UL); | |
168 | ||
169 | HUB_S((u64 *)LOCAL_MMR_ADDR(SH_INT_CMPD), expires); | |
170 | } | |
171 | ||
172 | /* | |
173 | * This function must be called with interrupts disabled and preemption off | |
174 | * in order to insure that the setup succeeds in a deterministic time frame. | |
175 | * It will check if the interrupt setup succeeded. | |
176 | */ | |
cbacdd95 | 177 | static int mmtimer_setup(int cpu, int comparator, unsigned long expires) |
1da177e4 LT |
178 | { |
179 | ||
180 | switch (comparator) { | |
181 | case 0: | |
cbacdd95 | 182 | mmtimer_setup_int_0(cpu, expires); |
1da177e4 LT |
183 | break; |
184 | case 1: | |
cbacdd95 | 185 | mmtimer_setup_int_1(cpu, expires); |
1da177e4 LT |
186 | break; |
187 | case 2: | |
cbacdd95 | 188 | mmtimer_setup_int_2(cpu, expires); |
1da177e4 LT |
189 | break; |
190 | } | |
191 | /* We might've missed our expiration time */ | |
cbacdd95 | 192 | if (rtc_time() <= expires) |
1da177e4 LT |
193 | return 1; |
194 | ||
195 | /* | |
196 | * If an interrupt is already pending then its okay | |
197 | * if not then we failed | |
198 | */ | |
199 | return mmtimer_int_pending(comparator); | |
200 | } | |
201 | ||
cbacdd95 | 202 | static int mmtimer_disable_int(long nasid, int comparator) |
1da177e4 LT |
203 | { |
204 | switch (comparator) { | |
205 | case 0: | |
206 | nasid == -1 ? HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC1_INT_ENABLE), | |
207 | 0UL) : REMOTE_HUB_S(nasid, SH_RTC1_INT_ENABLE, 0UL); | |
208 | break; | |
209 | case 1: | |
210 | nasid == -1 ? HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC2_INT_ENABLE), | |
211 | 0UL) : REMOTE_HUB_S(nasid, SH_RTC2_INT_ENABLE, 0UL); | |
212 | break; | |
213 | case 2: | |
214 | nasid == -1 ? HUB_S((u64 *)LOCAL_MMR_ADDR(SH_RTC3_INT_ENABLE), | |
215 | 0UL) : REMOTE_HUB_S(nasid, SH_RTC3_INT_ENABLE, 0UL); | |
216 | break; | |
217 | default: | |
218 | return -EFAULT; | |
219 | } | |
220 | return 0; | |
221 | } | |
222 | ||
cbacdd95 | 223 | #define COMPARATOR 1 /* The comparator to use */ |
1da177e4 | 224 | |
cbacdd95 DS |
225 | #define TIMER_OFF 0xbadcabLL /* Timer is not setup */ |
226 | #define TIMER_SET 0 /* Comparator is set for this timer */ | |
227 | ||
228 | /* There is one of these for each timer */ | |
229 | struct mmtimer { | |
230 | struct rb_node list; | |
1da177e4 | 231 | struct k_itimer *timer; |
1da177e4 | 232 | int cpu; |
cbacdd95 DS |
233 | }; |
234 | ||
235 | struct mmtimer_node { | |
236 | spinlock_t lock ____cacheline_aligned; | |
237 | struct rb_root timer_head; | |
238 | struct rb_node *next; | |
1da177e4 | 239 | struct tasklet_struct tasklet; |
cbacdd95 DS |
240 | }; |
241 | static struct mmtimer_node *timers; | |
242 | ||
243 | ||
244 | /* | |
245 | * Add a new mmtimer struct to the node's mmtimer list. | |
246 | * This function assumes the struct mmtimer_node is locked. | |
247 | */ | |
248 | static void mmtimer_add_list(struct mmtimer *n) | |
249 | { | |
250 | int nodeid = n->timer->it.mmtimer.node; | |
251 | unsigned long expires = n->timer->it.mmtimer.expires; | |
252 | struct rb_node **link = &timers[nodeid].timer_head.rb_node; | |
253 | struct rb_node *parent = NULL; | |
254 | struct mmtimer *x; | |
255 | ||
256 | /* | |
257 | * Find the right place in the rbtree: | |
258 | */ | |
259 | while (*link) { | |
260 | parent = *link; | |
261 | x = rb_entry(parent, struct mmtimer, list); | |
262 | ||
263 | if (expires < x->timer->it.mmtimer.expires) | |
264 | link = &(*link)->rb_left; | |
265 | else | |
266 | link = &(*link)->rb_right; | |
267 | } | |
268 | ||
269 | /* | |
270 | * Insert the timer to the rbtree and check whether it | |
271 | * replaces the first pending timer | |
272 | */ | |
273 | rb_link_node(&n->list, parent, link); | |
274 | rb_insert_color(&n->list, &timers[nodeid].timer_head); | |
275 | ||
276 | if (!timers[nodeid].next || expires < rb_entry(timers[nodeid].next, | |
277 | struct mmtimer, list)->timer->it.mmtimer.expires) | |
278 | timers[nodeid].next = &n->list; | |
279 | } | |
280 | ||
281 | /* | |
282 | * Set the comparator for the next timer. | |
283 | * This function assumes the struct mmtimer_node is locked. | |
284 | */ | |
285 | static void mmtimer_set_next_timer(int nodeid) | |
286 | { | |
287 | struct mmtimer_node *n = &timers[nodeid]; | |
288 | struct mmtimer *x; | |
289 | struct k_itimer *t; | |
290 | int o; | |
291 | ||
292 | restart: | |
293 | if (n->next == NULL) | |
294 | return; | |
1da177e4 | 295 | |
cbacdd95 DS |
296 | x = rb_entry(n->next, struct mmtimer, list); |
297 | t = x->timer; | |
298 | if (!t->it.mmtimer.incr) { | |
299 | /* Not an interval timer */ | |
300 | if (!mmtimer_setup(x->cpu, COMPARATOR, | |
301 | t->it.mmtimer.expires)) { | |
302 | /* Late setup, fire now */ | |
303 | tasklet_schedule(&n->tasklet); | |
304 | } | |
305 | return; | |
306 | } | |
307 | ||
308 | /* Interval timer */ | |
309 | o = 0; | |
310 | while (!mmtimer_setup(x->cpu, COMPARATOR, t->it.mmtimer.expires)) { | |
311 | unsigned long e, e1; | |
312 | struct rb_node *next; | |
313 | t->it.mmtimer.expires += t->it.mmtimer.incr << o; | |
314 | t->it_overrun += 1 << o; | |
315 | o++; | |
316 | if (o > 20) { | |
317 | printk(KERN_ALERT "mmtimer: cannot reschedule timer\n"); | |
318 | t->it.mmtimer.clock = TIMER_OFF; | |
319 | n->next = rb_next(&x->list); | |
320 | rb_erase(&x->list, &n->timer_head); | |
321 | kfree(x); | |
322 | goto restart; | |
323 | } | |
324 | ||
325 | e = t->it.mmtimer.expires; | |
326 | next = rb_next(&x->list); | |
327 | ||
328 | if (next == NULL) | |
329 | continue; | |
330 | ||
331 | e1 = rb_entry(next, struct mmtimer, list)-> | |
332 | timer->it.mmtimer.expires; | |
333 | if (e > e1) { | |
334 | n->next = next; | |
335 | rb_erase(&x->list, &n->timer_head); | |
336 | mmtimer_add_list(x); | |
337 | goto restart; | |
338 | } | |
339 | } | |
340 | } | |
1da177e4 LT |
341 | |
342 | /** | |
343 | * mmtimer_ioctl - ioctl interface for /dev/mmtimer | |
1da177e4 LT |
344 | * @file: file structure for the device |
345 | * @cmd: command to execute | |
346 | * @arg: optional argument to command | |
347 | * | |
348 | * Executes the command specified by @cmd. Returns 0 for success, < 0 for | |
349 | * failure. | |
350 | * | |
351 | * Valid commands: | |
352 | * | |
353 | * %MMTIMER_GETOFFSET - Should return the offset (relative to the start | |
354 | * of the page where the registers are mapped) for the counter in question. | |
355 | * | |
356 | * %MMTIMER_GETRES - Returns the resolution of the clock in femto (10^-15) | |
357 | * seconds | |
358 | * | |
359 | * %MMTIMER_GETFREQ - Copies the frequency of the clock in Hz to the address | |
360 | * specified by @arg | |
361 | * | |
362 | * %MMTIMER_GETBITS - Returns the number of bits in the clock's counter | |
363 | * | |
364 | * %MMTIMER_MMAPAVAIL - Returns 1 if the registers can be mmap'd into userspace | |
365 | * | |
366 | * %MMTIMER_GETCOUNTER - Gets the current value in the counter and places it | |
367 | * in the address specified by @arg. | |
368 | */ | |
4cddb886 AC |
369 | static long mmtimer_ioctl(struct file *file, unsigned int cmd, |
370 | unsigned long arg) | |
1da177e4 LT |
371 | { |
372 | int ret = 0; | |
373 | ||
4cddb886 AC |
374 | lock_kernel(); |
375 | ||
1da177e4 LT |
376 | switch (cmd) { |
377 | case MMTIMER_GETOFFSET: /* offset of the counter */ | |
378 | /* | |
379 | * SN RTC registers are on their own 64k page | |
380 | */ | |
381 | if(PAGE_SIZE <= (1 << 16)) | |
382 | ret = (((long)RTC_COUNTER_ADDR) & (PAGE_SIZE-1)) / 8; | |
383 | else | |
384 | ret = -ENOSYS; | |
385 | break; | |
386 | ||
387 | case MMTIMER_GETRES: /* resolution of the clock in 10^-15 s */ | |
388 | if(copy_to_user((unsigned long __user *)arg, | |
389 | &mmtimer_femtoperiod, sizeof(unsigned long))) | |
4cddb886 | 390 | ret = -EFAULT; |
1da177e4 LT |
391 | break; |
392 | ||
393 | case MMTIMER_GETFREQ: /* frequency in Hz */ | |
394 | if(copy_to_user((unsigned long __user *)arg, | |
395 | &sn_rtc_cycles_per_second, | |
396 | sizeof(unsigned long))) | |
4cddb886 | 397 | ret = -EFAULT; |
1da177e4 LT |
398 | break; |
399 | ||
400 | case MMTIMER_GETBITS: /* number of bits in the clock */ | |
401 | ret = RTC_BITS; | |
402 | break; | |
403 | ||
404 | case MMTIMER_MMAPAVAIL: /* can we mmap the clock into userspace? */ | |
405 | ret = (PAGE_SIZE <= (1 << 16)) ? 1 : 0; | |
406 | break; | |
407 | ||
408 | case MMTIMER_GETCOUNTER: | |
409 | if(copy_to_user((unsigned long __user *)arg, | |
410 | RTC_COUNTER_ADDR, sizeof(unsigned long))) | |
4cddb886 | 411 | ret = -EFAULT; |
1da177e4 LT |
412 | break; |
413 | default: | |
4cddb886 | 414 | ret = -ENOTTY; |
1da177e4 LT |
415 | break; |
416 | } | |
4cddb886 | 417 | unlock_kernel(); |
1da177e4 LT |
418 | return ret; |
419 | } | |
420 | ||
421 | /** | |
422 | * mmtimer_mmap - maps the clock's registers into userspace | |
423 | * @file: file structure for the device | |
424 | * @vma: VMA to map the registers into | |
425 | * | |
426 | * Calls remap_pfn_range() to map the clock's registers into | |
427 | * the calling process' address space. | |
428 | */ | |
429 | static int mmtimer_mmap(struct file *file, struct vm_area_struct *vma) | |
430 | { | |
431 | unsigned long mmtimer_addr; | |
432 | ||
433 | if (vma->vm_end - vma->vm_start != PAGE_SIZE) | |
434 | return -EINVAL; | |
435 | ||
436 | if (vma->vm_flags & VM_WRITE) | |
437 | return -EPERM; | |
438 | ||
439 | if (PAGE_SIZE > (1 << 16)) | |
440 | return -ENOSYS; | |
441 | ||
1da177e4 LT |
442 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
443 | ||
444 | mmtimer_addr = __pa(RTC_COUNTER_ADDR); | |
445 | mmtimer_addr &= ~(PAGE_SIZE - 1); | |
446 | mmtimer_addr &= 0xfffffffffffffffUL; | |
447 | ||
448 | if (remap_pfn_range(vma, vma->vm_start, mmtimer_addr >> PAGE_SHIFT, | |
449 | PAGE_SIZE, vma->vm_page_prot)) { | |
450 | printk(KERN_ERR "remap_pfn_range failed in mmtimer.c\n"); | |
451 | return -EAGAIN; | |
452 | } | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static struct miscdevice mmtimer_miscdev = { | |
458 | SGI_MMTIMER, | |
459 | MMTIMER_NAME, | |
460 | &mmtimer_fops | |
461 | }; | |
462 | ||
463 | static struct timespec sgi_clock_offset; | |
464 | static int sgi_clock_period; | |
465 | ||
466 | /* | |
467 | * Posix Timer Interface | |
468 | */ | |
469 | ||
470 | static struct timespec sgi_clock_offset; | |
471 | static int sgi_clock_period; | |
472 | ||
473 | static int sgi_clock_get(clockid_t clockid, struct timespec *tp) | |
474 | { | |
475 | u64 nsec; | |
476 | ||
477 | nsec = rtc_time() * sgi_clock_period | |
478 | + sgi_clock_offset.tv_nsec; | |
f8bd2258 RZ |
479 | *tp = ns_to_timespec(nsec); |
480 | tp->tv_sec += sgi_clock_offset.tv_sec; | |
1da177e4 LT |
481 | return 0; |
482 | }; | |
483 | ||
484 | static int sgi_clock_set(clockid_t clockid, struct timespec *tp) | |
485 | { | |
486 | ||
487 | u64 nsec; | |
f8bd2258 | 488 | u32 rem; |
1da177e4 LT |
489 | |
490 | nsec = rtc_time() * sgi_clock_period; | |
491 | ||
f8bd2258 | 492 | sgi_clock_offset.tv_sec = tp->tv_sec - div_u64_rem(nsec, NSEC_PER_SEC, &rem); |
1da177e4 LT |
493 | |
494 | if (rem <= tp->tv_nsec) | |
495 | sgi_clock_offset.tv_nsec = tp->tv_sec - rem; | |
496 | else { | |
497 | sgi_clock_offset.tv_nsec = tp->tv_sec + NSEC_PER_SEC - rem; | |
498 | sgi_clock_offset.tv_sec--; | |
499 | } | |
500 | return 0; | |
501 | } | |
502 | ||
1da177e4 LT |
503 | /** |
504 | * mmtimer_interrupt - timer interrupt handler | |
505 | * @irq: irq received | |
506 | * @dev_id: device the irq came from | |
1da177e4 LT |
507 | * |
508 | * Called when one of the comarators matches the counter, This | |
509 | * routine will send signals to processes that have requested | |
510 | * them. | |
511 | * | |
512 | * This interrupt is run in an interrupt context | |
513 | * by the SHUB. It is therefore safe to locally access SHub | |
514 | * registers. | |
515 | */ | |
516 | static irqreturn_t | |
7d12e780 | 517 | mmtimer_interrupt(int irq, void *dev_id) |
1da177e4 | 518 | { |
1da177e4 LT |
519 | unsigned long expires = 0; |
520 | int result = IRQ_NONE; | |
76832c28 | 521 | unsigned indx = cpu_to_node(smp_processor_id()); |
cbacdd95 | 522 | struct mmtimer *base; |
1da177e4 | 523 | |
cbacdd95 DS |
524 | spin_lock(&timers[indx].lock); |
525 | base = rb_entry(timers[indx].next, struct mmtimer, list); | |
526 | if (base == NULL) { | |
527 | spin_unlock(&timers[indx].lock); | |
528 | return result; | |
529 | } | |
530 | ||
531 | if (base->cpu == smp_processor_id()) { | |
532 | if (base->timer) | |
533 | expires = base->timer->it.mmtimer.expires; | |
534 | /* expires test won't work with shared irqs */ | |
535 | if ((mmtimer_int_pending(COMPARATOR) > 0) || | |
536 | (expires && (expires <= rtc_time()))) { | |
537 | mmtimer_clr_int_pending(COMPARATOR); | |
538 | tasklet_schedule(&timers[indx].tasklet); | |
539 | result = IRQ_HANDLED; | |
1da177e4 | 540 | } |
1da177e4 | 541 | } |
cbacdd95 | 542 | spin_unlock(&timers[indx].lock); |
1da177e4 LT |
543 | return result; |
544 | } | |
545 | ||
cbacdd95 DS |
546 | static void mmtimer_tasklet(unsigned long data) |
547 | { | |
548 | int nodeid = data; | |
549 | struct mmtimer_node *mn = &timers[nodeid]; | |
0fbcae22 | 550 | struct mmtimer *x; |
cbacdd95 | 551 | struct k_itimer *t; |
1da177e4 LT |
552 | unsigned long flags; |
553 | ||
1da177e4 | 554 | /* Send signal and deal with periodic signals */ |
cbacdd95 DS |
555 | spin_lock_irqsave(&mn->lock, flags); |
556 | if (!mn->next) | |
1da177e4 | 557 | goto out; |
1da177e4 | 558 | |
cbacdd95 DS |
559 | x = rb_entry(mn->next, struct mmtimer, list); |
560 | t = x->timer; | |
561 | ||
562 | if (t->it.mmtimer.clock == TIMER_OFF) | |
563 | goto out; | |
564 | ||
565 | t->it_overrun = 0; | |
1da177e4 | 566 | |
cbacdd95 DS |
567 | mn->next = rb_next(&x->list); |
568 | rb_erase(&x->list, &mn->timer_head); | |
1da177e4 | 569 | |
cbacdd95 | 570 | if (posix_timer_event(t, 0) != 0) |
1da177e4 | 571 | t->it_overrun++; |
cbacdd95 | 572 | |
1da177e4 | 573 | if(t->it.mmtimer.incr) { |
cbacdd95 DS |
574 | t->it.mmtimer.expires += t->it.mmtimer.incr; |
575 | mmtimer_add_list(x); | |
1da177e4 LT |
576 | } else { |
577 | /* Ensure we don't false trigger in mmtimer_interrupt */ | |
cbacdd95 | 578 | t->it.mmtimer.clock = TIMER_OFF; |
1da177e4 | 579 | t->it.mmtimer.expires = 0; |
cbacdd95 | 580 | kfree(x); |
1da177e4 | 581 | } |
cbacdd95 DS |
582 | /* Set comparator for next timer, if there is one */ |
583 | mmtimer_set_next_timer(nodeid); | |
584 | ||
1da177e4 LT |
585 | t->it_overrun_last = t->it_overrun; |
586 | out: | |
cbacdd95 | 587 | spin_unlock_irqrestore(&mn->lock, flags); |
1da177e4 LT |
588 | } |
589 | ||
590 | static int sgi_timer_create(struct k_itimer *timer) | |
591 | { | |
592 | /* Insure that a newly created timer is off */ | |
593 | timer->it.mmtimer.clock = TIMER_OFF; | |
594 | return 0; | |
595 | } | |
596 | ||
597 | /* This does not really delete a timer. It just insures | |
598 | * that the timer is not active | |
599 | * | |
600 | * Assumption: it_lock is already held with irq's disabled | |
601 | */ | |
602 | static int sgi_timer_del(struct k_itimer *timr) | |
603 | { | |
1da177e4 | 604 | cnodeid_t nodeid = timr->it.mmtimer.node; |
1da177e4 LT |
605 | unsigned long irqflags; |
606 | ||
cbacdd95 DS |
607 | spin_lock_irqsave(&timers[nodeid].lock, irqflags); |
608 | if (timr->it.mmtimer.clock != TIMER_OFF) { | |
609 | unsigned long expires = timr->it.mmtimer.expires; | |
610 | struct rb_node *n = timers[nodeid].timer_head.rb_node; | |
611 | struct mmtimer *uninitialized_var(t); | |
612 | int r = 0; | |
613 | ||
1da177e4 LT |
614 | timr->it.mmtimer.clock = TIMER_OFF; |
615 | timr->it.mmtimer.expires = 0; | |
cbacdd95 DS |
616 | |
617 | while (n) { | |
618 | t = rb_entry(n, struct mmtimer, list); | |
619 | if (t->timer == timr) | |
620 | break; | |
621 | ||
622 | if (expires < t->timer->it.mmtimer.expires) | |
623 | n = n->rb_left; | |
624 | else | |
625 | n = n->rb_right; | |
626 | } | |
627 | ||
628 | if (!n) { | |
629 | spin_unlock_irqrestore(&timers[nodeid].lock, irqflags); | |
630 | return 0; | |
631 | } | |
632 | ||
633 | if (timers[nodeid].next == n) { | |
634 | timers[nodeid].next = rb_next(n); | |
635 | r = 1; | |
636 | } | |
637 | ||
638 | rb_erase(n, &timers[nodeid].timer_head); | |
639 | kfree(t); | |
640 | ||
641 | if (r) { | |
642 | mmtimer_disable_int(cnodeid_to_nasid(nodeid), | |
643 | COMPARATOR); | |
644 | mmtimer_set_next_timer(nodeid); | |
645 | } | |
1da177e4 | 646 | } |
cbacdd95 | 647 | spin_unlock_irqrestore(&timers[nodeid].lock, irqflags); |
1da177e4 LT |
648 | return 0; |
649 | } | |
650 | ||
1da177e4 LT |
651 | /* Assumption: it_lock is already held with irq's disabled */ |
652 | static void sgi_timer_get(struct k_itimer *timr, struct itimerspec *cur_setting) | |
653 | { | |
654 | ||
655 | if (timr->it.mmtimer.clock == TIMER_OFF) { | |
656 | cur_setting->it_interval.tv_nsec = 0; | |
657 | cur_setting->it_interval.tv_sec = 0; | |
658 | cur_setting->it_value.tv_nsec = 0; | |
659 | cur_setting->it_value.tv_sec =0; | |
660 | return; | |
661 | } | |
662 | ||
f8bd2258 RZ |
663 | cur_setting->it_interval = ns_to_timespec(timr->it.mmtimer.incr * sgi_clock_period); |
664 | cur_setting->it_value = ns_to_timespec((timr->it.mmtimer.expires - rtc_time()) * sgi_clock_period); | |
1da177e4 LT |
665 | } |
666 | ||
667 | ||
668 | static int sgi_timer_set(struct k_itimer *timr, int flags, | |
669 | struct itimerspec * new_setting, | |
670 | struct itimerspec * old_setting) | |
671 | { | |
1da177e4 LT |
672 | unsigned long when, period, irqflags; |
673 | int err = 0; | |
674 | cnodeid_t nodeid; | |
cbacdd95 DS |
675 | struct mmtimer *base; |
676 | struct rb_node *n; | |
1da177e4 LT |
677 | |
678 | if (old_setting) | |
679 | sgi_timer_get(timr, old_setting); | |
680 | ||
681 | sgi_timer_del(timr); | |
f8bd2258 RZ |
682 | when = timespec_to_ns(&new_setting->it_value); |
683 | period = timespec_to_ns(&new_setting->it_interval); | |
1da177e4 LT |
684 | |
685 | if (when == 0) | |
686 | /* Clear timer */ | |
687 | return 0; | |
688 | ||
cbacdd95 DS |
689 | base = kmalloc(sizeof(struct mmtimer), GFP_KERNEL); |
690 | if (base == NULL) | |
691 | return -ENOMEM; | |
692 | ||
1da177e4 LT |
693 | if (flags & TIMER_ABSTIME) { |
694 | struct timespec n; | |
695 | unsigned long now; | |
696 | ||
697 | getnstimeofday(&n); | |
f8bd2258 | 698 | now = timespec_to_ns(&n); |
1da177e4 LT |
699 | if (when > now) |
700 | when -= now; | |
701 | else | |
702 | /* Fire the timer immediately */ | |
703 | when = 0; | |
704 | } | |
705 | ||
706 | /* | |
707 | * Convert to sgi clock period. Need to keep rtc_time() as near as possible | |
708 | * to getnstimeofday() in order to be as faithful as possible to the time | |
709 | * specified. | |
710 | */ | |
711 | when = (when + sgi_clock_period - 1) / sgi_clock_period + rtc_time(); | |
712 | period = (period + sgi_clock_period - 1) / sgi_clock_period; | |
713 | ||
714 | /* | |
715 | * We are allocating a local SHub comparator. If we would be moved to another | |
716 | * cpu then another SHub may be local to us. Prohibit that by switching off | |
717 | * preemption. | |
718 | */ | |
719 | preempt_disable(); | |
720 | ||
55642d36 | 721 | nodeid = cpu_to_node(smp_processor_id()); |
1da177e4 | 722 | |
cbacdd95 DS |
723 | /* Lock the node timer structure */ |
724 | spin_lock_irqsave(&timers[nodeid].lock, irqflags); | |
1da177e4 | 725 | |
76832c28 DS |
726 | base->timer = timr; |
727 | base->cpu = smp_processor_id(); | |
1da177e4 | 728 | |
cbacdd95 | 729 | timr->it.mmtimer.clock = TIMER_SET; |
1da177e4 LT |
730 | timr->it.mmtimer.node = nodeid; |
731 | timr->it.mmtimer.incr = period; | |
732 | timr->it.mmtimer.expires = when; | |
733 | ||
cbacdd95 DS |
734 | n = timers[nodeid].next; |
735 | ||
736 | /* Add the new struct mmtimer to node's timer list */ | |
737 | mmtimer_add_list(base); | |
738 | ||
739 | if (timers[nodeid].next == n) { | |
740 | /* No need to reprogram comparator for now */ | |
741 | spin_unlock_irqrestore(&timers[nodeid].lock, irqflags); | |
742 | preempt_enable(); | |
743 | return err; | |
1da177e4 LT |
744 | } |
745 | ||
cbacdd95 DS |
746 | /* We need to reprogram the comparator */ |
747 | if (n) | |
748 | mmtimer_disable_int(cnodeid_to_nasid(nodeid), COMPARATOR); | |
749 | ||
750 | mmtimer_set_next_timer(nodeid); | |
751 | ||
752 | /* Unlock the node timer structure */ | |
753 | spin_unlock_irqrestore(&timers[nodeid].lock, irqflags); | |
1da177e4 LT |
754 | |
755 | preempt_enable(); | |
756 | ||
757 | return err; | |
758 | } | |
759 | ||
760 | static struct k_clock sgi_clock = { | |
761 | .res = 0, | |
762 | .clock_set = sgi_clock_set, | |
763 | .clock_get = sgi_clock_get, | |
764 | .timer_create = sgi_timer_create, | |
765 | .nsleep = do_posix_clock_nonanosleep, | |
766 | .timer_set = sgi_timer_set, | |
767 | .timer_del = sgi_timer_del, | |
768 | .timer_get = sgi_timer_get | |
769 | }; | |
770 | ||
771 | /** | |
772 | * mmtimer_init - device initialization routine | |
773 | * | |
774 | * Does initial setup for the mmtimer device. | |
775 | */ | |
776 | static int __init mmtimer_init(void) | |
777 | { | |
76832c28 | 778 | cnodeid_t node, maxn = -1; |
1da177e4 LT |
779 | |
780 | if (!ia64_platform_is("sn2")) | |
f032f908 | 781 | return 0; |
1da177e4 LT |
782 | |
783 | /* | |
784 | * Sanity check the cycles/sec variable | |
785 | */ | |
786 | if (sn_rtc_cycles_per_second < 100000) { | |
787 | printk(KERN_ERR "%s: unable to determine clock frequency\n", | |
788 | MMTIMER_NAME); | |
5d469ec0 | 789 | goto out1; |
1da177e4 LT |
790 | } |
791 | ||
792 | mmtimer_femtoperiod = ((unsigned long)1E15 + sn_rtc_cycles_per_second / | |
793 | 2) / sn_rtc_cycles_per_second; | |
794 | ||
0f2ed4c6 | 795 | if (request_irq(SGI_MMTIMER_VECTOR, mmtimer_interrupt, IRQF_PERCPU, MMTIMER_NAME, NULL)) { |
1da177e4 LT |
796 | printk(KERN_WARNING "%s: unable to allocate interrupt.", |
797 | MMTIMER_NAME); | |
5d469ec0 | 798 | goto out1; |
1da177e4 LT |
799 | } |
800 | ||
1da177e4 LT |
801 | if (misc_register(&mmtimer_miscdev)) { |
802 | printk(KERN_ERR "%s: failed to register device\n", | |
803 | MMTIMER_NAME); | |
5d469ec0 | 804 | goto out2; |
1da177e4 LT |
805 | } |
806 | ||
76832c28 DS |
807 | /* Get max numbered node, calculate slots needed */ |
808 | for_each_online_node(node) { | |
809 | maxn = node; | |
810 | } | |
811 | maxn++; | |
812 | ||
813 | /* Allocate list of node ptrs to mmtimer_t's */ | |
cbacdd95 | 814 | timers = kzalloc(sizeof(struct mmtimer_node)*maxn, GFP_KERNEL); |
76832c28 DS |
815 | if (timers == NULL) { |
816 | printk(KERN_ERR "%s: failed to allocate memory for device\n", | |
817 | MMTIMER_NAME); | |
5d469ec0 | 818 | goto out3; |
76832c28 DS |
819 | } |
820 | ||
cbacdd95 | 821 | /* Initialize struct mmtimer's for each online node */ |
76832c28 | 822 | for_each_online_node(node) { |
cbacdd95 DS |
823 | spin_lock_init(&timers[node].lock); |
824 | tasklet_init(&timers[node].tasklet, mmtimer_tasklet, | |
825 | (unsigned long) node); | |
76832c28 DS |
826 | } |
827 | ||
1da177e4 LT |
828 | sgi_clock_period = sgi_clock.res = NSEC_PER_SEC / sn_rtc_cycles_per_second; |
829 | register_posix_clock(CLOCK_SGI_CYCLE, &sgi_clock); | |
830 | ||
831 | printk(KERN_INFO "%s: v%s, %ld MHz\n", MMTIMER_DESC, MMTIMER_VERSION, | |
832 | sn_rtc_cycles_per_second/(unsigned long)1E6); | |
833 | ||
834 | return 0; | |
5d469ec0 | 835 | |
5d469ec0 | 836 | out3: |
cbacdd95 | 837 | kfree(timers); |
5d469ec0 NH |
838 | misc_deregister(&mmtimer_miscdev); |
839 | out2: | |
840 | free_irq(SGI_MMTIMER_VECTOR, NULL); | |
841 | out1: | |
842 | return -1; | |
1da177e4 LT |
843 | } |
844 | ||
845 | module_init(mmtimer_init); |