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Char: mxser, update documentation
[deliverable/linux.git] / drivers / char / mxser.c
CommitLineData
1da177e4
LT		 1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
80ff8a80
JS		 4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
5 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
1da177e4 6 *
1c45607a
JS		 7 * This code is loosely based on the 1.8 moxa driver which is based on
8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
1da177e4
LT		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
8ea2c2ec 14 * (at your option) any later version.
1da177e4 15 *
1da177e4
LT		 16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
17 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com.
18 * - Fixed x86_64 cleanness
1da177e4
LT		 19 */
20
1da177e4 21#include <linux/module.h>
1da177e4
LT		 22#include <linux/errno.h>
23#include <linux/signal.h>
24#include <linux/sched.h>
25#include <linux/timer.h>
26#include <linux/interrupt.h>
27#include <linux/tty.h>
28#include <linux/tty_flip.h>
29#include <linux/serial.h>
30#include <linux/serial_reg.h>
31#include <linux/major.h>
32#include <linux/string.h>
33#include <linux/fcntl.h>
34#include <linux/ptrace.h>
35#include <linux/gfp.h>
36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/delay.h>
39#include <linux/pci.h>
1977f032 40#include <linux/bitops.h>
1da177e4
LT		 41
42#include <asm/system.h>
43#include <asm/io.h>
44#include <asm/irq.h>
1da177e4
LT		 45#include <asm/uaccess.h>
46
47#include "mxser.h"
48
e129deff 49#define MXSER_VERSION "2.0.4" /* 1.12 */
1da177e4
LT		 50#define MXSERMAJOR 174
51#define MXSERCUMAJOR 175
52
1da177e4 53#define MXSER_BOARDS 4 /* Max. boards */
1da177e4 54#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
1c45607a
JS		 55#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
56#define MXSER_ISR_PASS_LIMIT 100
1da177e4
LT		 57
58#define MXSER_ERR_IOADDR -1
59#define MXSER_ERR_IRQ -2
60#define MXSER_ERR_IRQ_CONFLIT -3
61#define MXSER_ERR_VECTOR -4
62
1c45607a
JS		 63/*CheckIsMoxaMust return value*/
64#define MOXA_OTHER_UART 0x00
65#define MOXA_MUST_MU150_HWID 0x01
66#define MOXA_MUST_MU860_HWID 0x02
67
1da177e4
LT		 68#define WAKEUP_CHARS 256
69
70#define UART_MCR_AFE 0x20
71#define UART_LSR_SPECIAL 0x1E
72
e129deff 73#define PCI_DEVICE_ID_POS104UL 0x1044
1c45607a 74#define PCI_DEVICE_ID_CB108 0x1080
e129deff 75#define PCI_DEVICE_ID_CP102UF 0x1023
1c45607a 76#define PCI_DEVICE_ID_CB114 0x1142
80ff8a80 77#define PCI_DEVICE_ID_CP114UL 0x1143
1c45607a
JS		 78#define PCI_DEVICE_ID_CB134I 0x1341
79#define PCI_DEVICE_ID_CP138U 0x1380
1da177e4 80
1da177e4
LT		 81
82#define C168_ASIC_ID 1
83#define C104_ASIC_ID 2
84#define C102_ASIC_ID 0xB
85#define CI132_ASIC_ID 4
86#define CI134_ASIC_ID 3
87#define CI104J_ASIC_ID 5
88
1c45607a
JS		 89#define MXSER_HIGHBAUD 1
90#define MXSER_HAS2 2
1da177e4 91
8ea2c2ec 92/* This is only for PCI */
1c45607a 93static const struct {
1da177e4
LT		 94 int type;
95 int tx_fifo;
96 int rx_fifo;
97 int xmit_fifo_size;
98 int rx_high_water;
99 int rx_trigger;
100 int rx_low_water;
101 long max_baud;
1c45607a 102} Gpci_uart_info[] = {
1da177e4
LT		 103 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
104 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
105 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
106};
1c45607a 107#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
1da177e4 108
1c45607a
JS		 109struct mxser_cardinfo {
110 char *name;
111 unsigned int nports;
112 unsigned int flags;
113};
1da177e4 114
1c45607a
JS		 115static const struct mxser_cardinfo mxser_cards[] = {
116/* 0*/ { "C168 series", 8, },
117 { "C104 series", 4, },
118 { "CI-104J series", 4, },
119 { "C168H/PCI series", 8, },
120 { "C104H/PCI series", 4, },
121/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
122 { "CI-132 series", 4, MXSER_HAS2 },
123 { "CI-134 series", 4, },
124 { "CP-132 series", 2, },
125 { "CP-114 series", 4, },
126/*10*/ { "CT-114 series", 4, },
127 { "CP-102 series", 2, MXSER_HIGHBAUD },
128 { "CP-104U series", 4, },
129 { "CP-168U series", 8, },
130 { "CP-132U series", 2, },
131/*15*/ { "CP-134U series", 4, },
132 { "CP-104JU series", 4, },
133 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
134 { "CP-118U series", 8, },
135 { "CP-102UL series", 2, },
136/*20*/ { "CP-102U series", 2, },
137 { "CP-118EL series", 8, },
138 { "CP-168EL series", 8, },
139 { "CP-104EL series", 4, },
140 { "CB-108 series", 8, },
141/*25*/ { "CB-114 series", 4, },
142 { "CB-134I series", 4, },
143 { "CP-138U series", 8, },
80ff8a80 144 { "POS-104UL series", 4, },
e129deff
JS		 145 { "CP-114UL series", 4, },
146/*30*/ { "CP-102UF series", 2, }
1c45607a 147};
1da177e4 148
1c45607a
JS		 149/* driver_data correspond to the lines in the structure above
150 see also ISA probe function before you change something */
1da177e4 151static struct pci_device_id mxser_pcibrds[] = {
1c45607a
JS		 152 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
153 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
154 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
155 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
156 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
157 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
158 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
159 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
160 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
161 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
162 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
163 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
164 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
165 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
166 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
167 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
168 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
169 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
170 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
171 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
172 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
173 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
174 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
80ff8a80 175 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 29 },
e129deff 176 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 30 },
1c45607a 177 { }
1da177e4 178};
1da177e4
LT		 179MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
180
1da177e4
LT		 181static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 };
182static int ttymajor = MXSERMAJOR;
1da177e4
LT		 183
184/* Variables for insmod */
185
186MODULE_AUTHOR("Casper Yang");
187MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
8d3b33f6
RR		 188module_param_array(ioaddr, int, NULL, 0);
189module_param(ttymajor, int, 0);
1da177e4
LT		 190MODULE_LICENSE("GPL");
191
192struct mxser_log {
193 int tick;
194 unsigned long rxcnt[MXSER_PORTS];
195 unsigned long txcnt[MXSER_PORTS];
196};
197
198
199struct mxser_mon {
200 unsigned long rxcnt;
201 unsigned long txcnt;
202 unsigned long up_rxcnt;
203 unsigned long up_txcnt;
204 int modem_status;
205 unsigned char hold_reason;
206};
207
208struct mxser_mon_ext {
209 unsigned long rx_cnt[32];
210 unsigned long tx_cnt[32];
211 unsigned long up_rxcnt[32];
212 unsigned long up_txcnt[32];
213 int modem_status[32];
214
215 long baudrate[32];
216 int databits[32];
217 int stopbits[32];
218 int parity[32];
219 int flowctrl[32];
220 int fifo[32];
221 int iftype[32];
222};
8ea2c2ec 223
1c45607a
JS		 224struct mxser_board;
225
226struct mxser_port {
0ad9e7d1 227 struct tty_port port;
1c45607a 228 struct mxser_board *board;
1c45607a
JS		 229
230 unsigned long ioaddr;
231 unsigned long opmode_ioaddr;
232 int max_baud;
1da177e4 233
1da177e4
LT		 234 int rx_high_water;
235 int rx_trigger; /* Rx fifo trigger level */
236 int rx_low_water;
237 int baud_base; /* max. speed */
1da177e4 238 int type; /* UART type */
1c45607a 239
1da177e4 240 int x_char; /* xon/xoff character */
1da177e4
LT		 241 int IER; /* Interrupt Enable Register */
242 int MCR; /* Modem control register */
1c45607a
JS		 243
244 unsigned char stop_rx;
245 unsigned char ldisc_stop_rx;
246
247 int custom_divisor;
1c45607a 248 unsigned char err_shadow;
1c45607a 249
1c45607a
JS		 250 struct async_icount icount; /* kernel counters for 4 input interrupts */
251 int timeout;
252
253 int read_status_mask;
254 int ignore_status_mask;
255 int xmit_fifo_size;
1da177e4
LT		 256 int xmit_head;
257 int xmit_tail;
258 int xmit_cnt;
1c45607a 259
606d099c 260 struct ktermios normal_termios;
1c45607a 261
1da177e4 262 struct mxser_mon mon_data;
1c45607a 263
1da177e4 264 spinlock_t slock;
1c45607a
JS		 265 wait_queue_head_t delta_msr_wait;
266};
267
268struct mxser_board {
269 unsigned int idx;
270 int irq;
271 const struct mxser_cardinfo *info;
272 unsigned long vector;
273 unsigned long vector_mask;
274
275 int chip_flag;
276 int uart_type;
277
278 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
1da177e4
LT		 279};
280
1da177e4
LT		 281struct mxser_mstatus {
282 tcflag_t cflag;
283 int cts;
284 int dsr;
285 int ri;
286 int dcd;
287};
288
1da177e4
LT		 289static int mxserBoardCAP[MXSER_BOARDS] = {
290 0, 0, 0, 0
8ea2c2ec 291 /* 0x180, 0x280, 0x200, 0x320 */
1da177e4
LT		 292};
293
1c45607a 294static struct mxser_board mxser_boards[MXSER_BOARDS];
1da177e4 295static struct tty_driver *mxvar_sdriver;
1da177e4 296static struct mxser_log mxvar_log;
1da177e4 297static int mxser_set_baud_method[MXSER_PORTS + 1];
1da177e4 298
148ff86b
CH		 299static void mxser_enable_must_enchance_mode(unsigned long baseio)
300{
301 u8 oldlcr;
302 u8 efr;
303
304 oldlcr = inb(baseio + UART_LCR);
305 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
306
307 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
308 efr |= MOXA_MUST_EFR_EFRB_ENABLE;
309
310 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
311 outb(oldlcr, baseio + UART_LCR);
312}
313
314static void mxser_disable_must_enchance_mode(unsigned long baseio)
315{
316 u8 oldlcr;
317 u8 efr;
318
319 oldlcr = inb(baseio + UART_LCR);
320 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
321
322 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
323 efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
324
325 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
326 outb(oldlcr, baseio + UART_LCR);
327}
328
329static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
330{
331 u8 oldlcr;
332 u8 efr;
333
334 oldlcr = inb(baseio + UART_LCR);
335 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
336
337 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
338 efr &= ~MOXA_MUST_EFR_BANK_MASK;
339 efr |= MOXA_MUST_EFR_BANK0;
340
341 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
342 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
343 outb(oldlcr, baseio + UART_LCR);
344}
345
346static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
347{
348 u8 oldlcr;
349 u8 efr;
350
351 oldlcr = inb(baseio + UART_LCR);
352 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
353
354 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
355 efr &= ~MOXA_MUST_EFR_BANK_MASK;
356 efr |= MOXA_MUST_EFR_BANK0;
357
358 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
359 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
360 outb(oldlcr, baseio + UART_LCR);
361}
362
363static void mxser_set_must_fifo_value(struct mxser_port *info)
364{
365 u8 oldlcr;
366 u8 efr;
367
368 oldlcr = inb(info->ioaddr + UART_LCR);
369 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
370
371 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
372 efr &= ~MOXA_MUST_EFR_BANK_MASK;
373 efr |= MOXA_MUST_EFR_BANK1;
374
375 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
376 outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
377 outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
378 outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
379 outb(oldlcr, info->ioaddr + UART_LCR);
380}
381
382static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
383{
384 u8 oldlcr;
385 u8 efr;
386
387 oldlcr = inb(baseio + UART_LCR);
388 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
389
390 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
391 efr &= ~MOXA_MUST_EFR_BANK_MASK;
392 efr |= MOXA_MUST_EFR_BANK2;
393
394 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
395 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
396 outb(oldlcr, baseio + UART_LCR);
397}
398
399static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
400{
401 u8 oldlcr;
402 u8 efr;
403
404 oldlcr = inb(baseio + UART_LCR);
405 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
406
407 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
408 efr &= ~MOXA_MUST_EFR_BANK_MASK;
409 efr |= MOXA_MUST_EFR_BANK2;
410
411 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
412 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
413 outb(oldlcr, baseio + UART_LCR);
414}
415
416static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
417{
418 u8 oldlcr;
419 u8 efr;
420
421 oldlcr = inb(baseio + UART_LCR);
422 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
423
424 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
425 efr &= ~MOXA_MUST_EFR_SF_MASK;
426
427 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
428 outb(oldlcr, baseio + UART_LCR);
429}
430
431static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
432{
433 u8 oldlcr;
434 u8 efr;
435
436 oldlcr = inb(baseio + UART_LCR);
437 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
438
439 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
440 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
441 efr |= MOXA_MUST_EFR_SF_TX1;
442
443 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
444 outb(oldlcr, baseio + UART_LCR);
445}
446
447static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
448{
449 u8 oldlcr;
450 u8 efr;
451
452 oldlcr = inb(baseio + UART_LCR);
453 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
454
455 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
456 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
457
458 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
459 outb(oldlcr, baseio + UART_LCR);
460}
461
462static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
463{
464 u8 oldlcr;
465 u8 efr;
466
467 oldlcr = inb(baseio + UART_LCR);
468 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
469
470 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
471 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
472 efr |= MOXA_MUST_EFR_SF_RX1;
473
474 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
475 outb(oldlcr, baseio + UART_LCR);
476}
477
478static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
479{
480 u8 oldlcr;
481 u8 efr;
482
483 oldlcr = inb(baseio + UART_LCR);
484 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
485
486 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
487 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
488
489 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
490 outb(oldlcr, baseio + UART_LCR);
491}
492
b8cc5549 493#ifdef CONFIG_PCI
1c45607a 494static int __devinit CheckIsMoxaMust(unsigned long io)
1da177e4
LT		 495{
496 u8 oldmcr, hwid;
497 int i;
498
499 outb(0, io + UART_LCR);
148ff86b 500 mxser_disable_must_enchance_mode(io);
1da177e4
LT		 501 oldmcr = inb(io + UART_MCR);
502 outb(0, io + UART_MCR);
148ff86b 503 mxser_set_must_xon1_value(io, 0x11);
1da177e4
LT		 504 if ((hwid = inb(io + UART_MCR)) != 0) {
505 outb(oldmcr, io + UART_MCR);
8ea2c2ec 506 return MOXA_OTHER_UART;
1da177e4
LT		 507 }
508
148ff86b 509 mxser_get_must_hardware_id(io, &hwid);
1c45607a
JS		 510 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
511 if (hwid == Gpci_uart_info[i].type)
8ea2c2ec 512 return (int)hwid;
1da177e4
LT		 513 }
514 return MOXA_OTHER_UART;
515}
b8cc5549 516#endif
1da177e4 517
1c45607a 518static void process_txrx_fifo(struct mxser_port *info)
1da177e4
LT		 519{
520 int i;
521
522 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
523 info->rx_trigger = 1;
524 info->rx_high_water = 1;
525 info->rx_low_water = 1;
526 info->xmit_fifo_size = 1;
1c45607a
JS		 527 } else
528 for (i = 0; i < UART_INFO_NUM; i++)
529 if (info->board->chip_flag == Gpci_uart_info[i].type) {
1da177e4
LT		 530 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
531 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
532 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
533 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
534 break;
535 }
1da177e4
LT		 536}
537
1c45607a 538static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
1da177e4 539{
72800df9 540 static unsigned char mxser_msr[MXSER_PORTS + 1];
1c45607a 541 unsigned char status = 0;
1da177e4 542
1c45607a 543 status = inb(baseaddr + UART_MSR);
1da177e4 544
1c45607a
JS		 545 mxser_msr[port] &= 0x0F;
546 mxser_msr[port] |= status;
547 status = mxser_msr[port];
548 if (mode)
549 mxser_msr[port] = 0;
1da177e4 550
1c45607a
JS		 551 return status;
552}
1da177e4 553
1c45607a
JS		 554static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp,
555 struct mxser_port *port)
556{
557 DECLARE_WAITQUEUE(wait, current);
558 int retval;
559 int do_clocal = 0;
560 unsigned long flags;
1da177e4 561
1c45607a
JS		 562 /*
563 * If non-blocking mode is set, or the port is not enabled,
564 * then make the check up front and then exit.
565 */
566 if ((filp->f_flags & O_NONBLOCK) ||
567 test_bit(TTY_IO_ERROR, &tty->flags)) {
0ad9e7d1 568 port->port.flags |= ASYNC_NORMAL_ACTIVE;
1c45607a
JS		 569 return 0;
570 }
1da177e4 571
1c45607a
JS		 572 if (tty->termios->c_cflag & CLOCAL)
573 do_clocal = 1;
1da177e4 574
1da177e4 575 /*
1c45607a
JS		 576 * Block waiting for the carrier detect and the line to become
577 * free (i.e., not in use by the callout). While we are in
0ad9e7d1 578 * this loop, port->port.count is dropped by one, so that
1c45607a
JS		 579 * mxser_close() knows when to free things. We restore it upon
580 * exit, either normal or abnormal.
1da177e4 581 */
1c45607a 582 retval = 0;
0ad9e7d1 583 add_wait_queue(&port->port.open_wait, &wait);
1da177e4 584
1c45607a
JS		 585 spin_lock_irqsave(&port->slock, flags);
586 if (!tty_hung_up_p(filp))
0ad9e7d1 587 port->port.count--;
1c45607a 588 spin_unlock_irqrestore(&port->slock, flags);
0ad9e7d1 589 port->port.blocked_open++;
1c45607a
JS		 590 while (1) {
591 spin_lock_irqsave(&port->slock, flags);
592 outb(inb(port->ioaddr + UART_MCR) |
593 UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR);
594 spin_unlock_irqrestore(&port->slock, flags);
595 set_current_state(TASK_INTERRUPTIBLE);
0ad9e7d1
AC		 596 if (tty_hung_up_p(filp) || !(port->port.flags & ASYNC_INITIALIZED)) {
597 if (port->port.flags & ASYNC_HUP_NOTIFY)
1c45607a
JS		 598 retval = -EAGAIN;
599 else
600 retval = -ERESTARTSYS;
601 break;
602 }
0ad9e7d1 603 if (!(port->port.flags & ASYNC_CLOSING) &&
1c45607a
JS		 604 (do_clocal ||
605 (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD)))
606 break;
607 if (signal_pending(current)) {
608 retval = -ERESTARTSYS;
609 break;
610 }
611 schedule();
1da177e4 612 }
1c45607a 613 set_current_state(TASK_RUNNING);
0ad9e7d1 614 remove_wait_queue(&port->port.open_wait, &wait);
1c45607a 615 if (!tty_hung_up_p(filp))
0ad9e7d1
AC		 616 port->port.count++;
617 port->port.blocked_open--;
1c45607a 618 if (retval)
1da177e4 619 return retval;
0ad9e7d1 620 port->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 621 return 0;
622}
623
1c45607a 624static int mxser_set_baud(struct mxser_port *info, long newspd)
1da177e4 625{
1c45607a
JS		 626 int quot = 0, baud;
627 unsigned char cval;
1da177e4 628
0ad9e7d1 629 if (!info->port.tty || !info->port.tty->termios)
1c45607a 630 return -1;
1da177e4 631
1c45607a
JS		 632 if (!(info->ioaddr))
633 return -1;
1da177e4 634
1c45607a
JS		 635 if (newspd > info->max_baud)
636 return -1;
1da177e4 637
1c45607a
JS		 638 if (newspd == 134) {
639 quot = 2 * info->baud_base / 269;
0ad9e7d1 640 tty_encode_baud_rate(info->port.tty, 134, 134);
1c45607a
JS		 641 } else if (newspd) {
642 quot = info->baud_base / newspd;
643 if (quot == 0)
644 quot = 1;
645 baud = info->baud_base/quot;
0ad9e7d1 646 tty_encode_baud_rate(info->port.tty, baud, baud);
1c45607a
JS		 647 } else {
648 quot = 0;
649 }
1da177e4 650
1c45607a
JS		 651 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
652 info->timeout += HZ / 50; /* Add .02 seconds of slop */
1da177e4 653
1c45607a
JS		 654 if (quot) {
655 info->MCR |= UART_MCR_DTR;
656 outb(info->MCR, info->ioaddr + UART_MCR);
657 } else {
658 info->MCR &= ~UART_MCR_DTR;
659 outb(info->MCR, info->ioaddr + UART_MCR);
660 return 0;
661 }
1da177e4 662
1c45607a 663 cval = inb(info->ioaddr + UART_LCR);
1da177e4 664
1c45607a 665 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
1da177e4 666
1c45607a
JS		 667 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
668 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
669 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
1da177e4 670
1c45607a 671#ifdef BOTHER
0ad9e7d1 672 if (C_BAUD(info->port.tty) == BOTHER) {
1c45607a
JS		 673 quot = info->baud_base % newspd;
674 quot *= 8;
675 if (quot % newspd > newspd / 2) {
676 quot /= newspd;
677 quot++;
678 } else
679 quot /= newspd;
680
148ff86b 681 mxser_set_must_enum_value(info->ioaddr, quot);
1c45607a
JS		 682 } else
683#endif
148ff86b 684 mxser_set_must_enum_value(info->ioaddr, 0);
1da177e4 685
8ea2c2ec 686 return 0;
1da177e4 687}
1da177e4 688
1c45607a
JS		 689/*
690 * This routine is called to set the UART divisor registers to match
691 * the specified baud rate for a serial port.
692 */
693static int mxser_change_speed(struct mxser_port *info,
694 struct ktermios *old_termios)
1da177e4 695{
1c45607a
JS		 696 unsigned cflag, cval, fcr;
697 int ret = 0;
698 unsigned char status;
1da177e4 699
0ad9e7d1 700 if (!info->port.tty || !info->port.tty->termios)
1c45607a 701 return ret;
0ad9e7d1 702 cflag = info->port.tty->termios->c_cflag;
1c45607a
JS		 703 if (!(info->ioaddr))
704 return ret;
1da177e4 705
0ad9e7d1
AC		 706 if (mxser_set_baud_method[info->port.tty->index] == 0)
707 mxser_set_baud(info, tty_get_baud_rate(info->port.tty));
1da177e4 708
1c45607a
JS		 709 /* byte size and parity */
710 switch (cflag & CSIZE) {
711 case CS5:
712 cval = 0x00;
713 break;
714 case CS6:
715 cval = 0x01;
716 break;
717 case CS7:
718 cval = 0x02;
719 break;
720 case CS8:
721 cval = 0x03;
722 break;
723 default:
724 cval = 0x00;
725 break; /* too keep GCC shut... */
726 }
727 if (cflag & CSTOPB)
728 cval |= 0x04;
729 if (cflag & PARENB)
730 cval |= UART_LCR_PARITY;
731 if (!(cflag & PARODD))
732 cval |= UART_LCR_EPAR;
733 if (cflag & CMSPAR)
734 cval |= UART_LCR_SPAR;
1da177e4 735
1c45607a
JS		 736 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
737 if (info->board->chip_flag) {
738 fcr = UART_FCR_ENABLE_FIFO;
739 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 740 mxser_set_must_fifo_value(info);
1c45607a
JS		 741 } else
742 fcr = 0;
743 } else {
744 fcr = UART_FCR_ENABLE_FIFO;
745 if (info->board->chip_flag) {
746 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 747 mxser_set_must_fifo_value(info);
1c45607a
JS		 748 } else {
749 switch (info->rx_trigger) {
750 case 1:
751 fcr |= UART_FCR_TRIGGER_1;
752 break;
753 case 4:
754 fcr |= UART_FCR_TRIGGER_4;
755 break;
756 case 8:
757 fcr |= UART_FCR_TRIGGER_8;
758 break;
759 default:
760 fcr |= UART_FCR_TRIGGER_14;
761 break;
762 }
1da177e4 763 }
1da177e4
LT		 764 }
765
1c45607a
JS		 766 /* CTS flow control flag and modem status interrupts */
767 info->IER &= ~UART_IER_MSI;
768 info->MCR &= ~UART_MCR_AFE;
769 if (cflag & CRTSCTS) {
0ad9e7d1 770 info->port.flags |= ASYNC_CTS_FLOW;
1c45607a
JS		 771 info->IER |= UART_IER_MSI;
772 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
773 info->MCR |= UART_MCR_AFE;
774 } else {
775 status = inb(info->ioaddr + UART_MSR);
0ad9e7d1 776 if (info->port.tty->hw_stopped) {
1c45607a 777 if (status & UART_MSR_CTS) {
0ad9e7d1 778 info->port.tty->hw_stopped = 0;
1c45607a
JS		 779 if (info->type != PORT_16550A &&
780 !info->board->chip_flag) {
781 outb(info->IER & ~UART_IER_THRI,
782 info->ioaddr +
783 UART_IER);
784 info->IER |= UART_IER_THRI;
785 outb(info->IER, info->ioaddr +
786 UART_IER);
787 }
0ad9e7d1 788 tty_wakeup(info->port.tty);
1c45607a
JS		 789 }
790 } else {
791 if (!(status & UART_MSR_CTS)) {
0ad9e7d1 792 info->port.tty->hw_stopped = 1;
1c45607a
JS		 793 if ((info->type != PORT_16550A) &&
794 (!info->board->chip_flag)) {
795 info->IER &= ~UART_IER_THRI;
796 outb(info->IER, info->ioaddr +
797 UART_IER);
798 }
799 }
800 }
1da177e4 801 }
1c45607a 802 } else {
0ad9e7d1 803 info->port.flags &= ~ASYNC_CTS_FLOW;
1c45607a
JS		 804 }
805 outb(info->MCR, info->ioaddr + UART_MCR);
806 if (cflag & CLOCAL) {
0ad9e7d1 807 info->port.flags &= ~ASYNC_CHECK_CD;
1c45607a 808 } else {
0ad9e7d1 809 info->port.flags |= ASYNC_CHECK_CD;
1c45607a
JS		 810 info->IER |= UART_IER_MSI;
811 }
812 outb(info->IER, info->ioaddr + UART_IER);
813
814 /*
815 * Set up parity check flag
816 */
817 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
0ad9e7d1 818 if (I_INPCK(info->port.tty))
1c45607a 819 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
0ad9e7d1 820 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1c45607a 821 info->read_status_mask |= UART_LSR_BI;
1da177e4 822
1c45607a 823 info->ignore_status_mask = 0;
1da177e4 824
0ad9e7d1 825 if (I_IGNBRK(info->port.tty)) {
1c45607a
JS		 826 info->ignore_status_mask |= UART_LSR_BI;
827 info->read_status_mask |= UART_LSR_BI;
8ea2c2ec 828 /*
1c45607a
JS		 829 * If we're ignore parity and break indicators, ignore
830 * overruns too. (For real raw support).
8ea2c2ec 831 */
0ad9e7d1 832 if (I_IGNPAR(info->port.tty)) {
1c45607a
JS		 833 info->ignore_status_mask |=
834 UART_LSR_OE |
835 UART_LSR_PE |
836 UART_LSR_FE;
837 info->read_status_mask |=
838 UART_LSR_OE |
839 UART_LSR_PE |
840 UART_LSR_FE;
841 }
1da177e4 842 }
1c45607a 843 if (info->board->chip_flag) {
0ad9e7d1
AC		 844 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(info->port.tty));
845 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(info->port.tty));
846 if (I_IXON(info->port.tty)) {
148ff86b
CH		 847 mxser_enable_must_rx_software_flow_control(
848 info->ioaddr);
1c45607a 849 } else {
148ff86b
CH		 850 mxser_disable_must_rx_software_flow_control(
851 info->ioaddr);
1da177e4 852 }
0ad9e7d1 853 if (I_IXOFF(info->port.tty)) {
148ff86b
CH		 854 mxser_enable_must_tx_software_flow_control(
855 info->ioaddr);
1c45607a 856 } else {
148ff86b
CH		 857 mxser_disable_must_tx_software_flow_control(
858 info->ioaddr);
1da177e4
LT		 859 }
860 }
1da177e4 861
1da177e4 862
1c45607a
JS		 863 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
864 outb(cval, info->ioaddr + UART_LCR);
1da177e4 865
1c45607a 866 return ret;
1da177e4
LT		 867}
868
1c45607a 869static void mxser_check_modem_status(struct mxser_port *port, int status)
1da177e4 870{
1c45607a
JS		 871 /* update input line counters */
872 if (status & UART_MSR_TERI)
873 port->icount.rng++;
874 if (status & UART_MSR_DDSR)
875 port->icount.dsr++;
876 if (status & UART_MSR_DDCD)
877 port->icount.dcd++;
878 if (status & UART_MSR_DCTS)
879 port->icount.cts++;
880 port->mon_data.modem_status = status;
881 wake_up_interruptible(&port->delta_msr_wait);
1da177e4 882
0ad9e7d1 883 if ((port->port.flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
1c45607a 884 if (status & UART_MSR_DCD)
0ad9e7d1 885 wake_up_interruptible(&port->port.open_wait);
1c45607a 886 }
1da177e4 887
0ad9e7d1
AC		 888 if (port->port.flags & ASYNC_CTS_FLOW) {
889 if (port->port.tty->hw_stopped) {
1c45607a 890 if (status & UART_MSR_CTS) {
0ad9e7d1 891 port->port.tty->hw_stopped = 0;
1c45607a
JS		 892
893 if ((port->type != PORT_16550A) &&
894 (!port->board->chip_flag)) {
895 outb(port->IER & ~UART_IER_THRI,
896 port->ioaddr + UART_IER);
897 port->IER |= UART_IER_THRI;
898 outb(port->IER, port->ioaddr +
899 UART_IER);
900 }
0ad9e7d1 901 tty_wakeup(port->port.tty);
1c45607a
JS		 902 }
903 } else {
904 if (!(status & UART_MSR_CTS)) {
0ad9e7d1 905 port->port.tty->hw_stopped = 1;
1c45607a
JS		 906 if (port->type != PORT_16550A &&
907 !port->board->chip_flag) {
908 port->IER &= ~UART_IER_THRI;
909 outb(port->IER, port->ioaddr +
910 UART_IER);
911 }
912 }
913 }
1da177e4
LT		 914 }
915}
916
1c45607a 917static int mxser_startup(struct mxser_port *info)
1da177e4 918{
1c45607a
JS		 919 unsigned long page;
920 unsigned long flags;
1da177e4 921
1c45607a
JS		 922 page = __get_free_page(GFP_KERNEL);
923 if (!page)
924 return -ENOMEM;
1da177e4 925
1c45607a 926 spin_lock_irqsave(&info->slock, flags);
1da177e4 927
0ad9e7d1 928 if (info->port.flags & ASYNC_INITIALIZED) {
1c45607a
JS		 929 free_page(page);
930 spin_unlock_irqrestore(&info->slock, flags);
931 return 0;
932 }
6f08b72c 933
1c45607a 934 if (!info->ioaddr || !info->type) {
0ad9e7d1
AC		 935 if (info->port.tty)
936 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1c45607a
JS		 937 free_page(page);
938 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 939 return 0;
1c45607a 940 }
0ad9e7d1 941 if (info->port.xmit_buf)
1c45607a
JS		 942 free_page(page);
943 else
0ad9e7d1 944 info->port.xmit_buf = (unsigned char *) page;
1da177e4 945
1da177e4 946 /*
1c45607a
JS		 947 * Clear the FIFO buffers and disable them
948 * (they will be reenabled in mxser_change_speed())
1da177e4 949 */
1c45607a
JS		 950 if (info->board->chip_flag)
951 outb((UART_FCR_CLEAR_RCVR |
952 UART_FCR_CLEAR_XMIT |
953 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
954 else
955 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
956 info->ioaddr + UART_FCR);
1da177e4 957
1c45607a
JS		 958 /*
959 * At this point there's no way the LSR could still be 0xFF;
960 * if it is, then bail out, because there's likely no UART
961 * here.
962 */
963 if (inb(info->ioaddr + UART_LSR) == 0xff) {
964 spin_unlock_irqrestore(&info->slock, flags);
965 if (capable(CAP_SYS_ADMIN)) {
0ad9e7d1
AC		 966 if (info->port.tty)
967 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1c45607a
JS		 968 return 0;
969 } else
970 return -ENODEV;
971 }
1da177e4 972
1c45607a
JS		 973 /*
974 * Clear the interrupt registers.
975 */
976 (void) inb(info->ioaddr + UART_LSR);
977 (void) inb(info->ioaddr + UART_RX);
978 (void) inb(info->ioaddr + UART_IIR);
979 (void) inb(info->ioaddr + UART_MSR);
980
981 /*
982 * Now, initialize the UART
983 */
984 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
985 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
986 outb(info->MCR, info->ioaddr + UART_MCR);
987
988 /*
989 * Finally, enable interrupts
990 */
991 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
992
993 if (info->board->chip_flag)
994 info->IER |= MOXA_MUST_IER_EGDAI;
995 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
996
997 /*
998 * And clear the interrupt registers again for luck.
999 */
1000 (void) inb(info->ioaddr + UART_LSR);
1001 (void) inb(info->ioaddr + UART_RX);
1002 (void) inb(info->ioaddr + UART_IIR);
1003 (void) inb(info->ioaddr + UART_MSR);
1004
0ad9e7d1
AC		 1005 if (info->port.tty)
1006 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1c45607a
JS		 1007 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1008
1009 /*
1010 * and set the speed of the serial port
1011 */
1012 mxser_change_speed(info, NULL);
0ad9e7d1 1013 info->port.flags |= ASYNC_INITIALIZED;
1c45607a
JS		 1014 spin_unlock_irqrestore(&info->slock, flags);
1015
1016 return 0;
1017}
1018
1019/*
1020 * This routine will shutdown a serial port; interrupts maybe disabled, and
1021 * DTR is dropped if the hangup on close termio flag is on.
1022 */
1023static void mxser_shutdown(struct mxser_port *info)
1024{
1025 unsigned long flags;
1026
0ad9e7d1 1027 if (!(info->port.flags & ASYNC_INITIALIZED))
1c45607a
JS		 1028 return;
1029
1030 spin_lock_irqsave(&info->slock, flags);
1031
1032 /*
1033 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
1034 * here so the queue might never be waken up
1035 */
1036 wake_up_interruptible(&info->delta_msr_wait);
1037
1038 /*
1039 * Free the IRQ, if necessary
1040 */
0ad9e7d1
AC		 1041 if (info->port.xmit_buf) {
1042 free_page((unsigned long) info->port.xmit_buf);
1043 info->port.xmit_buf = NULL;
1da177e4
LT		 1044 }
1045
1c45607a
JS		 1046 info->IER = 0;
1047 outb(0x00, info->ioaddr + UART_IER);
1048
0ad9e7d1 1049 if (!info->port.tty || (info->port.tty->termios->c_cflag & HUPCL))
1c45607a
JS		 1050 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS);
1051 outb(info->MCR, info->ioaddr + UART_MCR);
1052
1053 /* clear Rx/Tx FIFO's */
1054 if (info->board->chip_flag)
1055 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
1056 MOXA_MUST_FCR_GDA_MODE_ENABLE,
1057 info->ioaddr + UART_FCR);
1058 else
1059 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1060 info->ioaddr + UART_FCR);
1061
1062 /* read data port to reset things */
1063 (void) inb(info->ioaddr + UART_RX);
1064
0ad9e7d1
AC		 1065 if (info->port.tty)
1066 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1c45607a 1067
0ad9e7d1 1068 info->port.flags &= ~ASYNC_INITIALIZED;
1c45607a
JS		 1069
1070 if (info->board->chip_flag)
1071 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
1072
1073 spin_unlock_irqrestore(&info->slock, flags);
1074}
1075
1076/*
1077 * This routine is called whenever a serial port is opened. It
1078 * enables interrupts for a serial port, linking in its async structure into
1079 * the IRQ chain. It also performs the serial-specific
1080 * initialization for the tty structure.
1081 */
1082static int mxser_open(struct tty_struct *tty, struct file *filp)
1083{
1084 struct mxser_port *info;
1085 unsigned long flags;
1086 int retval, line;
1087
1088 line = tty->index;
1089 if (line == MXSER_PORTS)
1090 return 0;
1091 if (line < 0 || line > MXSER_PORTS)
1092 return -ENODEV;
1093 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1094 if (!info->ioaddr)
1095 return -ENODEV;
1096
1097 tty->driver_data = info;
0ad9e7d1 1098 info->port.tty = tty;
8ea2c2ec 1099 /*
1c45607a
JS		 1100 * Start up serial port
1101 */
1102 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1103 info->port.count++;
1c45607a
JS		 1104 spin_unlock_irqrestore(&info->slock, flags);
1105 retval = mxser_startup(info);
1106 if (retval)
1107 return retval;
1108
1109 retval = mxser_block_til_ready(tty, filp, info);
1110 if (retval)
1111 return retval;
1da177e4 1112
8cddd707 1113 /* unmark here for very high baud rate (ex. 921600 bps) used */
1da177e4
LT		 1114 tty->low_latency = 1;
1115 return 0;
1116}
1117
978e595f
AC		 1118static void mxser_flush_buffer(struct tty_struct *tty)
1119{
1120 struct mxser_port *info = tty->driver_data;
1121 char fcr;
1122 unsigned long flags;
1123
1124
1125 spin_lock_irqsave(&info->slock, flags);
1126 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1127
1128 fcr = inb(info->ioaddr + UART_FCR);
1129 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1130 info->ioaddr + UART_FCR);
1131 outb(fcr, info->ioaddr + UART_FCR);
1132
1133 spin_unlock_irqrestore(&info->slock, flags);
1134
1135 tty_wakeup(tty);
1136}
1137
1138
1da177e4
LT		 1139/*
1140 * This routine is called when the serial port gets closed. First, we
1141 * wait for the last remaining data to be sent. Then, we unlink its
1142 * async structure from the interrupt chain if necessary, and we free
1143 * that IRQ if nothing is left in the chain.
1144 */
1145static void mxser_close(struct tty_struct *tty, struct file *filp)
1146{
1c45607a 1147 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1148
1149 unsigned long timeout;
1150 unsigned long flags;
1da177e4
LT		 1151
1152 if (tty->index == MXSER_PORTS)
1153 return;
1154 if (!info)
6f08b72c 1155 return;
1da177e4
LT		 1156
1157 spin_lock_irqsave(&info->slock, flags);
1158
1159 if (tty_hung_up_p(filp)) {
1160 spin_unlock_irqrestore(&info->slock, flags);
1161 return;
1162 }
0ad9e7d1 1163 if ((tty->count == 1) && (info->port.count != 1)) {
1da177e4
LT		 1164 /*
1165 * Uh, oh. tty->count is 1, which means that the tty
0ad9e7d1 1166 * structure will be freed. Info->port.count should always
1da177e4
LT		 1167 * be one in these conditions. If it's greater than
1168 * one, we've got real problems, since it means the
1169 * serial port won't be shutdown.
1170 */
8ea2c2ec 1171 printk(KERN_ERR "mxser_close: bad serial port count; "
0ad9e7d1
AC		 1172 "tty->count is 1, info->port.count is %d\n", info->port.count);
1173 info->port.count = 1;
1da177e4 1174 }
0ad9e7d1 1175 if (--info->port.count < 0) {
8ea2c2ec 1176 printk(KERN_ERR "mxser_close: bad serial port count for "
0ad9e7d1
AC		 1177 "ttys%d: %d\n", tty->index, info->port.count);
1178 info->port.count = 0;
1da177e4 1179 }
0ad9e7d1 1180 if (info->port.count) {
1da177e4
LT		 1181 spin_unlock_irqrestore(&info->slock, flags);
1182 return;
1183 }
0ad9e7d1 1184 info->port.flags |= ASYNC_CLOSING;
1da177e4
LT		 1185 spin_unlock_irqrestore(&info->slock, flags);
1186 /*
1187 * Save the termios structure, since this port may have
1188 * separate termios for callout and dialin.
1189 */
0ad9e7d1 1190 if (info->port.flags & ASYNC_NORMAL_ACTIVE)
1da177e4
LT		 1191 info->normal_termios = *tty->termios;
1192 /*
1193 * Now we wait for the transmit buffer to clear; and we notify
1194 * the line discipline to only process XON/XOFF characters.
1195 */
1196 tty->closing = 1;
44b7d1b3
AC		 1197 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
1198 tty_wait_until_sent(tty, info->port.closing_wait);
1da177e4
LT		 1199 /*
1200 * At this point we stop accepting input. To do this, we
1201 * disable the receive line status interrupts, and tell the
1202 * interrupt driver to stop checking the data ready bit in the
1203 * line status register.
1204 */
1205 info->IER &= ~UART_IER_RLSI;
1c45607a 1206 if (info->board->chip_flag)
1da177e4 1207 info->IER &= ~MOXA_MUST_RECV_ISR;
1c45607a 1208
0ad9e7d1 1209 if (info->port.flags & ASYNC_INITIALIZED) {
1c45607a 1210 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1211 /*
1212 * Before we drop DTR, make sure the UART transmitter
1213 * has completely drained; this is especially
1214 * important if there is a transmit FIFO!
1215 */
1216 timeout = jiffies + HZ;
1c45607a 1217 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
da4cd8df 1218 schedule_timeout_interruptible(5);
1da177e4
LT		 1219 if (time_after(jiffies, timeout))
1220 break;
1221 }
1222 }
1223 mxser_shutdown(info);
1224
978e595f 1225 mxser_flush_buffer(tty);
1c45607a
JS		 1226 tty_ldisc_flush(tty);
1227
1da177e4 1228 tty->closing = 0;
0ad9e7d1
AC		 1229 info->port.tty = NULL;
1230 if (info->port.blocked_open) {
44b7d1b3
AC		 1231 if (info->port.close_delay)
1232 schedule_timeout_interruptible(info->port.close_delay);
0ad9e7d1 1233 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1234 }
1235
0ad9e7d1 1236 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING);
1da177e4
LT		 1237}
1238
1239static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1240{
1241 int c, total = 0;
1c45607a 1242 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1243 unsigned long flags;
1244
0ad9e7d1 1245 if (!info->port.xmit_buf)
8ea2c2ec 1246 return 0;
1da177e4
LT		 1247
1248 while (1) {
8ea2c2ec
JJ		 1249 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1250 SERIAL_XMIT_SIZE - info->xmit_head));
1da177e4
LT		 1251 if (c <= 0)
1252 break;
1253
0ad9e7d1 1254 memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
1da177e4 1255 spin_lock_irqsave(&info->slock, flags);
8ea2c2ec
JJ		 1256 info->xmit_head = (info->xmit_head + c) &
1257 (SERIAL_XMIT_SIZE - 1);
1da177e4
LT		 1258 info->xmit_cnt += c;
1259 spin_unlock_irqrestore(&info->slock, flags);
1260
1261 buf += c;
1262 count -= c;
1263 total += c;
1da177e4
LT		 1264 }
1265
1c45607a 1266 if (info->xmit_cnt && !tty->stopped) {
8ea2c2ec
JJ		 1267 if (!tty->hw_stopped ||
1268 (info->type == PORT_16550A) ||
1c45607a 1269 (info->board->chip_flag)) {
1da177e4 1270 spin_lock_irqsave(&info->slock, flags);
1c45607a
JS		 1271 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1272 UART_IER);
1da177e4 1273 info->IER |= UART_IER_THRI;
1c45607a 1274 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1275 spin_unlock_irqrestore(&info->slock, flags);
1276 }
1277 }
1278 return total;
1279}
1280
0be2eade 1281static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1282{
1c45607a 1283 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1284 unsigned long flags;
1285
0ad9e7d1 1286 if (!info->port.xmit_buf)
0be2eade 1287 return 0;
1da177e4
LT		 1288
1289 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
0be2eade 1290 return 0;
1da177e4
LT		 1291
1292 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1293 info->port.xmit_buf[info->xmit_head++] = ch;
1da177e4
LT		 1294 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1295 info->xmit_cnt++;
1296 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 1297 if (!tty->stopped) {
8ea2c2ec
JJ		 1298 if (!tty->hw_stopped ||
1299 (info->type == PORT_16550A) ||
1c45607a 1300 info->board->chip_flag) {
1da177e4 1301 spin_lock_irqsave(&info->slock, flags);
1c45607a 1302 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1303 info->IER |= UART_IER_THRI;
1c45607a 1304 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1305 spin_unlock_irqrestore(&info->slock, flags);
1306 }
1307 }
0be2eade 1308 return 1;
1da177e4
LT		 1309}
1310
1311
1312static void mxser_flush_chars(struct tty_struct *tty)
1313{
1c45607a 1314 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1315 unsigned long flags;
1316
8ea2c2ec
JJ		 1317 if (info->xmit_cnt <= 0 ||
1318 tty->stopped ||
0ad9e7d1 1319 !info->port.xmit_buf ||
8ea2c2ec
JJ		 1320 (tty->hw_stopped &&
1321 (info->type != PORT_16550A) &&
1c45607a 1322 (!info->board->chip_flag)
8ea2c2ec 1323 ))
1da177e4
LT		 1324 return;
1325
1326 spin_lock_irqsave(&info->slock, flags);
1327
1c45607a 1328 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1329 info->IER |= UART_IER_THRI;
1c45607a 1330 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1331
1332 spin_unlock_irqrestore(&info->slock, flags);
1333}
1334
1335static int mxser_write_room(struct tty_struct *tty)
1336{
1c45607a 1337 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1338 int ret;
1339
1340 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1341 if (ret < 0)
1342 ret = 0;
8ea2c2ec 1343 return ret;
1da177e4
LT		 1344}
1345
1346static int mxser_chars_in_buffer(struct tty_struct *tty)
1347{
1c45607a 1348 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1349 return info->xmit_cnt;
1350}
1351
1c45607a
JS		 1352/*
1353 * ------------------------------------------------------------
1354 * friends of mxser_ioctl()
1355 * ------------------------------------------------------------
1356 */
1357static int mxser_get_serial_info(struct mxser_port *info,
1358 struct serial_struct __user *retinfo)
1359{
1360 struct serial_struct tmp = {
1361 .type = info->type,
0ad9e7d1 1362 .line = info->port.tty->index,
1c45607a
JS		 1363 .port = info->ioaddr,
1364 .irq = info->board->irq,
0ad9e7d1 1365 .flags = info->port.flags,
1c45607a 1366 .baud_base = info->baud_base,
44b7d1b3
AC		 1367 .close_delay = info->port.close_delay,
1368 .closing_wait = info->port.closing_wait,
1c45607a
JS		 1369 .custom_divisor = info->custom_divisor,
1370 .hub6 = 0
1371 };
1372 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1373 return -EFAULT;
1374 return 0;
1375}
1376
1377static int mxser_set_serial_info(struct mxser_port *info,
1378 struct serial_struct __user *new_info)
1da177e4 1379{
1c45607a 1380 struct serial_struct new_serial;
80ff8a80 1381 speed_t baud;
1c45607a
JS		 1382 unsigned long sl_flags;
1383 unsigned int flags;
1384 int retval = 0;
1da177e4 1385
1c45607a 1386 if (!new_info || !info->ioaddr)
80ff8a80 1387 return -ENODEV;
1c45607a
JS		 1388 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1389 return -EFAULT;
1da177e4 1390
80ff8a80
JS		 1391 if (new_serial.irq != info->board->irq ||
1392 new_serial.port != info->ioaddr)
1393 return -EINVAL;
1da177e4 1394
0ad9e7d1 1395 flags = info->port.flags & ASYNC_SPD_MASK;
1da177e4 1396
1c45607a
JS		 1397 if (!capable(CAP_SYS_ADMIN)) {
1398 if ((new_serial.baud_base != info->baud_base) ||
44b7d1b3 1399 (new_serial.close_delay != info->port.close_delay) ||
0ad9e7d1 1400 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK)))
1c45607a 1401 return -EPERM;
0ad9e7d1 1402 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
1c45607a
JS		 1403 (new_serial.flags & ASYNC_USR_MASK));
1404 } else {
1da177e4 1405 /*
1c45607a
JS		 1406 * OK, past this point, all the error checking has been done.
1407 * At this point, we start making changes.....
1da177e4 1408 */
0ad9e7d1 1409 info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) |
1c45607a 1410 (new_serial.flags & ASYNC_FLAGS));
44b7d1b3
AC		 1411 info->port.close_delay = new_serial.close_delay * HZ / 100;
1412 info->port.closing_wait = new_serial.closing_wait * HZ / 100;
0ad9e7d1
AC		 1413 info->port.tty->low_latency =
1414 (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
0ad9e7d1 1415 if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
80ff8a80
JS		 1416 (new_serial.baud_base != info->baud_base ||
1417 new_serial.custom_divisor !=
1418 info->custom_divisor)) {
1419 baud = new_serial.baud_base / new_serial.custom_divisor;
0ad9e7d1 1420 tty_encode_baud_rate(info->port.tty, baud, baud);
80ff8a80 1421 }
1c45607a 1422 }
fc83815c 1423
1c45607a 1424 info->type = new_serial.type;
1da177e4 1425
1c45607a
JS		 1426 process_txrx_fifo(info);
1427
0ad9e7d1
AC		 1428 if (info->port.flags & ASYNC_INITIALIZED) {
1429 if (flags != (info->port.flags & ASYNC_SPD_MASK)) {
1c45607a
JS		 1430 spin_lock_irqsave(&info->slock, sl_flags);
1431 mxser_change_speed(info, NULL);
1432 spin_unlock_irqrestore(&info->slock, sl_flags);
1da177e4 1433 }
1c45607a
JS		 1434 } else
1435 retval = mxser_startup(info);
1da177e4 1436
1c45607a
JS		 1437 return retval;
1438}
1da177e4 1439
1c45607a
JS		 1440/*
1441 * mxser_get_lsr_info - get line status register info
1442 *
1443 * Purpose: Let user call ioctl() to get info when the UART physically
1444 * is emptied. On bus types like RS485, the transmitter must
1445 * release the bus after transmitting. This must be done when
1446 * the transmit shift register is empty, not be done when the
1447 * transmit holding register is empty. This functionality
1448 * allows an RS485 driver to be written in user space.
1449 */
1450static int mxser_get_lsr_info(struct mxser_port *info,
1451 unsigned int __user *value)
1452{
1453 unsigned char status;
1454 unsigned int result;
1455 unsigned long flags;
1da177e4 1456
1c45607a
JS		 1457 spin_lock_irqsave(&info->slock, flags);
1458 status = inb(info->ioaddr + UART_LSR);
1459 spin_unlock_irqrestore(&info->slock, flags);
1460 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1461 return put_user(result, value);
1462}
1da177e4 1463
1c45607a
JS		 1464static int mxser_tiocmget(struct tty_struct *tty, struct file *file)
1465{
1466 struct mxser_port *info = tty->driver_data;
1467 unsigned char control, status;
1468 unsigned long flags;
1da177e4 1469
8ea2c2ec 1470
1c45607a
JS		 1471 if (tty->index == MXSER_PORTS)
1472 return -ENOIOCTLCMD;
1473 if (test_bit(TTY_IO_ERROR, &tty->flags))
1474 return -EIO;
1da177e4 1475
1c45607a 1476 control = info->MCR;
1da177e4 1477
1c45607a
JS		 1478 spin_lock_irqsave(&info->slock, flags);
1479 status = inb(info->ioaddr + UART_MSR);
1480 if (status & UART_MSR_ANY_DELTA)
1481 mxser_check_modem_status(info, status);
1482 spin_unlock_irqrestore(&info->slock, flags);
1483 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1484 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1485 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1486 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1487 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1488 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1489}
1da177e4 1490
1c45607a
JS		 1491static int mxser_tiocmset(struct tty_struct *tty, struct file *file,
1492 unsigned int set, unsigned int clear)
1493{
1494 struct mxser_port *info = tty->driver_data;
1495 unsigned long flags;
1da177e4 1496
1da177e4 1497
1c45607a
JS		 1498 if (tty->index == MXSER_PORTS)
1499 return -ENOIOCTLCMD;
1500 if (test_bit(TTY_IO_ERROR, &tty->flags))
1501 return -EIO;
1da177e4 1502
1c45607a 1503 spin_lock_irqsave(&info->slock, flags);
1da177e4 1504
1c45607a
JS		 1505 if (set & TIOCM_RTS)
1506 info->MCR |= UART_MCR_RTS;
1507 if (set & TIOCM_DTR)
1508 info->MCR |= UART_MCR_DTR;
1da177e4 1509
1c45607a
JS		 1510 if (clear & TIOCM_RTS)
1511 info->MCR &= ~UART_MCR_RTS;
1512 if (clear & TIOCM_DTR)
1513 info->MCR &= ~UART_MCR_DTR;
8ea2c2ec 1514
1c45607a
JS		 1515 outb(info->MCR, info->ioaddr + UART_MCR);
1516 spin_unlock_irqrestore(&info->slock, flags);
1517 return 0;
1518}
1da177e4 1519
1c45607a
JS		 1520static int __init mxser_program_mode(int port)
1521{
1522 int id, i, j, n;
1523
1524 outb(0, port);
1525 outb(0, port);
1526 outb(0, port);
1527 (void)inb(port);
1528 (void)inb(port);
1529 outb(0, port);
1530 (void)inb(port);
1531
1532 id = inb(port + 1) & 0x1F;
1533 if ((id != C168_ASIC_ID) &&
1534 (id != C104_ASIC_ID) &&
1535 (id != C102_ASIC_ID) &&
1536 (id != CI132_ASIC_ID) &&
1537 (id != CI134_ASIC_ID) &&
1538 (id != CI104J_ASIC_ID))
1539 return -1;
1540 for (i = 0, j = 0; i < 4; i++) {
1541 n = inb(port + 2);
1542 if (n == 'M') {
1543 j = 1;
1544 } else if ((j == 1) && (n == 1)) {
1545 j = 2;
1546 break;
1547 } else
1548 j = 0;
1da177e4 1549 }
1c45607a
JS		 1550 if (j != 2)
1551 id = -2;
1552 return id;
1da177e4
LT		 1553}
1554
1c45607a
JS		 1555static void __init mxser_normal_mode(int port)
1556{
1557 int i, n;
1558
1559 outb(0xA5, port + 1);
1560 outb(0x80, port + 3);
1561 outb(12, port + 0); /* 9600 bps */
1562 outb(0, port + 1);
1563 outb(0x03, port + 3); /* 8 data bits */
1564 outb(0x13, port + 4); /* loop back mode */
1565 for (i = 0; i < 16; i++) {
1566 n = inb(port + 5);
1567 if ((n & 0x61) == 0x60)
1568 break;
1569 if ((n & 1) == 1)
1570 (void)inb(port);
1571 }
1572 outb(0x00, port + 4);
1573}
1574
1575#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1576#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1577#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1578#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1579#define EN_CCMD 0x000 /* Chip's command register */
1580#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1581#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1582#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1583#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1584#define EN0_DCFG 0x00E /* Data configuration reg WR */
1585#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1586#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1587#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
1588static int __init mxser_read_register(int port, unsigned short *regs)
1589{
1590 int i, k, value, id;
1591 unsigned int j;
1592
1593 id = mxser_program_mode(port);
1594 if (id < 0)
1595 return id;
1596 for (i = 0; i < 14; i++) {
1597 k = (i & 0x3F) | 0x180;
1598 for (j = 0x100; j > 0; j >>= 1) {
1599 outb(CHIP_CS, port);
1600 if (k & j) {
1601 outb(CHIP_CS | CHIP_DO, port);
1602 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1603 } else {
1604 outb(CHIP_CS, port);
1605 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1606 }
1607 }
1608 (void)inb(port);
1609 value = 0;
1610 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1611 outb(CHIP_CS, port);
1612 outb(CHIP_CS | CHIP_SK, port);
1613 if (inb(port) & CHIP_DI)
1614 value |= j;
1615 }
1616 regs[i] = value;
1617 outb(0, port);
1618 }
1619 mxser_normal_mode(port);
1620 return id;
1621}
1da177e4
LT		 1622
1623static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1624{
1c45607a
JS		 1625 struct mxser_port *port;
1626 int result, status;
1627 unsigned int i, j;
9d6d162d 1628 int ret = 0;
1da177e4
LT		 1629
1630 switch (cmd) {
1da177e4 1631 case MOXA_GET_MAJOR:
41aee9a1
JS		 1632 printk(KERN_WARNING "mxser: '%s' uses deprecated ioctl %x, fix "
1633 "your userspace\n", current->comm, cmd);
1c45607a 1634 return put_user(ttymajor, (int __user *)argp);
1da177e4
LT		 1635
1636 case MOXA_CHKPORTENABLE:
1637 result = 0;
9d6d162d 1638 lock_kernel();
1c45607a
JS		 1639 for (i = 0; i < MXSER_BOARDS; i++)
1640 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1641 if (mxser_boards[i].ports[j].ioaddr)
1642 result |= (1 << i);
9d6d162d 1643 unlock_kernel();
8ea2c2ec 1644 return put_user(result, (unsigned long __user *)argp);
1da177e4 1645 case MOXA_GETDATACOUNT:
9d6d162d 1646 lock_kernel();
1da177e4 1647 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
9d6d162d
AC		 1648 ret = -EFAULT;
1649 unlock_kernel();
1650 return ret;
72800df9
JS		 1651 case MOXA_GETMSTATUS: {
1652 struct mxser_mstatus ms, __user *msu = argp;
9d6d162d 1653 lock_kernel();
1c45607a
JS		 1654 for (i = 0; i < MXSER_BOARDS; i++)
1655 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1656 port = &mxser_boards[i].ports[j];
72800df9 1657 memset(&ms, 0, sizeof(ms));
1c45607a 1658
72800df9
JS		 1659 if (!port->ioaddr)
1660 goto copy;
1da177e4 1661
0ad9e7d1 1662 if (!port->port.tty || !port->port.tty->termios)
72800df9 1663 ms.cflag = port->normal_termios.c_cflag;
1c45607a 1664 else
72800df9 1665 ms.cflag = port->port.tty->termios->c_cflag;
1da177e4 1666
1c45607a 1667 status = inb(port->ioaddr + UART_MSR);
72800df9
JS		 1668 if (status & UART_MSR_DCD)
1669 ms.dcd = 1;
1670 if (status & UART_MSR_DSR)
1671 ms.dsr = 1;
1672 if (status & UART_MSR_CTS)
1673 ms.cts = 1;
1674 copy:
1675 if (copy_to_user(msu, &ms, sizeof(ms))) {
1676 unlock_kernel();
1677 return -EFAULT;
1678 }
1679 msu++;
1c45607a 1680 }
9d6d162d 1681 unlock_kernel();
1da177e4 1682 return 0;
72800df9 1683 }
8ea2c2ec 1684 case MOXA_ASPP_MON_EXT: {
72800df9
JS		 1685 struct mxser_mon_ext *me; /* it's 2k, stack unfriendly */
1686 unsigned int cflag, iflag, p;
1687 u8 opmode;
1688
1689 me = kzalloc(sizeof(*me), GFP_KERNEL);
1690 if (!me)
1691 return -ENOMEM;
1c45607a 1692
9d6d162d 1693 lock_kernel();
72800df9
JS		 1694 for (i = 0, p = 0; i < MXSER_BOARDS; i++) {
1695 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++, p++) {
1696 if (p >= ARRAY_SIZE(me->rx_cnt)) {
1697 i = MXSER_BOARDS;
1698 break;
1699 }
1c45607a
JS		 1700 port = &mxser_boards[i].ports[j];
1701 if (!port->ioaddr)
1da177e4
LT		 1702 continue;
1703
72800df9 1704 status = mxser_get_msr(port->ioaddr, 0, p);
1c45607a 1705
1da177e4 1706 if (status & UART_MSR_TERI)
1c45607a 1707 port->icount.rng++;
1da177e4 1708 if (status & UART_MSR_DDSR)
1c45607a 1709 port->icount.dsr++;
1da177e4 1710 if (status & UART_MSR_DDCD)
1c45607a 1711 port->icount.dcd++;
1da177e4 1712 if (status & UART_MSR_DCTS)
1c45607a
JS		 1713 port->icount.cts++;
1714
1715 port->mon_data.modem_status = status;
72800df9
JS		 1716 me->rx_cnt[p] = port->mon_data.rxcnt;
1717 me->tx_cnt[p] = port->mon_data.txcnt;
1718 me->up_rxcnt[p] = port->mon_data.up_rxcnt;
1719 me->up_txcnt[p] = port->mon_data.up_txcnt;
1720 me->modem_status[p] =
1c45607a 1721 port->mon_data.modem_status;
72800df9 1722 me->baudrate[p] = tty_get_baud_rate(port->port.tty);
1c45607a 1723
0ad9e7d1 1724 if (!port->port.tty || !port->port.tty->termios) {
1c45607a
JS		 1725 cflag = port->normal_termios.c_cflag;
1726 iflag = port->normal_termios.c_iflag;
1da177e4 1727 } else {
0ad9e7d1
AC		 1728 cflag = port->port.tty->termios->c_cflag;
1729 iflag = port->port.tty->termios->c_iflag;
1da177e4
LT		 1730 }
1731
72800df9
JS		 1732 me->databits[p] = cflag & CSIZE;
1733 me->stopbits[p] = cflag & CSTOPB;
1734 me->parity[p] = cflag & (PARENB | PARODD |
1735 CMSPAR);
1da177e4
LT		 1736
1737 if (cflag & CRTSCTS)
72800df9 1738 me->flowctrl[p] |= 0x03;
1da177e4
LT		 1739
1740 if (iflag & (IXON | IXOFF))
72800df9 1741 me->flowctrl[p] |= 0x0C;
1da177e4 1742
1c45607a 1743 if (port->type == PORT_16550A)
72800df9 1744 me->fifo[p] = 1;
1da177e4 1745
72800df9
JS		 1746 opmode = inb(port->opmode_ioaddr) >>
1747 ((p % 4) * 2);
1da177e4 1748 opmode &= OP_MODE_MASK;
72800df9 1749 me->iftype[p] = opmode;
1da177e4 1750 }
9d6d162d
AC		 1751 }
1752 unlock_kernel();
72800df9
JS		 1753 if (copy_to_user(argp, me, sizeof(*me)))
1754 ret = -EFAULT;
1755 kfree(me);
1756 return ret;
9d6d162d
AC		 1757 }
1758 default:
1da177e4
LT		 1759 return -ENOIOCTLCMD;
1760 }
1761 return 0;
1762}
1763
1c45607a
JS		 1764static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1765 struct async_icount *cprev)
1da177e4 1766{
1c45607a
JS		 1767 struct async_icount cnow;
1768 unsigned long flags;
1769 int ret;
1da177e4 1770
1c45607a
JS		 1771 spin_lock_irqsave(&info->slock, flags);
1772 cnow = info->icount; /* atomic copy */
1773 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 1774
1c45607a
JS		 1775 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1776 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1777 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1778 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1da177e4 1779
1c45607a
JS		 1780 *cprev = cnow;
1781
1782 return ret;
1783}
1784
1785static int mxser_ioctl(struct tty_struct *tty, struct file *file,
1786 unsigned int cmd, unsigned long arg)
1da177e4 1787{
1c45607a
JS		 1788 struct mxser_port *info = tty->driver_data;
1789 struct async_icount cnow;
1c45607a
JS		 1790 unsigned long flags;
1791 void __user *argp = (void __user *)arg;
1792 int retval;
1da177e4 1793
1c45607a
JS		 1794 if (tty->index == MXSER_PORTS)
1795 return mxser_ioctl_special(cmd, argp);
1da177e4 1796
1c45607a
JS		 1797 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1798 int p;
1799 unsigned long opmode;
1800 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1801 int shiftbit;
1802 unsigned char val, mask;
1da177e4 1803
1c45607a
JS		 1804 p = tty->index % 4;
1805 if (cmd == MOXA_SET_OP_MODE) {
1806 if (get_user(opmode, (int __user *) argp))
1807 return -EFAULT;
1808 if (opmode != RS232_MODE &&
1809 opmode != RS485_2WIRE_MODE &&
1810 opmode != RS422_MODE &&
1811 opmode != RS485_4WIRE_MODE)
1812 return -EFAULT;
9d6d162d 1813 lock_kernel();
1c45607a
JS		 1814 mask = ModeMask[p];
1815 shiftbit = p * 2;
1816 val = inb(info->opmode_ioaddr);
1817 val &= mask;
1818 val |= (opmode << shiftbit);
1819 outb(val, info->opmode_ioaddr);
9d6d162d 1820 unlock_kernel();
1c45607a 1821 } else {
9d6d162d 1822 lock_kernel();
1c45607a
JS		 1823 shiftbit = p * 2;
1824 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1825 opmode &= OP_MODE_MASK;
9d6d162d 1826 unlock_kernel();
1c45607a
JS		 1827 if (put_user(opmode, (int __user *)argp))
1828 return -EFAULT;
1829 }
1830 return 0;
1831 }
1832
1833 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT &&
1834 test_bit(TTY_IO_ERROR, &tty->flags))
1835 return -EIO;
1836
1837 switch (cmd) {
1c45607a 1838 case TIOCGSERIAL:
9d6d162d
AC		 1839 lock_kernel();
1840 retval = mxser_get_serial_info(info, argp);
1841 unlock_kernel();
1842 return retval;
1c45607a 1843 case TIOCSSERIAL:
9d6d162d
AC		 1844 lock_kernel();
1845 retval = mxser_set_serial_info(info, argp);
1846 unlock_kernel();
1847 return retval;
1c45607a 1848 case TIOCSERGETLSR: /* Get line status register */
9d6d162d 1849 return mxser_get_lsr_info(info, argp);
1c45607a
JS		 1850 /*
1851 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1852 * - mask passed in arg for lines of interest
1853 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1854 * Caller should use TIOCGICOUNT to see which one it was
1855 */
1856 case TIOCMIWAIT:
1857 spin_lock_irqsave(&info->slock, flags);
1858 cnow = info->icount; /* note the counters on entry */
1859 spin_unlock_irqrestore(&info->slock, flags);
1860
1861 return wait_event_interruptible(info->delta_msr_wait,
1862 mxser_cflags_changed(info, arg, &cnow));
1863 /*
1864 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1865 * Return: write counters to the user passed counter struct
1866 * NB: both 1->0 and 0->1 transitions are counted except for
1867 * RI where only 0->1 is counted.
1868 */
41aee9a1
JS		 1869 case TIOCGICOUNT: {
1870 struct serial_icounter_struct icnt = { 0 };
1c45607a
JS		 1871 spin_lock_irqsave(&info->slock, flags);
1872 cnow = info->icount;
1873 spin_unlock_irqrestore(&info->slock, flags);
41aee9a1
JS		 1874
1875 icnt.frame = cnow.frame;
1876 icnt.brk = cnow.brk;
1877 icnt.overrun = cnow.overrun;
1878 icnt.buf_overrun = cnow.buf_overrun;
1879 icnt.parity = cnow.parity;
1880 icnt.rx = cnow.rx;
1881 icnt.tx = cnow.tx;
1882 icnt.cts = cnow.cts;
1883 icnt.dsr = cnow.dsr;
1884 icnt.rng = cnow.rng;
1885 icnt.dcd = cnow.dcd;
1886
1887 return copy_to_user(argp, &icnt, sizeof(icnt)) ? -EFAULT : 0;
1888 }
1c45607a
JS		 1889 case MOXA_HighSpeedOn:
1890 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1891 case MOXA_SDS_RSTICOUNTER:
9d6d162d 1892 lock_kernel();
1c45607a
JS		 1893 info->mon_data.rxcnt = 0;
1894 info->mon_data.txcnt = 0;
9d6d162d 1895 unlock_kernel();
1c45607a
JS		 1896 return 0;
1897
1898 case MOXA_ASPP_OQUEUE:{
1899 int len, lsr;
1900
9d6d162d 1901 lock_kernel();
1c45607a 1902 len = mxser_chars_in_buffer(tty);
1c45607a 1903 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT;
1c45607a 1904 len += (lsr ? 0 : 1);
9d6d162d 1905 unlock_kernel();
1c45607a
JS		 1906
1907 return put_user(len, (int __user *)argp);
1908 }
1909 case MOXA_ASPP_MON: {
1910 int mcr, status;
1911
9d6d162d 1912 lock_kernel();
1c45607a
JS		 1913 status = mxser_get_msr(info->ioaddr, 1, tty->index);
1914 mxser_check_modem_status(info, status);
1915
1916 mcr = inb(info->ioaddr + UART_MCR);
1917 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1918 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1919 else
1920 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1921
1922 if (mcr & MOXA_MUST_MCR_TX_XON)
1923 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1924 else
1925 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1926
0ad9e7d1 1927 if (info->port.tty->hw_stopped)
1c45607a
JS		 1928 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1929 else
1930 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
9d6d162d 1931 unlock_kernel();
1c45607a
JS		 1932 if (copy_to_user(argp, &info->mon_data,
1933 sizeof(struct mxser_mon)))
1934 return -EFAULT;
1935
1936 return 0;
1937 }
1938 case MOXA_ASPP_LSTATUS: {
1939 if (put_user(info->err_shadow, (unsigned char __user *)argp))
1940 return -EFAULT;
1941
1942 info->err_shadow = 0;
1943 return 0;
1944 }
1945 case MOXA_SET_BAUD_METHOD: {
1946 int method;
1947
1948 if (get_user(method, (int __user *)argp))
1949 return -EFAULT;
1950 mxser_set_baud_method[tty->index] = method;
1951 return put_user(method, (int __user *)argp);
1952 }
1953 default:
1954 return -ENOIOCTLCMD;
1955 }
1956 return 0;
1957}
1958
1959static void mxser_stoprx(struct tty_struct *tty)
1960{
1961 struct mxser_port *info = tty->driver_data;
1962
1963 info->ldisc_stop_rx = 1;
1964 if (I_IXOFF(tty)) {
1965 if (info->board->chip_flag) {
1966 info->IER &= ~MOXA_MUST_RECV_ISR;
1967 outb(info->IER, info->ioaddr + UART_IER);
1968 } else {
1969 info->x_char = STOP_CHAR(tty);
1970 outb(0, info->ioaddr + UART_IER);
1971 info->IER |= UART_IER_THRI;
1972 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1973 }
1974 }
1975
0ad9e7d1 1976 if (info->port.tty->termios->c_cflag & CRTSCTS) {
1c45607a
JS		 1977 info->MCR &= ~UART_MCR_RTS;
1978 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1979 }
1980}
1981
1982/*
1983 * This routine is called by the upper-layer tty layer to signal that
1984 * incoming characters should be throttled.
1985 */
1986static void mxser_throttle(struct tty_struct *tty)
1987{
1da177e4 1988 mxser_stoprx(tty);
1da177e4
LT		 1989}
1990
1991static void mxser_unthrottle(struct tty_struct *tty)
1992{
1c45607a 1993 struct mxser_port *info = tty->driver_data;
1da177e4 1994
1c45607a
JS		 1995 /* startrx */
1996 info->ldisc_stop_rx = 0;
1997 if (I_IXOFF(tty)) {
1998 if (info->x_char)
1999 info->x_char = 0;
2000 else {
2001 if (info->board->chip_flag) {
2002 info->IER |= MOXA_MUST_RECV_ISR;
2003 outb(info->IER, info->ioaddr + UART_IER);
2004 } else {
2005 info->x_char = START_CHAR(tty);
2006 outb(0, info->ioaddr + UART_IER);
2007 info->IER |= UART_IER_THRI;
2008 outb(info->IER, info->ioaddr + UART_IER);
2009 }
1da177e4 2010 }
1c45607a 2011 }
1da177e4 2012
0ad9e7d1 2013 if (info->port.tty->termios->c_cflag & CRTSCTS) {
1c45607a
JS		 2014 info->MCR |= UART_MCR_RTS;
2015 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 2016 }
2017}
2018
2019/*
2020 * mxser_stop() and mxser_start()
2021 *
2022 * This routines are called before setting or resetting tty->stopped.
2023 * They enable or disable transmitter interrupts, as necessary.
2024 */
2025static void mxser_stop(struct tty_struct *tty)
2026{
1c45607a 2027 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2028 unsigned long flags;
2029
2030 spin_lock_irqsave(&info->slock, flags);
2031 if (info->IER & UART_IER_THRI) {
2032 info->IER &= ~UART_IER_THRI;
1c45607a 2033 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 2034 }
2035 spin_unlock_irqrestore(&info->slock, flags);
2036}
2037
2038static void mxser_start(struct tty_struct *tty)
2039{
1c45607a 2040 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2041 unsigned long flags;
2042
2043 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 2044 if (info->xmit_cnt && info->port.xmit_buf) {
1c45607a 2045 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 2046 info->IER |= UART_IER_THRI;
1c45607a 2047 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 2048 }
2049 spin_unlock_irqrestore(&info->slock, flags);
2050}
2051
1c45607a
JS		 2052static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
2053{
2054 struct mxser_port *info = tty->driver_data;
2055 unsigned long flags;
2056
2057 spin_lock_irqsave(&info->slock, flags);
2058 mxser_change_speed(info, old_termios);
2059 spin_unlock_irqrestore(&info->slock, flags);
2060
2061 if ((old_termios->c_cflag & CRTSCTS) &&
2062 !(tty->termios->c_cflag & CRTSCTS)) {
2063 tty->hw_stopped = 0;
2064 mxser_start(tty);
2065 }
2066
2067 /* Handle sw stopped */
2068 if ((old_termios->c_iflag & IXON) &&
2069 !(tty->termios->c_iflag & IXON)) {
2070 tty->stopped = 0;
2071
2072 if (info->board->chip_flag) {
2073 spin_lock_irqsave(&info->slock, flags);
148ff86b
CH		 2074 mxser_disable_must_rx_software_flow_control(
2075 info->ioaddr);
1c45607a
JS		 2076 spin_unlock_irqrestore(&info->slock, flags);
2077 }
2078
2079 mxser_start(tty);
2080 }
2081}
2082
1da177e4
LT		 2083/*
2084 * mxser_wait_until_sent() --- wait until the transmitter is empty
2085 */
2086static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
2087{
1c45607a 2088 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2089 unsigned long orig_jiffies, char_time;
2090 int lsr;
2091
2092 if (info->type == PORT_UNKNOWN)
2093 return;
2094
2095 if (info->xmit_fifo_size == 0)
2096 return; /* Just in case.... */
2097
2098 orig_jiffies = jiffies;
2099 /*
2100 * Set the check interval to be 1/5 of the estimated time to
2101 * send a single character, and make it at least 1. The check
2102 * interval should also be less than the timeout.
2103 *
2104 * Note: we have to use pretty tight timings here to satisfy
2105 * the NIST-PCTS.
2106 */
2107 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
2108 char_time = char_time / 5;
2109 if (char_time == 0)
2110 char_time = 1;
2111 if (timeout && timeout < char_time)
2112 char_time = timeout;
2113 /*
2114 * If the transmitter hasn't cleared in twice the approximate
2115 * amount of time to send the entire FIFO, it probably won't
2116 * ever clear. This assumes the UART isn't doing flow
2117 * control, which is currently the case. Hence, if it ever
2118 * takes longer than info->timeout, this is probably due to a
2119 * UART bug of some kind. So, we clamp the timeout parameter at
2120 * 2*info->timeout.
2121 */
2122 if (!timeout || timeout > 2 * info->timeout)
2123 timeout = 2 * info->timeout;
2124#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
8ea2c2ec
JJ		 2125 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
2126 timeout, char_time);
1da177e4
LT		 2127 printk("jiff=%lu...", jiffies);
2128#endif
978e595f 2129 lock_kernel();
1c45607a 2130 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
1da177e4
LT		 2131#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2132 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
2133#endif
da4cd8df 2134 schedule_timeout_interruptible(char_time);
1da177e4 2135 if (signal_pending(current))
1c45607a
JS		 2136 break;
2137 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2138 break;
1da177e4 2139 }
1c45607a 2140 set_current_state(TASK_RUNNING);
978e595f 2141 unlock_kernel();
1da177e4 2142
1c45607a
JS		 2143#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2144 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
2145#endif
2146}
1da177e4 2147
1c45607a
JS		 2148/*
2149 * This routine is called by tty_hangup() when a hangup is signaled.
2150 */
2151static void mxser_hangup(struct tty_struct *tty)
2152{
2153 struct mxser_port *info = tty->driver_data;
1da177e4 2154
1c45607a
JS		 2155 mxser_flush_buffer(tty);
2156 mxser_shutdown(info);
0ad9e7d1
AC		 2157 info->port.count = 0;
2158 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
2159 info->port.tty = NULL;
2160 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 2161}
2162
1c45607a
JS		 2163/*
2164 * mxser_rs_break() --- routine which turns the break handling on or off
2165 */
9e98966c 2166static int mxser_rs_break(struct tty_struct *tty, int break_state)
1da177e4 2167{
1c45607a 2168 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2169 unsigned long flags;
2170
1c45607a
JS		 2171 spin_lock_irqsave(&info->slock, flags);
2172 if (break_state == -1)
2173 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2174 info->ioaddr + UART_LCR);
2175 else
2176 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2177 info->ioaddr + UART_LCR);
2178 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 2179 return 0;
1c45607a 2180}
1da177e4 2181
1c45607a
JS		 2182static void mxser_receive_chars(struct mxser_port *port, int *status)
2183{
0ad9e7d1 2184 struct tty_struct *tty = port->port.tty;
1c45607a
JS		 2185 unsigned char ch, gdl;
2186 int ignored = 0;
2187 int cnt = 0;
2188 int recv_room;
2189 int max = 256;
1da177e4 2190
1c45607a
JS		 2191 recv_room = tty->receive_room;
2192 if ((recv_room == 0) && (!port->ldisc_stop_rx))
2193 mxser_stoprx(tty);
1da177e4 2194
1c45607a 2195 if (port->board->chip_flag != MOXA_OTHER_UART) {
1da177e4 2196
1c45607a
JS		 2197 if (*status & UART_LSR_SPECIAL)
2198 goto intr_old;
2199 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2200 (*status & MOXA_MUST_LSR_RERR))
2201 goto intr_old;
2202 if (*status & MOXA_MUST_LSR_RERR)
2203 goto intr_old;
1da177e4 2204
1c45607a
JS		 2205 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2206
2207 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2208 gdl &= MOXA_MUST_GDL_MASK;
2209 if (gdl >= recv_room) {
2210 if (!port->ldisc_stop_rx)
2211 mxser_stoprx(tty);
2212 }
2213 while (gdl--) {
2214 ch = inb(port->ioaddr + UART_RX);
2215 tty_insert_flip_char(tty, ch, 0);
2216 cnt++;
2217 }
2218 goto end_intr;
1da177e4 2219 }
1c45607a
JS		 2220intr_old:
2221
2222 do {
2223 if (max-- < 0)
2224 break;
1da177e4 2225
1c45607a
JS		 2226 ch = inb(port->ioaddr + UART_RX);
2227 if (port->board->chip_flag && (*status & UART_LSR_OE))
2228 outb(0x23, port->ioaddr + UART_FCR);
2229 *status &= port->read_status_mask;
2230 if (*status & port->ignore_status_mask) {
2231 if (++ignored > 100)
2232 break;
2233 } else {
2234 char flag = 0;
2235 if (*status & UART_LSR_SPECIAL) {
2236 if (*status & UART_LSR_BI) {
2237 flag = TTY_BREAK;
2238 port->icount.brk++;
1da177e4 2239
0ad9e7d1 2240 if (port->port.flags & ASYNC_SAK)
1c45607a
JS		 2241 do_SAK(tty);
2242 } else if (*status & UART_LSR_PE) {
2243 flag = TTY_PARITY;
2244 port->icount.parity++;
2245 } else if (*status & UART_LSR_FE) {
2246 flag = TTY_FRAME;
2247 port->icount.frame++;
2248 } else if (*status & UART_LSR_OE) {
2249 flag = TTY_OVERRUN;
2250 port->icount.overrun++;
2251 } else
2252 flag = TTY_BREAK;
2253 }
2254 tty_insert_flip_char(tty, ch, flag);
2255 cnt++;
2256 if (cnt >= recv_room) {
2257 if (!port->ldisc_stop_rx)
2258 mxser_stoprx(tty);
2259 break;
2260 }
1da177e4 2261
1c45607a 2262 }
1da177e4 2263
1c45607a
JS		 2264 if (port->board->chip_flag)
2265 break;
1da177e4 2266
1c45607a
JS		 2267 *status = inb(port->ioaddr + UART_LSR);
2268 } while (*status & UART_LSR_DR);
1da177e4 2269
1c45607a 2270end_intr:
0ad9e7d1 2271 mxvar_log.rxcnt[port->port.tty->index] += cnt;
1c45607a
JS		 2272 port->mon_data.rxcnt += cnt;
2273 port->mon_data.up_rxcnt += cnt;
1da177e4 2274
1c45607a
JS		 2275 /*
2276 * We are called from an interrupt context with &port->slock
2277 * being held. Drop it temporarily in order to prevent
2278 * recursive locking.
2279 */
2280 spin_unlock(&port->slock);
2281 tty_flip_buffer_push(tty);
2282 spin_lock(&port->slock);
1da177e4
LT		 2283}
2284
1c45607a 2285static void mxser_transmit_chars(struct mxser_port *port)
1da177e4 2286{
1c45607a 2287 int count, cnt;
1da177e4 2288
1c45607a
JS		 2289 if (port->x_char) {
2290 outb(port->x_char, port->ioaddr + UART_TX);
2291 port->x_char = 0;
0ad9e7d1 2292 mxvar_log.txcnt[port->port.tty->index]++;
1c45607a
JS		 2293 port->mon_data.txcnt++;
2294 port->mon_data.up_txcnt++;
2295 port->icount.tx++;
2296 return;
2297 }
1da177e4 2298
0ad9e7d1 2299 if (port->port.xmit_buf == NULL)
1c45607a 2300 return;
1da177e4 2301
0ad9e7d1
AC		 2302 if ((port->xmit_cnt <= 0) || port->port.tty->stopped ||
2303 (port->port.tty->hw_stopped &&
1c45607a
JS		 2304 (port->type != PORT_16550A) &&
2305 (!port->board->chip_flag))) {
2306 port->IER &= ~UART_IER_THRI;
2307 outb(port->IER, port->ioaddr + UART_IER);
2308 return;
1da177e4
LT		 2309 }
2310
1c45607a
JS		 2311 cnt = port->xmit_cnt;
2312 count = port->xmit_fifo_size;
2313 do {
0ad9e7d1 2314 outb(port->port.xmit_buf[port->xmit_tail++],
1c45607a
JS		 2315 port->ioaddr + UART_TX);
2316 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2317 if (--port->xmit_cnt <= 0)
2318 break;
2319 } while (--count > 0);
0ad9e7d1 2320 mxvar_log.txcnt[port->port.tty->index] += (cnt - port->xmit_cnt);
1da177e4 2321
1c45607a
JS		 2322 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2323 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2324 port->icount.tx += (cnt - port->xmit_cnt);
1da177e4 2325
1c45607a 2326 if (port->xmit_cnt < WAKEUP_CHARS)
0ad9e7d1 2327 tty_wakeup(port->port.tty);
1c45607a
JS		 2328
2329 if (port->xmit_cnt <= 0) {
2330 port->IER &= ~UART_IER_THRI;
2331 outb(port->IER, port->ioaddr + UART_IER);
1da177e4 2332 }
1da177e4
LT		 2333}
2334
2335/*
1c45607a 2336 * This is the serial driver's generic interrupt routine
1da177e4 2337 */
1c45607a 2338static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1da177e4 2339{
1c45607a
JS		 2340 int status, iir, i;
2341 struct mxser_board *brd = NULL;
2342 struct mxser_port *port;
2343 int max, irqbits, bits, msr;
2344 unsigned int int_cnt, pass_counter = 0;
2345 int handled = IRQ_NONE;
1da177e4 2346
1c45607a
JS		 2347 for (i = 0; i < MXSER_BOARDS; i++)
2348 if (dev_id == &mxser_boards[i]) {
2349 brd = dev_id;
2350 break;
2351 }
1da177e4 2352
1c45607a
JS		 2353 if (i == MXSER_BOARDS)
2354 goto irq_stop;
2355 if (brd == NULL)
2356 goto irq_stop;
2357 max = brd->info->nports;
2358 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2359 irqbits = inb(brd->vector) & brd->vector_mask;
2360 if (irqbits == brd->vector_mask)
2361 break;
1da177e4 2362
1c45607a
JS		 2363 handled = IRQ_HANDLED;
2364 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2365 if (irqbits == brd->vector_mask)
2366 break;
2367 if (bits & irqbits)
2368 continue;
2369 port = &brd->ports[i];
2370
2371 int_cnt = 0;
2372 spin_lock(&port->slock);
2373 do {
2374 iir = inb(port->ioaddr + UART_IIR);
2375 if (iir & UART_IIR_NO_INT)
2376 break;
2377 iir &= MOXA_MUST_IIR_MASK;
0ad9e7d1
AC		 2378 if (!port->port.tty ||
2379 (port->port.flags & ASYNC_CLOSING) ||
2380 !(port->port.flags &
1c45607a
JS		 2381 ASYNC_INITIALIZED)) {
2382 status = inb(port->ioaddr + UART_LSR);
2383 outb(0x27, port->ioaddr + UART_FCR);
2384 inb(port->ioaddr + UART_MSR);
2385 break;
2386 }
1da177e4 2387
1c45607a
JS		 2388 status = inb(port->ioaddr + UART_LSR);
2389
2390 if (status & UART_LSR_PE)
2391 port->err_shadow |= NPPI_NOTIFY_PARITY;
2392 if (status & UART_LSR_FE)
2393 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2394 if (status & UART_LSR_OE)
2395 port->err_shadow |=
2396 NPPI_NOTIFY_HW_OVERRUN;
2397 if (status & UART_LSR_BI)
2398 port->err_shadow |= NPPI_NOTIFY_BREAK;
2399
2400 if (port->board->chip_flag) {
2401 if (iir == MOXA_MUST_IIR_GDA ||
2402 iir == MOXA_MUST_IIR_RDA ||
2403 iir == MOXA_MUST_IIR_RTO ||
2404 iir == MOXA_MUST_IIR_LSR)
2405 mxser_receive_chars(port,
2406 &status);
2407
2408 } else {
2409 status &= port->read_status_mask;
2410 if (status & UART_LSR_DR)
2411 mxser_receive_chars(port,
2412 &status);
2413 }
2414 msr = inb(port->ioaddr + UART_MSR);
2415 if (msr & UART_MSR_ANY_DELTA)
2416 mxser_check_modem_status(port, msr);
2417
2418 if (port->board->chip_flag) {
2419 if (iir == 0x02 && (status &
2420 UART_LSR_THRE))
2421 mxser_transmit_chars(port);
2422 } else {
2423 if (status & UART_LSR_THRE)
2424 mxser_transmit_chars(port);
2425 }
2426 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2427 spin_unlock(&port->slock);
2428 }
2429 }
1da177e4 2430
1c45607a
JS		 2431irq_stop:
2432 return handled;
2433}
1da177e4 2434
1c45607a
JS		 2435static const struct tty_operations mxser_ops = {
2436 .open = mxser_open,
2437 .close = mxser_close,
2438 .write = mxser_write,
2439 .put_char = mxser_put_char,
2440 .flush_chars = mxser_flush_chars,
2441 .write_room = mxser_write_room,
2442 .chars_in_buffer = mxser_chars_in_buffer,
2443 .flush_buffer = mxser_flush_buffer,
2444 .ioctl = mxser_ioctl,
2445 .throttle = mxser_throttle,
2446 .unthrottle = mxser_unthrottle,
2447 .set_termios = mxser_set_termios,
2448 .stop = mxser_stop,
2449 .start = mxser_start,
2450 .hangup = mxser_hangup,
2451 .break_ctl = mxser_rs_break,
2452 .wait_until_sent = mxser_wait_until_sent,
2453 .tiocmget = mxser_tiocmget,
2454 .tiocmset = mxser_tiocmset,
2455};
1da177e4 2456
1c45607a
JS		 2457/*
2458 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2459 */
1da177e4 2460
1c45607a
JS		 2461static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev,
2462 unsigned int irq)
2463{
2464 if (irq)
2465 free_irq(brd->irq, brd);
2466 if (pdev != NULL) { /* PCI */
2467#ifdef CONFIG_PCI
2468 pci_release_region(pdev, 2);
2469 pci_release_region(pdev, 3);
2470#endif
2471 } else {
2472 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2473 release_region(brd->vector, 1);
2474 }
1da177e4
LT		 2475}
2476
1c45607a
JS		 2477static int __devinit mxser_initbrd(struct mxser_board *brd,
2478 struct pci_dev *pdev)
1da177e4 2479{
1c45607a
JS		 2480 struct mxser_port *info;
2481 unsigned int i;
2482 int retval;
1da177e4 2483
1c45607a 2484 printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud);
1da177e4 2485
1c45607a
JS		 2486 for (i = 0; i < brd->info->nports; i++) {
2487 info = &brd->ports[i];
44b7d1b3 2488 tty_port_init(&info->port);
1c45607a
JS		 2489 info->board = brd;
2490 info->stop_rx = 0;
2491 info->ldisc_stop_rx = 0;
1da177e4 2492
1c45607a
JS		 2493 /* Enhance mode enabled here */
2494 if (brd->chip_flag != MOXA_OTHER_UART)
148ff86b 2495 mxser_enable_must_enchance_mode(info->ioaddr);
1da177e4 2496
0ad9e7d1 2497 info->port.flags = ASYNC_SHARE_IRQ;
1c45607a 2498 info->type = brd->uart_type;
1da177e4 2499
1c45607a 2500 process_txrx_fifo(info);
1da177e4 2501
1c45607a 2502 info->custom_divisor = info->baud_base * 16;
44b7d1b3
AC		 2503 info->port.close_delay = 5 * HZ / 10;
2504 info->port.closing_wait = 30 * HZ;
1c45607a 2505 info->normal_termios = mxvar_sdriver->init_termios;
1c45607a
JS		 2506 init_waitqueue_head(&info->delta_msr_wait);
2507 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2508 info->err_shadow = 0;
2509 spin_lock_init(&info->slock);
1da177e4 2510
1c45607a
JS		 2511 /* before set INT ISR, disable all int */
2512 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2513 info->ioaddr + UART_IER);
2514 }
1da177e4 2515
1c45607a
JS		 2516 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2517 brd);
2518 if (retval) {
2519 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2520 "conflict with another device.\n",
2521 brd->info->name, brd->irq);
2522 /* We hold resources, we need to release them. */
2523 mxser_release_res(brd, pdev, 0);
2524 }
2525 return retval;
2526}
1da177e4 2527
1c45607a 2528static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
1da177e4
LT		 2529{
2530 int id, i, bits;
2531 unsigned short regs[16], irq;
2532 unsigned char scratch, scratch2;
2533
1c45607a 2534 brd->chip_flag = MOXA_OTHER_UART;
1da177e4
LT		 2535
2536 id = mxser_read_register(cap, regs);
1c45607a
JS		 2537 switch (id) {
2538 case C168_ASIC_ID:
2539 brd->info = &mxser_cards[0];
2540 break;
2541 case C104_ASIC_ID:
2542 brd->info = &mxser_cards[1];
2543 break;
2544 case CI104J_ASIC_ID:
2545 brd->info = &mxser_cards[2];
2546 break;
2547 case C102_ASIC_ID:
2548 brd->info = &mxser_cards[5];
2549 break;
2550 case CI132_ASIC_ID:
2551 brd->info = &mxser_cards[6];
2552 break;
2553 case CI134_ASIC_ID:
2554 brd->info = &mxser_cards[7];
2555 break;
2556 default:
8ea2c2ec 2557 return 0;
1c45607a 2558 }
1da177e4
LT		 2559
2560 irq = 0;
1c45607a
JS		 2561 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2562 Flag-hack checks if configuration should be read as 2-port here. */
2563 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
1da177e4
LT		 2564 irq = regs[9] & 0xF000;
2565 irq = irq | (irq >> 4);
2566 if (irq != (regs[9] & 0xFF00))
8ea2c2ec 2567 return MXSER_ERR_IRQ_CONFLIT;
1c45607a 2568 } else if (brd->info->nports == 4) {
1da177e4
LT		 2569 irq = regs[9] & 0xF000;
2570 irq = irq | (irq >> 4);
2571 irq = irq | (irq >> 8);
2572 if (irq != regs[9])
8ea2c2ec 2573 return MXSER_ERR_IRQ_CONFLIT;
1c45607a 2574 } else if (brd->info->nports == 8) {
1da177e4
LT		 2575 irq = regs[9] & 0xF000;
2576 irq = irq | (irq >> 4);
2577 irq = irq | (irq >> 8);
2578 if ((irq != regs[9]) || (irq != regs[10]))
8ea2c2ec 2579 return MXSER_ERR_IRQ_CONFLIT;
1da177e4
LT		 2580 }
2581
8ea2c2ec
JJ		 2582 if (!irq)
2583 return MXSER_ERR_IRQ;
1c45607a 2584 brd->irq = ((int)(irq & 0xF000) >> 12);
1da177e4 2585 for (i = 0; i < 8; i++)
1c45607a 2586 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
8ea2c2ec
JJ		 2587 if ((regs[12] & 0x80) == 0)
2588 return MXSER_ERR_VECTOR;
1c45607a 2589 brd->vector = (int)regs[11]; /* interrupt vector */
1da177e4 2590 if (id == 1)
1c45607a 2591 brd->vector_mask = 0x00FF;
1da177e4 2592 else
1c45607a 2593 brd->vector_mask = 0x000F;
1da177e4
LT		 2594 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2595 if (regs[12] & bits) {
1c45607a
JS		 2596 brd->ports[i].baud_base = 921600;
2597 brd->ports[i].max_baud = 921600;
1da177e4 2598 } else {
1c45607a
JS		 2599 brd->ports[i].baud_base = 115200;
2600 brd->ports[i].max_baud = 115200;
1da177e4
LT		 2601 }
2602 }
2603 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2604 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2605 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2606 outb(scratch2, cap + UART_LCR);
2607 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2608 scratch = inb(cap + UART_IIR);
2609
2610 if (scratch & 0xC0)
1c45607a 2611 brd->uart_type = PORT_16550A;
1da177e4 2612 else
1c45607a
JS		 2613 brd->uart_type = PORT_16450;
2614 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
2615 "mxser(IO)"))
2616 return MXSER_ERR_IOADDR;
2617 if (!request_region(brd->vector, 1, "mxser(vector)")) {
2618 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2619 return MXSER_ERR_VECTOR;
2620 }
2621 return brd->info->nports;
1da177e4
LT		 2622}
2623
1c45607a
JS		 2624static int __devinit mxser_probe(struct pci_dev *pdev,
2625 const struct pci_device_id *ent)
1da177e4 2626{
1c45607a
JS		 2627#ifdef CONFIG_PCI
2628 struct mxser_board *brd;
2629 unsigned int i, j;
2630 unsigned long ioaddress;
2631 int retval = -EINVAL;
1da177e4 2632
1c45607a
JS		 2633 for (i = 0; i < MXSER_BOARDS; i++)
2634 if (mxser_boards[i].info == NULL)
2635 break;
2636
2637 if (i >= MXSER_BOARDS) {
2638 printk(KERN_ERR "Too many Smartio/Industio family boards found "
2639 "(maximum %d), board not configured\n", MXSER_BOARDS);
2640 goto err;
2641 }
2642
2643 brd = &mxser_boards[i];
2644 brd->idx = i * MXSER_PORTS_PER_BOARD;
2645 printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n",
2646 mxser_cards[ent->driver_data].name,
2647 pdev->bus->number, PCI_SLOT(pdev->devfn));
2648
2649 retval = pci_enable_device(pdev);
2650 if (retval) {
2651 printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n");
2652 goto err;
2653 }
2654
2655 /* io address */
2656 ioaddress = pci_resource_start(pdev, 2);
2657 retval = pci_request_region(pdev, 2, "mxser(IO)");
2658 if (retval)
2659 goto err;
2660
2661 brd->info = &mxser_cards[ent->driver_data];
2662 for (i = 0; i < brd->info->nports; i++)
2663 brd->ports[i].ioaddr = ioaddress + 8 * i;
2664
2665 /* vector */
2666 ioaddress = pci_resource_start(pdev, 3);
2667 retval = pci_request_region(pdev, 3, "mxser(vector)");
2668 if (retval)
2669 goto err_relio;
2670 brd->vector = ioaddress;
2671
2672 /* irq */
2673 brd->irq = pdev->irq;
2674
2675 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2676 brd->uart_type = PORT_16550A;
2677 brd->vector_mask = 0;
2678
2679 for (i = 0; i < brd->info->nports; i++) {
2680 for (j = 0; j < UART_INFO_NUM; j++) {
2681 if (Gpci_uart_info[j].type == brd->chip_flag) {
2682 brd->ports[i].max_baud =
2683 Gpci_uart_info[j].max_baud;
2684
2685 /* exception....CP-102 */
2686 if (brd->info->flags & MXSER_HIGHBAUD)
2687 brd->ports[i].max_baud = 921600;
2688 break;
1da177e4
LT		 2689 }
2690 }
1c45607a
JS		 2691 }
2692
2693 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2694 for (i = 0; i < brd->info->nports; i++) {
2695 if (i < 4)
2696 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2697 else
2698 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
1da177e4 2699 }
1c45607a
JS		 2700 outb(0, ioaddress + 4); /* default set to RS232 mode */
2701 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
1da177e4 2702 }
1c45607a
JS		 2703
2704 for (i = 0; i < brd->info->nports; i++) {
2705 brd->vector_mask |= (1 << i);
2706 brd->ports[i].baud_base = 921600;
2707 }
2708
2709 /* mxser_initbrd will hook ISR. */
2710 retval = mxser_initbrd(brd, pdev);
2711 if (retval)
2712 goto err_null;
2713
2714 for (i = 0; i < brd->info->nports; i++)
2715 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2716
2717 pci_set_drvdata(pdev, brd);
2718
2719 return 0;
2720err_relio:
2721 pci_release_region(pdev, 2);
2722err_null:
2723 brd->info = NULL;
2724err:
2725 return retval;
2726#else
2727 return -ENODEV;
2728#endif
1da177e4
LT		 2729}
2730
1c45607a 2731static void __devexit mxser_remove(struct pci_dev *pdev)
1da177e4 2732{
1c45607a
JS		 2733 struct mxser_board *brd = pci_get_drvdata(pdev);
2734 unsigned int i;
1da177e4 2735
1c45607a
JS		 2736 for (i = 0; i < brd->info->nports; i++)
2737 tty_unregister_device(mxvar_sdriver, brd->idx + i);
1da177e4 2738
1c45607a
JS		 2739 mxser_release_res(brd, pdev, 1);
2740 brd->info = NULL;
1da177e4
LT		 2741}
2742
1c45607a
JS		 2743static struct pci_driver mxser_driver = {
2744 .name = "mxser",
2745 .id_table = mxser_pcibrds,
2746 .probe = mxser_probe,
2747 .remove = __devexit_p(mxser_remove)
2748};
2749
2750static int __init mxser_module_init(void)
1da177e4 2751{
1c45607a
JS		 2752 struct mxser_board *brd;
2753 unsigned long cap;
2754 unsigned int i, m, isaloop;
2755 int retval, b;
1da177e4 2756
1c45607a
JS		 2757 pr_debug("Loading module mxser ...\n");
2758
2759 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2760 if (!mxvar_sdriver)
2761 return -ENOMEM;
2762
2763 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2764 MXSER_VERSION);
2765
2766 /* Initialize the tty_driver structure */
2767 mxvar_sdriver->owner = THIS_MODULE;
2768 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
2769 mxvar_sdriver->name = "ttyMI";
2770 mxvar_sdriver->major = ttymajor;
2771 mxvar_sdriver->minor_start = 0;
2772 mxvar_sdriver->num = MXSER_PORTS + 1;
2773 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2774 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2775 mxvar_sdriver->init_termios = tty_std_termios;
2776 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2777 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2778 tty_set_operations(mxvar_sdriver, &mxser_ops);
2779
2780 retval = tty_register_driver(mxvar_sdriver);
2781 if (retval) {
2782 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2783 "tty driver !\n");
2784 goto err_put;
1da177e4 2785 }
1c45607a 2786
1c45607a
JS		 2787 m = 0;
2788 /* Start finding ISA boards here */
2789 for (isaloop = 0; isaloop < 2; isaloop++)
2790 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
2791 if (!isaloop)
2792 cap = mxserBoardCAP[b]; /* predefined */
2793 else
2794 cap = ioaddr[b]; /* module param */
2795
2796 if (!cap)
2797 continue;
2798
2799 brd = &mxser_boards[m];
2800 retval = mxser_get_ISA_conf(cap, brd);
2801
2802 if (retval != 0)
2803 printk(KERN_INFO "Found MOXA %s board "
2804 "(CAP=0x%x)\n",
2805 brd->info->name, ioaddr[b]);
2806
2807 if (retval <= 0) {
2808 if (retval == MXSER_ERR_IRQ)
2809 printk(KERN_ERR "Invalid interrupt "
2810 "number, board not "
2811 "configured\n");
2812 else if (retval == MXSER_ERR_IRQ_CONFLIT)
2813 printk(KERN_ERR "Invalid interrupt "
2814 "number, board not "
2815 "configured\n");
2816 else if (retval == MXSER_ERR_VECTOR)
2817 printk(KERN_ERR "Invalid interrupt "
2818 "vector, board not "
2819 "configured\n");
2820 else if (retval == MXSER_ERR_IOADDR)
2821 printk(KERN_ERR "Invalid I/O address, "
2822 "board not configured\n");
2823
2824 brd->info = NULL;
2825 continue;
2826 }
2827
2828 /* mxser_initbrd will hook ISR. */
2829 if (mxser_initbrd(brd, NULL) < 0) {
2830 brd->info = NULL;
2831 continue;
2832 }
2833
2834 brd->idx = m * MXSER_PORTS_PER_BOARD;
2835 for (i = 0; i < brd->info->nports; i++)
2836 tty_register_device(mxvar_sdriver, brd->idx + i,
2837 NULL);
2838
2839 m++;
2840 }
2841
2842 retval = pci_register_driver(&mxser_driver);
2843 if (retval) {
2844 printk(KERN_ERR "Can't register pci driver\n");
2845 if (!m) {
2846 retval = -ENODEV;
2847 goto err_unr;
2848 } /* else: we have some ISA cards under control */
2849 }
2850
2851 pr_debug("Done.\n");
2852
2853 return 0;
2854err_unr:
2855 tty_unregister_driver(mxvar_sdriver);
2856err_put:
2857 put_tty_driver(mxvar_sdriver);
2858 return retval;
2859}
2860
2861static void __exit mxser_module_exit(void)
2862{
2863 unsigned int i, j;
2864
2865 pr_debug("Unloading module mxser ...\n");
2866
2867 pci_unregister_driver(&mxser_driver);
2868
2869 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2870 if (mxser_boards[i].info != NULL)
2871 for (j = 0; j < mxser_boards[i].info->nports; j++)
2872 tty_unregister_device(mxvar_sdriver,
2873 mxser_boards[i].idx + j);
2874 tty_unregister_driver(mxvar_sdriver);
2875 put_tty_driver(mxvar_sdriver);
2876
2877 for (i = 0; i < MXSER_BOARDS; i++)
2878 if (mxser_boards[i].info != NULL)
2879 mxser_release_res(&mxser_boards[i], NULL, 1);
2880
2881 pr_debug("Done.\n");
1da177e4
LT		 2882}
2883
2884module_init(mxser_module_init);
2885module_exit(mxser_module_exit);
Linux kernel - Deliverables
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