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Merge branch 'audit.b37' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/audit...
[deliverable/linux.git] / drivers / char / mxser_new.c
CommitLineData
037ad48b
JS		 1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
3306ce3d 4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com.tw).
c88cb8f9 5 * Copyright (C) 2006 Jiri Slaby <jirislaby@gmail.com>
037ad48b 6 *
c88cb8f9
JS		 7 * This code is loosely based on the 1.8 moxa driver which is based on
8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
037ad48b
JS		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
037ad48b
JS		 16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
17 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com.
18 * - Fixed x86_64 cleanness
19 * - Fixed sleep with spinlock held in mxser_send_break
20 */
21
037ad48b
JS		 22#include <linux/module.h>
23#include <linux/autoconf.h>
24#include <linux/errno.h>
25#include <linux/signal.h>
26#include <linux/sched.h>
27#include <linux/timer.h>
28#include <linux/interrupt.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/serial.h>
32#include <linux/serial_reg.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/fcntl.h>
36#include <linux/ptrace.h>
37#include <linux/gfp.h>
38#include <linux/ioport.h>
39#include <linux/mm.h>
40#include <linux/smp_lock.h>
41#include <linux/delay.h>
42#include <linux/pci.h>
43
44#include <asm/system.h>
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/bitops.h>
48#include <asm/uaccess.h>
49
771f2d1a 50#include "mxser_new.h"
037ad48b 51
f64c84a1 52#define MXSER_VERSION "2.0.1" /* 1.9.15 */
037ad48b
JS		 53#define MXSERMAJOR 174
54#define MXSERCUMAJOR 175
55
037ad48b 56#define MXSER_BOARDS 4 /* Max. boards */
037ad48b 57#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
a8b74de9 58#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
18b95576 59#define MXSER_ISR_PASS_LIMIT 100
037ad48b
JS		 60
61#define MXSER_ERR_IOADDR -1
62#define MXSER_ERR_IRQ -2
63#define MXSER_ERR_IRQ_CONFLIT -3
64#define MXSER_ERR_VECTOR -4
65
ed79ba12
JS		 66/*CheckIsMoxaMust return value*/
67#define MOXA_OTHER_UART 0x00
68#define MOXA_MUST_MU150_HWID 0x01
69#define MOXA_MUST_MU860_HWID 0x02
70
037ad48b
JS		 71#define WAKEUP_CHARS 256
72
73#define UART_MCR_AFE 0x20
74#define UART_LSR_SPECIAL 0x1E
75
76#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK|\
77 IXON|IXOFF))
78
037ad48b
JS		 79#define C168_ASIC_ID 1
80#define C104_ASIC_ID 2
81#define C102_ASIC_ID 0xB
82#define CI132_ASIC_ID 4
83#define CI134_ASIC_ID 3
84#define CI104J_ASIC_ID 5
85
cd7ed64e
JS		 86#define MXSER_HIGHBAUD 1
87#define MXSER_HAS2 2
037ad48b
JS		 88
89/* This is only for PCI */
cd7ed64e 90static const struct {
037ad48b
JS		 91 int type;
92 int tx_fifo;
93 int rx_fifo;
94 int xmit_fifo_size;
95 int rx_high_water;
96 int rx_trigger;
97 int rx_low_water;
98 long max_baud;
cd7ed64e 99} Gpci_uart_info[] = {
037ad48b
JS		 100 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
101 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
102 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
103};
cd7ed64e
JS		 104#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
105
106struct mxser_cardinfo {
107 unsigned int nports;
108 char *name;
109 unsigned int flags;
110};
111
112static const struct mxser_cardinfo mxser_cards[] = {
113 { 8, "C168 series", }, /* C168-ISA */
114 { 4, "C104 series", }, /* C104-ISA */
115 { 4, "CI-104J series", }, /* CI104J */
116 { 8, "C168H/PCI series", }, /* C168-PCI */
117 { 4, "C104H/PCI series", }, /* C104-PCI */
118 { 4, "C102 series", MXSER_HAS2 }, /* C102-ISA */
119 { 4, "CI-132 series", MXSER_HAS2 }, /* CI132 */
120 { 4, "CI-134 series", }, /* CI134 */
121 { 2, "CP-132 series", }, /* CP132 */
122 { 4, "CP-114 series", }, /* CP114 */
123 { 4, "CT-114 series", }, /* CT114 */
124 { 2, "CP-102 series", MXSER_HIGHBAUD }, /* CP102 */
125 { 4, "CP-104U series", }, /* CP104U */
126 { 8, "CP-168U series", }, /* CP168U */
127 { 2, "CP-132U series", }, /* CP132U */
128 { 4, "CP-134U series", }, /* CP134U */
129 { 4, "CP-104JU series", }, /* CP104JU */
130 { 8, "Moxa UC7000 Serial", }, /* RC7000 */
131 { 8, "CP-118U series", }, /* CP118U */
132 { 2, "CP-102UL series", }, /* CP102UL */
133 { 2, "CP-102U series", }, /* CP102U */
134 { 8, "CP-118EL series", }, /* CP118EL */
135 { 8, "CP-168EL series", }, /* CP168EL */
136 { 4, "CP-104EL series", } /* CP104EL */
137};
037ad48b 138
cd7ed64e
JS		 139/* driver_data correspond to the lines in the structure above
140 see also ISA probe function before you change something */
037ad48b 141static struct pci_device_id mxser_pcibrds[] = {
3306ce3d 142 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C168),
cd7ed64e 143 .driver_data = 3 },
3306ce3d 144 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C104),
cd7ed64e 145 .driver_data = 4 },
3306ce3d 146 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132),
cd7ed64e 147 .driver_data = 8 },
3306ce3d 148 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114),
cd7ed64e 149 .driver_data = 9 },
3306ce3d 150 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CT114),
cd7ed64e 151 .driver_data = 10 },
3306ce3d 152 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102),
cd7ed64e 153 .driver_data = 11 },
3306ce3d 154 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104U),
cd7ed64e 155 .driver_data = 12 },
3306ce3d 156 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168U),
cd7ed64e 157 .driver_data = 13 },
3306ce3d 158 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132U),
cd7ed64e 159 .driver_data = 14 },
3306ce3d 160 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134U),
cd7ed64e 161 .driver_data = 15 },
3306ce3d 162 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104JU),
cd7ed64e 163 .driver_data = 16 },
3306ce3d 164 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_RC7000),
cd7ed64e 165 .driver_data = 17 },
3306ce3d 166 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118U),
cd7ed64e 167 .driver_data = 18 },
3306ce3d 168 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102UL),
cd7ed64e 169 .driver_data = 19 },
3306ce3d 170 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102U),
cd7ed64e 171 .driver_data = 20 },
3306ce3d 172 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL),
cd7ed64e 173 .driver_data = 21 },
3306ce3d 174 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL),
cd7ed64e 175 .driver_data = 22 },
3306ce3d 176 { PCI_DEVICE(PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL),
cd7ed64e 177 .driver_data = 23 },
3306ce3d 178 { }
037ad48b 179};
037ad48b
JS		 180MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
181
f64c84a1
JS		 182static int mxvar_baud_table[] = {
183 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
184 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600
185};
186static unsigned int mxvar_baud_table1[] = {
187 0, B50, B75, B110, B134, B150, B200, B300, B600, B1200, B1800, B2400,
188 B4800, B9600, B19200, B38400, B57600, B115200, B230400, B460800, B921600
189};
190#define BAUD_TABLE_NO ARRAY_SIZE(mxvar_baud_table)
191
192#define B_SPEC B2000000
193
037ad48b
JS		 194static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 };
195static int ttymajor = MXSERMAJOR;
196static int calloutmajor = MXSERCUMAJOR;
037ad48b
JS		 197
198/* Variables for insmod */
199
200MODULE_AUTHOR("Casper Yang");
201MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
202module_param_array(ioaddr, int, NULL, 0);
203module_param(ttymajor, int, 0);
037ad48b
JS		 204MODULE_LICENSE("GPL");
205
206struct mxser_log {
207 int tick;
208 unsigned long rxcnt[MXSER_PORTS];
209 unsigned long txcnt[MXSER_PORTS];
210};
211
212
213struct mxser_mon {
214 unsigned long rxcnt;
215 unsigned long txcnt;
216 unsigned long up_rxcnt;
217 unsigned long up_txcnt;
218 int modem_status;
219 unsigned char hold_reason;
220};
221
222struct mxser_mon_ext {
223 unsigned long rx_cnt[32];
224 unsigned long tx_cnt[32];
225 unsigned long up_rxcnt[32];
226 unsigned long up_txcnt[32];
227 int modem_status[32];
228
229 long baudrate[32];
230 int databits[32];
231 int stopbits[32];
232 int parity[32];
233 int flowctrl[32];
234 int fifo[32];
235 int iftype[32];
236};
237
55b307da
JS		 238struct mxser_board;
239
240struct mxser_port {
241 struct mxser_board *board;
242 struct tty_struct *tty;
243
244 unsigned long ioaddr;
245 unsigned long opmode_ioaddr;
246 int max_baud;
037ad48b 247
037ad48b
JS		 248 int rx_high_water;
249 int rx_trigger; /* Rx fifo trigger level */
250 int rx_low_water;
251 int baud_base; /* max. speed */
55b307da 252 long realbaud;
037ad48b 253 int type; /* UART type */
55b307da 254 int flags; /* defined in tty.h */
f64c84a1 255 int speed;
55b307da 256
037ad48b 257 int x_char; /* xon/xoff character */
037ad48b
JS		 258 int IER; /* Interrupt Enable Register */
259 int MCR; /* Modem control register */
55b307da
JS		 260
261 unsigned char stop_rx;
262 unsigned char ldisc_stop_rx;
263
264 int custom_divisor;
265 int close_delay;
266 unsigned short closing_wait;
267 unsigned char err_shadow;
037ad48b 268 unsigned long event;
55b307da 269
037ad48b
JS		 270 int count; /* # of fd on device */
271 int blocked_open; /* # of blocked opens */
55b307da
JS		 272 struct async_icount icount; /* kernel counters for 4 input interrupts */
273 int timeout;
274
275 int read_status_mask;
276 int ignore_status_mask;
277 int xmit_fifo_size;
037ad48b
JS		 278 unsigned char *xmit_buf;
279 int xmit_head;
280 int xmit_tail;
281 int xmit_cnt;
55b307da 282
606d099c 283 struct ktermios normal_termios;
55b307da
JS		 284
285 struct mxser_mon mon_data;
286
287 spinlock_t slock;
037ad48b 288 wait_queue_head_t open_wait;
037ad48b 289 wait_queue_head_t delta_msr_wait;
55b307da
JS		 290};
291
292struct mxser_board {
2094e757 293 unsigned int idx;
55b307da 294 int irq;
cd7ed64e 295 const struct mxser_cardinfo *info;
55b307da
JS		 296 unsigned long vector;
297 unsigned long vector_mask;
298
299 int chip_flag;
300 int uart_type;
301
302 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
037ad48b
JS		 303};
304
305struct mxser_mstatus {
306 tcflag_t cflag;
307 int cts;
308 int dsr;
309 int ri;
310 int dcd;
311};
312
313static struct mxser_mstatus GMStatus[MXSER_PORTS];
314
315static int mxserBoardCAP[MXSER_BOARDS] = {
316 0, 0, 0, 0
317 /* 0x180, 0x280, 0x200, 0x320 */
318};
319
55b307da 320static struct mxser_board mxser_boards[MXSER_BOARDS];
037ad48b 321static struct tty_driver *mxvar_sdriver;
037ad48b
JS		 322static struct mxser_log mxvar_log;
323static int mxvar_diagflag;
324static unsigned char mxser_msr[MXSER_PORTS + 1];
325static struct mxser_mon_ext mon_data_ext;
326static int mxser_set_baud_method[MXSER_PORTS + 1];
037ad48b 327
fb0c9295 328#ifdef CONFIG_PCI
c76b0930 329static int __devinit CheckIsMoxaMust(int io)
037ad48b
JS		 330{
331 u8 oldmcr, hwid;
332 int i;
333
334 outb(0, io + UART_LCR);
335 DISABLE_MOXA_MUST_ENCHANCE_MODE(io);
336 oldmcr = inb(io + UART_MCR);
337 outb(0, io + UART_MCR);
338 SET_MOXA_MUST_XON1_VALUE(io, 0x11);
339 if ((hwid = inb(io + UART_MCR)) != 0) {
340 outb(oldmcr, io + UART_MCR);
341 return MOXA_OTHER_UART;
342 }
343
344 GET_MOXA_MUST_HARDWARE_ID(io, &hwid);
cd7ed64e
JS		 345 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
346 if (hwid == Gpci_uart_info[i].type)
037ad48b
JS		 347 return (int)hwid;
348 }
349 return MOXA_OTHER_UART;
350}
fb0c9295 351#endif
037ad48b 352
55b307da 353static void process_txrx_fifo(struct mxser_port *info)
037ad48b
JS		 354{
355 int i;
356
357 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
358 info->rx_trigger = 1;
359 info->rx_high_water = 1;
360 info->rx_low_water = 1;
361 info->xmit_fifo_size = 1;
55b307da
JS		 362 } else
363 for (i = 0; i < UART_INFO_NUM; i++)
364 if (info->board->chip_flag == Gpci_uart_info[i].type) {
037ad48b
JS		 365 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
366 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
367 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
368 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
369 break;
370 }
037ad48b
JS		 371}
372
a8dea4ec
JS		 373static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
374{
375 unsigned char status = 0;
037ad48b 376
a8dea4ec 377 status = inb(baseaddr + UART_MSR);
037ad48b 378
a8dea4ec
JS		 379 mxser_msr[port] &= 0x0F;
380 mxser_msr[port] |= status;
381 status = mxser_msr[port];
382 if (mode)
383 mxser_msr[port] = 0;
037ad48b 384
a8dea4ec
JS		 385 return status;
386}
55b307da 387
a8dea4ec
JS		 388static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp,
389 struct mxser_port *port)
390{
391 DECLARE_WAITQUEUE(wait, current);
392 int retval;
393 int do_clocal = 0;
394 unsigned long flags;
395
396 /*
397 * If non-blocking mode is set, or the port is not enabled,
398 * then make the check up front and then exit.
399 */
214efebb
JS		 400 if ((filp->f_flags & O_NONBLOCK) ||
401 test_bit(TTY_IO_ERROR, &tty->flags)) {
a8dea4ec
JS		 402 port->flags |= ASYNC_NORMAL_ACTIVE;
403 return 0;
037ad48b 404 }
a8dea4ec
JS		 405
406 if (tty->termios->c_cflag & CLOCAL)
407 do_clocal = 1;
408
037ad48b 409 /*
a8dea4ec
JS		 410 * Block waiting for the carrier detect and the line to become
411 * free (i.e., not in use by the callout). While we are in
412 * this loop, port->count is dropped by one, so that
413 * mxser_close() knows when to free things. We restore it upon
414 * exit, either normal or abnormal.
037ad48b 415 */
a8dea4ec
JS		 416 retval = 0;
417 add_wait_queue(&port->open_wait, &wait);
037ad48b 418
a8dea4ec
JS		 419 spin_lock_irqsave(&port->slock, flags);
420 if (!tty_hung_up_p(filp))
421 port->count--;
422 spin_unlock_irqrestore(&port->slock, flags);
423 port->blocked_open++;
424 while (1) {
425 spin_lock_irqsave(&port->slock, flags);
426 outb(inb(port->ioaddr + UART_MCR) |
427 UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR);
428 spin_unlock_irqrestore(&port->slock, flags);
429 set_current_state(TASK_INTERRUPTIBLE);
430 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)) {
431 if (port->flags & ASYNC_HUP_NOTIFY)
432 retval = -EAGAIN;
433 else
434 retval = -ERESTARTSYS;
435 break;
436 }
437 if (!(port->flags & ASYNC_CLOSING) &&
438 (do_clocal ||
439 (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD)))
440 break;
441 if (signal_pending(current)) {
442 retval = -ERESTARTSYS;
443 break;
444 }
445 schedule();
037ad48b 446 }
a8dea4ec
JS		 447 set_current_state(TASK_RUNNING);
448 remove_wait_queue(&port->open_wait, &wait);
449 if (!tty_hung_up_p(filp))
450 port->count++;
451 port->blocked_open--;
452 if (retval)
453 return retval;
454 port->flags |= ASYNC_NORMAL_ACTIVE;
037ad48b
JS		 455 return 0;
456}
457
a8dea4ec 458static int mxser_set_baud(struct mxser_port *info, long newspd)
037ad48b 459{
f64c84a1 460 unsigned int i;
a8dea4ec
JS		 461 int quot = 0;
462 unsigned char cval;
463 int ret = 0;
037ad48b 464
a8dea4ec
JS		 465 if (!info->tty || !info->tty->termios)
466 return ret;
037ad48b 467
a8dea4ec
JS		 468 if (!(info->ioaddr))
469 return ret;
037ad48b 470
a8dea4ec
JS		 471 if (newspd > info->max_baud)
472 return 0;
037ad48b 473
a8dea4ec 474 info->realbaud = newspd;
f64c84a1
JS		 475 for (i = 0; i < BAUD_TABLE_NO; i++)
476 if (newspd == mxvar_baud_table[i])
477 break;
478 if (i == BAUD_TABLE_NO) {
479 quot = info->baud_base / info->speed;
480 if (info->speed <= 0 || info->speed > info->max_baud)
481 quot = 0;
a8dea4ec 482 } else {
f64c84a1
JS		 483 if (newspd == 134) {
484 quot = (2 * info->baud_base / 269);
485 } else if (newspd) {
486 quot = info->baud_base / newspd;
487 if (quot == 0)
488 quot = 1;
489 } else {
490 quot = 0;
491 }
037ad48b
JS		 492 }
493
a8dea4ec
JS		 494 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
495 info->timeout += HZ / 50; /* Add .02 seconds of slop */
037ad48b 496
a8dea4ec 497 if (quot) {
a8dea4ec
JS		 498 info->MCR |= UART_MCR_DTR;
499 outb(info->MCR, info->ioaddr + UART_MCR);
a8dea4ec 500 } else {
a8dea4ec
JS		 501 info->MCR &= ~UART_MCR_DTR;
502 outb(info->MCR, info->ioaddr + UART_MCR);
a8dea4ec 503 return ret;
037ad48b 504 }
037ad48b 505
a8dea4ec 506 cval = inb(info->ioaddr + UART_LCR);
037ad48b 507
a8dea4ec 508 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
037ad48b 509
a8dea4ec
JS		 510 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
511 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
512 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
037ad48b 513
f64c84a1
JS		 514 if (i == BAUD_TABLE_NO) {
515 quot = info->baud_base % info->speed;
516 quot *= 8;
517 if ((quot % info->speed) > (info->speed / 2)) {
518 quot /= info->speed;
519 quot++;
520 } else {
521 quot /= info->speed;
522 }
523 SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, quot);
524 } else
525 SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, 0);
037ad48b 526
a8dea4ec
JS		 527 return ret;
528}
037ad48b 529
a8dea4ec
JS		 530/*
531 * This routine is called to set the UART divisor registers to match
532 * the specified baud rate for a serial port.
533 */
534static int mxser_change_speed(struct mxser_port *info,
606d099c 535 struct ktermios *old_termios)
a8dea4ec
JS		 536{
537 unsigned cflag, cval, fcr;
538 int ret = 0;
539 unsigned char status;
540 long baud;
037ad48b 541
a8dea4ec
JS		 542 if (!info->tty || !info->tty->termios)
543 return ret;
544 cflag = info->tty->termios->c_cflag;
545 if (!(info->ioaddr))
546 return ret;
037ad48b 547
a8dea4ec 548 if (mxser_set_baud_method[info->tty->index] == 0) {
f64c84a1
JS		 549 if ((cflag & CBAUD) == B_SPEC)
550 baud = info->speed;
551 else
552 baud = tty_get_baud_rate(info->tty);
a8dea4ec
JS		 553 mxser_set_baud(info, baud);
554 }
037ad48b 555
a8dea4ec
JS		 556 /* byte size and parity */
557 switch (cflag & CSIZE) {
558 case CS5:
559 cval = 0x00;
560 break;
561 case CS6:
562 cval = 0x01;
563 break;
564 case CS7:
565 cval = 0x02;
566 break;
567 case CS8:
568 cval = 0x03;
569 break;
570 default:
571 cval = 0x00;
572 break; /* too keep GCC shut... */
573 }
574 if (cflag & CSTOPB)
575 cval |= 0x04;
576 if (cflag & PARENB)
577 cval |= UART_LCR_PARITY;
578 if (!(cflag & PARODD))
579 cval |= UART_LCR_EPAR;
580 if (cflag & CMSPAR)
581 cval |= UART_LCR_SPAR;
037ad48b 582
a8dea4ec
JS		 583 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
584 if (info->board->chip_flag) {
585 fcr = UART_FCR_ENABLE_FIFO;
586 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
587 SET_MOXA_MUST_FIFO_VALUE(info);
588 } else
589 fcr = 0;
590 } else {
591 fcr = UART_FCR_ENABLE_FIFO;
a8dea4ec
JS		 592 if (info->board->chip_flag) {
593 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
594 SET_MOXA_MUST_FIFO_VALUE(info);
595 } else {
a8dea4ec
JS		 596 switch (info->rx_trigger) {
597 case 1:
598 fcr |= UART_FCR_TRIGGER_1;
599 break;
600 case 4:
601 fcr |= UART_FCR_TRIGGER_4;
602 break;
603 case 8:
604 fcr |= UART_FCR_TRIGGER_8;
605 break;
606 default:
607 fcr |= UART_FCR_TRIGGER_14;
608 break;
609 }
037ad48b 610 }
037ad48b
JS		 611 }
612
a8dea4ec
JS		 613 /* CTS flow control flag and modem status interrupts */
614 info->IER &= ~UART_IER_MSI;
615 info->MCR &= ~UART_MCR_AFE;
616 if (cflag & CRTSCTS) {
617 info->flags |= ASYNC_CTS_FLOW;
618 info->IER |= UART_IER_MSI;
619 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
620 info->MCR |= UART_MCR_AFE;
a8dea4ec 621 } else {
a8dea4ec 622 status = inb(info->ioaddr + UART_MSR);
a8dea4ec
JS		 623 if (info->tty->hw_stopped) {
624 if (status & UART_MSR_CTS) {
625 info->tty->hw_stopped = 0;
626 if (info->type != PORT_16550A &&
627 !info->board->chip_flag) {
628 outb(info->IER & ~UART_IER_THRI,
629 info->ioaddr +
630 UART_IER);
631 info->IER |= UART_IER_THRI;
632 outb(info->IER, info->ioaddr +
633 UART_IER);
634 }
47c85c0d
JS		 635 tty_wakeup(info->tty);
636 }
a8dea4ec
JS		 637 } else {
638 if (!(status & UART_MSR_CTS)) {
639 info->tty->hw_stopped = 1;
640 if ((info->type != PORT_16550A) &&
641 (!info->board->chip_flag)) {
642 info->IER &= ~UART_IER_THRI;
643 outb(info->IER, info->ioaddr +
644 UART_IER);
645 }
646 }
647 }
648 }
649 } else {
650 info->flags &= ~ASYNC_CTS_FLOW;
651 }
652 outb(info->MCR, info->ioaddr + UART_MCR);
653 if (cflag & CLOCAL) {
654 info->flags &= ~ASYNC_CHECK_CD;
655 } else {
656 info->flags |= ASYNC_CHECK_CD;
657 info->IER |= UART_IER_MSI;
658 }
659 outb(info->IER, info->ioaddr + UART_IER);
037ad48b 660
a8dea4ec
JS		 661 /*
662 * Set up parity check flag
663 */
664 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
665 if (I_INPCK(info->tty))
666 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
667 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
668 info->read_status_mask |= UART_LSR_BI;
037ad48b 669
a8dea4ec 670 info->ignore_status_mask = 0;
037ad48b 671
a8dea4ec
JS		 672 if (I_IGNBRK(info->tty)) {
673 info->ignore_status_mask |= UART_LSR_BI;
674 info->read_status_mask |= UART_LSR_BI;
675 /*
676 * If we're ignore parity and break indicators, ignore
677 * overruns too. (For real raw support).
678 */
679 if (I_IGNPAR(info->tty)) {
680 info->ignore_status_mask |=
681 UART_LSR_OE |
682 UART_LSR_PE |
683 UART_LSR_FE;
684 info->read_status_mask |=
685 UART_LSR_OE |
686 UART_LSR_PE |
687 UART_LSR_FE;
037ad48b 688 }
037ad48b 689 }
a8dea4ec 690 if (info->board->chip_flag) {
a8dea4ec
JS		 691 SET_MOXA_MUST_XON1_VALUE(info->ioaddr, START_CHAR(info->tty));
692 SET_MOXA_MUST_XOFF1_VALUE(info->ioaddr, STOP_CHAR(info->tty));
693 if (I_IXON(info->tty)) {
694 ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
695 } else {
696 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
037ad48b 697 }
a8dea4ec
JS		 698 if (I_IXOFF(info->tty)) {
699 ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
700 } else {
701 DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
037ad48b
JS		 702 }
703 }
037ad48b 704
037ad48b 705
a8dea4ec
JS		 706 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
707 outb(cval, info->ioaddr + UART_LCR);
037ad48b 708
a8dea4ec 709 return ret;
037ad48b
JS		 710}
711
a8dea4ec 712static void mxser_check_modem_status(struct mxser_port *port, int status)
037ad48b 713{
a8dea4ec
JS		 714 /* update input line counters */
715 if (status & UART_MSR_TERI)
716 port->icount.rng++;
717 if (status & UART_MSR_DDSR)
718 port->icount.dsr++;
719 if (status & UART_MSR_DDCD)
720 port->icount.dcd++;
721 if (status & UART_MSR_DCTS)
722 port->icount.cts++;
723 port->mon_data.modem_status = status;
724 wake_up_interruptible(&port->delta_msr_wait);
037ad48b 725
a8dea4ec
JS		 726 if ((port->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
727 if (status & UART_MSR_DCD)
728 wake_up_interruptible(&port->open_wait);
a8dea4ec 729 }
037ad48b 730
a8dea4ec
JS		 731 if (port->flags & ASYNC_CTS_FLOW) {
732 if (port->tty->hw_stopped) {
733 if (status & UART_MSR_CTS) {
734 port->tty->hw_stopped = 0;
735
736 if ((port->type != PORT_16550A) &&
737 (!port->board->chip_flag)) {
738 outb(port->IER & ~UART_IER_THRI,
739 port->ioaddr + UART_IER);
740 port->IER |= UART_IER_THRI;
741 outb(port->IER, port->ioaddr +
742 UART_IER);
743 }
47c85c0d 744 tty_wakeup(port->tty);
a8dea4ec
JS		 745 }
746 } else {
747 if (!(status & UART_MSR_CTS)) {
748 port->tty->hw_stopped = 1;
749 if (port->type != PORT_16550A &&
750 !port->board->chip_flag) {
751 port->IER &= ~UART_IER_THRI;
752 outb(port->IER, port->ioaddr +
753 UART_IER);
754 }
755 }
756 }
757 }
037ad48b
JS		 758}
759
a8dea4ec 760static int mxser_startup(struct mxser_port *info)
037ad48b 761{
a8dea4ec
JS		 762 unsigned long page;
763 unsigned long flags;
037ad48b 764
a8dea4ec
JS		 765 page = __get_free_page(GFP_KERNEL);
766 if (!page)
767 return -ENOMEM;
037ad48b 768
a8dea4ec 769 spin_lock_irqsave(&info->slock, flags);
037ad48b 770
a8dea4ec
JS		 771 if (info->flags & ASYNC_INITIALIZED) {
772 free_page(page);
773 spin_unlock_irqrestore(&info->slock, flags);
774 return 0;
775 }
037ad48b 776
a8dea4ec
JS		 777 if (!info->ioaddr || !info->type) {
778 if (info->tty)
779 set_bit(TTY_IO_ERROR, &info->tty->flags);
780 free_page(page);
781 spin_unlock_irqrestore(&info->slock, flags);
037ad48b 782 return 0;
a8dea4ec
JS		 783 }
784 if (info->xmit_buf)
785 free_page(page);
786 else
787 info->xmit_buf = (unsigned char *) page;
037ad48b 788
037ad48b 789 /*
a8dea4ec
JS		 790 * Clear the FIFO buffers and disable them
791 * (they will be reenabled in mxser_change_speed())
037ad48b 792 */
a8dea4ec
JS		 793 if (info->board->chip_flag)
794 outb((UART_FCR_CLEAR_RCVR |
795 UART_FCR_CLEAR_XMIT |
796 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
797 else
798 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
799 info->ioaddr + UART_FCR);
800
801 /*
802 * At this point there's no way the LSR could still be 0xFF;
803 * if it is, then bail out, because there's likely no UART
804 * here.
805 */
806 if (inb(info->ioaddr + UART_LSR) == 0xff) {
807 spin_unlock_irqrestore(&info->slock, flags);
808 if (capable(CAP_SYS_ADMIN)) {
809 if (info->tty)
810 set_bit(TTY_IO_ERROR, &info->tty->flags);
811 return 0;
812 } else
813 return -ENODEV;
814 }
815
816 /*
817 * Clear the interrupt registers.
818 */
819 (void) inb(info->ioaddr + UART_LSR);
820 (void) inb(info->ioaddr + UART_RX);
821 (void) inb(info->ioaddr + UART_IIR);
822 (void) inb(info->ioaddr + UART_MSR);
823
824 /*
825 * Now, initialize the UART
826 */
827 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
828 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
829 outb(info->MCR, info->ioaddr + UART_MCR);
830
831 /*
832 * Finally, enable interrupts
833 */
834 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
a8dea4ec 835
a8dea4ec
JS		 836 if (info->board->chip_flag)
837 info->IER |= MOXA_MUST_IER_EGDAI;
a8dea4ec
JS		 838 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
839
840 /*
841 * And clear the interrupt registers again for luck.
842 */
843 (void) inb(info->ioaddr + UART_LSR);
844 (void) inb(info->ioaddr + UART_RX);
845 (void) inb(info->ioaddr + UART_IIR);
846 (void) inb(info->ioaddr + UART_MSR);
847
848 if (info->tty)
849 clear_bit(TTY_IO_ERROR, &info->tty->flags);
850 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
851
852 /*
853 * and set the speed of the serial port
854 */
a8dea4ec 855 mxser_change_speed(info, NULL);
5ff7205d 856 info->flags |= ASYNC_INITIALIZED;
f64c84a1 857 spin_unlock_irqrestore(&info->slock, flags);
a8dea4ec 858
a8dea4ec
JS		 859 return 0;
860}
861
862/*
863 * This routine will shutdown a serial port; interrupts maybe disabled, and
864 * DTR is dropped if the hangup on close termio flag is on.
865 */
866static void mxser_shutdown(struct mxser_port *info)
867{
868 unsigned long flags;
869
870 if (!(info->flags & ASYNC_INITIALIZED))
871 return;
872
873 spin_lock_irqsave(&info->slock, flags);
874
875 /*
876 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
877 * here so the queue might never be waken up
878 */
879 wake_up_interruptible(&info->delta_msr_wait);
880
881 /*
882 * Free the IRQ, if necessary
883 */
884 if (info->xmit_buf) {
885 free_page((unsigned long) info->xmit_buf);
886 info->xmit_buf = NULL;
887 }
888
889 info->IER = 0;
890 outb(0x00, info->ioaddr + UART_IER);
891
892 if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
893 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS);
894 outb(info->MCR, info->ioaddr + UART_MCR);
895
896 /* clear Rx/Tx FIFO's */
a8dea4ec
JS		 897 if (info->board->chip_flag)
898 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
899 MOXA_MUST_FCR_GDA_MODE_ENABLE,
900 info->ioaddr + UART_FCR);
901 else
a8dea4ec
JS		 902 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
903 info->ioaddr + UART_FCR);
904
905 /* read data port to reset things */
906 (void) inb(info->ioaddr + UART_RX);
907
908 if (info->tty)
909 set_bit(TTY_IO_ERROR, &info->tty->flags);
910
911 info->flags &= ~ASYNC_INITIALIZED;
912
a8dea4ec
JS		 913 if (info->board->chip_flag)
914 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
a8dea4ec
JS		 915
916 spin_unlock_irqrestore(&info->slock, flags);
917}
918
919/*
920 * This routine is called whenever a serial port is opened. It
921 * enables interrupts for a serial port, linking in its async structure into
922 * the IRQ chain. It also performs the serial-specific
923 * initialization for the tty structure.
924 */
925static int mxser_open(struct tty_struct *tty, struct file *filp)
926{
927 struct mxser_port *info;
5ff7205d 928 unsigned long flags;
a8dea4ec
JS		 929 int retval, line;
930
a8dea4ec
JS		 931 line = tty->index;
932 if (line == MXSER_PORTS)
933 return 0;
934 if (line < 0 || line > MXSER_PORTS)
935 return -ENODEV;
936 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
937 if (!info->ioaddr)
938 return -ENODEV;
939
940 tty->driver_data = info;
941 info->tty = tty;
942 /*
943 * Start up serial port
944 */
5ff7205d 945 spin_lock_irqsave(&info->slock, flags);
a8dea4ec 946 info->count++;
5ff7205d 947 spin_unlock_irqrestore(&info->slock, flags);
a8dea4ec
JS		 948 retval = mxser_startup(info);
949 if (retval)
950 return retval;
951
952 retval = mxser_block_til_ready(tty, filp, info);
953 if (retval)
954 return retval;
955
e079f495 956 /* unmark here for very high baud rate (ex. 921600 bps) used */
037ad48b
JS		 957 tty->low_latency = 1;
958 return 0;
959}
960
961/*
962 * This routine is called when the serial port gets closed. First, we
963 * wait for the last remaining data to be sent. Then, we unlink its
964 * async structure from the interrupt chain if necessary, and we free
965 * that IRQ if nothing is left in the chain.
966 */
967static void mxser_close(struct tty_struct *tty, struct file *filp)
968{
55b307da 969 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 970
971 unsigned long timeout;
972 unsigned long flags;
037ad48b
JS		 973
974 if (tty->index == MXSER_PORTS)
975 return;
976 if (!info)
977 return;
978
979 spin_lock_irqsave(&info->slock, flags);
980
981 if (tty_hung_up_p(filp)) {
982 spin_unlock_irqrestore(&info->slock, flags);
983 return;
984 }
985 if ((tty->count == 1) && (info->count != 1)) {
986 /*
987 * Uh, oh. tty->count is 1, which means that the tty
988 * structure will be freed. Info->count should always
989 * be one in these conditions. If it's greater than
990 * one, we've got real problems, since it means the
991 * serial port won't be shutdown.
992 */
993 printk(KERN_ERR "mxser_close: bad serial port count; "
994 "tty->count is 1, info->count is %d\n", info->count);
995 info->count = 1;
996 }
997 if (--info->count < 0) {
998 printk(KERN_ERR "mxser_close: bad serial port count for "
55b307da 999 "ttys%d: %d\n", tty->index, info->count);
037ad48b
JS		 1000 info->count = 0;
1001 }
1002 if (info->count) {
1003 spin_unlock_irqrestore(&info->slock, flags);
1004 return;
1005 }
1006 info->flags |= ASYNC_CLOSING;
1007 spin_unlock_irqrestore(&info->slock, flags);
1008 /*
1009 * Save the termios structure, since this port may have
1010 * separate termios for callout and dialin.
1011 */
1012 if (info->flags & ASYNC_NORMAL_ACTIVE)
1013 info->normal_termios = *tty->termios;
1014 /*
1015 * Now we wait for the transmit buffer to clear; and we notify
1016 * the line discipline to only process XON/XOFF characters.
1017 */
1018 tty->closing = 1;
1019 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
1020 tty_wait_until_sent(tty, info->closing_wait);
1021 /*
1022 * At this point we stop accepting input. To do this, we
1023 * disable the receive line status interrupts, and tell the
1024 * interrupt driver to stop checking the data ready bit in the
1025 * line status register.
1026 */
1027 info->IER &= ~UART_IER_RLSI;
55b307da 1028 if (info->board->chip_flag)
037ad48b 1029 info->IER &= ~MOXA_MUST_RECV_ISR;
e079f495 1030
037ad48b 1031 if (info->flags & ASYNC_INITIALIZED) {
55b307da 1032 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1033 /*
1034 * Before we drop DTR, make sure the UART transmitter
1035 * has completely drained; this is especially
1036 * important if there is a transmit FIFO!
1037 */
1038 timeout = jiffies + HZ;
55b307da 1039 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
037ad48b
JS		 1040 schedule_timeout_interruptible(5);
1041 if (time_after(jiffies, timeout))
1042 break;
1043 }
1044 }
1045 mxser_shutdown(info);
1046
1047 if (tty->driver->flush_buffer)
1048 tty->driver->flush_buffer(tty);
1049
7e8bcf9a 1050 tty_ldisc_flush(tty);
037ad48b
JS		 1051
1052 tty->closing = 0;
1053 info->event = 0;
1054 info->tty = NULL;
1055 if (info->blocked_open) {
1056 if (info->close_delay)
1057 schedule_timeout_interruptible(info->close_delay);
1058 wake_up_interruptible(&info->open_wait);
1059 }
1060
1061 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING);
037ad48b
JS		 1062}
1063
1064static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1065{
1066 int c, total = 0;
55b307da 1067 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1068 unsigned long flags;
1069
1070 if (!info->xmit_buf)
1071 return 0;
1072
1073 while (1) {
1074 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1075 SERIAL_XMIT_SIZE - info->xmit_head));
1076 if (c <= 0)
1077 break;
1078
1079 memcpy(info->xmit_buf + info->xmit_head, buf, c);
1080 spin_lock_irqsave(&info->slock, flags);
1081 info->xmit_head = (info->xmit_head + c) &
1082 (SERIAL_XMIT_SIZE - 1);
1083 info->xmit_cnt += c;
1084 spin_unlock_irqrestore(&info->slock, flags);
1085
1086 buf += c;
1087 count -= c;
1088 total += c;
1089 }
1090
e079f495 1091 if (info->xmit_cnt && !tty->stopped) {
037ad48b
JS		 1092 if (!tty->hw_stopped ||
1093 (info->type == PORT_16550A) ||
55b307da 1094 (info->board->chip_flag)) {
037ad48b 1095 spin_lock_irqsave(&info->slock, flags);
55b307da
JS		 1096 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1097 UART_IER);
037ad48b 1098 info->IER |= UART_IER_THRI;
55b307da 1099 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1100 spin_unlock_irqrestore(&info->slock, flags);
1101 }
1102 }
1103 return total;
1104}
1105
1106static void mxser_put_char(struct tty_struct *tty, unsigned char ch)
1107{
55b307da 1108 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1109 unsigned long flags;
1110
1111 if (!info->xmit_buf)
1112 return;
1113
1114 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
1115 return;
1116
1117 spin_lock_irqsave(&info->slock, flags);
1118 info->xmit_buf[info->xmit_head++] = ch;
1119 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1120 info->xmit_cnt++;
1121 spin_unlock_irqrestore(&info->slock, flags);
e079f495 1122 if (!tty->stopped) {
037ad48b
JS		 1123 if (!tty->hw_stopped ||
1124 (info->type == PORT_16550A) ||
55b307da 1125 info->board->chip_flag) {
037ad48b 1126 spin_lock_irqsave(&info->slock, flags);
55b307da 1127 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
037ad48b 1128 info->IER |= UART_IER_THRI;
55b307da 1129 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1130 spin_unlock_irqrestore(&info->slock, flags);
1131 }
1132 }
1133}
1134
1135
1136static void mxser_flush_chars(struct tty_struct *tty)
1137{
55b307da 1138 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1139 unsigned long flags;
1140
1141 if (info->xmit_cnt <= 0 ||
1142 tty->stopped ||
1143 !info->xmit_buf ||
1144 (tty->hw_stopped &&
1145 (info->type != PORT_16550A) &&
55b307da 1146 (!info->board->chip_flag)
037ad48b
JS		 1147 ))
1148 return;
1149
1150 spin_lock_irqsave(&info->slock, flags);
1151
55b307da 1152 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
037ad48b 1153 info->IER |= UART_IER_THRI;
55b307da 1154 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1155
1156 spin_unlock_irqrestore(&info->slock, flags);
1157}
1158
1159static int mxser_write_room(struct tty_struct *tty)
1160{
55b307da 1161 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1162 int ret;
1163
1164 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1165 if (ret < 0)
1166 ret = 0;
1167 return ret;
1168}
1169
1170static int mxser_chars_in_buffer(struct tty_struct *tty)
1171{
55b307da 1172 struct mxser_port *info = tty->driver_data;
925e9c1c 1173 return info->xmit_cnt;
037ad48b
JS		 1174}
1175
1176static void mxser_flush_buffer(struct tty_struct *tty)
1177{
55b307da 1178 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1179 char fcr;
1180 unsigned long flags;
1181
1182
1183 spin_lock_irqsave(&info->slock, flags);
1184 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1185
55b307da 1186 fcr = inb(info->ioaddr + UART_FCR);
037ad48b 1187 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
55b307da
JS		 1188 info->ioaddr + UART_FCR);
1189 outb(fcr, info->ioaddr + UART_FCR);
037ad48b
JS		 1190
1191 spin_unlock_irqrestore(&info->slock, flags);
037ad48b 1192
7e8bcf9a 1193 tty_wakeup(tty);
037ad48b
JS		 1194}
1195
a8dea4ec
JS		 1196/*
1197 * ------------------------------------------------------------
1198 * friends of mxser_ioctl()
1199 * ------------------------------------------------------------
1200 */
1201static int mxser_get_serial_info(struct mxser_port *info,
1202 struct serial_struct __user *retinfo)
037ad48b 1203{
a8dea4ec 1204 struct serial_struct tmp;
037ad48b 1205
a8dea4ec
JS		 1206 if (!retinfo)
1207 return -EFAULT;
1208 memset(&tmp, 0, sizeof(tmp));
1209 tmp.type = info->type;
1210 tmp.line = info->tty->index;
1211 tmp.port = info->ioaddr;
1212 tmp.irq = info->board->irq;
1213 tmp.flags = info->flags;
1214 tmp.baud_base = info->baud_base;
1215 tmp.close_delay = info->close_delay;
1216 tmp.closing_wait = info->closing_wait;
1217 tmp.custom_divisor = info->custom_divisor;
1218 tmp.hub6 = 0;
1219 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1220 return -EFAULT;
1221 return 0;
1222}
037ad48b 1223
a8dea4ec
JS		 1224static int mxser_set_serial_info(struct mxser_port *info,
1225 struct serial_struct __user *new_info)
1226{
1227 struct serial_struct new_serial;
f64c84a1 1228 unsigned long sl_flags;
a8dea4ec
JS		 1229 unsigned int flags;
1230 int retval = 0;
037ad48b 1231
a8dea4ec
JS		 1232 if (!new_info || !info->ioaddr)
1233 return -EFAULT;
1234 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1235 return -EFAULT;
037ad48b 1236
a8dea4ec
JS		 1237 if ((new_serial.irq != info->board->irq) ||
1238 (new_serial.port != info->ioaddr) ||
1239 (new_serial.custom_divisor != info->custom_divisor) ||
1240 (new_serial.baud_base != info->baud_base))
1241 return -EPERM;
037ad48b 1242
a8dea4ec
JS		 1243 flags = info->flags & ASYNC_SPD_MASK;
1244
1245 if (!capable(CAP_SYS_ADMIN)) {
1246 if ((new_serial.baud_base != info->baud_base) ||
1247 (new_serial.close_delay != info->close_delay) ||
1248 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK)))
1249 return -EPERM;
1250 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
1251 (new_serial.flags & ASYNC_USR_MASK));
1252 } else {
037ad48b 1253 /*
a8dea4ec
JS		 1254 * OK, past this point, all the error checking has been done.
1255 * At this point, we start making changes.....
037ad48b 1256 */
a8dea4ec
JS		 1257 info->flags = ((info->flags & ~ASYNC_FLAGS) |
1258 (new_serial.flags & ASYNC_FLAGS));
1259 info->close_delay = new_serial.close_delay * HZ / 100;
1260 info->closing_wait = new_serial.closing_wait * HZ / 100;
1261 info->tty->low_latency =
1262 (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
e079f495 1263 info->tty->low_latency = 0;
a8dea4ec 1264 }
037ad48b 1265
a8dea4ec 1266 info->type = new_serial.type;
037ad48b 1267
a8dea4ec
JS		 1268 process_txrx_fifo(info);
1269
1270 if (info->flags & ASYNC_INITIALIZED) {
f64c84a1
JS		 1271 if (flags != (info->flags & ASYNC_SPD_MASK)) {
1272 spin_lock_irqsave(&info->slock, sl_flags);
a8dea4ec 1273 mxser_change_speed(info, NULL);
f64c84a1
JS		 1274 spin_unlock_irqrestore(&info->slock, sl_flags);
1275 }
a8dea4ec
JS		 1276 } else
1277 retval = mxser_startup(info);
1278
1279 return retval;
1280}
037ad48b 1281
a8dea4ec
JS		 1282/*
1283 * mxser_get_lsr_info - get line status register info
1284 *
1285 * Purpose: Let user call ioctl() to get info when the UART physically
1286 * is emptied. On bus types like RS485, the transmitter must
1287 * release the bus after transmitting. This must be done when
1288 * the transmit shift register is empty, not be done when the
1289 * transmit holding register is empty. This functionality
1290 * allows an RS485 driver to be written in user space.
1291 */
1292static int mxser_get_lsr_info(struct mxser_port *info,
1293 unsigned int __user *value)
1294{
1295 unsigned char status;
1296 unsigned int result;
1297 unsigned long flags;
037ad48b 1298
a8dea4ec
JS		 1299 spin_lock_irqsave(&info->slock, flags);
1300 status = inb(info->ioaddr + UART_LSR);
1301 spin_unlock_irqrestore(&info->slock, flags);
1302 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1303 return put_user(result, value);
1304}
037ad48b 1305
a8dea4ec
JS		 1306/*
1307 * This routine sends a break character out the serial port.
1308 */
1309static void mxser_send_break(struct mxser_port *info, int duration)
1310{
1311 unsigned long flags;
037ad48b 1312
a8dea4ec
JS		 1313 if (!info->ioaddr)
1314 return;
1315 set_current_state(TASK_INTERRUPTIBLE);
1316 spin_lock_irqsave(&info->slock, flags);
1317 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
1318 info->ioaddr + UART_LCR);
1319 spin_unlock_irqrestore(&info->slock, flags);
1320 schedule_timeout(duration);
1321 spin_lock_irqsave(&info->slock, flags);
1322 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
1323 info->ioaddr + UART_LCR);
1324 spin_unlock_irqrestore(&info->slock, flags);
1325}
037ad48b 1326
a8dea4ec
JS		 1327static int mxser_tiocmget(struct tty_struct *tty, struct file *file)
1328{
1329 struct mxser_port *info = tty->driver_data;
1330 unsigned char control, status;
1331 unsigned long flags;
037ad48b 1332
037ad48b 1333
a8dea4ec
JS		 1334 if (tty->index == MXSER_PORTS)
1335 return -ENOIOCTLCMD;
214efebb 1336 if (test_bit(TTY_IO_ERROR, &tty->flags))
a8dea4ec 1337 return -EIO;
037ad48b 1338
a8dea4ec 1339 control = info->MCR;
037ad48b 1340
a8dea4ec
JS		 1341 spin_lock_irqsave(&info->slock, flags);
1342 status = inb(info->ioaddr + UART_MSR);
1343 if (status & UART_MSR_ANY_DELTA)
1344 mxser_check_modem_status(info, status);
1345 spin_unlock_irqrestore(&info->slock, flags);
1346 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1347 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1348 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1349 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1350 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1351 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1352}
037ad48b 1353
a8dea4ec
JS		 1354static int mxser_tiocmset(struct tty_struct *tty, struct file *file,
1355 unsigned int set, unsigned int clear)
1356{
1357 struct mxser_port *info = tty->driver_data;
1358 unsigned long flags;
037ad48b 1359
037ad48b 1360
a8dea4ec
JS		 1361 if (tty->index == MXSER_PORTS)
1362 return -ENOIOCTLCMD;
214efebb 1363 if (test_bit(TTY_IO_ERROR, &tty->flags))
a8dea4ec 1364 return -EIO;
037ad48b 1365
a8dea4ec 1366 spin_lock_irqsave(&info->slock, flags);
037ad48b 1367
a8dea4ec
JS		 1368 if (set & TIOCM_RTS)
1369 info->MCR |= UART_MCR_RTS;
1370 if (set & TIOCM_DTR)
1371 info->MCR |= UART_MCR_DTR;
037ad48b 1372
a8dea4ec
JS		 1373 if (clear & TIOCM_RTS)
1374 info->MCR &= ~UART_MCR_RTS;
1375 if (clear & TIOCM_DTR)
1376 info->MCR &= ~UART_MCR_DTR;
037ad48b 1377
a8dea4ec
JS		 1378 outb(info->MCR, info->ioaddr + UART_MCR);
1379 spin_unlock_irqrestore(&info->slock, flags);
037ad48b
JS		 1380 return 0;
1381}
1382
c76b0930 1383static int __init mxser_program_mode(int port)
037ad48b 1384{
a8dea4ec 1385 int id, i, j, n;
037ad48b 1386
a8dea4ec
JS		 1387 outb(0, port);
1388 outb(0, port);
1389 outb(0, port);
1390 (void)inb(port);
1391 (void)inb(port);
1392 outb(0, port);
1393 (void)inb(port);
037ad48b 1394
a8dea4ec
JS		 1395 id = inb(port + 1) & 0x1F;
1396 if ((id != C168_ASIC_ID) &&
1397 (id != C104_ASIC_ID) &&
1398 (id != C102_ASIC_ID) &&
1399 (id != CI132_ASIC_ID) &&
1400 (id != CI134_ASIC_ID) &&
1401 (id != CI104J_ASIC_ID))
1402 return -1;
1403 for (i = 0, j = 0; i < 4; i++) {
1404 n = inb(port + 2);
1405 if (n == 'M') {
1406 j = 1;
1407 } else if ((j == 1) && (n == 1)) {
1408 j = 2;
1409 break;
1410 } else
1411 j = 0;
1412 }
1413 if (j != 2)
1414 id = -2;
1415 return id;
1416}
1417
c76b0930 1418static void __init mxser_normal_mode(int port)
a8dea4ec
JS		 1419{
1420 int i, n;
1421
1422 outb(0xA5, port + 1);
1423 outb(0x80, port + 3);
1424 outb(12, port + 0); /* 9600 bps */
1425 outb(0, port + 1);
1426 outb(0x03, port + 3); /* 8 data bits */
1427 outb(0x13, port + 4); /* loop back mode */
1428 for (i = 0; i < 16; i++) {
1429 n = inb(port + 5);
1430 if ((n & 0x61) == 0x60)
1431 break;
1432 if ((n & 1) == 1)
1433 (void)inb(port);
1434 }
1435 outb(0x00, port + 4);
1436}
1437
1438#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1439#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1440#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1441#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1442#define EN_CCMD 0x000 /* Chip's command register */
1443#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1444#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1445#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1446#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1447#define EN0_DCFG 0x00E /* Data configuration reg WR */
1448#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1449#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1450#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
c76b0930 1451static int __init mxser_read_register(int port, unsigned short *regs)
a8dea4ec
JS		 1452{
1453 int i, k, value, id;
1454 unsigned int j;
1455
1456 id = mxser_program_mode(port);
1457 if (id < 0)
1458 return id;
1459 for (i = 0; i < 14; i++) {
1460 k = (i & 0x3F) | 0x180;
1461 for (j = 0x100; j > 0; j >>= 1) {
1462 outb(CHIP_CS, port);
1463 if (k & j) {
1464 outb(CHIP_CS | CHIP_DO, port);
1465 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1466 } else {
1467 outb(CHIP_CS, port);
1468 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1469 }
1470 }
1471 (void)inb(port);
1472 value = 0;
1473 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1474 outb(CHIP_CS, port);
1475 outb(CHIP_CS | CHIP_SK, port);
1476 if (inb(port) & CHIP_DI)
1477 value |= j;
1478 }
1479 regs[i] = value;
1480 outb(0, port);
1481 }
1482 mxser_normal_mode(port);
1483 return id;
1484}
1485
a8dea4ec
JS		 1486static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1487{
1488 struct mxser_port *port;
1489 int result, status;
1490 unsigned int i, j;
1491
1492 switch (cmd) {
1493 case MOXA_GET_CONF:
1494/* if (copy_to_user(argp, mxsercfg,
1495 sizeof(struct mxser_hwconf) * 4))
1496 return -EFAULT;
1497 return 0;*/
1498 return -ENXIO;
1499 case MOXA_GET_MAJOR:
1500 if (copy_to_user(argp, &ttymajor, sizeof(int)))
1501 return -EFAULT;
1502 return 0;
1503
1504 case MOXA_GET_CUMAJOR:
1505 if (copy_to_user(argp, &calloutmajor, sizeof(int)))
037ad48b
JS		 1506 return -EFAULT;
1507 return 0;
1508
1509 case MOXA_CHKPORTENABLE:
1510 result = 0;
55b307da
JS		 1511
1512 for (i = 0; i < MXSER_BOARDS; i++)
1513 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1514 if (mxser_boards[i].ports[j].ioaddr)
1515 result |= (1 << i);
1516
037ad48b
JS		 1517 return put_user(result, (unsigned long __user *)argp);
1518 case MOXA_GETDATACOUNT:
1519 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
1520 return -EFAULT;
1521 return 0;
1522 case MOXA_GETMSTATUS:
55b307da
JS		 1523 for (i = 0; i < MXSER_BOARDS; i++)
1524 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1525 port = &mxser_boards[i].ports[j];
1526
1527 GMStatus[i].ri = 0;
1528 if (!port->ioaddr) {
1529 GMStatus[i].dcd = 0;
1530 GMStatus[i].dsr = 0;
1531 GMStatus[i].cts = 0;
1532 continue;
1533 }
037ad48b 1534
55b307da
JS		 1535 if (!port->tty || !port->tty->termios)
1536 GMStatus[i].cflag =
1537 port->normal_termios.c_cflag;
1538 else
1539 GMStatus[i].cflag =
1540 port->tty->termios->c_cflag;
037ad48b 1541
55b307da
JS		 1542 status = inb(port->ioaddr + UART_MSR);
1543 if (status & 0x80 /*UART_MSR_DCD */ )
1544 GMStatus[i].dcd = 1;
1545 else
1546 GMStatus[i].dcd = 0;
037ad48b 1547
55b307da
JS		 1548 if (status & 0x20 /*UART_MSR_DSR */ )
1549 GMStatus[i].dsr = 1;
1550 else
1551 GMStatus[i].dsr = 0;
037ad48b
JS		 1552
1553
55b307da
JS		 1554 if (status & 0x10 /*UART_MSR_CTS */ )
1555 GMStatus[i].cts = 1;
1556 else
1557 GMStatus[i].cts = 0;
1558 }
037ad48b
JS		 1559 if (copy_to_user(argp, GMStatus,
1560 sizeof(struct mxser_mstatus) * MXSER_PORTS))
1561 return -EFAULT;
1562 return 0;
1563 case MOXA_ASPP_MON_EXT: {
55b307da
JS		 1564 int status, p, shiftbit;
1565 unsigned long opmode;
1566 unsigned cflag, iflag;
037ad48b 1567
55b307da
JS		 1568 for (i = 0; i < MXSER_BOARDS; i++)
1569 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1570 port = &mxser_boards[i].ports[j];
1571 if (!port->ioaddr)
037ad48b
JS		 1572 continue;
1573
55b307da 1574 status = mxser_get_msr(port->ioaddr, 0, i);
55b307da 1575
037ad48b 1576 if (status & UART_MSR_TERI)
55b307da 1577 port->icount.rng++;
037ad48b 1578 if (status & UART_MSR_DDSR)
55b307da 1579 port->icount.dsr++;
037ad48b 1580 if (status & UART_MSR_DDCD)
55b307da 1581 port->icount.dcd++;
037ad48b 1582 if (status & UART_MSR_DCTS)
55b307da
JS		 1583 port->icount.cts++;
1584
1585 port->mon_data.modem_status = status;
1586 mon_data_ext.rx_cnt[i] = port->mon_data.rxcnt;
1587 mon_data_ext.tx_cnt[i] = port->mon_data.txcnt;
1588 mon_data_ext.up_rxcnt[i] =
1589 port->mon_data.up_rxcnt;
1590 mon_data_ext.up_txcnt[i] =
1591 port->mon_data.up_txcnt;
1592 mon_data_ext.modem_status[i] =
1593 port->mon_data.modem_status;
1594 mon_data_ext.baudrate[i] = port->realbaud;
1595
1596 if (!port->tty || !port->tty->termios) {
1597 cflag = port->normal_termios.c_cflag;
1598 iflag = port->normal_termios.c_iflag;
037ad48b 1599 } else {
55b307da
JS		 1600 cflag = port->tty->termios->c_cflag;
1601 iflag = port->tty->termios->c_iflag;
037ad48b
JS		 1602 }
1603
1604 mon_data_ext.databits[i] = cflag & CSIZE;
1605
1606 mon_data_ext.stopbits[i] = cflag & CSTOPB;
1607
55b307da
JS		 1608 mon_data_ext.parity[i] =
1609 cflag & (PARENB | PARODD | CMSPAR);
037ad48b
JS		 1610
1611 mon_data_ext.flowctrl[i] = 0x00;
1612
1613 if (cflag & CRTSCTS)
1614 mon_data_ext.flowctrl[i] |= 0x03;
1615
1616 if (iflag & (IXON | IXOFF))
1617 mon_data_ext.flowctrl[i] |= 0x0C;
1618
55b307da 1619 if (port->type == PORT_16550A)
037ad48b
JS		 1620 mon_data_ext.fifo[i] = 1;
1621 else
1622 mon_data_ext.fifo[i] = 0;
1623
1624 p = i % 4;
1625 shiftbit = p * 2;
55b307da 1626 opmode = inb(port->opmode_ioaddr) >> shiftbit;
037ad48b
JS		 1627 opmode &= OP_MODE_MASK;
1628
1629 mon_data_ext.iftype[i] = opmode;
1630
1631 }
55b307da
JS		 1632 if (copy_to_user(argp, &mon_data_ext,
1633 sizeof(mon_data_ext)))
037ad48b
JS		 1634 return -EFAULT;
1635
1636 return 0;
1637
55b307da 1638 } default:
037ad48b
JS		 1639 return -ENOIOCTLCMD;
1640 }
1641 return 0;
1642}
1643
a8dea4ec
JS		 1644static int mxser_ioctl(struct tty_struct *tty, struct file *file,
1645 unsigned int cmd, unsigned long arg)
037ad48b 1646{
55b307da 1647 struct mxser_port *info = tty->driver_data;
a8dea4ec
JS		 1648 struct async_icount cprev, cnow; /* kernel counter temps */
1649 struct serial_icounter_struct __user *p_cuser;
1650 unsigned long templ;
1651 unsigned long flags;
f64c84a1 1652 unsigned int i;
a8dea4ec
JS		 1653 void __user *argp = (void __user *)arg;
1654 int retval;
037ad48b 1655
a8dea4ec
JS		 1656 if (tty->index == MXSER_PORTS)
1657 return mxser_ioctl_special(cmd, argp);
1658
a8dea4ec
JS		 1659 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1660 int p;
1661 unsigned long opmode;
1662 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1663 int shiftbit;
1664 unsigned char val, mask;
1665
1666 p = tty->index % 4;
1667 if (cmd == MOXA_SET_OP_MODE) {
1668 if (get_user(opmode, (int __user *) argp))
1669 return -EFAULT;
1670 if (opmode != RS232_MODE &&
1671 opmode != RS485_2WIRE_MODE &&
1672 opmode != RS422_MODE &&
1673 opmode != RS485_4WIRE_MODE)
1674 return -EFAULT;
1675 mask = ModeMask[p];
1676 shiftbit = p * 2;
1677 val = inb(info->opmode_ioaddr);
1678 val &= mask;
1679 val |= (opmode << shiftbit);
1680 outb(val, info->opmode_ioaddr);
1681 } else {
1682 shiftbit = p * 2;
1683 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1684 opmode &= OP_MODE_MASK;
1685 if (copy_to_user(argp, &opmode, sizeof(int)))
1686 return -EFAULT;
3306ce3d 1687 }
a8dea4ec 1688 return 0;
037ad48b
JS		 1689 }
1690
f64c84a1
JS		 1691 if (cmd == MOXA_SET_SPECIAL_BAUD_RATE) {
1692 int speed;
1693
1694 if (get_user(speed, (int __user *)argp))
1695 return -EFAULT;
1696 if (speed <= 0 || speed > info->max_baud)
1697 return -EFAULT;
1698 if (!info->tty || !info->tty->termios || !info->ioaddr)
1699 return 0;
1700 info->tty->termios->c_cflag &= ~(CBAUD | CBAUDEX);
1701 for (i = 0; i < BAUD_TABLE_NO; i++)
1702 if (speed == mxvar_baud_table[i])
1703 break;
1704 if (i == BAUD_TABLE_NO) {
1705 info->tty->termios->c_cflag |= B_SPEC;
1706 } else if (speed != 0)
1707 info->tty->termios->c_cflag |= mxvar_baud_table1[i];
1708
1709 info->speed = speed;
1710 spin_lock_irqsave(&info->slock, flags);
a136e99f 1711 mxser_change_speed(info, NULL);
f64c84a1
JS		 1712 spin_unlock_irqrestore(&info->slock, flags);
1713
1714 return 0;
1715 } else if (cmd == MOXA_GET_SPECIAL_BAUD_RATE) {
1716 if (copy_to_user(argp, &info->speed, sizeof(int)))
1717 return -EFAULT;
1718 return 0;
1719 }
1720
214efebb
JS		 1721 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT &&
1722 test_bit(TTY_IO_ERROR, &tty->flags))
1723 return -EIO;
1724
a8dea4ec
JS		 1725 switch (cmd) {
1726 case TCSBRK: /* SVID version: non-zero arg --> no break */
1727 retval = tty_check_change(tty);
1728 if (retval)
1729 return retval;
1730 tty_wait_until_sent(tty, 0);
1731 if (!arg)
1732 mxser_send_break(info, HZ / 4); /* 1/4 second */
1733 return 0;
1734 case TCSBRKP: /* support for POSIX tcsendbreak() */
1735 retval = tty_check_change(tty);
1736 if (retval)
1737 return retval;
1738 tty_wait_until_sent(tty, 0);
1739 mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4);
1740 return 0;
1741 case TIOCGSOFTCAR:
1742 return put_user(C_CLOCAL(tty) ? 1 : 0, (unsigned long __user *)argp);
1743 case TIOCSSOFTCAR:
1744 if (get_user(templ, (unsigned long __user *) argp))
1745 return -EFAULT;
1746 arg = templ;
1747 tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0));
1748 return 0;
1749 case TIOCGSERIAL:
1750 return mxser_get_serial_info(info, argp);
1751 case TIOCSSERIAL:
1752 return mxser_set_serial_info(info, argp);
1753 case TIOCSERGETLSR: /* Get line status register */
1754 return mxser_get_lsr_info(info, argp);
1755 /*
1756 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1757 * - mask passed in arg for lines of interest
1758 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1759 * Caller should use TIOCGICOUNT to see which one it was
1760 */
1761 case TIOCMIWAIT: {
1762 DECLARE_WAITQUEUE(wait, current);
1763 int ret;
1764 spin_lock_irqsave(&info->slock, flags);
1765 cprev = info->icount; /* note the counters on entry */
1766 spin_unlock_irqrestore(&info->slock, flags);
037ad48b 1767
a8dea4ec
JS		 1768 add_wait_queue(&info->delta_msr_wait, &wait);
1769 while (1) {
1770 spin_lock_irqsave(&info->slock, flags);
1771 cnow = info->icount; /* atomic copy */
1772 spin_unlock_irqrestore(&info->slock, flags);
037ad48b 1773
a8dea4ec
JS		 1774 set_current_state(TASK_INTERRUPTIBLE);
1775 if (((arg & TIOCM_RNG) &&
1776 (cnow.rng != cprev.rng)) ||
1777 ((arg & TIOCM_DSR) &&
1778 (cnow.dsr != cprev.dsr)) ||
1779 ((arg & TIOCM_CD) &&
1780 (cnow.dcd != cprev.dcd)) ||
1781 ((arg & TIOCM_CTS) &&
1782 (cnow.cts != cprev.cts))) {
1783 ret = 0;
1784 break;
3306ce3d 1785 }
a8dea4ec
JS		 1786 /* see if a signal did it */
1787 if (signal_pending(current)) {
1788 ret = -ERESTARTSYS;
1789 break;
1790 }
1791 cprev = cnow;
037ad48b 1792 }
a8dea4ec
JS		 1793 current->state = TASK_RUNNING;
1794 remove_wait_queue(&info->delta_msr_wait, &wait);
1795 break;
037ad48b 1796 }
a8dea4ec
JS		 1797 /* NOTREACHED */
1798 /*
1799 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1800 * Return: write counters to the user passed counter struct
1801 * NB: both 1->0 and 0->1 transitions are counted except for
1802 * RI where only 0->1 is counted.
1803 */
1804 case TIOCGICOUNT:
1805 spin_lock_irqsave(&info->slock, flags);
1806 cnow = info->icount;
1807 spin_unlock_irqrestore(&info->slock, flags);
1808 p_cuser = argp;
a8dea4ec
JS		 1809 if (put_user(cnow.frame, &p_cuser->frame))
1810 return -EFAULT;
1811 if (put_user(cnow.brk, &p_cuser->brk))
1812 return -EFAULT;
1813 if (put_user(cnow.overrun, &p_cuser->overrun))
1814 return -EFAULT;
1815 if (put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1816 return -EFAULT;
1817 if (put_user(cnow.parity, &p_cuser->parity))
1818 return -EFAULT;
1819 if (put_user(cnow.rx, &p_cuser->rx))
1820 return -EFAULT;
1821 if (put_user(cnow.tx, &p_cuser->tx))
1822 return -EFAULT;
1823 put_user(cnow.cts, &p_cuser->cts);
1824 put_user(cnow.dsr, &p_cuser->dsr);
1825 put_user(cnow.rng, &p_cuser->rng);
1826 put_user(cnow.dcd, &p_cuser->dcd);
1827 return 0;
1828 case MOXA_HighSpeedOn:
1829 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1830 case MOXA_SDS_RSTICOUNTER:
1831 info->mon_data.rxcnt = 0;
1832 info->mon_data.txcnt = 0;
1833 return 0;
a8dea4ec
JS		 1834 case MOXA_ASPP_SETBAUD:{
1835 long baud;
1836 if (get_user(baud, (long __user *)argp))
1837 return -EFAULT;
f64c84a1 1838 spin_lock_irqsave(&info->slock, flags);
a8dea4ec 1839 mxser_set_baud(info, baud);
f64c84a1 1840 spin_unlock_irqrestore(&info->slock, flags);
a8dea4ec
JS		 1841 return 0;
1842 }
1843 case MOXA_ASPP_GETBAUD:
1844 if (copy_to_user(argp, &info->realbaud, sizeof(long)))
1845 return -EFAULT;
037ad48b 1846
a8dea4ec 1847 return 0;
037ad48b 1848
a8dea4ec
JS		 1849 case MOXA_ASPP_OQUEUE:{
1850 int len, lsr;
037ad48b 1851
a8dea4ec
JS		 1852 len = mxser_chars_in_buffer(tty);
1853
1854 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT;
1855
1856 len += (lsr ? 0 : 1);
1857
1858 if (copy_to_user(argp, &len, sizeof(int)))
1859 return -EFAULT;
1860
1861 return 0;
037ad48b 1862 }
a8dea4ec
JS		 1863 case MOXA_ASPP_MON: {
1864 int mcr, status;
037ad48b 1865
a8dea4ec
JS		 1866 status = mxser_get_msr(info->ioaddr, 1, tty->index);
1867 mxser_check_modem_status(info, status);
1868
1869 mcr = inb(info->ioaddr + UART_MCR);
1870 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1871 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1872 else
1873 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1874
1875 if (mcr & MOXA_MUST_MCR_TX_XON)
1876 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1877 else
1878 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1879
1880 if (info->tty->hw_stopped)
1881 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1882 else
1883 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
1884
1885 if (copy_to_user(argp, &info->mon_data,
1886 sizeof(struct mxser_mon)))
1887 return -EFAULT;
1888
1889 return 0;
1890 }
1891 case MOXA_ASPP_LSTATUS: {
1892 if (copy_to_user(argp, &info->err_shadow,
1893 sizeof(unsigned char)))
1894 return -EFAULT;
1895
1896 info->err_shadow = 0;
1897 return 0;
1898 }
1899 case MOXA_SET_BAUD_METHOD: {
1900 int method;
1901
1902 if (get_user(method, (int __user *)argp))
1903 return -EFAULT;
1904 mxser_set_baud_method[tty->index] = method;
1905 if (copy_to_user(argp, &method, sizeof(int)))
1906 return -EFAULT;
1907
1908 return 0;
1909 }
1910 default:
1911 return -ENOIOCTLCMD;
1912 }
1913 return 0;
1914}
1915
1916static void mxser_stoprx(struct tty_struct *tty)
1917{
1918 struct mxser_port *info = tty->driver_data;
037ad48b 1919
a8dea4ec
JS		 1920 info->ldisc_stop_rx = 1;
1921 if (I_IXOFF(tty)) {
55b307da 1922 if (info->board->chip_flag) {
a8dea4ec
JS		 1923 info->IER &= ~MOXA_MUST_RECV_ISR;
1924 outb(info->IER, info->ioaddr + UART_IER);
925e9c1c 1925 } else {
a8dea4ec
JS		 1926 info->x_char = STOP_CHAR(tty);
1927 outb(0, info->ioaddr + UART_IER);
1928 info->IER |= UART_IER_THRI;
1929 outb(info->IER, info->ioaddr + UART_IER);
037ad48b 1930 }
a8dea4ec 1931 }
037ad48b 1932
a8dea4ec
JS		 1933 if (info->tty->termios->c_cflag & CRTSCTS) {
1934 info->MCR &= ~UART_MCR_RTS;
1935 outb(info->MCR, info->ioaddr + UART_MCR);
1936 }
1937}
1938
1939/*
1940 * This routine is called by the upper-layer tty layer to signal that
1941 * incoming characters should be throttled.
1942 */
1943static void mxser_throttle(struct tty_struct *tty)
1944{
1945 mxser_stoprx(tty);
1946}
1947
1948static void mxser_unthrottle(struct tty_struct *tty)
1949{
1950 struct mxser_port *info = tty->driver_data;
1951
1952 /* startrx */
1953 info->ldisc_stop_rx = 0;
1954 if (I_IXOFF(tty)) {
1955 if (info->x_char)
1956 info->x_char = 0;
1957 else {
a8dea4ec
JS		 1958 if (info->board->chip_flag) {
1959 info->IER |= MOXA_MUST_RECV_ISR;
1960 outb(info->IER, info->ioaddr + UART_IER);
925e9c1c 1961 } else {
a8dea4ec
JS		 1962 info->x_char = START_CHAR(tty);
1963 outb(0, info->ioaddr + UART_IER);
1964 info->IER |= UART_IER_THRI;
1965 outb(info->IER, info->ioaddr + UART_IER);
1966 }
1967 }
1968 }
1969
1970 if (info->tty->termios->c_cflag & CRTSCTS) {
1971 info->MCR |= UART_MCR_RTS;
1972 outb(info->MCR, info->ioaddr + UART_MCR);
037ad48b
JS		 1973 }
1974}
1975
1976/*
1977 * mxser_stop() and mxser_start()
1978 *
1979 * This routines are called before setting or resetting tty->stopped.
1980 * They enable or disable transmitter interrupts, as necessary.
1981 */
1982static void mxser_stop(struct tty_struct *tty)
1983{
55b307da 1984 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1985 unsigned long flags;
1986
1987 spin_lock_irqsave(&info->slock, flags);
1988 if (info->IER & UART_IER_THRI) {
1989 info->IER &= ~UART_IER_THRI;
55b307da 1990 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 1991 }
1992 spin_unlock_irqrestore(&info->slock, flags);
1993}
1994
1995static void mxser_start(struct tty_struct *tty)
1996{
55b307da 1997 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 1998 unsigned long flags;
1999
2000 spin_lock_irqsave(&info->slock, flags);
e079f495 2001 if (info->xmit_cnt && info->xmit_buf) {
55b307da 2002 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
037ad48b 2003 info->IER |= UART_IER_THRI;
55b307da 2004 outb(info->IER, info->ioaddr + UART_IER);
037ad48b
JS		 2005 }
2006 spin_unlock_irqrestore(&info->slock, flags);
2007}
2008
606d099c 2009static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
a8dea4ec
JS		 2010{
2011 struct mxser_port *info = tty->driver_data;
2012 unsigned long flags;
2013
2014 if ((tty->termios->c_cflag != old_termios->c_cflag) ||
2015 (RELEVANT_IFLAG(tty->termios->c_iflag) != RELEVANT_IFLAG(old_termios->c_iflag))) {
2016
f64c84a1 2017 spin_lock_irqsave(&info->slock, flags);
a8dea4ec 2018 mxser_change_speed(info, old_termios);
f64c84a1 2019 spin_unlock_irqrestore(&info->slock, flags);
a8dea4ec
JS		 2020
2021 if ((old_termios->c_cflag & CRTSCTS) &&
2022 !(tty->termios->c_cflag & CRTSCTS)) {
2023 tty->hw_stopped = 0;
2024 mxser_start(tty);
2025 }
2026 }
2027
e079f495 2028 /* Handle sw stopped */
a8dea4ec
JS		 2029 if ((old_termios->c_iflag & IXON) &&
2030 !(tty->termios->c_iflag & IXON)) {
2031 tty->stopped = 0;
2032
a8dea4ec
JS		 2033 if (info->board->chip_flag) {
2034 spin_lock_irqsave(&info->slock, flags);
2035 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
2036 spin_unlock_irqrestore(&info->slock, flags);
2037 }
a8dea4ec
JS		 2038
2039 mxser_start(tty);
2040 }
2041}
2042
037ad48b
JS		 2043/*
2044 * mxser_wait_until_sent() --- wait until the transmitter is empty
2045 */
2046static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
2047{
55b307da 2048 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 2049 unsigned long orig_jiffies, char_time;
2050 int lsr;
2051
2052 if (info->type == PORT_UNKNOWN)
2053 return;
2054
2055 if (info->xmit_fifo_size == 0)
2056 return; /* Just in case.... */
2057
2058 orig_jiffies = jiffies;
2059 /*
2060 * Set the check interval to be 1/5 of the estimated time to
2061 * send a single character, and make it at least 1. The check
2062 * interval should also be less than the timeout.
2063 *
2064 * Note: we have to use pretty tight timings here to satisfy
2065 * the NIST-PCTS.
2066 */
2067 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
2068 char_time = char_time / 5;
2069 if (char_time == 0)
2070 char_time = 1;
2071 if (timeout && timeout < char_time)
2072 char_time = timeout;
2073 /*
2074 * If the transmitter hasn't cleared in twice the approximate
2075 * amount of time to send the entire FIFO, it probably won't
2076 * ever clear. This assumes the UART isn't doing flow
2077 * control, which is currently the case. Hence, if it ever
2078 * takes longer than info->timeout, this is probably due to a
2079 * UART bug of some kind. So, we clamp the timeout parameter at
2080 * 2*info->timeout.
2081 */
2082 if (!timeout || timeout > 2 * info->timeout)
2083 timeout = 2 * info->timeout;
2084#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2085 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
2086 timeout, char_time);
2087 printk("jiff=%lu...", jiffies);
2088#endif
55b307da 2089 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
037ad48b
JS		 2090#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2091 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
2092#endif
2093 schedule_timeout_interruptible(char_time);
2094 if (signal_pending(current))
2095 break;
2096 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2097 break;
2098 }
2099 set_current_state(TASK_RUNNING);
2100
2101#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
2102 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
a8dea4ec
JS		 2103#endif
2104}
037ad48b 2105
a8dea4ec
JS		 2106/*
2107 * This routine is called by tty_hangup() when a hangup is signaled.
2108 */
02d3fca0 2109static void mxser_hangup(struct tty_struct *tty)
a8dea4ec
JS		 2110{
2111 struct mxser_port *info = tty->driver_data;
037ad48b 2112
a8dea4ec
JS		 2113 mxser_flush_buffer(tty);
2114 mxser_shutdown(info);
2115 info->event = 0;
2116 info->count = 0;
2117 info->flags &= ~ASYNC_NORMAL_ACTIVE;
2118 info->tty = NULL;
2119 wake_up_interruptible(&info->open_wait);
037ad48b
JS		 2120}
2121
a8dea4ec
JS		 2122/*
2123 * mxser_rs_break() --- routine which turns the break handling on or off
2124 */
2125static void mxser_rs_break(struct tty_struct *tty, int break_state)
037ad48b 2126{
a8dea4ec 2127 struct mxser_port *info = tty->driver_data;
037ad48b
JS		 2128 unsigned long flags;
2129
a8dea4ec
JS		 2130 spin_lock_irqsave(&info->slock, flags);
2131 if (break_state == -1)
2132 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2133 info->ioaddr + UART_LCR);
2134 else
2135 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2136 info->ioaddr + UART_LCR);
2137 spin_unlock_irqrestore(&info->slock, flags);
2138}
037ad48b 2139
a8dea4ec
JS		 2140static void mxser_receive_chars(struct mxser_port *port, int *status)
2141{
2142 struct tty_struct *tty = port->tty;
2143 unsigned char ch, gdl;
2144 int ignored = 0;
2145 int cnt = 0;
2146 int recv_room;
2147 int max = 256;
a8dea4ec
JS		 2148
2149 recv_room = tty->receive_room;
e079f495 2150 if ((recv_room == 0) && (!port->ldisc_stop_rx))
a8dea4ec 2151 mxser_stoprx(tty);
037ad48b 2152
a8dea4ec 2153 if (port->board->chip_flag != MOXA_OTHER_UART) {
037ad48b 2154
a8dea4ec
JS		 2155 if (*status & UART_LSR_SPECIAL)
2156 goto intr_old;
a8dea4ec
JS		 2157 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2158 (*status & MOXA_MUST_LSR_RERR))
2159 goto intr_old;
a8dea4ec
JS		 2160 if (*status & MOXA_MUST_LSR_RERR)
2161 goto intr_old;
2162
2163 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2164
a8dea4ec
JS		 2165 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2166 gdl &= MOXA_MUST_GDL_MASK;
2167 if (gdl >= recv_room) {
e079f495 2168 if (!port->ldisc_stop_rx)
a8dea4ec 2169 mxser_stoprx(tty);
a8dea4ec
JS		 2170 }
2171 while (gdl--) {
2172 ch = inb(port->ioaddr + UART_RX);
2173 tty_insert_flip_char(tty, ch, 0);
2174 cnt++;
2175 }
2176 goto end_intr;
037ad48b 2177 }
e079f495 2178intr_old:
037ad48b 2179
a8dea4ec
JS		 2180 do {
2181 if (max-- < 0)
2182 break;
037ad48b 2183
a8dea4ec 2184 ch = inb(port->ioaddr + UART_RX);
e079f495 2185 if (port->board->chip_flag && (*status & UART_LSR_OE))
a8dea4ec
JS		 2186 outb(0x23, port->ioaddr + UART_FCR);
2187 *status &= port->read_status_mask;
a8dea4ec
JS		 2188 if (*status & port->ignore_status_mask) {
2189 if (++ignored > 100)
2190 break;
2191 } else {
2192 char flag = 0;
2193 if (*status & UART_LSR_SPECIAL) {
2194 if (*status & UART_LSR_BI) {
2195 flag = TTY_BREAK;
a8dea4ec 2196 port->icount.brk++;
037ad48b 2197
a8dea4ec
JS		 2198 if (port->flags & ASYNC_SAK)
2199 do_SAK(tty);
2200 } else if (*status & UART_LSR_PE) {
2201 flag = TTY_PARITY;
a8dea4ec
JS		 2202 port->icount.parity++;
2203 } else if (*status & UART_LSR_FE) {
2204 flag = TTY_FRAME;
a8dea4ec
JS		 2205 port->icount.frame++;
2206 } else if (*status & UART_LSR_OE) {
2207 flag = TTY_OVERRUN;
a8dea4ec 2208 port->icount.overrun++;
f64c84a1
JS		 2209 } else
2210 flag = TTY_BREAK;
925e9c1c 2211 }
a8dea4ec
JS		 2212 tty_insert_flip_char(tty, ch, flag);
2213 cnt++;
2214 if (cnt >= recv_room) {
e079f495 2215 if (!port->ldisc_stop_rx)
a8dea4ec 2216 mxser_stoprx(tty);
a8dea4ec
JS		 2217 break;
2218 }
037ad48b 2219
a8dea4ec 2220 }
037ad48b 2221
a8dea4ec
JS		 2222 if (port->board->chip_flag)
2223 break;
037ad48b 2224
a8dea4ec 2225 *status = inb(port->ioaddr + UART_LSR);
a8dea4ec 2226 } while (*status & UART_LSR_DR);
037ad48b 2227
e079f495 2228end_intr:
a8dea4ec
JS		 2229 mxvar_log.rxcnt[port->tty->index] += cnt;
2230 port->mon_data.rxcnt += cnt;
2231 port->mon_data.up_rxcnt += cnt;
a8dea4ec
JS		 2232
2233 tty_flip_buffer_push(tty);
037ad48b
JS		 2234}
2235
a8dea4ec 2236static void mxser_transmit_chars(struct mxser_port *port)
037ad48b 2237{
a8dea4ec 2238 int count, cnt;
037ad48b 2239
a8dea4ec
JS		 2240 if (port->x_char) {
2241 outb(port->x_char, port->ioaddr + UART_TX);
2242 port->x_char = 0;
2243 mxvar_log.txcnt[port->tty->index]++;
2244 port->mon_data.txcnt++;
2245 port->mon_data.up_txcnt++;
a8dea4ec 2246 port->icount.tx++;
f574874b 2247 return;
037ad48b
JS		 2248 }
2249
a8dea4ec 2250 if (port->xmit_buf == 0)
f574874b 2251 return;
037ad48b 2252
925e9c1c
JS		 2253 if ((port->xmit_cnt <= 0) || port->tty->stopped ||
2254 (port->tty->hw_stopped &&
a8dea4ec
JS		 2255 (port->type != PORT_16550A) &&
2256 (!port->board->chip_flag))) {
2257 port->IER &= ~UART_IER_THRI;
2258 outb(port->IER, port->ioaddr + UART_IER);
f574874b 2259 return;
a8dea4ec 2260 }
037ad48b 2261
a8dea4ec
JS		 2262 cnt = port->xmit_cnt;
2263 count = port->xmit_fifo_size;
2264 do {
2265 outb(port->xmit_buf[port->xmit_tail++],
2266 port->ioaddr + UART_TX);
2267 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2268 if (--port->xmit_cnt <= 0)
2269 break;
2270 } while (--count > 0);
2271 mxvar_log.txcnt[port->tty->index] += (cnt - port->xmit_cnt);
55b307da 2272
a8dea4ec
JS		 2273 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2274 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
a8dea4ec 2275 port->icount.tx += (cnt - port->xmit_cnt);
037ad48b 2276
47c85c0d
JS		 2277 if (port->xmit_cnt < WAKEUP_CHARS)
2278 tty_wakeup(port->tty);
2279
a8dea4ec
JS		 2280 if (port->xmit_cnt <= 0) {
2281 port->IER &= ~UART_IER_THRI;
2282 outb(port->IER, port->ioaddr + UART_IER);
2283 }
037ad48b
JS		 2284}
2285
2286/*
a8dea4ec 2287 * This is the serial driver's generic interrupt routine
037ad48b 2288 */
b1d1c8dd 2289static irqreturn_t mxser_interrupt(int irq, void *dev_id)
037ad48b 2290{
a8dea4ec
JS		 2291 int status, iir, i;
2292 struct mxser_board *brd = NULL;
2293 struct mxser_port *port;
2294 int max, irqbits, bits, msr;
18b95576 2295 unsigned int int_cnt, pass_counter = 0;
a8dea4ec 2296 int handled = IRQ_NONE;
037ad48b 2297
a8dea4ec
JS		 2298 for (i = 0; i < MXSER_BOARDS; i++)
2299 if (dev_id == &mxser_boards[i]) {
2300 brd = dev_id;
2301 break;
2302 }
037ad48b 2303
a8dea4ec
JS		 2304 if (i == MXSER_BOARDS)
2305 goto irq_stop;
2306 if (brd == NULL)
2307 goto irq_stop;
cd7ed64e 2308 max = brd->info->nports;
18b95576 2309 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
a8dea4ec
JS		 2310 irqbits = inb(brd->vector) & brd->vector_mask;
2311 if (irqbits == brd->vector_mask)
2312 break;
037ad48b 2313
a8dea4ec
JS		 2314 handled = IRQ_HANDLED;
2315 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2316 if (irqbits == brd->vector_mask)
2317 break;
2318 if (bits & irqbits)
2319 continue;
2320 port = &brd->ports[i];
037ad48b 2321
a8dea4ec 2322 int_cnt = 0;
f574874b 2323 spin_lock(&port->slock);
a8dea4ec 2324 do {
a8dea4ec
JS		 2325 iir = inb(port->ioaddr + UART_IIR);
2326 if (iir & UART_IIR_NO_INT)
2327 break;
2328 iir &= MOXA_MUST_IIR_MASK;
f574874b
JS		 2329 if (!port->tty ||
2330 (port->flags & ASYNC_CLOSING) ||
2331 !(port->flags &
2332 ASYNC_INITIALIZED)) {
a8dea4ec
JS		 2333 status = inb(port->ioaddr + UART_LSR);
2334 outb(0x27, port->ioaddr + UART_FCR);
2335 inb(port->ioaddr + UART_MSR);
2336 break;
2337 }
037ad48b 2338
a8dea4ec
JS		 2339 status = inb(port->ioaddr + UART_LSR);
2340
2341 if (status & UART_LSR_PE)
2342 port->err_shadow |= NPPI_NOTIFY_PARITY;
2343 if (status & UART_LSR_FE)
2344 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2345 if (status & UART_LSR_OE)
2346 port->err_shadow |=
2347 NPPI_NOTIFY_HW_OVERRUN;
2348 if (status & UART_LSR_BI)
2349 port->err_shadow |= NPPI_NOTIFY_BREAK;
2350
2351 if (port->board->chip_flag) {
a8dea4ec
JS		 2352 if (iir == MOXA_MUST_IIR_GDA ||
2353 iir == MOXA_MUST_IIR_RDA ||
2354 iir == MOXA_MUST_IIR_RTO ||
2355 iir == MOXA_MUST_IIR_LSR)
2356 mxser_receive_chars(port,
2357 &status);
2358
2359 } else {
a8dea4ec
JS		 2360 status &= port->read_status_mask;
2361 if (status & UART_LSR_DR)
2362 mxser_receive_chars(port,
2363 &status);
2364 }
2365 msr = inb(port->ioaddr + UART_MSR);
2366 if (msr & UART_MSR_ANY_DELTA)
2367 mxser_check_modem_status(port, msr);
2368
a8dea4ec
JS		 2369 if (port->board->chip_flag) {
2370 if (iir == 0x02 && (status &
2371 UART_LSR_THRE))
2372 mxser_transmit_chars(port);
2373 } else {
a8dea4ec
JS		 2374 if (status & UART_LSR_THRE)
2375 mxser_transmit_chars(port);
2376 }
2377 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
f574874b 2378 spin_unlock(&port->slock);
a8dea4ec 2379 }
a8dea4ec
JS		 2380 }
2381
e079f495 2382irq_stop:
a8dea4ec 2383 return handled;
037ad48b
JS		 2384}
2385
a8dea4ec
JS		 2386static const struct tty_operations mxser_ops = {
2387 .open = mxser_open,
2388 .close = mxser_close,
2389 .write = mxser_write,
2390 .put_char = mxser_put_char,
2391 .flush_chars = mxser_flush_chars,
2392 .write_room = mxser_write_room,
2393 .chars_in_buffer = mxser_chars_in_buffer,
2394 .flush_buffer = mxser_flush_buffer,
2395 .ioctl = mxser_ioctl,
2396 .throttle = mxser_throttle,
2397 .unthrottle = mxser_unthrottle,
2398 .set_termios = mxser_set_termios,
2399 .stop = mxser_stop,
2400 .start = mxser_start,
2401 .hangup = mxser_hangup,
2402 .break_ctl = mxser_rs_break,
2403 .wait_until_sent = mxser_wait_until_sent,
2404 .tiocmget = mxser_tiocmget,
2405 .tiocmset = mxser_tiocmset,
2406};
2407
2408/*
2409 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2410 */
2411
2094e757
JS		 2412static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev,
2413 unsigned int irq)
171d3a86 2414{
171d3a86
JS		 2415 if (irq)
2416 free_irq(brd->irq, brd);
2417 if (pdev != NULL) { /* PCI */
fb0c9295 2418#ifdef CONFIG_PCI
171d3a86
JS		 2419 pci_release_region(pdev, 2);
2420 pci_release_region(pdev, 3);
fb0c9295 2421#endif
171d3a86 2422 } else {
cd7ed64e 2423 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
171d3a86
JS		 2424 release_region(brd->vector, 1);
2425 }
2426}
2427
2094e757
JS		 2428static int __devinit mxser_initbrd(struct mxser_board *brd,
2429 struct pci_dev *pdev)
037ad48b 2430{
a8dea4ec
JS		 2431 struct mxser_port *info;
2432 unsigned int i;
2433 int retval;
2434
2435 printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud);
2436
cd7ed64e 2437 for (i = 0; i < brd->info->nports; i++) {
a8dea4ec
JS		 2438 info = &brd->ports[i];
2439 info->board = brd;
2440 info->stop_rx = 0;
2441 info->ldisc_stop_rx = 0;
037ad48b 2442
a8dea4ec
JS		 2443 /* Enhance mode enabled here */
2444 if (brd->chip_flag != MOXA_OTHER_UART)
2445 ENABLE_MOXA_MUST_ENCHANCE_MODE(info->ioaddr);
037ad48b 2446
a8dea4ec
JS		 2447 info->flags = ASYNC_SHARE_IRQ;
2448 info->type = brd->uart_type;
037ad48b 2449
a8dea4ec 2450 process_txrx_fifo(info);
037ad48b 2451
a8dea4ec
JS		 2452 info->custom_divisor = info->baud_base * 16;
2453 info->close_delay = 5 * HZ / 10;
2454 info->closing_wait = 30 * HZ;
a8dea4ec
JS		 2455 info->normal_termios = mxvar_sdriver->init_termios;
2456 init_waitqueue_head(&info->open_wait);
a8dea4ec 2457 init_waitqueue_head(&info->delta_msr_wait);
f64c84a1 2458 info->speed = 9600;
a8dea4ec
JS		 2459 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2460 info->err_shadow = 0;
2461 spin_lock_init(&info->slock);
037ad48b 2462
a8dea4ec
JS		 2463 /* before set INT ISR, disable all int */
2464 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2465 info->ioaddr + UART_IER);
2466 }
037ad48b 2467
c493edd1
JS		 2468 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2469 brd);
a8dea4ec
JS		 2470 if (retval) {
2471 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2472 "conflict with another device.\n",
cd7ed64e 2473 brd->info->name, brd->irq);
171d3a86 2474 /* We hold resources, we need to release them. */
2094e757 2475 mxser_release_res(brd, pdev, 0);
a8dea4ec 2476 }
45257fa9 2477 return retval;
037ad48b
JS		 2478}
2479
943f2959 2480static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
037ad48b
JS		 2481{
2482 int id, i, bits;
2483 unsigned short regs[16], irq;
2484 unsigned char scratch, scratch2;
2485
55b307da 2486 brd->chip_flag = MOXA_OTHER_UART;
037ad48b
JS		 2487
2488 id = mxser_read_register(cap, regs);
cd7ed64e
JS		 2489 switch (id) {
2490 case C168_ASIC_ID:
2491 brd->info = &mxser_cards[0];
2492 break;
2493 case C104_ASIC_ID:
2494 brd->info = &mxser_cards[1];
2495 break;
2496 case CI104J_ASIC_ID:
2497 brd->info = &mxser_cards[2];
2498 break;
2499 case C102_ASIC_ID:
2500 brd->info = &mxser_cards[5];
2501 break;
2502 case CI132_ASIC_ID:
2503 brd->info = &mxser_cards[6];
2504 break;
2505 case CI134_ASIC_ID:
2506 brd->info = &mxser_cards[7];
2507 break;
2508 default:
037ad48b 2509 return 0;
cd7ed64e 2510 }
037ad48b
JS		 2511
2512 irq = 0;
cd7ed64e
JS		 2513 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2514 Flag-hack checks if configuration should be read as 2-port here. */
2515 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
037ad48b
JS		 2516 irq = regs[9] & 0xF000;
2517 irq = irq | (irq >> 4);
2518 if (irq != (regs[9] & 0xFF00))
2519 return MXSER_ERR_IRQ_CONFLIT;
cd7ed64e 2520 } else if (brd->info->nports == 4) {
037ad48b
JS		 2521 irq = regs[9] & 0xF000;
2522 irq = irq | (irq >> 4);
2523 irq = irq | (irq >> 8);
2524 if (irq != regs[9])
2525 return MXSER_ERR_IRQ_CONFLIT;
cd7ed64e 2526 } else if (brd->info->nports == 8) {
037ad48b
JS		 2527 irq = regs[9] & 0xF000;
2528 irq = irq | (irq >> 4);
2529 irq = irq | (irq >> 8);
2530 if ((irq != regs[9]) || (irq != regs[10]))
2531 return MXSER_ERR_IRQ_CONFLIT;
2532 }
2533
a8dea4ec
JS		 2534 if (!irq)
2535 return MXSER_ERR_IRQ;
2536 brd->irq = ((int)(irq & 0xF000) >> 12);
2537 for (i = 0; i < 8; i++)
2538 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
2539 if ((regs[12] & 0x80) == 0)
2540 return MXSER_ERR_VECTOR;
2541 brd->vector = (int)regs[11]; /* interrupt vector */
2542 if (id == 1)
2543 brd->vector_mask = 0x00FF;
2544 else
2545 brd->vector_mask = 0x000F;
2546 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2547 if (regs[12] & bits) {
2548 brd->ports[i].baud_base = 921600;
e079f495 2549 brd->ports[i].max_baud = 921600;
a8dea4ec
JS		 2550 } else {
2551 brd->ports[i].baud_base = 115200;
e079f495 2552 brd->ports[i].max_baud = 115200;
a8dea4ec
JS		 2553 }
2554 }
2555 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2556 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2557 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2558 outb(scratch2, cap + UART_LCR);
2559 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2560 scratch = inb(cap + UART_IIR);
2561
2562 if (scratch & 0xC0)
2563 brd->uart_type = PORT_16550A;
2564 else
2565 brd->uart_type = PORT_16450;
cd7ed64e
JS		 2566 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
2567 "mxser(IO)"))
a8dea4ec
JS		 2568 return MXSER_ERR_IOADDR;
2569 if (!request_region(brd->vector, 1, "mxser(vector)")) {
cd7ed64e 2570 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
a8dea4ec
JS		 2571 return MXSER_ERR_VECTOR;
2572 }
cd7ed64e 2573 return brd->info->nports;
a8dea4ec
JS		 2574}
2575
2094e757
JS		 2576static int __devinit mxser_probe(struct pci_dev *pdev,
2577 const struct pci_device_id *ent)
a8dea4ec 2578{
fb0c9295 2579#ifdef CONFIG_PCI
2094e757 2580 struct mxser_board *brd;
a8dea4ec
JS		 2581 unsigned int i, j;
2582 unsigned long ioaddress;
2094e757
JS		 2583 int retval = -EINVAL;
2584
2585 for (i = 0; i < MXSER_BOARDS; i++)
2586 if (mxser_boards[i].info == NULL)
2587 break;
2588
2589 if (i >= MXSER_BOARDS) {
2590 printk(KERN_ERR "Too many Smartio/Industio family boards found "
2591 "(maximum %d), board not configured\n", MXSER_BOARDS);
2592 goto err;
2593 }
2594
2595 brd = &mxser_boards[i];
2596 brd->idx = i * MXSER_PORTS_PER_BOARD;
2597 printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n",
2598 mxser_cards[ent->driver_data].name,
2599 pdev->bus->number, PCI_SLOT(pdev->devfn));
2600
2601 retval = pci_enable_device(pdev);
2602 if (retval) {
2603 printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n");
2604 goto err;
2605 }
a8dea4ec
JS		 2606
2607 /* io address */
a8dea4ec
JS		 2608 ioaddress = pci_resource_start(pdev, 2);
2609 retval = pci_request_region(pdev, 2, "mxser(IO)");
2610 if (retval)
2611 goto err;
2612
2094e757 2613 brd->info = &mxser_cards[ent->driver_data];
cd7ed64e 2614 for (i = 0; i < brd->info->nports; i++)
a8dea4ec
JS		 2615 brd->ports[i].ioaddr = ioaddress + 8 * i;
2616
2617 /* vector */
2618 ioaddress = pci_resource_start(pdev, 3);
2619 retval = pci_request_region(pdev, 3, "mxser(vector)");
2620 if (retval)
2621 goto err_relio;
2622 brd->vector = ioaddress;
2623
2624 /* irq */
2625 brd->irq = pdev->irq;
2626
2627 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2628 brd->uart_type = PORT_16550A;
2629 brd->vector_mask = 0;
2630
cd7ed64e 2631 for (i = 0; i < brd->info->nports; i++) {
a8dea4ec
JS		 2632 for (j = 0; j < UART_INFO_NUM; j++) {
2633 if (Gpci_uart_info[j].type == brd->chip_flag) {
2634 brd->ports[i].max_baud =
2635 Gpci_uart_info[j].max_baud;
2636
2637 /* exception....CP-102 */
cd7ed64e 2638 if (brd->info->flags & MXSER_HIGHBAUD)
a8dea4ec
JS		 2639 brd->ports[i].max_baud = 921600;
2640 break;
2641 }
2642 }
2643 }
2644
2645 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
cd7ed64e 2646 for (i = 0; i < brd->info->nports; i++) {
a8dea4ec
JS		 2647 if (i < 4)
2648 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2649 else
2650 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
2651 }
2652 outb(0, ioaddress + 4); /* default set to RS232 mode */
2653 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
2654 }
2655
cd7ed64e 2656 for (i = 0; i < brd->info->nports; i++) {
a8dea4ec
JS		 2657 brd->vector_mask |= (1 << i);
2658 brd->ports[i].baud_base = 921600;
2659 }
2094e757
JS		 2660
2661 /* mxser_initbrd will hook ISR. */
45257fa9
JS		 2662 retval = mxser_initbrd(brd, pdev);
2663 if (retval)
2664 goto err_null;
2094e757
JS		 2665
2666 for (i = 0; i < brd->info->nports; i++)
2667 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2668
2669 pci_set_drvdata(pdev, brd);
2670
a8dea4ec
JS		 2671 return 0;
2672err_relio:
2673 pci_release_region(pdev, 2);
45257fa9 2674err_null:
2094e757 2675 brd->info = NULL;
a8dea4ec
JS		 2676err:
2677 return retval;
fb0c9295
JS		 2678#else
2679 return -ENODEV;
2680#endif
a8dea4ec
JS		 2681}
2682
2094e757
JS		 2683static void __devexit mxser_remove(struct pci_dev *pdev)
2684{
2685 struct mxser_board *brd = pci_get_drvdata(pdev);
2686 unsigned int i;
2687
2688 for (i = 0; i < brd->info->nports; i++)
2689 tty_unregister_device(mxvar_sdriver, brd->idx + i);
2690
2691 mxser_release_res(brd, pdev, 1);
45257fa9 2692 brd->info = NULL;
2094e757
JS		 2693}
2694
2695static struct pci_driver mxser_driver = {
2696 .name = "mxser",
2697 .id_table = mxser_pcibrds,
2698 .probe = mxser_probe,
2699 .remove = __devexit_p(mxser_remove)
2700};
2701
a8dea4ec
JS		 2702static int __init mxser_module_init(void)
2703{
a8dea4ec 2704 struct mxser_board *brd;
eae4436a
JS		 2705 unsigned long cap;
2706 unsigned int i, m, isaloop;
2094e757 2707 int retval, b;
a8dea4ec
JS		 2708
2709 pr_debug("Loading module mxser ...\n");
2710
2711 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2712 if (!mxvar_sdriver)
2713 return -ENOMEM;
a8dea4ec 2714
a8dea4ec
JS		 2715 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2716 MXSER_VERSION);
2717
2718 /* Initialize the tty_driver structure */
31f87cf4 2719 mxvar_sdriver->owner = THIS_MODULE;
a8dea4ec 2720 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
e930790d 2721 mxvar_sdriver->name = "ttyMI";
a8dea4ec
JS		 2722 mxvar_sdriver->major = ttymajor;
2723 mxvar_sdriver->minor_start = 0;
2724 mxvar_sdriver->num = MXSER_PORTS + 1;
2725 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2726 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2727 mxvar_sdriver->init_termios = tty_std_termios;
2728 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
938ef180 2729 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
a8dea4ec 2730 tty_set_operations(mxvar_sdriver, &mxser_ops);
a8dea4ec 2731
938ef180
JS		 2732 retval = tty_register_driver(mxvar_sdriver);
2733 if (retval) {
2734 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2735 "tty driver !\n");
2736 goto err_put;
2737 }
2738
a8dea4ec
JS		 2739 mxvar_diagflag = 0;
2740
2741 m = 0;
2742 /* Start finding ISA boards here */
eae4436a
JS		 2743 for (isaloop = 0; isaloop < 2; isaloop++)
2744 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
2745 if (!isaloop)
2746 cap = mxserBoardCAP[b]; /* predefined */
2747 else
2748 cap = ioaddr[b]; /* module param */
a8dea4ec 2749
eae4436a
JS		 2750 if (!cap)
2751 continue;
a8dea4ec 2752
eae4436a
JS		 2753 brd = &mxser_boards[m];
2754 retval = mxser_get_ISA_conf(cap, brd);
2755
2756 if (retval != 0)
2757 printk(KERN_INFO "Found MOXA %s board "
2758 "(CAP=0x%x)\n",
cd7ed64e 2759 brd->info->name, ioaddr[b]);
eae4436a
JS		 2760
2761 if (retval <= 0) {
2762 if (retval == MXSER_ERR_IRQ)
2763 printk(KERN_ERR "Invalid interrupt "
2764 "number, board not "
2765 "configured\n");
2766 else if (retval == MXSER_ERR_IRQ_CONFLIT)
2767 printk(KERN_ERR "Invalid interrupt "
2768 "number, board not "
2769 "configured\n");
2770 else if (retval == MXSER_ERR_VECTOR)
2771 printk(KERN_ERR "Invalid interrupt "
2772 "vector, board not "
2773 "configured\n");
2774 else if (retval == MXSER_ERR_IOADDR)
2775 printk(KERN_ERR "Invalid I/O address, "
2776 "board not configured\n");
a8dea4ec 2777
2094e757 2778 brd->info = NULL;
eae4436a
JS		 2779 continue;
2780 }
a8dea4ec 2781
eae4436a 2782 /* mxser_initbrd will hook ISR. */
2094e757
JS		 2783 if (mxser_initbrd(brd, NULL) < 0) {
2784 brd->info = NULL;
a8dea4ec
JS		 2785 continue;
2786 }
2094e757
JS		 2787
2788 brd->idx = m * MXSER_PORTS_PER_BOARD;
cd7ed64e 2789 for (i = 0; i < brd->info->nports; i++)
2094e757
JS		 2790 tty_register_device(mxvar_sdriver, brd->idx + i,
2791 NULL);
938ef180 2792
a8dea4ec 2793 m++;
a8dea4ec 2794 }
037ad48b 2795
2094e757
JS		 2796 retval = pci_register_driver(&mxser_driver);
2797 if (retval) {
2798 printk(KERN_ERR "Can't register pci driver\n");
2799 if (!m) {
2800 retval = -ENODEV;
2801 goto err_unr;
2802 } /* else: we have some ISA cards under control */
037ad48b 2803 }
a8dea4ec
JS		 2804
2805 pr_debug("Done.\n");
2806
938ef180
JS		 2807 return 0;
2808err_unr:
2809 tty_unregister_driver(mxvar_sdriver);
2810err_put:
2811 put_tty_driver(mxvar_sdriver);
a8dea4ec 2812 return retval;
037ad48b
JS		 2813}
2814
a8dea4ec 2815static void __exit mxser_module_exit(void)
037ad48b 2816{
2094e757 2817 unsigned int i, j;
037ad48b 2818
a8dea4ec 2819 pr_debug("Unloading module mxser ...\n");
037ad48b 2820
2094e757
JS		 2821 pci_unregister_driver(&mxser_driver);
2822
2823 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2824 if (mxser_boards[i].info != NULL)
2825 for (j = 0; j < mxser_boards[i].info->nports; j++)
2826 tty_unregister_device(mxvar_sdriver,
2827 mxser_boards[i].idx + j);
ead568c9
JS		 2828 tty_unregister_driver(mxvar_sdriver);
2829 put_tty_driver(mxvar_sdriver);
037ad48b 2830
171d3a86 2831 for (i = 0; i < MXSER_BOARDS; i++)
cd7ed64e 2832 if (mxser_boards[i].info != NULL)
2094e757 2833 mxser_release_res(&mxser_boards[i], NULL, 1);
037ad48b 2834
a8dea4ec 2835 pr_debug("Done.\n");
037ad48b
JS		 2836}
2837
2838module_init(mxser_module_init);
2839module_exit(mxser_module_exit);
Linux kernel - Deliverables
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