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[deliverable/linux.git] / drivers / char / pcmcia / synclink_cs.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/pcmcia/synclink_cs.c
3 *
a7482a2e 4 * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
1da177e4
LT		 5 *
6 * Device driver for Microgate SyncLink PC Card
7 * multiprotocol serial adapter.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * This code is released under the GNU General Public License (GPL)
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
26 * OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30#if defined(__i386__)
31# define BREAKPOINT() asm(" int $3");
32#else
33# define BREAKPOINT() { }
34#endif
35
36#define MAX_DEVICE_COUNT 4
37
1da177e4
LT		 38#include <linux/module.h>
39#include <linux/errno.h>
40#include <linux/signal.h>
41#include <linux/sched.h>
42#include <linux/timer.h>
43#include <linux/time.h>
44#include <linux/interrupt.h>
1da177e4
LT		 45#include <linux/tty.h>
46#include <linux/tty_flip.h>
47#include <linux/serial.h>
48#include <linux/major.h>
49#include <linux/string.h>
50#include <linux/fcntl.h>
51#include <linux/ptrace.h>
52#include <linux/ioport.h>
53#include <linux/mm.h>
87687144 54#include <linux/seq_file.h>
1da177e4
LT		 55#include <linux/slab.h>
56#include <linux/netdevice.h>
57#include <linux/vmalloc.h>
58#include <linux/init.h>
1da177e4
LT		 59#include <linux/delay.h>
60#include <linux/ioctl.h>
3dd1247f 61#include <linux/synclink.h>
1da177e4
LT		 62
63#include <asm/system.h>
64#include <asm/io.h>
65#include <asm/irq.h>
66#include <asm/dma.h>
67#include <linux/bitops.h>
68#include <asm/types.h>
69#include <linux/termios.h>
70#include <linux/workqueue.h>
71#include <linux/hdlc.h>
72
1da177e4
LT		 73#include <pcmcia/cistpl.h>
74#include <pcmcia/cisreg.h>
75#include <pcmcia/ds.h>
76
af69c7f9
PF		 77#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
78#define SYNCLINK_GENERIC_HDLC 1
79#else
80#define SYNCLINK_GENERIC_HDLC 0
1da177e4
LT		 81#endif
82
83#define GET_USER(error,value,addr) error = get_user(value,addr)
84#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
85#define PUT_USER(error,value,addr) error = put_user(value,addr)
86#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
87
88#include <asm/uaccess.h>
89
1da177e4
LT		 90static MGSL_PARAMS default_params = {
91 MGSL_MODE_HDLC, /* unsigned long mode */
92 0, /* unsigned char loopback; */
93 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
94 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
95 0, /* unsigned long clock_speed; */
96 0xff, /* unsigned char addr_filter; */
97 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
98 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
99 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
100 9600, /* unsigned long data_rate; */
101 8, /* unsigned char data_bits; */
102 1, /* unsigned char stop_bits; */
103 ASYNC_PARITY_NONE /* unsigned char parity; */
104};
105
106typedef struct
107{
108 int count;
109 unsigned char status;
110 char data[1];
111} RXBUF;
112
113/* The queue of BH actions to be performed */
114
115#define BH_RECEIVE 1
116#define BH_TRANSMIT 2
117#define BH_STATUS 4
118
119#define IO_PIN_SHUTDOWN_LIMIT 100
120
121#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
122
123struct _input_signal_events {
d12341f9 124 int ri_up;
1da177e4
LT		 125 int ri_down;
126 int dsr_up;
127 int dsr_down;
128 int dcd_up;
129 int dcd_down;
130 int cts_up;
131 int cts_down;
132};
133
134
135/*
136 * Device instance data structure
137 */
d12341f9 138
1da177e4 139typedef struct _mgslpc_info {
eeb46134 140 struct tty_port port;
1da177e4
LT		 141 void *if_ptr; /* General purpose pointer (used by SPPP) */
142 int magic;
1da177e4 143 int line;
d12341f9 144
1da177e4 145 struct mgsl_icount icount;
d12341f9 146
1da177e4
LT		 147 int timeout;
148 int x_char; /* xon/xoff character */
1da177e4 149 unsigned char read_status_mask;
d12341f9 150 unsigned char ignore_status_mask;
1da177e4
LT		 151
152 unsigned char *tx_buf;
153 int tx_put;
154 int tx_get;
155 int tx_count;
156
157 /* circular list of fixed length rx buffers */
158
159 unsigned char *rx_buf; /* memory allocated for all rx buffers */
160 int rx_buf_total_size; /* size of memory allocated for rx buffers */
161 int rx_put; /* index of next empty rx buffer */
162 int rx_get; /* index of next full rx buffer */
163 int rx_buf_size; /* size in bytes of single rx buffer */
164 int rx_buf_count; /* total number of rx buffers */
165 int rx_frame_count; /* number of full rx buffers */
d12341f9 166
1da177e4
LT		 167 wait_queue_head_t status_event_wait_q;
168 wait_queue_head_t event_wait_q;
169 struct timer_list tx_timer; /* HDLC transmit timeout timer */
170 struct _mgslpc_info *next_device; /* device list link */
171
172 unsigned short imra_value;
173 unsigned short imrb_value;
174 unsigned char pim_value;
175
176 spinlock_t lock;
177 struct work_struct task; /* task structure for scheduling bh */
178
179 u32 max_frame_size;
180
181 u32 pending_bh;
182
0fab6de0
JP		 183 bool bh_running;
184 bool bh_requested;
d12341f9 185
1da177e4
LT		 186 int dcd_chkcount; /* check counts to prevent */
187 int cts_chkcount; /* too many IRQs if a signal */
188 int dsr_chkcount; /* is floating */
189 int ri_chkcount;
190
0fab6de0
JP		 191 bool rx_enabled;
192 bool rx_overflow;
1da177e4 193
0fab6de0
JP		 194 bool tx_enabled;
195 bool tx_active;
196 bool tx_aborting;
1da177e4
LT		 197 u32 idle_mode;
198
199 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
200
201 char device_name[25]; /* device instance name */
202
203 unsigned int io_base; /* base I/O address of adapter */
204 unsigned int irq_level;
d12341f9 205
1da177e4
LT		 206 MGSL_PARAMS params; /* communications parameters */
207
208 unsigned char serial_signals; /* current serial signal states */
209
0fab6de0 210 bool irq_occurred; /* for diagnostics use */
1da177e4
LT		 211 char testing_irq;
212 unsigned int init_error; /* startup error (DIAGS) */
213
214 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
0fab6de0 215 bool drop_rts_on_tx_done;
1da177e4
LT		 216
217 struct _input_signal_events input_signal_events;
218
219 /* PCMCIA support */
fd238232 220 struct pcmcia_device *p_dev;
1da177e4
LT		 221 int stop;
222
223 /* SPPP/Cisco HDLC device parts */
224 int netcount;
1da177e4
LT		 225 spinlock_t netlock;
226
af69c7f9 227#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 228 struct net_device *netdev;
229#endif
230
231} MGSLPC_INFO;
232
233#define MGSLPC_MAGIC 0x5402
234
235/*
236 * The size of the serial xmit buffer is 1 page, or 4096 bytes
237 */
238#define TXBUFSIZE 4096
239
d12341f9 240
1da177e4
LT		 241#define CHA 0x00 /* channel A offset */
242#define CHB 0x40 /* channel B offset */
243
244/*
245 * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
246 */
247#undef PVR
248
249#define RXFIFO 0
250#define TXFIFO 0
251#define STAR 0x20
252#define CMDR 0x20
253#define RSTA 0x21
254#define PRE 0x21
255#define MODE 0x22
256#define TIMR 0x23
257#define XAD1 0x24
258#define XAD2 0x25
259#define RAH1 0x26
260#define RAH2 0x27
261#define DAFO 0x27
262#define RAL1 0x28
263#define RFC 0x28
264#define RHCR 0x29
265#define RAL2 0x29
266#define RBCL 0x2a
267#define XBCL 0x2a
268#define RBCH 0x2b
269#define XBCH 0x2b
270#define CCR0 0x2c
271#define CCR1 0x2d
272#define CCR2 0x2e
273#define CCR3 0x2f
274#define VSTR 0x34
275#define BGR 0x34
276#define RLCR 0x35
277#define AML 0x36
278#define AMH 0x37
279#define GIS 0x38
280#define IVA 0x38
281#define IPC 0x39
282#define ISR 0x3a
283#define IMR 0x3a
284#define PVR 0x3c
285#define PIS 0x3d
286#define PIM 0x3d
287#define PCR 0x3e
288#define CCR4 0x3f
d12341f9 289
1da177e4 290// IMR/ISR
d12341f9 291
1da177e4
LT		 292#define IRQ_BREAK_ON BIT15 // rx break detected
293#define IRQ_DATAOVERRUN BIT14 // receive data overflow
294#define IRQ_ALLSENT BIT13 // all sent
295#define IRQ_UNDERRUN BIT12 // transmit data underrun
296#define IRQ_TIMER BIT11 // timer interrupt
297#define IRQ_CTS BIT10 // CTS status change
298#define IRQ_TXREPEAT BIT9 // tx message repeat
299#define IRQ_TXFIFO BIT8 // transmit pool ready
300#define IRQ_RXEOM BIT7 // receive message end
301#define IRQ_EXITHUNT BIT6 // receive frame start
302#define IRQ_RXTIME BIT6 // rx char timeout
303#define IRQ_DCD BIT2 // carrier detect status change
304#define IRQ_OVERRUN BIT1 // receive frame overflow
305#define IRQ_RXFIFO BIT0 // receive pool full
d12341f9 306
1da177e4 307// STAR
d12341f9 308
1da177e4
LT		 309#define XFW BIT6 // transmit FIFO write enable
310#define CEC BIT2 // command executing
311#define CTS BIT1 // CTS state
d12341f9 312
1da177e4
LT		 313#define PVR_DTR BIT0
314#define PVR_DSR BIT1
315#define PVR_RI BIT2
316#define PVR_AUTOCTS BIT3
317#define PVR_RS232 0x20 /* 0010b */
318#define PVR_V35 0xe0 /* 1110b */
319#define PVR_RS422 0x40 /* 0100b */
d12341f9
JG		 320
321/* Register access functions */
322
1da177e4
LT		 323#define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
324#define read_reg(info, reg) inb((info)->io_base + (reg))
325
d12341f9 326#define read_reg16(info, reg) inw((info)->io_base + (reg))
1da177e4 327#define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
d12341f9 328
1da177e4
LT		 329#define set_reg_bits(info, reg, mask) \
330 write_reg(info, (reg), \
d12341f9 331 (unsigned char) (read_reg(info, (reg)) | (mask)))
1da177e4
LT		 332#define clear_reg_bits(info, reg, mask) \
333 write_reg(info, (reg), \
d12341f9 334 (unsigned char) (read_reg(info, (reg)) & ~(mask)))
1da177e4
LT		 335/*
336 * interrupt enable/disable routines
d12341f9
JG		 337 */
338static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 339{
340 if (channel == CHA) {
341 info->imra_value |= mask;
342 write_reg16(info, CHA + IMR, info->imra_value);
343 } else {
344 info->imrb_value |= mask;
345 write_reg16(info, CHB + IMR, info->imrb_value);
346 }
347}
d12341f9 348static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
1da177e4
LT		 349{
350 if (channel == CHA) {
351 info->imra_value &= ~mask;
352 write_reg16(info, CHA + IMR, info->imra_value);
353 } else {
354 info->imrb_value &= ~mask;
355 write_reg16(info, CHB + IMR, info->imrb_value);
356 }
357}
358
359#define port_irq_disable(info, mask) \
360 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
361
362#define port_irq_enable(info, mask) \
363 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
364
365static void rx_start(MGSLPC_INFO *info);
366static void rx_stop(MGSLPC_INFO *info);
367
eeb46134 368static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 369static void tx_stop(MGSLPC_INFO *info);
370static void tx_set_idle(MGSLPC_INFO *info);
371
372static void get_signals(MGSLPC_INFO *info);
373static void set_signals(MGSLPC_INFO *info);
374
375static void reset_device(MGSLPC_INFO *info);
376
377static void hdlc_mode(MGSLPC_INFO *info);
378static void async_mode(MGSLPC_INFO *info);
379
380static void tx_timeout(unsigned long context);
381
eeb46134 382static int carrier_raised(struct tty_port *port);
fcc8ac18 383static void dtr_rts(struct tty_port *port, int onoff);
1da177e4 384
af69c7f9 385#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 386#define dev_to_port(D) (dev_to_hdlc(D)->priv)
387static void hdlcdev_tx_done(MGSLPC_INFO *info);
388static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
389static int hdlcdev_init(MGSLPC_INFO *info);
390static void hdlcdev_exit(MGSLPC_INFO *info);
391#endif
392
393static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
394
0fab6de0
JP		 395static bool register_test(MGSLPC_INFO *info);
396static bool irq_test(MGSLPC_INFO *info);
1da177e4
LT		 397static int adapter_test(MGSLPC_INFO *info);
398
399static int claim_resources(MGSLPC_INFO *info);
400static void release_resources(MGSLPC_INFO *info);
401static void mgslpc_add_device(MGSLPC_INFO *info);
402static void mgslpc_remove_device(MGSLPC_INFO *info);
403
eeb46134 404static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 405static void rx_reset_buffers(MGSLPC_INFO *info);
406static int rx_alloc_buffers(MGSLPC_INFO *info);
407static void rx_free_buffers(MGSLPC_INFO *info);
408
7d12e780 409static irqreturn_t mgslpc_isr(int irq, void *dev_id);
1da177e4
LT		 410
411/*
412 * Bottom half interrupt handlers
413 */
c4028958 414static void bh_handler(struct work_struct *work);
eeb46134 415static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 416static void bh_status(MGSLPC_INFO *info);
417
418/*
419 * ioctl handlers
420 */
421static int tiocmget(struct tty_struct *tty, struct file *file);
422static int tiocmset(struct tty_struct *tty, struct file *file,
423 unsigned int set, unsigned int clear);
424static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
425static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
eeb46134 426static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
1da177e4
LT		 427static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
428static int set_txidle(MGSLPC_INFO *info, int idle_mode);
eeb46134 429static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
1da177e4
LT		 430static int tx_abort(MGSLPC_INFO *info);
431static int set_rxenable(MGSLPC_INFO *info, int enable);
432static int wait_events(MGSLPC_INFO *info, int __user *mask);
433
434static MGSLPC_INFO *mgslpc_device_list = NULL;
435static int mgslpc_device_count = 0;
436
437/*
438 * Set this param to non-zero to load eax with the
439 * .text section address and breakpoint on module load.
440 * This is useful for use with gdb and add-symbol-file command.
441 */
442static int break_on_load=0;
443
444/*
445 * Driver major number, defaults to zero to get auto
446 * assigned major number. May be forced as module parameter.
447 */
448static int ttymajor=0;
449
450static int debug_level = 0;
451static int maxframe[MAX_DEVICE_COUNT] = {0,};
1da177e4
LT		 452
453module_param(break_on_load, bool, 0);
454module_param(ttymajor, int, 0);
455module_param(debug_level, int, 0);
456module_param_array(maxframe, int, NULL, 0);
1da177e4
LT		 457
458MODULE_LICENSE("GPL");
459
460static char *driver_name = "SyncLink PC Card driver";
a7482a2e 461static char *driver_version = "$Revision: 4.34 $";
1da177e4
LT		 462
463static struct tty_driver *serial_driver;
464
465/* number of characters left in xmit buffer before we ask for more */
466#define WAKEUP_CHARS 256
467
eeb46134 468static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
1da177e4
LT		 469static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
470
471/* PCMCIA prototypes */
472
15b99ac1 473static int mgslpc_config(struct pcmcia_device *link);
1da177e4 474static void mgslpc_release(u_long arg);
cc3b4866 475static void mgslpc_detach(struct pcmcia_device *p_dev);
1da177e4 476
1da177e4
LT		 477/*
478 * 1st function defined in .text section. Calling this function in
479 * init_module() followed by a breakpoint allows a remote debugger
480 * (gdb) to get the .text address for the add-symbol-file command.
481 * This allows remote debugging of dynamically loadable modules.
482 */
483static void* mgslpc_get_text_ptr(void)
484{
485 return mgslpc_get_text_ptr;
486}
487
488/**
489 * line discipline callback wrappers
490 *
491 * The wrappers maintain line discipline references
492 * while calling into the line discipline.
493 *
1da177e4
LT		 494 * ldisc_receive_buf - pass receive data to line discipline
495 */
496
1da177e4
LT		 497static void ldisc_receive_buf(struct tty_struct *tty,
498 const __u8 *data, char *flags, int count)
499{
500 struct tty_ldisc *ld;
501 if (!tty)
502 return;
503 ld = tty_ldisc_ref(tty);
504 if (ld) {
a352def2
AC		 505 if (ld->ops->receive_buf)
506 ld->ops->receive_buf(tty, data, flags, count);
1da177e4
LT		 507 tty_ldisc_deref(ld);
508 }
509}
510
eeb46134
AC		 511static const struct tty_port_operations mgslpc_port_ops = {
512 .carrier_raised = carrier_raised,
fcc8ac18 513 .dtr_rts = dtr_rts
eeb46134
AC		 514};
515
15b99ac1 516static int mgslpc_probe(struct pcmcia_device *link)
1da177e4
LT		 517{
518 MGSLPC_INFO *info;
15b99ac1 519 int ret;
fd238232 520
1da177e4
LT		 521 if (debug_level >= DEBUG_LEVEL_INFO)
522 printk("mgslpc_attach\n");
fd238232 523
dd00cc48 524 info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
1da177e4
LT		 525 if (!info) {
526 printk("Error can't allocate device instance data\n");
f8cfa618 527 return -ENOMEM;
1da177e4
LT		 528 }
529
1da177e4 530 info->magic = MGSLPC_MAGIC;
eeb46134
AC		 531 tty_port_init(&info->port);
532 info->port.ops = &mgslpc_port_ops;
c4028958 533 INIT_WORK(&info->task, bh_handler);
1da177e4 534 info->max_frame_size = 4096;
eeb46134
AC		 535 info->port.close_delay = 5*HZ/10;
536 info->port.closing_wait = 30*HZ;
1da177e4
LT		 537 init_waitqueue_head(&info->status_event_wait_q);
538 init_waitqueue_head(&info->event_wait_q);
539 spin_lock_init(&info->lock);
540 spin_lock_init(&info->netlock);
541 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
d12341f9 542 info->idle_mode = HDLC_TXIDLE_FLAGS;
1da177e4
LT		 543 info->imra_value = 0xffff;
544 info->imrb_value = 0xffff;
545 info->pim_value = 0xff;
546
fba395ee 547 info->p_dev = link;
1da177e4 548 link->priv = info;
fd238232 549
fba395ee 550 /* Initialize the struct pcmcia_device structure */
1da177e4 551
15b99ac1
DB		 552 ret = mgslpc_config(link);
553 if (ret)
554 return ret;
1da177e4
LT		 555
556 mgslpc_add_device(info);
557
f8cfa618 558 return 0;
1da177e4
LT		 559}
560
561/* Card has been inserted.
562 */
563
00990e7c 564static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
aaa8cfda 565{
90abdc3b 566 return pcmcia_request_io(p_dev);
aaa8cfda
DB		 567}
568
15b99ac1 569static int mgslpc_config(struct pcmcia_device *link)
1da177e4 570{
1da177e4 571 MGSLPC_INFO *info = link->priv;
cbf624f0 572 int ret;
d12341f9 573
1da177e4
LT		 574 if (debug_level >= DEBUG_LEVEL_INFO)
575 printk("mgslpc_config(0x%p)\n", link);
576
00990e7c
DB		 577 link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
578
cbf624f0
DB		 579 ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
580 if (ret != 0)
581 goto failed;
1da177e4 582
7feabb64
DB		 583 link->config_index = 8;
584 link->config_regs = PRESENT_OPTION;
d12341f9 585
eb14120f 586 ret = pcmcia_request_irq(link, mgslpc_isr);
cbf624f0
DB		 587 if (ret)
588 goto failed;
1ac71e5a 589 ret = pcmcia_enable_device(link);
cbf624f0
DB		 590 if (ret)
591 goto failed;
1da177e4 592
9a017a91 593 info->io_base = link->resource[0]->start;
eb14120f 594 info->irq_level = link->irq;
15b99ac1 595 return 0;
1da177e4 596
cbf624f0 597failed:
1da177e4 598 mgslpc_release((u_long)link);
15b99ac1 599 return -ENODEV;
1da177e4
LT		 600}
601
602/* Card has been removed.
603 * Unregister device and release PCMCIA configuration.
604 * If device is open, postpone until it is closed.
605 */
606static void mgslpc_release(u_long arg)
607{
e2d40963 608 struct pcmcia_device *link = (struct pcmcia_device *)arg;
1da177e4 609
e2d40963
DB		 610 if (debug_level >= DEBUG_LEVEL_INFO)
611 printk("mgslpc_release(0x%p)\n", link);
1da177e4 612
e2d40963 613 pcmcia_disable_device(link);
1da177e4
LT		 614}
615
fba395ee 616static void mgslpc_detach(struct pcmcia_device *link)
1da177e4 617{
e2d40963
DB		 618 if (debug_level >= DEBUG_LEVEL_INFO)
619 printk("mgslpc_detach(0x%p)\n", link);
cc3b4866 620
e2d40963
DB		 621 ((MGSLPC_INFO *)link->priv)->stop = 1;
622 mgslpc_release((u_long)link);
1da177e4 623
e2d40963 624 mgslpc_remove_device((MGSLPC_INFO *)link->priv);
1da177e4
LT		 625}
626
fba395ee 627static int mgslpc_suspend(struct pcmcia_device *link)
98e4c28b 628{
98e4c28b
DB		 629 MGSLPC_INFO *info = link->priv;
630
98e4c28b 631 info->stop = 1;
98e4c28b
DB		 632
633 return 0;
634}
635
fba395ee 636static int mgslpc_resume(struct pcmcia_device *link)
98e4c28b 637{
98e4c28b
DB		 638 MGSLPC_INFO *info = link->priv;
639
98e4c28b
DB		 640 info->stop = 0;
641
642 return 0;
643}
644
645
0fab6de0 646static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
1da177e4
LT		 647 char *name, const char *routine)
648{
649#ifdef MGSLPC_PARANOIA_CHECK
650 static const char *badmagic =
651 "Warning: bad magic number for mgsl struct (%s) in %s\n";
652 static const char *badinfo =
653 "Warning: null mgslpc_info for (%s) in %s\n";
654
655 if (!info) {
656 printk(badinfo, name, routine);
0fab6de0 657 return true;
1da177e4
LT		 658 }
659 if (info->magic != MGSLPC_MAGIC) {
660 printk(badmagic, name, routine);
0fab6de0 661 return true;
1da177e4
LT		 662 }
663#else
664 if (!info)
0fab6de0 665 return true;
1da177e4 666#endif
0fab6de0 667 return false;
1da177e4
LT		 668}
669
670
671#define CMD_RXFIFO BIT7 // release current rx FIFO
672#define CMD_RXRESET BIT6 // receiver reset
673#define CMD_RXFIFO_READ BIT5
674#define CMD_START_TIMER BIT4
675#define CMD_TXFIFO BIT3 // release current tx FIFO
676#define CMD_TXEOM BIT1 // transmit end message
677#define CMD_TXRESET BIT0 // transmit reset
678
0fab6de0 679static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
1da177e4
LT		 680{
681 int i = 0;
d12341f9 682 /* wait for command completion */
1da177e4
LT		 683 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
684 udelay(1);
685 if (i++ == 1000)
0fab6de0 686 return false;
1da177e4 687 }
0fab6de0 688 return true;
1da177e4
LT		 689}
690
d12341f9 691static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
1da177e4
LT		 692{
693 wait_command_complete(info, channel);
694 write_reg(info, (unsigned char) (channel + CMDR), cmd);
695}
696
697static void tx_pause(struct tty_struct *tty)
698{
699 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
700 unsigned long flags;
d12341f9 701
1da177e4
LT		 702 if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
703 return;
704 if (debug_level >= DEBUG_LEVEL_INFO)
d12341f9
JG		 705 printk("tx_pause(%s)\n",info->device_name);
706
1da177e4
LT		 707 spin_lock_irqsave(&info->lock,flags);
708 if (info->tx_enabled)
709 tx_stop(info);
710 spin_unlock_irqrestore(&info->lock,flags);
711}
712
713static void tx_release(struct tty_struct *tty)
714{
715 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
716 unsigned long flags;
d12341f9 717
1da177e4
LT		 718 if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
719 return;
720 if (debug_level >= DEBUG_LEVEL_INFO)
d12341f9
JG		 721 printk("tx_release(%s)\n",info->device_name);
722
1da177e4
LT		 723 spin_lock_irqsave(&info->lock,flags);
724 if (!info->tx_enabled)
eeb46134 725 tx_start(info, tty);
1da177e4
LT		 726 spin_unlock_irqrestore(&info->lock,flags);
727}
728
729/* Return next bottom half action to perform.
730 * or 0 if nothing to do.
731 */
732static int bh_action(MGSLPC_INFO *info)
733{
734 unsigned long flags;
735 int rc = 0;
d12341f9 736
1da177e4
LT		 737 spin_lock_irqsave(&info->lock,flags);
738
739 if (info->pending_bh & BH_RECEIVE) {
740 info->pending_bh &= ~BH_RECEIVE;
741 rc = BH_RECEIVE;
742 } else if (info->pending_bh & BH_TRANSMIT) {
743 info->pending_bh &= ~BH_TRANSMIT;
744 rc = BH_TRANSMIT;
745 } else if (info->pending_bh & BH_STATUS) {
746 info->pending_bh &= ~BH_STATUS;
747 rc = BH_STATUS;
748 }
749
750 if (!rc) {
751 /* Mark BH routine as complete */
0fab6de0
JP		 752 info->bh_running = false;
753 info->bh_requested = false;
1da177e4 754 }
d12341f9 755
1da177e4 756 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 757
1da177e4
LT		 758 return rc;
759}
760
c4028958 761static void bh_handler(struct work_struct *work)
1da177e4 762{
c4028958 763 MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
eeb46134 764 struct tty_struct *tty;
1da177e4
LT		 765 int action;
766
767 if (!info)
768 return;
d12341f9 769
1da177e4
LT		 770 if (debug_level >= DEBUG_LEVEL_BH)
771 printk( "%s(%d):bh_handler(%s) entry\n",
772 __FILE__,__LINE__,info->device_name);
d12341f9 773
0fab6de0 774 info->bh_running = true;
eeb46134 775 tty = tty_port_tty_get(&info->port);
1da177e4
LT		 776
777 while((action = bh_action(info)) != 0) {
d12341f9 778
1da177e4
LT		 779 /* Process work item */
780 if ( debug_level >= DEBUG_LEVEL_BH )
781 printk( "%s(%d):bh_handler() work item action=%d\n",
782 __FILE__,__LINE__,action);
783
784 switch (action) {
d12341f9 785
1da177e4 786 case BH_RECEIVE:
eeb46134 787 while(rx_get_frame(info, tty));
1da177e4
LT		 788 break;
789 case BH_TRANSMIT:
eeb46134 790 bh_transmit(info, tty);
1da177e4
LT		 791 break;
792 case BH_STATUS:
793 bh_status(info);
794 break;
795 default:
796 /* unknown work item ID */
797 printk("Unknown work item ID=%08X!\n", action);
798 break;
799 }
800 }
801
eeb46134 802 tty_kref_put(tty);
1da177e4
LT		 803 if (debug_level >= DEBUG_LEVEL_BH)
804 printk( "%s(%d):bh_handler(%s) exit\n",
805 __FILE__,__LINE__,info->device_name);
806}
807
eeb46134 808static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4 809{
1da177e4
LT		 810 if (debug_level >= DEBUG_LEVEL_BH)
811 printk("bh_transmit() entry on %s\n", info->device_name);
812
b963a844 813 if (tty)
1da177e4 814 tty_wakeup(tty);
1da177e4
LT		 815}
816
cdaad343 817static void bh_status(MGSLPC_INFO *info)
1da177e4
LT		 818{
819 info->ri_chkcount = 0;
820 info->dsr_chkcount = 0;
821 info->dcd_chkcount = 0;
822 info->cts_chkcount = 0;
823}
824
d12341f9 825/* eom: non-zero = end of frame */
1da177e4
LT		 826static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
827{
828 unsigned char data[2];
829 unsigned char fifo_count, read_count, i;
830 RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
831
832 if (debug_level >= DEBUG_LEVEL_ISR)
833 printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
d12341f9 834
1da177e4
LT		 835 if (!info->rx_enabled)
836 return;
837
838 if (info->rx_frame_count >= info->rx_buf_count) {
839 /* no more free buffers */
840 issue_command(info, CHA, CMD_RXRESET);
841 info->pending_bh |= BH_RECEIVE;
0fab6de0 842 info->rx_overflow = true;
1da177e4
LT		 843 info->icount.buf_overrun++;
844 return;
845 }
846
847 if (eom) {
d12341f9 848 /* end of frame, get FIFO count from RBCL register */
1da177e4
LT		 849 if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
850 fifo_count = 32;
851 } else
852 fifo_count = 32;
d12341f9 853
1da177e4
LT		 854 do {
855 if (fifo_count == 1) {
856 read_count = 1;
857 data[0] = read_reg(info, CHA + RXFIFO);
858 } else {
859 read_count = 2;
860 *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
861 }
862 fifo_count -= read_count;
863 if (!fifo_count && eom)
864 buf->status = data[--read_count];
865
866 for (i = 0; i < read_count; i++) {
867 if (buf->count >= info->max_frame_size) {
868 /* frame too large, reset receiver and reset current buffer */
869 issue_command(info, CHA, CMD_RXRESET);
870 buf->count = 0;
871 return;
872 }
873 *(buf->data + buf->count) = data[i];
874 buf->count++;
875 }
876 } while (fifo_count);
877
878 if (eom) {
879 info->pending_bh |= BH_RECEIVE;
880 info->rx_frame_count++;
881 info->rx_put++;
882 if (info->rx_put >= info->rx_buf_count)
883 info->rx_put = 0;
884 }
885 issue_command(info, CHA, CMD_RXFIFO);
886}
887
eeb46134 888static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
1da177e4 889{
33f0f88f 890 unsigned char data, status, flag;
1da177e4 891 int fifo_count;
33f0f88f 892 int work = 0;
1da177e4
LT		 893 struct mgsl_icount *icount = &info->icount;
894
895 if (tcd) {
d12341f9 896 /* early termination, get FIFO count from RBCL register */
1da177e4
LT		 897 fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
898
899 /* Zero fifo count could mean 0 or 32 bytes available.
900 * If BIT5 of STAR is set then at least 1 byte is available.
901 */
902 if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
903 fifo_count = 32;
904 } else
905 fifo_count = 32;
33f0f88f
AC		 906
907 tty_buffer_request_room(tty, fifo_count);
d12341f9 908 /* Flush received async data to receive data buffer. */
1da177e4
LT		 909 while (fifo_count) {
910 data = read_reg(info, CHA + RXFIFO);
911 status = read_reg(info, CHA + RXFIFO);
912 fifo_count -= 2;
913
1da177e4 914 icount->rx++;
33f0f88f 915 flag = TTY_NORMAL;
1da177e4
LT		 916
917 // if no frameing/crc error then save data
918 // BIT7:parity error
919 // BIT6:framing error
920
921 if (status & (BIT7 + BIT6)) {
d12341f9 922 if (status & BIT7)
1da177e4
LT		 923 icount->parity++;
924 else
925 icount->frame++;
926
927 /* discard char if tty control flags say so */
928 if (status & info->ignore_status_mask)
929 continue;
d12341f9 930
1da177e4
LT		 931 status &= info->read_status_mask;
932
933 if (status & BIT7)
33f0f88f 934 flag = TTY_PARITY;
1da177e4 935 else if (status & BIT6)
33f0f88f 936 flag = TTY_FRAME;
1da177e4 937 }
33f0f88f 938 work += tty_insert_flip_char(tty, data, flag);
1da177e4
LT		 939 }
940 issue_command(info, CHA, CMD_RXFIFO);
941
942 if (debug_level >= DEBUG_LEVEL_ISR) {
33f0f88f
AC		 943 printk("%s(%d):rx_ready_async",
944 __FILE__,__LINE__);
1da177e4
LT		 945 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
946 __FILE__,__LINE__,icount->rx,icount->brk,
947 icount->parity,icount->frame,icount->overrun);
948 }
d12341f9 949
33f0f88f 950 if (work)
1da177e4
LT		 951 tty_flip_buffer_push(tty);
952}
953
954
eeb46134 955static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 956{
957 if (!info->tx_active)
958 return;
d12341f9 959
0fab6de0
JP		 960 info->tx_active = false;
961 info->tx_aborting = false;
1da177e4
LT		 962
963 if (info->params.mode == MGSL_MODE_ASYNC)
964 return;
965
966 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9
JG		 967 del_timer(&info->tx_timer);
968
1da177e4
LT		 969 if (info->drop_rts_on_tx_done) {
970 get_signals(info);
971 if (info->serial_signals & SerialSignal_RTS) {
972 info->serial_signals &= ~SerialSignal_RTS;
973 set_signals(info);
974 }
0fab6de0 975 info->drop_rts_on_tx_done = false;
1da177e4
LT		 976 }
977
af69c7f9 978#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 979 if (info->netcount)
980 hdlcdev_tx_done(info);
d12341f9 981 else
1da177e4
LT		 982#endif
983 {
eeb46134 984 if (tty->stopped || tty->hw_stopped) {
1da177e4
LT		 985 tx_stop(info);
986 return;
987 }
988 info->pending_bh |= BH_TRANSMIT;
989 }
990}
991
eeb46134 992static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 993{
994 unsigned char fifo_count = 32;
995 int c;
996
997 if (debug_level >= DEBUG_LEVEL_ISR)
998 printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
999
1000 if (info->params.mode == MGSL_MODE_HDLC) {
1001 if (!info->tx_active)
1002 return;
1003 } else {
eeb46134 1004 if (tty->stopped || tty->hw_stopped) {
1da177e4
LT		 1005 tx_stop(info);
1006 return;
1007 }
1008 if (!info->tx_count)
0fab6de0 1009 info->tx_active = false;
1da177e4
LT		 1010 }
1011
1012 if (!info->tx_count)
1013 return;
1014
1015 while (info->tx_count && fifo_count) {
1016 c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
d12341f9 1017
1da177e4
LT		 1018 if (c == 1) {
1019 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
1020 } else {
1021 write_reg16(info, CHA + TXFIFO,
1022 *((unsigned short*)(info->tx_buf + info->tx_get)));
1023 }
1024 info->tx_count -= c;
1025 info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
1026 fifo_count -= c;
1027 }
1028
1029 if (info->params.mode == MGSL_MODE_ASYNC) {
1030 if (info->tx_count < WAKEUP_CHARS)
1031 info->pending_bh |= BH_TRANSMIT;
1032 issue_command(info, CHA, CMD_TXFIFO);
1033 } else {
1034 if (info->tx_count)
1035 issue_command(info, CHA, CMD_TXFIFO);
1036 else
1037 issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
1038 }
1039}
1040
eeb46134 1041static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1042{
1043 get_signals(info);
1044 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1045 irq_disable(info, CHB, IRQ_CTS);
1046 info->icount.cts++;
1047 if (info->serial_signals & SerialSignal_CTS)
1048 info->input_signal_events.cts_up++;
1049 else
1050 info->input_signal_events.cts_down++;
1051 wake_up_interruptible(&info->status_event_wait_q);
1052 wake_up_interruptible(&info->event_wait_q);
1053
eeb46134
AC		 1054 if (info->port.flags & ASYNC_CTS_FLOW) {
1055 if (tty->hw_stopped) {
1da177e4
LT		 1056 if (info->serial_signals & SerialSignal_CTS) {
1057 if (debug_level >= DEBUG_LEVEL_ISR)
1058 printk("CTS tx start...");
eeb46134
AC		 1059 if (tty)
1060 tty->hw_stopped = 0;
1061 tx_start(info, tty);
1da177e4
LT		 1062 info->pending_bh |= BH_TRANSMIT;
1063 return;
1064 }
1065 } else {
1066 if (!(info->serial_signals & SerialSignal_CTS)) {
1067 if (debug_level >= DEBUG_LEVEL_ISR)
1068 printk("CTS tx stop...");
eeb46134
AC		 1069 if (tty)
1070 tty->hw_stopped = 1;
1da177e4
LT		 1071 tx_stop(info);
1072 }
1073 }
1074 }
1075 info->pending_bh |= BH_STATUS;
1076}
1077
eeb46134 1078static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1079{
1080 get_signals(info);
1081 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1082 irq_disable(info, CHB, IRQ_DCD);
1083 info->icount.dcd++;
1084 if (info->serial_signals & SerialSignal_DCD) {
1085 info->input_signal_events.dcd_up++;
1086 }
1087 else
1088 info->input_signal_events.dcd_down++;
af69c7f9 1089#if SYNCLINK_GENERIC_HDLC
fbeff3c1
KH		 1090 if (info->netcount) {
1091 if (info->serial_signals & SerialSignal_DCD)
1092 netif_carrier_on(info->netdev);
1093 else
1094 netif_carrier_off(info->netdev);
1095 }
1da177e4
LT		 1096#endif
1097 wake_up_interruptible(&info->status_event_wait_q);
1098 wake_up_interruptible(&info->event_wait_q);
1099
eeb46134 1100 if (info->port.flags & ASYNC_CHECK_CD) {
1da177e4
LT		 1101 if (debug_level >= DEBUG_LEVEL_ISR)
1102 printk("%s CD now %s...", info->device_name,
1103 (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
1104 if (info->serial_signals & SerialSignal_DCD)
eeb46134 1105 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1106 else {
1107 if (debug_level >= DEBUG_LEVEL_ISR)
1108 printk("doing serial hangup...");
eeb46134
AC		 1109 if (tty)
1110 tty_hangup(tty);
1da177e4
LT		 1111 }
1112 }
1113 info->pending_bh |= BH_STATUS;
1114}
1115
1116static void dsr_change(MGSLPC_INFO *info)
1117{
1118 get_signals(info);
1119 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1120 port_irq_disable(info, PVR_DSR);
1121 info->icount.dsr++;
1122 if (info->serial_signals & SerialSignal_DSR)
1123 info->input_signal_events.dsr_up++;
1124 else
1125 info->input_signal_events.dsr_down++;
1126 wake_up_interruptible(&info->status_event_wait_q);
1127 wake_up_interruptible(&info->event_wait_q);
1128 info->pending_bh |= BH_STATUS;
1129}
1130
1131static void ri_change(MGSLPC_INFO *info)
1132{
1133 get_signals(info);
1134 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1135 port_irq_disable(info, PVR_RI);
1136 info->icount.rng++;
1137 if (info->serial_signals & SerialSignal_RI)
1138 info->input_signal_events.ri_up++;
1139 else
1140 info->input_signal_events.ri_down++;
1141 wake_up_interruptible(&info->status_event_wait_q);
1142 wake_up_interruptible(&info->event_wait_q);
1143 info->pending_bh |= BH_STATUS;
1144}
1145
1146/* Interrupt service routine entry point.
d12341f9 1147 *
1da177e4 1148 * Arguments:
d12341f9 1149 *
1da177e4
LT		 1150 * irq interrupt number that caused interrupt
1151 * dev_id device ID supplied during interrupt registration
1da177e4 1152 */
a6f97b29 1153static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
1da177e4 1154{
a6f97b29 1155 MGSLPC_INFO *info = dev_id;
eeb46134 1156 struct tty_struct *tty;
1da177e4
LT		 1157 unsigned short isr;
1158 unsigned char gis, pis;
1159 int count=0;
1160
d12341f9 1161 if (debug_level >= DEBUG_LEVEL_ISR)
a6f97b29 1162 printk("mgslpc_isr(%d) entry.\n", info->irq_level);
d12341f9 1163
e2d40963 1164 if (!(info->p_dev->_locked))
1da177e4
LT		 1165 return IRQ_HANDLED;
1166
eeb46134
AC		 1167 tty = tty_port_tty_get(&info->port);
1168
1da177e4
LT		 1169 spin_lock(&info->lock);
1170
1171 while ((gis = read_reg(info, CHA + GIS))) {
d12341f9 1172 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4
LT		 1173 printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
1174
1175 if ((gis & 0x70) || count > 1000) {
1176 printk("synclink_cs:hardware failed or ejected\n");
1177 break;
1178 }
1179 count++;
1180
1181 if (gis & (BIT1 + BIT0)) {
1182 isr = read_reg16(info, CHB + ISR);
1183 if (isr & IRQ_DCD)
eeb46134 1184 dcd_change(info, tty);
1da177e4 1185 if (isr & IRQ_CTS)
eeb46134 1186 cts_change(info, tty);
1da177e4
LT		 1187 }
1188 if (gis & (BIT3 + BIT2))
1189 {
1190 isr = read_reg16(info, CHA + ISR);
1191 if (isr & IRQ_TIMER) {
0fab6de0 1192 info->irq_occurred = true;
1da177e4
LT		 1193 irq_disable(info, CHA, IRQ_TIMER);
1194 }
1195
d12341f9 1196 /* receive IRQs */
1da177e4
LT		 1197 if (isr & IRQ_EXITHUNT) {
1198 info->icount.exithunt++;
1199 wake_up_interruptible(&info->event_wait_q);
1200 }
1201 if (isr & IRQ_BREAK_ON) {
1202 info->icount.brk++;
eeb46134
AC		 1203 if (info->port.flags & ASYNC_SAK)
1204 do_SAK(tty);
1da177e4
LT		 1205 }
1206 if (isr & IRQ_RXTIME) {
1207 issue_command(info, CHA, CMD_RXFIFO_READ);
1208 }
1209 if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
1210 if (info->params.mode == MGSL_MODE_HDLC)
d12341f9 1211 rx_ready_hdlc(info, isr & IRQ_RXEOM);
1da177e4 1212 else
eeb46134 1213 rx_ready_async(info, isr & IRQ_RXEOM, tty);
1da177e4
LT		 1214 }
1215
d12341f9 1216 /* transmit IRQs */
1da177e4
LT		 1217 if (isr & IRQ_UNDERRUN) {
1218 if (info->tx_aborting)
1219 info->icount.txabort++;
1220 else
1221 info->icount.txunder++;
eeb46134 1222 tx_done(info, tty);
1da177e4
LT		 1223 }
1224 else if (isr & IRQ_ALLSENT) {
1225 info->icount.txok++;
eeb46134 1226 tx_done(info, tty);
1da177e4
LT		 1227 }
1228 else if (isr & IRQ_TXFIFO)
eeb46134 1229 tx_ready(info, tty);
1da177e4
LT		 1230 }
1231 if (gis & BIT7) {
1232 pis = read_reg(info, CHA + PIS);
1233 if (pis & BIT1)
1234 dsr_change(info);
1235 if (pis & BIT2)
1236 ri_change(info);
1237 }
1238 }
d12341f9
JG		 1239
1240 /* Request bottom half processing if there's something
1da177e4
LT		 1241 * for it to do and the bh is not already running
1242 */
1243
1244 if (info->pending_bh && !info->bh_running && !info->bh_requested) {
d12341f9 1245 if ( debug_level >= DEBUG_LEVEL_ISR )
1da177e4
LT		 1246 printk("%s(%d):%s queueing bh task.\n",
1247 __FILE__,__LINE__,info->device_name);
1248 schedule_work(&info->task);
0fab6de0 1249 info->bh_requested = true;
1da177e4
LT		 1250 }
1251
1252 spin_unlock(&info->lock);
eeb46134 1253 tty_kref_put(tty);
d12341f9
JG		 1254
1255 if (debug_level >= DEBUG_LEVEL_ISR)
1da177e4 1256 printk("%s(%d):mgslpc_isr(%d)exit.\n",
a6f97b29 1257 __FILE__, __LINE__, info->irq_level);
1da177e4
LT		 1258
1259 return IRQ_HANDLED;
1260}
1261
1262/* Initialize and start device.
1263 */
eeb46134 1264static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1265{
1266 int retval = 0;
d12341f9 1267
1da177e4
LT		 1268 if (debug_level >= DEBUG_LEVEL_INFO)
1269 printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
d12341f9 1270
eeb46134 1271 if (info->port.flags & ASYNC_INITIALIZED)
1da177e4 1272 return 0;
d12341f9 1273
1da177e4
LT		 1274 if (!info->tx_buf) {
1275 /* allocate a page of memory for a transmit buffer */
1276 info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1277 if (!info->tx_buf) {
1278 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1279 __FILE__,__LINE__,info->device_name);
1280 return -ENOMEM;
1281 }
1282 }
1283
1284 info->pending_bh = 0;
d12341f9 1285
a7482a2e
PF		 1286 memset(&info->icount, 0, sizeof(info->icount));
1287
40565f19 1288 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
1da177e4
LT		 1289
1290 /* Allocate and claim adapter resources */
1291 retval = claim_resources(info);
d12341f9 1292
1da177e4
LT		 1293 /* perform existance check and diagnostics */
1294 if ( !retval )
1295 retval = adapter_test(info);
d12341f9 1296
1da177e4 1297 if ( retval ) {
eeb46134
AC		 1298 if (capable(CAP_SYS_ADMIN) && tty)
1299 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4
LT		 1300 release_resources(info);
1301 return retval;
1302 }
1303
1304 /* program hardware for current parameters */
eeb46134 1305 mgslpc_change_params(info, tty);
d12341f9 1306
eeb46134
AC		 1307 if (tty)
1308 clear_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1309
eeb46134 1310 info->port.flags |= ASYNC_INITIALIZED;
d12341f9 1311
1da177e4
LT		 1312 return 0;
1313}
1314
1315/* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
1316 */
eeb46134 1317static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
1da177e4
LT		 1318{
1319 unsigned long flags;
d12341f9 1320
eeb46134 1321 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 1322 return;
1323
1324 if (debug_level >= DEBUG_LEVEL_INFO)
1325 printk("%s(%d):mgslpc_shutdown(%s)\n",
1326 __FILE__,__LINE__, info->device_name );
1327
1328 /* clear status wait queue because status changes */
1329 /* can't happen after shutting down the hardware */
1330 wake_up_interruptible(&info->status_event_wait_q);
1331 wake_up_interruptible(&info->event_wait_q);
1332
40565f19 1333 del_timer_sync(&info->tx_timer);
1da177e4
LT		 1334
1335 if (info->tx_buf) {
1336 free_page((unsigned long) info->tx_buf);
1337 info->tx_buf = NULL;
1338 }
1339
1340 spin_lock_irqsave(&info->lock,flags);
1341
1342 rx_stop(info);
1343 tx_stop(info);
1344
1345 /* TODO:disable interrupts instead of reset to preserve signal states */
1346 reset_device(info);
d12341f9 1347
eeb46134 1348 if (!tty || tty->termios->c_cflag & HUPCL) {
1da177e4
LT		 1349 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1350 set_signals(info);
1351 }
d12341f9 1352
1da177e4
LT		 1353 spin_unlock_irqrestore(&info->lock,flags);
1354
d12341f9
JG		 1355 release_resources(info);
1356
eeb46134
AC		 1357 if (tty)
1358 set_bit(TTY_IO_ERROR, &tty->flags);
1da177e4 1359
eeb46134 1360 info->port.flags &= ~ASYNC_INITIALIZED;
1da177e4
LT		 1361}
1362
eeb46134 1363static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1364{
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&info->lock,flags);
d12341f9 1368
1da177e4
LT		 1369 rx_stop(info);
1370 tx_stop(info);
1371 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1372
1da177e4
LT		 1373 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1374 hdlc_mode(info);
1375 else
1376 async_mode(info);
d12341f9 1377
1da177e4 1378 set_signals(info);
d12341f9 1379
1da177e4
LT		 1380 info->dcd_chkcount = 0;
1381 info->cts_chkcount = 0;
1382 info->ri_chkcount = 0;
1383 info->dsr_chkcount = 0;
1384
1385 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
1386 port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
1387 get_signals(info);
d12341f9 1388
eeb46134 1389 if (info->netcount || (tty && (tty->termios->c_cflag & CREAD)))
1da177e4 1390 rx_start(info);
d12341f9 1391
1da177e4
LT		 1392 spin_unlock_irqrestore(&info->lock,flags);
1393}
1394
1395/* Reconfigure adapter based on new parameters
1396 */
eeb46134 1397static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 1398{
1399 unsigned cflag;
1400 int bits_per_char;
1401
eeb46134 1402 if (!tty || !tty->termios)
1da177e4 1403 return;
d12341f9 1404
1da177e4
LT		 1405 if (debug_level >= DEBUG_LEVEL_INFO)
1406 printk("%s(%d):mgslpc_change_params(%s)\n",
1407 __FILE__,__LINE__, info->device_name );
d12341f9 1408
eeb46134 1409 cflag = tty->termios->c_cflag;
1da177e4
LT		 1410
1411 /* if B0 rate (hangup) specified then negate DTR and RTS */
1412 /* otherwise assert DTR and RTS */
1413 if (cflag & CBAUD)
1414 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1415 else
1416 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
d12341f9 1417
1da177e4 1418 /* byte size and parity */
d12341f9 1419
1da177e4
LT		 1420 switch (cflag & CSIZE) {
1421 case CS5: info->params.data_bits = 5; break;
1422 case CS6: info->params.data_bits = 6; break;
1423 case CS7: info->params.data_bits = 7; break;
1424 case CS8: info->params.data_bits = 8; break;
1425 default: info->params.data_bits = 7; break;
1426 }
d12341f9 1427
1da177e4
LT		 1428 if (cflag & CSTOPB)
1429 info->params.stop_bits = 2;
1430 else
1431 info->params.stop_bits = 1;
1432
1433 info->params.parity = ASYNC_PARITY_NONE;
1434 if (cflag & PARENB) {
1435 if (cflag & PARODD)
1436 info->params.parity = ASYNC_PARITY_ODD;
1437 else
1438 info->params.parity = ASYNC_PARITY_EVEN;
1439#ifdef CMSPAR
1440 if (cflag & CMSPAR)
1441 info->params.parity = ASYNC_PARITY_SPACE;
1442#endif
1443 }
1444
1445 /* calculate number of jiffies to transmit a full
1446 * FIFO (32 bytes) at specified data rate
1447 */
d12341f9 1448 bits_per_char = info->params.data_bits +
1da177e4
LT		 1449 info->params.stop_bits + 1;
1450
1451 /* if port data rate is set to 460800 or less then
1452 * allow tty settings to override, otherwise keep the
1453 * current data rate.
1454 */
1455 if (info->params.data_rate <= 460800) {
eeb46134 1456 info->params.data_rate = tty_get_baud_rate(tty);
1da177e4 1457 }
d12341f9 1458
1da177e4 1459 if ( info->params.data_rate ) {
d12341f9 1460 info->timeout = (32*HZ*bits_per_char) /
1da177e4
LT		 1461 info->params.data_rate;
1462 }
1463 info->timeout += HZ/50; /* Add .02 seconds of slop */
1464
1465 if (cflag & CRTSCTS)
eeb46134 1466 info->port.flags |= ASYNC_CTS_FLOW;
1da177e4 1467 else
eeb46134 1468 info->port.flags &= ~ASYNC_CTS_FLOW;
d12341f9 1469
1da177e4 1470 if (cflag & CLOCAL)
eeb46134 1471 info->port.flags &= ~ASYNC_CHECK_CD;
1da177e4 1472 else
eeb46134 1473 info->port.flags |= ASYNC_CHECK_CD;
1da177e4
LT		 1474
1475 /* process tty input control flags */
d12341f9 1476
1da177e4 1477 info->read_status_mask = 0;
eeb46134 1478 if (I_INPCK(tty))
1da177e4 1479 info->read_status_mask |= BIT7 | BIT6;
eeb46134 1480 if (I_IGNPAR(tty))
1da177e4
LT		 1481 info->ignore_status_mask |= BIT7 | BIT6;
1482
eeb46134 1483 mgslpc_program_hw(info, tty);
1da177e4
LT		 1484}
1485
1486/* Add a character to the transmit buffer
1487 */
d7e752e2 1488static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4
LT		 1489{
1490 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1491 unsigned long flags;
1492
1493 if (debug_level >= DEBUG_LEVEL_INFO) {
1494 printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
1495 __FILE__,__LINE__,ch,info->device_name);
1496 }
1497
1498 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
d7e752e2 1499 return 0;
1da177e4 1500
326f28e9 1501 if (!info->tx_buf)
d7e752e2 1502 return 0;
1da177e4
LT		 1503
1504 spin_lock_irqsave(&info->lock,flags);
d12341f9 1505
1da177e4
LT		 1506 if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
1507 if (info->tx_count < TXBUFSIZE - 1) {
1508 info->tx_buf[info->tx_put++] = ch;
1509 info->tx_put &= TXBUFSIZE-1;
1510 info->tx_count++;
1511 }
1512 }
d12341f9 1513
1da177e4 1514 spin_unlock_irqrestore(&info->lock,flags);
d7e752e2 1515 return 1;
1da177e4
LT		 1516}
1517
1518/* Enable transmitter so remaining characters in the
1519 * transmit buffer are sent.
1520 */
1521static void mgslpc_flush_chars(struct tty_struct *tty)
1522{
1523 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1524 unsigned long flags;
d12341f9 1525
1da177e4
LT		 1526 if (debug_level >= DEBUG_LEVEL_INFO)
1527 printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
1528 __FILE__,__LINE__,info->device_name,info->tx_count);
d12341f9 1529
1da177e4
LT		 1530 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
1531 return;
1532
1533 if (info->tx_count <= 0 || tty->stopped ||
1534 tty->hw_stopped || !info->tx_buf)
1535 return;
1536
1537 if (debug_level >= DEBUG_LEVEL_INFO)
1538 printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
1539 __FILE__,__LINE__,info->device_name);
1540
1541 spin_lock_irqsave(&info->lock,flags);
1542 if (!info->tx_active)
eeb46134 1543 tx_start(info, tty);
1da177e4
LT		 1544 spin_unlock_irqrestore(&info->lock,flags);
1545}
1546
1547/* Send a block of data
d12341f9 1548 *
1da177e4 1549 * Arguments:
d12341f9 1550 *
1da177e4
LT		 1551 * tty pointer to tty information structure
1552 * buf pointer to buffer containing send data
1553 * count size of send data in bytes
d12341f9 1554 *
1da177e4
LT		 1555 * Returns: number of characters written
1556 */
1557static int mgslpc_write(struct tty_struct * tty,
1558 const unsigned char *buf, int count)
1559{
1560 int c, ret = 0;
1561 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1562 unsigned long flags;
d12341f9 1563
1da177e4
LT		 1564 if (debug_level >= DEBUG_LEVEL_INFO)
1565 printk( "%s(%d):mgslpc_write(%s) count=%d\n",
1566 __FILE__,__LINE__,info->device_name,count);
d12341f9 1567
1da177e4 1568 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
326f28e9 1569 !info->tx_buf)
1da177e4
LT		 1570 goto cleanup;
1571
1572 if (info->params.mode == MGSL_MODE_HDLC) {
1573 if (count > TXBUFSIZE) {
1574 ret = -EIO;
1575 goto cleanup;
1576 }
1577 if (info->tx_active)
1578 goto cleanup;
1579 else if (info->tx_count)
1580 goto start;
1581 }
1582
1583 for (;;) {
1584 c = min(count,
1585 min(TXBUFSIZE - info->tx_count - 1,
1586 TXBUFSIZE - info->tx_put));
1587 if (c <= 0)
1588 break;
d12341f9 1589
1da177e4
LT		 1590 memcpy(info->tx_buf + info->tx_put, buf, c);
1591
1592 spin_lock_irqsave(&info->lock,flags);
1593 info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
1594 info->tx_count += c;
1595 spin_unlock_irqrestore(&info->lock,flags);
1596
1597 buf += c;
1598 count -= c;
1599 ret += c;
1600 }
1601start:
1602 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1603 spin_lock_irqsave(&info->lock,flags);
1604 if (!info->tx_active)
eeb46134 1605 tx_start(info, tty);
1da177e4
LT		 1606 spin_unlock_irqrestore(&info->lock,flags);
1607 }
d12341f9 1608cleanup:
1da177e4
LT		 1609 if (debug_level >= DEBUG_LEVEL_INFO)
1610 printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
1611 __FILE__,__LINE__,info->device_name,ret);
1612 return ret;
1613}
1614
1615/* Return the count of free bytes in transmit buffer
1616 */
1617static int mgslpc_write_room(struct tty_struct *tty)
1618{
1619 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1620 int ret;
d12341f9 1621
1da177e4
LT		 1622 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
1623 return 0;
1624
1625 if (info->params.mode == MGSL_MODE_HDLC) {
1626 /* HDLC (frame oriented) mode */
1627 if (info->tx_active)
1628 return 0;
1629 else
1630 return HDLC_MAX_FRAME_SIZE;
1631 } else {
1632 ret = TXBUFSIZE - info->tx_count - 1;
1633 if (ret < 0)
1634 ret = 0;
1635 }
d12341f9 1636
1da177e4
LT		 1637 if (debug_level >= DEBUG_LEVEL_INFO)
1638 printk("%s(%d):mgslpc_write_room(%s)=%d\n",
1639 __FILE__,__LINE__, info->device_name, ret);
1640 return ret;
1641}
1642
1643/* Return the count of bytes in transmit buffer
1644 */
1645static int mgslpc_chars_in_buffer(struct tty_struct *tty)
1646{
1647 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1648 int rc;
d12341f9 1649
1da177e4
LT		 1650 if (debug_level >= DEBUG_LEVEL_INFO)
1651 printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
1652 __FILE__,__LINE__, info->device_name );
d12341f9 1653
1da177e4
LT		 1654 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
1655 return 0;
d12341f9 1656
1da177e4
LT		 1657 if (info->params.mode == MGSL_MODE_HDLC)
1658 rc = info->tx_active ? info->max_frame_size : 0;
1659 else
1660 rc = info->tx_count;
1661
1662 if (debug_level >= DEBUG_LEVEL_INFO)
1663 printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
1664 __FILE__,__LINE__, info->device_name, rc);
d12341f9 1665
1da177e4
LT		 1666 return rc;
1667}
1668
1669/* Discard all data in the send buffer
1670 */
1671static void mgslpc_flush_buffer(struct tty_struct *tty)
1672{
1673 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1674 unsigned long flags;
d12341f9 1675
1da177e4
LT		 1676 if (debug_level >= DEBUG_LEVEL_INFO)
1677 printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
1678 __FILE__,__LINE__, info->device_name );
d12341f9 1679
1da177e4
LT		 1680 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
1681 return;
d12341f9
JG		 1682
1683 spin_lock_irqsave(&info->lock,flags);
1da177e4 1684 info->tx_count = info->tx_put = info->tx_get = 0;
d12341f9 1685 del_timer(&info->tx_timer);
1da177e4
LT		 1686 spin_unlock_irqrestore(&info->lock,flags);
1687
1688 wake_up_interruptible(&tty->write_wait);
1689 tty_wakeup(tty);
1690}
1691
1692/* Send a high-priority XON/XOFF character
1693 */
1694static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
1695{
1696 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1697 unsigned long flags;
1698
1699 if (debug_level >= DEBUG_LEVEL_INFO)
1700 printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
1701 __FILE__,__LINE__, info->device_name, ch );
d12341f9 1702
1da177e4
LT		 1703 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
1704 return;
1705
1706 info->x_char = ch;
1707 if (ch) {
1708 spin_lock_irqsave(&info->lock,flags);
1709 if (!info->tx_enabled)
eeb46134 1710 tx_start(info, tty);
1da177e4
LT		 1711 spin_unlock_irqrestore(&info->lock,flags);
1712 }
1713}
1714
1715/* Signal remote device to throttle send data (our receive data)
1716 */
1717static void mgslpc_throttle(struct tty_struct * tty)
1718{
1719 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1720 unsigned long flags;
d12341f9 1721
1da177e4
LT		 1722 if (debug_level >= DEBUG_LEVEL_INFO)
1723 printk("%s(%d):mgslpc_throttle(%s) entry\n",
1724 __FILE__,__LINE__, info->device_name );
1725
1726 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
1727 return;
d12341f9 1728
1da177e4
LT		 1729 if (I_IXOFF(tty))
1730 mgslpc_send_xchar(tty, STOP_CHAR(tty));
d12341f9 1731
1da177e4
LT		 1732 if (tty->termios->c_cflag & CRTSCTS) {
1733 spin_lock_irqsave(&info->lock,flags);
1734 info->serial_signals &= ~SerialSignal_RTS;
1735 set_signals(info);
1736 spin_unlock_irqrestore(&info->lock,flags);
1737 }
1738}
1739
1740/* Signal remote device to stop throttling send data (our receive data)
1741 */
1742static void mgslpc_unthrottle(struct tty_struct * tty)
1743{
1744 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
1745 unsigned long flags;
d12341f9 1746
1da177e4
LT		 1747 if (debug_level >= DEBUG_LEVEL_INFO)
1748 printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
1749 __FILE__,__LINE__, info->device_name );
1750
1751 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
1752 return;
d12341f9 1753
1da177e4
LT		 1754 if (I_IXOFF(tty)) {
1755 if (info->x_char)
1756 info->x_char = 0;
1757 else
1758 mgslpc_send_xchar(tty, START_CHAR(tty));
1759 }
d12341f9 1760
1da177e4
LT		 1761 if (tty->termios->c_cflag & CRTSCTS) {
1762 spin_lock_irqsave(&info->lock,flags);
1763 info->serial_signals |= SerialSignal_RTS;
1764 set_signals(info);
1765 spin_unlock_irqrestore(&info->lock,flags);
1766 }
1767}
1768
1769/* get the current serial statistics
1770 */
1771static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
1772{
1773 int err;
1774 if (debug_level >= DEBUG_LEVEL_INFO)
1775 printk("get_params(%s)\n", info->device_name);
a7482a2e
PF		 1776 if (!user_icount) {
1777 memset(&info->icount, 0, sizeof(info->icount));
1778 } else {
1779 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
1780 if (err)
1781 return -EFAULT;
1782 }
1da177e4
LT		 1783 return 0;
1784}
1785
1786/* get the current serial parameters
1787 */
1788static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
1789{
1790 int err;
1791 if (debug_level >= DEBUG_LEVEL_INFO)
1792 printk("get_params(%s)\n", info->device_name);
1793 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
1794 if (err)
1795 return -EFAULT;
1796 return 0;
1797}
1798
1799/* set the serial parameters
d12341f9 1800 *
1da177e4 1801 * Arguments:
d12341f9 1802 *
1da177e4
LT		 1803 * info pointer to device instance data
1804 * new_params user buffer containing new serial params
1805 *
1806 * Returns: 0 if success, otherwise error code
1807 */
eeb46134 1808static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
1da177e4
LT		 1809{
1810 unsigned long flags;
1811 MGSL_PARAMS tmp_params;
1812 int err;
d12341f9 1813
1da177e4
LT		 1814 if (debug_level >= DEBUG_LEVEL_INFO)
1815 printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
1816 info->device_name );
1817 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
1818 if (err) {
1819 if ( debug_level >= DEBUG_LEVEL_INFO )
1820 printk( "%s(%d):set_params(%s) user buffer copy failed\n",
1821 __FILE__,__LINE__,info->device_name);
1822 return -EFAULT;
1823 }
d12341f9 1824
1da177e4
LT		 1825 spin_lock_irqsave(&info->lock,flags);
1826 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
1827 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 1828
eeb46134 1829 mgslpc_change_params(info, tty);
d12341f9 1830
1da177e4
LT		 1831 return 0;
1832}
1833
1834static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
1835{
1836 int err;
1837 if (debug_level >= DEBUG_LEVEL_INFO)
1838 printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
1839 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
1840 if (err)
1841 return -EFAULT;
1842 return 0;
1843}
1844
1845static int set_txidle(MGSLPC_INFO * info, int idle_mode)
1846{
1847 unsigned long flags;
1848 if (debug_level >= DEBUG_LEVEL_INFO)
1849 printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
1850 spin_lock_irqsave(&info->lock,flags);
1851 info->idle_mode = idle_mode;
1852 tx_set_idle(info);
1853 spin_unlock_irqrestore(&info->lock,flags);
1854 return 0;
1855}
1856
1857static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
1858{
1859 int err;
1860 if (debug_level >= DEBUG_LEVEL_INFO)
1861 printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
1862 COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
1863 if (err)
1864 return -EFAULT;
1865 return 0;
1866}
1867
1868static int set_interface(MGSLPC_INFO * info, int if_mode)
1869{
1870 unsigned long flags;
1871 unsigned char val;
1872 if (debug_level >= DEBUG_LEVEL_INFO)
1873 printk("set_interface(%s,%d)\n", info->device_name, if_mode);
1874 spin_lock_irqsave(&info->lock,flags);
1875 info->if_mode = if_mode;
1876
1877 val = read_reg(info, PVR) & 0x0f;
1878 switch (info->if_mode)
1879 {
1880 case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
1881 case MGSL_INTERFACE_V35: val |= PVR_V35; break;
1882 case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
1883 }
1884 write_reg(info, PVR, val);
1885
1886 spin_unlock_irqrestore(&info->lock,flags);
1887 return 0;
1888}
1889
eeb46134 1890static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
1da177e4
LT		 1891{
1892 unsigned long flags;
d12341f9 1893
1da177e4
LT		 1894 if (debug_level >= DEBUG_LEVEL_INFO)
1895 printk("set_txenable(%s,%d)\n", info->device_name, enable);
d12341f9 1896
1da177e4
LT		 1897 spin_lock_irqsave(&info->lock,flags);
1898 if (enable) {
1899 if (!info->tx_enabled)
eeb46134 1900 tx_start(info, tty);
1da177e4
LT		 1901 } else {
1902 if (info->tx_enabled)
1903 tx_stop(info);
1904 }
1905 spin_unlock_irqrestore(&info->lock,flags);
1906 return 0;
1907}
1908
1909static int tx_abort(MGSLPC_INFO * info)
1910{
1911 unsigned long flags;
d12341f9 1912
1da177e4
LT		 1913 if (debug_level >= DEBUG_LEVEL_INFO)
1914 printk("tx_abort(%s)\n", info->device_name);
d12341f9 1915
1da177e4
LT		 1916 spin_lock_irqsave(&info->lock,flags);
1917 if (info->tx_active && info->tx_count &&
1918 info->params.mode == MGSL_MODE_HDLC) {
1919 /* clear data count so FIFO is not filled on next IRQ.
1920 * This results in underrun and abort transmission.
1921 */
1922 info->tx_count = info->tx_put = info->tx_get = 0;
0fab6de0 1923 info->tx_aborting = true;
1da177e4
LT		 1924 }
1925 spin_unlock_irqrestore(&info->lock,flags);
1926 return 0;
1927}
1928
1929static int set_rxenable(MGSLPC_INFO * info, int enable)
1930{
1931 unsigned long flags;
d12341f9 1932
1da177e4
LT		 1933 if (debug_level >= DEBUG_LEVEL_INFO)
1934 printk("set_rxenable(%s,%d)\n", info->device_name, enable);
d12341f9 1935
1da177e4
LT		 1936 spin_lock_irqsave(&info->lock,flags);
1937 if (enable) {
1938 if (!info->rx_enabled)
1939 rx_start(info);
1940 } else {
1941 if (info->rx_enabled)
1942 rx_stop(info);
1943 }
1944 spin_unlock_irqrestore(&info->lock,flags);
1945 return 0;
1946}
1947
1948/* wait for specified event to occur
d12341f9 1949 *
1da177e4
LT		 1950 * Arguments: info pointer to device instance data
1951 * mask pointer to bitmask of events to wait for
1952 * Return Value: 0 if successful and bit mask updated with
1953 * of events triggerred,
1954 * otherwise error code
1955 */
1956static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
1957{
1958 unsigned long flags;
1959 int s;
1960 int rc=0;
1961 struct mgsl_icount cprev, cnow;
1962 int events;
1963 int mask;
1964 struct _input_signal_events oldsigs, newsigs;
1965 DECLARE_WAITQUEUE(wait, current);
1966
1967 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
1968 if (rc)
1969 return -EFAULT;
d12341f9 1970
1da177e4
LT		 1971 if (debug_level >= DEBUG_LEVEL_INFO)
1972 printk("wait_events(%s,%d)\n", info->device_name, mask);
1973
1974 spin_lock_irqsave(&info->lock,flags);
1975
1976 /* return immediately if state matches requested events */
1977 get_signals(info);
1978 s = info->serial_signals;
1979 events = mask &
1980 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
1981 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
1982 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
1983 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
1984 if (events) {
1985 spin_unlock_irqrestore(&info->lock,flags);
1986 goto exit;
1987 }
1988
1989 /* save current irq counts */
1990 cprev = info->icount;
1991 oldsigs = info->input_signal_events;
d12341f9 1992
1da177e4
LT		 1993 if ((info->params.mode == MGSL_MODE_HDLC) &&
1994 (mask & MgslEvent_ExitHuntMode))
1995 irq_enable(info, CHA, IRQ_EXITHUNT);
d12341f9 1996
1da177e4
LT		 1997 set_current_state(TASK_INTERRUPTIBLE);
1998 add_wait_queue(&info->event_wait_q, &wait);
d12341f9 1999
1da177e4 2000 spin_unlock_irqrestore(&info->lock,flags);
d12341f9
JG		 2001
2002
1da177e4
LT		 2003 for(;;) {
2004 schedule();
2005 if (signal_pending(current)) {
2006 rc = -ERESTARTSYS;
2007 break;
2008 }
d12341f9 2009
1da177e4
LT		 2010 /* get current irq counts */
2011 spin_lock_irqsave(&info->lock,flags);
2012 cnow = info->icount;
2013 newsigs = info->input_signal_events;
2014 set_current_state(TASK_INTERRUPTIBLE);
2015 spin_unlock_irqrestore(&info->lock,flags);
2016
2017 /* if no change, wait aborted for some reason */
2018 if (newsigs.dsr_up == oldsigs.dsr_up &&
2019 newsigs.dsr_down == oldsigs.dsr_down &&
2020 newsigs.dcd_up == oldsigs.dcd_up &&
2021 newsigs.dcd_down == oldsigs.dcd_down &&
2022 newsigs.cts_up == oldsigs.cts_up &&
2023 newsigs.cts_down == oldsigs.cts_down &&
2024 newsigs.ri_up == oldsigs.ri_up &&
2025 newsigs.ri_down == oldsigs.ri_down &&
2026 cnow.exithunt == cprev.exithunt &&
2027 cnow.rxidle == cprev.rxidle) {
2028 rc = -EIO;
2029 break;
2030 }
2031
2032 events = mask &
2033 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2034 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2035 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2036 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2037 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2038 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2039 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2040 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2041 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2042 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2043 if (events)
2044 break;
d12341f9 2045
1da177e4
LT		 2046 cprev = cnow;
2047 oldsigs = newsigs;
2048 }
d12341f9 2049
1da177e4
LT		 2050 remove_wait_queue(&info->event_wait_q, &wait);
2051 set_current_state(TASK_RUNNING);
2052
2053 if (mask & MgslEvent_ExitHuntMode) {
2054 spin_lock_irqsave(&info->lock,flags);
2055 if (!waitqueue_active(&info->event_wait_q))
2056 irq_disable(info, CHA, IRQ_EXITHUNT);
2057 spin_unlock_irqrestore(&info->lock,flags);
2058 }
2059exit:
2060 if (rc == 0)
2061 PUT_USER(rc, events, mask_ptr);
2062 return rc;
2063}
2064
2065static int modem_input_wait(MGSLPC_INFO *info,int arg)
2066{
2067 unsigned long flags;
2068 int rc;
2069 struct mgsl_icount cprev, cnow;
2070 DECLARE_WAITQUEUE(wait, current);
2071
2072 /* save current irq counts */
2073 spin_lock_irqsave(&info->lock,flags);
2074 cprev = info->icount;
2075 add_wait_queue(&info->status_event_wait_q, &wait);
2076 set_current_state(TASK_INTERRUPTIBLE);
2077 spin_unlock_irqrestore(&info->lock,flags);
2078
2079 for(;;) {
2080 schedule();
2081 if (signal_pending(current)) {
2082 rc = -ERESTARTSYS;
2083 break;
2084 }
2085
2086 /* get new irq counts */
2087 spin_lock_irqsave(&info->lock,flags);
2088 cnow = info->icount;
2089 set_current_state(TASK_INTERRUPTIBLE);
2090 spin_unlock_irqrestore(&info->lock,flags);
2091
2092 /* if no change, wait aborted for some reason */
2093 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2094 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2095 rc = -EIO;
2096 break;
2097 }
2098
2099 /* check for change in caller specified modem input */
2100 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2101 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2102 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2103 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2104 rc = 0;
2105 break;
2106 }
2107
2108 cprev = cnow;
2109 }
2110 remove_wait_queue(&info->status_event_wait_q, &wait);
2111 set_current_state(TASK_RUNNING);
2112 return rc;
2113}
2114
2115/* return the state of the serial control and status signals
2116 */
2117static int tiocmget(struct tty_struct *tty, struct file *file)
2118{
2119 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2120 unsigned int result;
2121 unsigned long flags;
2122
2123 spin_lock_irqsave(&info->lock,flags);
2124 get_signals(info);
2125 spin_unlock_irqrestore(&info->lock,flags);
2126
2127 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2128 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2129 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2130 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2131 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2132 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2133
2134 if (debug_level >= DEBUG_LEVEL_INFO)
2135 printk("%s(%d):%s tiocmget() value=%08X\n",
2136 __FILE__,__LINE__, info->device_name, result );
2137 return result;
2138}
2139
2140/* set modem control signals (DTR/RTS)
2141 */
2142static int tiocmset(struct tty_struct *tty, struct file *file,
2143 unsigned int set, unsigned int clear)
2144{
2145 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2146 unsigned long flags;
2147
2148 if (debug_level >= DEBUG_LEVEL_INFO)
2149 printk("%s(%d):%s tiocmset(%x,%x)\n",
2150 __FILE__,__LINE__,info->device_name, set, clear);
2151
2152 if (set & TIOCM_RTS)
2153 info->serial_signals |= SerialSignal_RTS;
2154 if (set & TIOCM_DTR)
2155 info->serial_signals |= SerialSignal_DTR;
2156 if (clear & TIOCM_RTS)
2157 info->serial_signals &= ~SerialSignal_RTS;
2158 if (clear & TIOCM_DTR)
2159 info->serial_signals &= ~SerialSignal_DTR;
2160
2161 spin_lock_irqsave(&info->lock,flags);
2162 set_signals(info);
2163 spin_unlock_irqrestore(&info->lock,flags);
2164
2165 return 0;
2166}
2167
2168/* Set or clear transmit break condition
2169 *
2170 * Arguments: tty pointer to tty instance data
2171 * break_state -1=set break condition, 0=clear
2172 */
9e98966c 2173static int mgslpc_break(struct tty_struct *tty, int break_state)
1da177e4
LT		 2174{
2175 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2176 unsigned long flags;
d12341f9 2177
1da177e4
LT		 2178 if (debug_level >= DEBUG_LEVEL_INFO)
2179 printk("%s(%d):mgslpc_break(%s,%d)\n",
2180 __FILE__,__LINE__, info->device_name, break_state);
d12341f9 2181
1da177e4 2182 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
9e98966c 2183 return -EINVAL;
1da177e4
LT		 2184
2185 spin_lock_irqsave(&info->lock,flags);
2186 if (break_state == -1)
2187 set_reg_bits(info, CHA+DAFO, BIT6);
d12341f9 2188 else
1da177e4
LT		 2189 clear_reg_bits(info, CHA+DAFO, BIT6);
2190 spin_unlock_irqrestore(&info->lock,flags);
9e98966c 2191 return 0;
1da177e4
LT		 2192}
2193
0587102c
AC		 2194static int mgslpc_get_icount(struct tty_struct *tty,
2195 struct serial_icounter_struct *icount)
2196{
2197 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2198 struct mgsl_icount cnow; /* kernel counter temps */
2199 unsigned long flags;
2200
2201 spin_lock_irqsave(&info->lock,flags);
2202 cnow = info->icount;
2203 spin_unlock_irqrestore(&info->lock,flags);
2204
2205 icount->cts = cnow.cts;
2206 icount->dsr = cnow.dsr;
2207 icount->rng = cnow.rng;
2208 icount->dcd = cnow.dcd;
2209 icount->rx = cnow.rx;
2210 icount->tx = cnow.tx;
2211 icount->frame = cnow.frame;
2212 icount->overrun = cnow.overrun;
2213 icount->parity = cnow.parity;
2214 icount->brk = cnow.brk;
2215 icount->buf_overrun = cnow.buf_overrun;
2216
2217 return 0;
2218}
2219
1da177e4 2220/* Service an IOCTL request
d12341f9 2221 *
1da177e4 2222 * Arguments:
d12341f9 2223 *
1da177e4
LT		 2224 * tty pointer to tty instance data
2225 * file pointer to associated file object for device
2226 * cmd IOCTL command code
2227 * arg command argument/context
d12341f9 2228 *
1da177e4
LT		 2229 * Return Value: 0 if success, otherwise error code
2230 */
2231static int mgslpc_ioctl(struct tty_struct *tty, struct file * file,
2232 unsigned int cmd, unsigned long arg)
2233{
2234 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2235 void __user *argp = (void __user *)arg;
d12341f9 2236
1da177e4
LT		 2237 if (debug_level >= DEBUG_LEVEL_INFO)
2238 printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2239 info->device_name, cmd );
d12341f9 2240
1da177e4
LT		 2241 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
2242 return -ENODEV;
2243
2244 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
0587102c 2245 (cmd != TIOCMIWAIT)) {
1da177e4
LT		 2246 if (tty->flags & (1 << TTY_IO_ERROR))
2247 return -EIO;
2248 }
2249
1da177e4
LT		 2250 switch (cmd) {
2251 case MGSL_IOCGPARAMS:
2252 return get_params(info, argp);
2253 case MGSL_IOCSPARAMS:
eeb46134 2254 return set_params(info, argp, tty);
1da177e4
LT		 2255 case MGSL_IOCGTXIDLE:
2256 return get_txidle(info, argp);
2257 case MGSL_IOCSTXIDLE:
2258 return set_txidle(info, (int)arg);
2259 case MGSL_IOCGIF:
2260 return get_interface(info, argp);
2261 case MGSL_IOCSIF:
2262 return set_interface(info,(int)arg);
2263 case MGSL_IOCTXENABLE:
eeb46134 2264 return set_txenable(info,(int)arg, tty);
1da177e4
LT		 2265 case MGSL_IOCRXENABLE:
2266 return set_rxenable(info,(int)arg);
2267 case MGSL_IOCTXABORT:
2268 return tx_abort(info);
2269 case MGSL_IOCGSTATS:
2270 return get_stats(info, argp);
2271 case MGSL_IOCWAITEVENT:
2272 return wait_events(info, argp);
2273 case TIOCMIWAIT:
2274 return modem_input_wait(info,(int)arg);
1da177e4
LT		 2275 default:
2276 return -ENOIOCTLCMD;
2277 }
2278 return 0;
2279}
2280
2281/* Set new termios settings
d12341f9 2282 *
1da177e4 2283 * Arguments:
d12341f9 2284 *
1da177e4
LT		 2285 * tty pointer to tty structure
2286 * termios pointer to buffer to hold returned old termios
2287 */
606d099c 2288static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 2289{
2290 MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
2291 unsigned long flags;
d12341f9 2292
1da177e4
LT		 2293 if (debug_level >= DEBUG_LEVEL_INFO)
2294 printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
2295 tty->driver->name );
d12341f9 2296
1da177e4
LT		 2297 /* just return if nothing has changed */
2298 if ((tty->termios->c_cflag == old_termios->c_cflag)
d12341f9 2299 && (RELEVANT_IFLAG(tty->termios->c_iflag)
1da177e4
LT		 2300 == RELEVANT_IFLAG(old_termios->c_iflag)))
2301 return;
2302
eeb46134 2303 mgslpc_change_params(info, tty);
1da177e4
LT		 2304
2305 /* Handle transition to B0 status */
2306 if (old_termios->c_cflag & CBAUD &&
2307 !(tty->termios->c_cflag & CBAUD)) {
2308 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2309 spin_lock_irqsave(&info->lock,flags);
2310 set_signals(info);
2311 spin_unlock_irqrestore(&info->lock,flags);
2312 }
d12341f9 2313
1da177e4
LT		 2314 /* Handle transition away from B0 status */
2315 if (!(old_termios->c_cflag & CBAUD) &&
2316 tty->termios->c_cflag & CBAUD) {
2317 info->serial_signals |= SerialSignal_DTR;
d12341f9 2318 if (!(tty->termios->c_cflag & CRTSCTS) ||
1da177e4
LT		 2319 !test_bit(TTY_THROTTLED, &tty->flags)) {
2320 info->serial_signals |= SerialSignal_RTS;
2321 }
2322 spin_lock_irqsave(&info->lock,flags);
2323 set_signals(info);
2324 spin_unlock_irqrestore(&info->lock,flags);
2325 }
d12341f9 2326
1da177e4
LT		 2327 /* Handle turning off CRTSCTS */
2328 if (old_termios->c_cflag & CRTSCTS &&
2329 !(tty->termios->c_cflag & CRTSCTS)) {
2330 tty->hw_stopped = 0;
2331 tx_release(tty);
2332 }
2333}
2334
2335static void mgslpc_close(struct tty_struct *tty, struct file * filp)
2336{
2337 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
eeb46134 2338 struct tty_port *port = &info->port;
1da177e4
LT		 2339
2340 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
2341 return;
d12341f9 2342
1da177e4
LT		 2343 if (debug_level >= DEBUG_LEVEL_INFO)
2344 printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
eeb46134 2345 __FILE__,__LINE__, info->device_name, port->count);
1da177e4 2346
eeb46134 2347 WARN_ON(!port->count);
d12341f9 2348
eeb46134 2349 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 2350 goto cleanup;
d12341f9 2351
eeb46134 2352 if (port->flags & ASYNC_INITIALIZED)
1da177e4
LT		 2353 mgslpc_wait_until_sent(tty, info->timeout);
2354
978e595f 2355 mgslpc_flush_buffer(tty);
1da177e4 2356
978e595f 2357 tty_ldisc_flush(tty);
eeb46134
AC		 2358 shutdown(info, tty);
2359
2360 tty_port_close_end(port, tty);
2361 tty_port_tty_set(port, NULL);
d12341f9 2362cleanup:
1da177e4
LT		 2363 if (debug_level >= DEBUG_LEVEL_INFO)
2364 printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
eeb46134 2365 tty->driver->name, port->count);
1da177e4
LT		 2366}
2367
2368/* Wait until the transmitter is empty.
2369 */
2370static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
2371{
2372 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
2373 unsigned long orig_jiffies, char_time;
2374
2375 if (!info )
2376 return;
2377
2378 if (debug_level >= DEBUG_LEVEL_INFO)
2379 printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
2380 __FILE__,__LINE__, info->device_name );
d12341f9 2381
1da177e4
LT		 2382 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
2383 return;
2384
eeb46134 2385 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4 2386 goto exit;
d12341f9 2387
1da177e4 2388 orig_jiffies = jiffies;
d12341f9 2389
1da177e4
LT		 2390 /* Set check interval to 1/5 of estimated time to
2391 * send a character, and make it at least 1. The check
2392 * interval should also be less than the timeout.
2393 * Note: use tight timings here to satisfy the NIST-PCTS.
d12341f9
JG		 2394 */
2395
1da177e4
LT		 2396 if ( info->params.data_rate ) {
2397 char_time = info->timeout/(32 * 5);
2398 if (!char_time)
2399 char_time++;
2400 } else
2401 char_time = 1;
d12341f9 2402
1da177e4
LT		 2403 if (timeout)
2404 char_time = min_t(unsigned long, char_time, timeout);
d12341f9 2405
1da177e4
LT		 2406 if (info->params.mode == MGSL_MODE_HDLC) {
2407 while (info->tx_active) {
2408 msleep_interruptible(jiffies_to_msecs(char_time));
2409 if (signal_pending(current))
2410 break;
2411 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2412 break;
2413 }
2414 } else {
2415 while ((info->tx_count || info->tx_active) &&
2416 info->tx_enabled) {
2417 msleep_interruptible(jiffies_to_msecs(char_time));
2418 if (signal_pending(current))
2419 break;
2420 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2421 break;
2422 }
2423 }
d12341f9 2424
1da177e4
LT		 2425exit:
2426 if (debug_level >= DEBUG_LEVEL_INFO)
2427 printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
2428 __FILE__,__LINE__, info->device_name );
2429}
2430
2431/* Called by tty_hangup() when a hangup is signaled.
2432 * This is the same as closing all open files for the port.
2433 */
2434static void mgslpc_hangup(struct tty_struct *tty)
2435{
2436 MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
d12341f9 2437
1da177e4
LT		 2438 if (debug_level >= DEBUG_LEVEL_INFO)
2439 printk("%s(%d):mgslpc_hangup(%s)\n",
2440 __FILE__,__LINE__, info->device_name );
d12341f9 2441
1da177e4
LT		 2442 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
2443 return;
2444
2445 mgslpc_flush_buffer(tty);
eeb46134
AC		 2446 shutdown(info, tty);
2447 tty_port_hangup(&info->port);
1da177e4
LT		 2448}
2449
eeb46134 2450static int carrier_raised(struct tty_port *port)
1da177e4 2451{
eeb46134
AC		 2452 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2453 unsigned long flags;
d12341f9 2454
eeb46134
AC		 2455 spin_lock_irqsave(&info->lock,flags);
2456 get_signals(info);
2457 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 2458
eeb46134
AC		 2459 if (info->serial_signals & SerialSignal_DCD)
2460 return 1;
2461 return 0;
2462}
d12341f9 2463
fcc8ac18 2464static void dtr_rts(struct tty_port *port, int onoff)
eeb46134
AC		 2465{
2466 MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
2467 unsigned long flags;
d12341f9 2468
eeb46134 2469 spin_lock_irqsave(&info->lock,flags);
fcc8ac18
AC		 2470 if (onoff)
2471 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2472 else
2473 info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
eeb46134
AC		 2474 set_signals(info);
2475 spin_unlock_irqrestore(&info->lock,flags);
1da177e4
LT		 2476}
2477
eeb46134 2478
1da177e4
LT		 2479static int mgslpc_open(struct tty_struct *tty, struct file * filp)
2480{
2481 MGSLPC_INFO *info;
eeb46134 2482 struct tty_port *port;
1da177e4
LT		 2483 int retval, line;
2484 unsigned long flags;
2485
d12341f9 2486 /* verify range of specified line number */
1da177e4
LT		 2487 line = tty->index;
2488 if ((line < 0) || (line >= mgslpc_device_count)) {
2489 printk("%s(%d):mgslpc_open with invalid line #%d.\n",
2490 __FILE__,__LINE__,line);
2491 return -ENODEV;
2492 }
2493
2494 /* find the info structure for the specified line */
2495 info = mgslpc_device_list;
2496 while(info && info->line != line)
2497 info = info->next_device;
2498 if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
2499 return -ENODEV;
d12341f9 2500
eeb46134 2501 port = &info->port;
1da177e4 2502 tty->driver_data = info;
eeb46134 2503 tty_port_tty_set(port, tty);
d12341f9 2504
1da177e4
LT		 2505 if (debug_level >= DEBUG_LEVEL_INFO)
2506 printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
eeb46134 2507 __FILE__,__LINE__,tty->driver->name, port->count);
1da177e4
LT		 2508
2509 /* If port is closing, signal caller to try again */
eeb46134
AC		 2510 if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
2511 if (port->flags & ASYNC_CLOSING)
2512 interruptible_sleep_on(&port->close_wait);
2513 retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 2514 -EAGAIN : -ERESTARTSYS);
2515 goto cleanup;
2516 }
d12341f9 2517
eeb46134 2518 tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 2519
2520 spin_lock_irqsave(&info->netlock, flags);
2521 if (info->netcount) {
2522 retval = -EBUSY;
2523 spin_unlock_irqrestore(&info->netlock, flags);
2524 goto cleanup;
2525 }
eeb46134
AC		 2526 spin_lock(&port->lock);
2527 port->count++;
2528 spin_unlock(&port->lock);
1da177e4
LT		 2529 spin_unlock_irqrestore(&info->netlock, flags);
2530
eeb46134 2531 if (port->count == 1) {
1da177e4 2532 /* 1st open on this device, init hardware */
eeb46134 2533 retval = startup(info, tty);
1da177e4
LT		 2534 if (retval < 0)
2535 goto cleanup;
2536 }
2537
eeb46134 2538 retval = tty_port_block_til_ready(&info->port, tty, filp);
1da177e4
LT		 2539 if (retval) {
2540 if (debug_level >= DEBUG_LEVEL_INFO)
2541 printk("%s(%d):block_til_ready(%s) returned %d\n",
2542 __FILE__,__LINE__, info->device_name, retval);
2543 goto cleanup;
2544 }
2545
2546 if (debug_level >= DEBUG_LEVEL_INFO)
2547 printk("%s(%d):mgslpc_open(%s) success\n",
2548 __FILE__,__LINE__, info->device_name);
2549 retval = 0;
d12341f9
JG		 2550
2551cleanup:
1da177e4
LT		 2552 return retval;
2553}
2554
2555/*
2556 * /proc fs routines....
2557 */
2558
87687144 2559static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
1da177e4
LT		 2560{
2561 char stat_buf[30];
1da177e4
LT		 2562 unsigned long flags;
2563
87687144 2564 seq_printf(m, "%s:io:%04X irq:%d",
1da177e4
LT		 2565 info->device_name, info->io_base, info->irq_level);
2566
2567 /* output current serial signal states */
2568 spin_lock_irqsave(&info->lock,flags);
2569 get_signals(info);
2570 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 2571
1da177e4
LT		 2572 stat_buf[0] = 0;
2573 stat_buf[1] = 0;
2574 if (info->serial_signals & SerialSignal_RTS)
2575 strcat(stat_buf, "|RTS");
2576 if (info->serial_signals & SerialSignal_CTS)
2577 strcat(stat_buf, "|CTS");
2578 if (info->serial_signals & SerialSignal_DTR)
2579 strcat(stat_buf, "|DTR");
2580 if (info->serial_signals & SerialSignal_DSR)
2581 strcat(stat_buf, "|DSR");
2582 if (info->serial_signals & SerialSignal_DCD)
2583 strcat(stat_buf, "|CD");
2584 if (info->serial_signals & SerialSignal_RI)
2585 strcat(stat_buf, "|RI");
2586
2587 if (info->params.mode == MGSL_MODE_HDLC) {
87687144 2588 seq_printf(m, " HDLC txok:%d rxok:%d",
1da177e4
LT		 2589 info->icount.txok, info->icount.rxok);
2590 if (info->icount.txunder)
87687144 2591 seq_printf(m, " txunder:%d", info->icount.txunder);
1da177e4 2592 if (info->icount.txabort)
87687144 2593 seq_printf(m, " txabort:%d", info->icount.txabort);
1da177e4 2594 if (info->icount.rxshort)
87687144 2595 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1da177e4 2596 if (info->icount.rxlong)
87687144 2597 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1da177e4 2598 if (info->icount.rxover)
87687144 2599 seq_printf(m, " rxover:%d", info->icount.rxover);
1da177e4 2600 if (info->icount.rxcrc)
87687144 2601 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1da177e4 2602 } else {
87687144 2603 seq_printf(m, " ASYNC tx:%d rx:%d",
1da177e4
LT		 2604 info->icount.tx, info->icount.rx);
2605 if (info->icount.frame)
87687144 2606 seq_printf(m, " fe:%d", info->icount.frame);
1da177e4 2607 if (info->icount.parity)
87687144 2608 seq_printf(m, " pe:%d", info->icount.parity);
1da177e4 2609 if (info->icount.brk)
87687144 2610 seq_printf(m, " brk:%d", info->icount.brk);
1da177e4 2611 if (info->icount.overrun)
87687144 2612 seq_printf(m, " oe:%d", info->icount.overrun);
1da177e4 2613 }
d12341f9 2614
1da177e4 2615 /* Append serial signal status to end */
87687144 2616 seq_printf(m, " %s\n", stat_buf+1);
d12341f9 2617
87687144 2618 seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1da177e4
LT		 2619 info->tx_active,info->bh_requested,info->bh_running,
2620 info->pending_bh);
1da177e4
LT		 2621}
2622
2623/* Called to print information about devices
2624 */
87687144 2625static int mgslpc_proc_show(struct seq_file *m, void *v)
1da177e4 2626{
1da177e4 2627 MGSLPC_INFO *info;
d12341f9 2628
87687144 2629 seq_printf(m, "synclink driver:%s\n", driver_version);
d12341f9 2630
1da177e4
LT		 2631 info = mgslpc_device_list;
2632 while( info ) {
87687144 2633 line_info(m, info);
1da177e4
LT		 2634 info = info->next_device;
2635 }
87687144
AD		 2636 return 0;
2637}
1da177e4 2638
87687144
AD		 2639static int mgslpc_proc_open(struct inode *inode, struct file *file)
2640{
2641 return single_open(file, mgslpc_proc_show, NULL);
1da177e4
LT		 2642}
2643
87687144
AD		 2644static const struct file_operations mgslpc_proc_fops = {
2645 .owner = THIS_MODULE,
2646 .open = mgslpc_proc_open,
2647 .read = seq_read,
2648 .llseek = seq_lseek,
2649 .release = single_release,
2650};
2651
cdaad343 2652static int rx_alloc_buffers(MGSLPC_INFO *info)
1da177e4
LT		 2653{
2654 /* each buffer has header and data */
2655 info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
2656
2657 /* calculate total allocation size for 8 buffers */
2658 info->rx_buf_total_size = info->rx_buf_size * 8;
2659
2660 /* limit total allocated memory */
2661 if (info->rx_buf_total_size > 0x10000)
2662 info->rx_buf_total_size = 0x10000;
2663
2664 /* calculate number of buffers */
2665 info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
2666
2667 info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
2668 if (info->rx_buf == NULL)
2669 return -ENOMEM;
2670
2671 rx_reset_buffers(info);
2672 return 0;
2673}
2674
cdaad343 2675static void rx_free_buffers(MGSLPC_INFO *info)
1da177e4 2676{
735d5661 2677 kfree(info->rx_buf);
1da177e4
LT		 2678 info->rx_buf = NULL;
2679}
2680
cdaad343 2681static int claim_resources(MGSLPC_INFO *info)
1da177e4
LT		 2682{
2683 if (rx_alloc_buffers(info) < 0 ) {
2684 printk( "Cant allocate rx buffer %s\n", info->device_name);
2685 release_resources(info);
2686 return -ENODEV;
d12341f9 2687 }
1da177e4
LT		 2688 return 0;
2689}
2690
cdaad343 2691static void release_resources(MGSLPC_INFO *info)
1da177e4
LT		 2692{
2693 if (debug_level >= DEBUG_LEVEL_INFO)
2694 printk("release_resources(%s)\n", info->device_name);
2695 rx_free_buffers(info);
2696}
2697
2698/* Add the specified device instance data structure to the
2699 * global linked list of devices and increment the device count.
d12341f9 2700 *
1da177e4
LT		 2701 * Arguments: info pointer to device instance data
2702 */
cdaad343 2703static void mgslpc_add_device(MGSLPC_INFO *info)
1da177e4
LT		 2704{
2705 info->next_device = NULL;
2706 info->line = mgslpc_device_count;
2707 sprintf(info->device_name,"ttySLP%d",info->line);
d12341f9 2708
1da177e4
LT		 2709 if (info->line < MAX_DEVICE_COUNT) {
2710 if (maxframe[info->line])
2711 info->max_frame_size = maxframe[info->line];
1da177e4
LT		 2712 }
2713
2714 mgslpc_device_count++;
d12341f9 2715
1da177e4
LT		 2716 if (!mgslpc_device_list)
2717 mgslpc_device_list = info;
d12341f9 2718 else {
1da177e4
LT		 2719 MGSLPC_INFO *current_dev = mgslpc_device_list;
2720 while( current_dev->next_device )
2721 current_dev = current_dev->next_device;
2722 current_dev->next_device = info;
2723 }
d12341f9 2724
1da177e4
LT		 2725 if (info->max_frame_size < 4096)
2726 info->max_frame_size = 4096;
2727 else if (info->max_frame_size > 65535)
2728 info->max_frame_size = 65535;
d12341f9 2729
1da177e4
LT		 2730 printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
2731 info->device_name, info->io_base, info->irq_level);
2732
af69c7f9 2733#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2734 hdlcdev_init(info);
2735#endif
2736}
2737
cdaad343 2738static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
1da177e4
LT		 2739{
2740 MGSLPC_INFO *info = mgslpc_device_list;
2741 MGSLPC_INFO *last = NULL;
2742
2743 while(info) {
2744 if (info == remove_info) {
2745 if (last)
2746 last->next_device = info->next_device;
2747 else
2748 mgslpc_device_list = info->next_device;
af69c7f9 2749#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 2750 hdlcdev_exit(info);
2751#endif
2752 release_resources(info);
2753 kfree(info);
2754 mgslpc_device_count--;
2755 return;
2756 }
2757 last = info;
2758 info = info->next_device;
2759 }
2760}
2761
4af48c8c
DB		 2762static struct pcmcia_device_id mgslpc_ids[] = {
2763 PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
2764 PCMCIA_DEVICE_NULL
2765};
2766MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
2767
1da177e4
LT		 2768static struct pcmcia_driver mgslpc_driver = {
2769 .owner = THIS_MODULE,
2e9b981a 2770 .name = "synclink_cs",
15b99ac1 2771 .probe = mgslpc_probe,
cc3b4866 2772 .remove = mgslpc_detach,
4af48c8c 2773 .id_table = mgslpc_ids,
98e4c28b
DB		 2774 .suspend = mgslpc_suspend,
2775 .resume = mgslpc_resume,
1da177e4
LT		 2776};
2777
b68e31d0 2778static const struct tty_operations mgslpc_ops = {
1da177e4
LT		 2779 .open = mgslpc_open,
2780 .close = mgslpc_close,
2781 .write = mgslpc_write,
2782 .put_char = mgslpc_put_char,
2783 .flush_chars = mgslpc_flush_chars,
2784 .write_room = mgslpc_write_room,
2785 .chars_in_buffer = mgslpc_chars_in_buffer,
2786 .flush_buffer = mgslpc_flush_buffer,
2787 .ioctl = mgslpc_ioctl,
2788 .throttle = mgslpc_throttle,
2789 .unthrottle = mgslpc_unthrottle,
2790 .send_xchar = mgslpc_send_xchar,
2791 .break_ctl = mgslpc_break,
2792 .wait_until_sent = mgslpc_wait_until_sent,
1da177e4
LT		 2793 .set_termios = mgslpc_set_termios,
2794 .stop = tx_pause,
2795 .start = tx_release,
2796 .hangup = mgslpc_hangup,
2797 .tiocmget = tiocmget,
2798 .tiocmset = tiocmset,
dc98d965 2799 .get_icount = mgslpc_get_icount,
87687144 2800 .proc_fops = &mgslpc_proc_fops,
1da177e4
LT		 2801};
2802
2803static void synclink_cs_cleanup(void)
2804{
2805 int rc;
2806
1da177e4
LT		 2807 while(mgslpc_device_list)
2808 mgslpc_remove_device(mgslpc_device_list);
2809
2810 if (serial_driver) {
2811 if ((rc = tty_unregister_driver(serial_driver)))
2812 printk("%s(%d) failed to unregister tty driver err=%d\n",
2813 __FILE__,__LINE__,rc);
2814 put_tty_driver(serial_driver);
2815 }
2816
2817 pcmcia_unregister_driver(&mgslpc_driver);
1da177e4
LT		 2818}
2819
2820static int __init synclink_cs_init(void)
2821{
2822 int rc;
2823
2824 if (break_on_load) {
2825 mgslpc_get_text_ptr();
2826 BREAKPOINT();
2827 }
2828
1da177e4
LT		 2829 if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
2830 return rc;
2831
2832 serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
2833 if (!serial_driver) {
2834 rc = -ENOMEM;
2835 goto error;
2836 }
2837
2838 /* Initialize the tty_driver structure */
d12341f9 2839
1da177e4
LT		 2840 serial_driver->owner = THIS_MODULE;
2841 serial_driver->driver_name = "synclink_cs";
2842 serial_driver->name = "ttySLP";
2843 serial_driver->major = ttymajor;
2844 serial_driver->minor_start = 64;
2845 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
2846 serial_driver->subtype = SERIAL_TYPE_NORMAL;
2847 serial_driver->init_termios = tty_std_termios;
2848 serial_driver->init_termios.c_cflag =
2849 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2850 serial_driver->flags = TTY_DRIVER_REAL_RAW;
2851 tty_set_operations(serial_driver, &mgslpc_ops);
2852
2853 if ((rc = tty_register_driver(serial_driver)) < 0) {
2854 printk("%s(%d):Couldn't register serial driver\n",
2855 __FILE__,__LINE__);
2856 put_tty_driver(serial_driver);
2857 serial_driver = NULL;
2858 goto error;
2859 }
d12341f9 2860
1da177e4
LT		 2861 printk("%s %s, tty major#%d\n",
2862 driver_name, driver_version,
2863 serial_driver->major);
d12341f9 2864
1da177e4
LT		 2865 return 0;
2866
2867error:
2868 synclink_cs_cleanup();
2869 return rc;
2870}
2871
d12341f9 2872static void __exit synclink_cs_exit(void)
1da177e4
LT		 2873{
2874 synclink_cs_cleanup();
2875}
2876
2877module_init(synclink_cs_init);
2878module_exit(synclink_cs_exit);
2879
2880static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
2881{
2882 unsigned int M, N;
2883 unsigned char val;
2884
d12341f9
JG		 2885 /* note:standard BRG mode is broken in V3.2 chip
2886 * so enhanced mode is always used
1da177e4
LT		 2887 */
2888
2889 if (rate) {
2890 N = 3686400 / rate;
2891 if (!N)
2892 N = 1;
2893 N >>= 1;
2894 for (M = 1; N > 64 && M < 16; M++)
2895 N >>= 1;
2896 N--;
2897
2898 /* BGR[5..0] = N
2899 * BGR[9..6] = M
2900 * BGR[7..0] contained in BGR register
2901 * BGR[9..8] contained in CCR2[7..6]
2902 * divisor = (N+1)*2^M
2903 *
2904 * Note: M *must* not be zero (causes asymetric duty cycle)
d12341f9 2905 */
1da177e4
LT		 2906 write_reg(info, (unsigned char) (channel + BGR),
2907 (unsigned char) ((M << 6) + N));
2908 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
2909 val |= ((M << 4) & 0xc0);
2910 write_reg(info, (unsigned char) (channel + CCR2), val);
2911 }
2912}
2913
2914/* Enabled the AUX clock output at the specified frequency.
2915 */
2916static void enable_auxclk(MGSLPC_INFO *info)
2917{
2918 unsigned char val;
d12341f9 2919
1da177e4
LT		 2920 /* MODE
2921 *
2922 * 07..06 MDS[1..0] 10 = transparent HDLC mode
2923 * 05 ADM Address Mode, 0 = no addr recognition
2924 * 04 TMD Timer Mode, 0 = external
2925 * 03 RAC Receiver Active, 0 = inactive
2926 * 02 RTS 0=RTS active during xmit, 1=RTS always active
2927 * 01 TRS Timer Resolution, 1=512
2928 * 00 TLP Test Loop, 0 = no loop
2929 *
2930 * 1000 0010
d12341f9 2931 */
1da177e4 2932 val = 0x82;
d12341f9
JG		 2933
2934 /* channel B RTS is used to enable AUXCLK driver on SP505 */
1da177e4
LT		 2935 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2936 val |= BIT2;
2937 write_reg(info, CHB + MODE, val);
d12341f9 2938
1da177e4
LT		 2939 /* CCR0
2940 *
2941 * 07 PU Power Up, 1=active, 0=power down
2942 * 06 MCE Master Clock Enable, 1=enabled
2943 * 05 Reserved, 0
2944 * 04..02 SC[2..0] Encoding
2945 * 01..00 SM[1..0] Serial Mode, 00=HDLC
2946 *
2947 * 11000000
d12341f9 2948 */
1da177e4 2949 write_reg(info, CHB + CCR0, 0xc0);
d12341f9 2950
1da177e4
LT		 2951 /* CCR1
2952 *
2953 * 07 SFLG Shared Flag, 0 = disable shared flags
2954 * 06 GALP Go Active On Loop, 0 = not used
2955 * 05 GLP Go On Loop, 0 = not used
2956 * 04 ODS Output Driver Select, 1=TxD is push-pull output
2957 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
2958 * 02..00 CM[2..0] Clock Mode
2959 *
2960 * 0001 0111
d12341f9 2961 */
1da177e4 2962 write_reg(info, CHB + CCR1, 0x17);
d12341f9 2963
1da177e4
LT		 2964 /* CCR2 (Channel B)
2965 *
2966 * 07..06 BGR[9..8] Baud rate bits 9..8
2967 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
2968 * 04 SSEL Clock source select, 1=submode b
2969 * 03 TOE 0=TxCLK is input, 1=TxCLK is output
2970 * 02 RWX Read/Write Exchange 0=disabled
2971 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
2972 * 00 DIV, data inversion 0=disabled, 1=enabled
2973 *
2974 * 0011 1000
d12341f9 2975 */
1da177e4
LT		 2976 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2977 write_reg(info, CHB + CCR2, 0x38);
2978 else
2979 write_reg(info, CHB + CCR2, 0x30);
d12341f9 2980
1da177e4
LT		 2981 /* CCR4
2982 *
2983 * 07 MCK4 Master Clock Divide by 4, 1=enabled
2984 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
2985 * 05 TST1 Test Pin, 0=normal operation
2986 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
2987 * 03..02 Reserved, must be 0
2988 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
2989 *
2990 * 0101 0000
d12341f9 2991 */
1da177e4 2992 write_reg(info, CHB + CCR4, 0x50);
d12341f9 2993
1da177e4
LT		 2994 /* if auxclk not enabled, set internal BRG so
2995 * CTS transitions can be detected (requires TxC)
d12341f9 2996 */
1da177e4
LT		 2997 if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
2998 mgslpc_set_rate(info, CHB, info->params.clock_speed);
2999 else
3000 mgslpc_set_rate(info, CHB, 921600);
3001}
3002
d12341f9 3003static void loopback_enable(MGSLPC_INFO *info)
1da177e4
LT		 3004{
3005 unsigned char val;
d12341f9
JG		 3006
3007 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
1da177e4
LT		 3008 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
3009 write_reg(info, CHA + CCR1, val);
d12341f9
JG		 3010
3011 /* CCR2:04 SSEL Clock source select, 1=submode b */
1da177e4
LT		 3012 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
3013 write_reg(info, CHA + CCR2, val);
d12341f9
JG		 3014
3015 /* set LinkSpeed if available, otherwise default to 2Mbps */
1da177e4
LT		 3016 if (info->params.clock_speed)
3017 mgslpc_set_rate(info, CHA, info->params.clock_speed);
3018 else
3019 mgslpc_set_rate(info, CHA, 1843200);
d12341f9
JG		 3020
3021 /* MODE:00 TLP Test Loop, 1=loopback enabled */
1da177e4
LT		 3022 val = read_reg(info, CHA + MODE) | BIT0;
3023 write_reg(info, CHA + MODE, val);
3024}
3025
cdaad343 3026static void hdlc_mode(MGSLPC_INFO *info)
1da177e4
LT		 3027{
3028 unsigned char val;
3029 unsigned char clkmode, clksubmode;
3030
d12341f9 3031 /* disable all interrupts */
1da177e4
LT		 3032 irq_disable(info, CHA, 0xffff);
3033 irq_disable(info, CHB, 0xffff);
3034 port_irq_disable(info, 0xff);
d12341f9
JG		 3035
3036 /* assume clock mode 0a, rcv=RxC xmt=TxC */
1da177e4
LT		 3037 clkmode = clksubmode = 0;
3038 if (info->params.flags & HDLC_FLAG_RXC_DPLL
3039 && info->params.flags & HDLC_FLAG_TXC_DPLL) {
d12341f9 3040 /* clock mode 7a, rcv = DPLL, xmt = DPLL */
1da177e4
LT		 3041 clkmode = 7;
3042 } else if (info->params.flags & HDLC_FLAG_RXC_BRG
3043 && info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3044 /* clock mode 7b, rcv = BRG, xmt = BRG */
1da177e4
LT		 3045 clkmode = 7;
3046 clksubmode = 1;
3047 } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
3048 if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3049 /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
1da177e4
LT		 3050 clkmode = 6;
3051 clksubmode = 1;
3052 } else {
d12341f9 3053 /* clock mode 6a, rcv = DPLL, xmt = TxC */
1da177e4
LT		 3054 clkmode = 6;
3055 }
3056 } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
d12341f9 3057 /* clock mode 0b, rcv = RxC, xmt = BRG */
1da177e4
LT		 3058 clksubmode = 1;
3059 }
d12341f9 3060
1da177e4
LT		 3061 /* MODE
3062 *
3063 * 07..06 MDS[1..0] 10 = transparent HDLC mode
3064 * 05 ADM Address Mode, 0 = no addr recognition
3065 * 04 TMD Timer Mode, 0 = external
3066 * 03 RAC Receiver Active, 0 = inactive
3067 * 02 RTS 0=RTS active during xmit, 1=RTS always active
3068 * 01 TRS Timer Resolution, 1=512
3069 * 00 TLP Test Loop, 0 = no loop
3070 *
3071 * 1000 0010
d12341f9 3072 */
1da177e4
LT		 3073 val = 0x82;
3074 if (info->params.loopback)
3075 val |= BIT0;
d12341f9
JG		 3076
3077 /* preserve RTS state */
1da177e4
LT		 3078 if (info->serial_signals & SerialSignal_RTS)
3079 val |= BIT2;
3080 write_reg(info, CHA + MODE, val);
d12341f9 3081
1da177e4
LT		 3082 /* CCR0
3083 *
3084 * 07 PU Power Up, 1=active, 0=power down
3085 * 06 MCE Master Clock Enable, 1=enabled
3086 * 05 Reserved, 0
3087 * 04..02 SC[2..0] Encoding
3088 * 01..00 SM[1..0] Serial Mode, 00=HDLC
3089 *
3090 * 11000000
d12341f9 3091 */
1da177e4
LT		 3092 val = 0xc0;
3093 switch (info->params.encoding)
3094 {
3095 case HDLC_ENCODING_NRZI:
3096 val |= BIT3;
3097 break;
3098 case HDLC_ENCODING_BIPHASE_SPACE:
3099 val |= BIT4;
3100 break; // FM0
3101 case HDLC_ENCODING_BIPHASE_MARK:
3102 val |= BIT4 + BIT2;
3103 break; // FM1
3104 case HDLC_ENCODING_BIPHASE_LEVEL:
3105 val |= BIT4 + BIT3;
3106 break; // Manchester
3107 }
3108 write_reg(info, CHA + CCR0, val);
d12341f9 3109
1da177e4
LT		 3110 /* CCR1
3111 *
3112 * 07 SFLG Shared Flag, 0 = disable shared flags
3113 * 06 GALP Go Active On Loop, 0 = not used
3114 * 05 GLP Go On Loop, 0 = not used
3115 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3116 * 03 ITF Interframe Time Fill, 0=mark, 1=flag
3117 * 02..00 CM[2..0] Clock Mode
3118 *
3119 * 0001 0000
d12341f9 3120 */
1da177e4
LT		 3121 val = 0x10 + clkmode;
3122 write_reg(info, CHA + CCR1, val);
d12341f9 3123
1da177e4
LT		 3124 /* CCR2
3125 *
3126 * 07..06 BGR[9..8] Baud rate bits 9..8
3127 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3128 * 04 SSEL Clock source select, 1=submode b
3129 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3130 * 02 RWX Read/Write Exchange 0=disabled
3131 * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
3132 * 00 DIV, data inversion 0=disabled, 1=enabled
3133 *
3134 * 0000 0000
d12341f9 3135 */
1da177e4
LT		 3136 val = 0x00;
3137 if (clkmode == 2 || clkmode == 3 || clkmode == 6
3138 || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
3139 val |= BIT5;
3140 if (clksubmode)
3141 val |= BIT4;
3142 if (info->params.crc_type == HDLC_CRC_32_CCITT)
3143 val |= BIT1;
3144 if (info->params.encoding == HDLC_ENCODING_NRZB)
3145 val |= BIT0;
3146 write_reg(info, CHA + CCR2, val);
d12341f9 3147
1da177e4
LT		 3148 /* CCR3
3149 *
3150 * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
3151 * 05 EPT Enable preamble transmission, 1=enabled
3152 * 04 RADD Receive address pushed to FIFO, 0=disabled
3153 * 03 CRL CRC Reset Level, 0=FFFF
3154 * 02 RCRC Rx CRC 0=On 1=Off
3155 * 01 TCRC Tx CRC 0=On 1=Off
3156 * 00 PSD DPLL Phase Shift Disable
3157 *
3158 * 0000 0000
d12341f9 3159 */
1da177e4
LT		 3160 val = 0x00;
3161 if (info->params.crc_type == HDLC_CRC_NONE)
3162 val |= BIT2 + BIT1;
3163 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
3164 val |= BIT5;
3165 switch (info->params.preamble_length)
3166 {
3167 case HDLC_PREAMBLE_LENGTH_16BITS:
3168 val |= BIT6;
3169 break;
3170 case HDLC_PREAMBLE_LENGTH_32BITS:
3171 val |= BIT6;
3172 break;
3173 case HDLC_PREAMBLE_LENGTH_64BITS:
3174 val |= BIT7 + BIT6;
3175 break;
3176 }
3177 write_reg(info, CHA + CCR3, val);
d12341f9
JG		 3178
3179 /* PRE - Preamble pattern */
1da177e4
LT		 3180 val = 0;
3181 switch (info->params.preamble)
3182 {
3183 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
3184 case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
3185 case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
3186 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
3187 }
3188 write_reg(info, CHA + PRE, val);
d12341f9 3189
1da177e4
LT		 3190 /* CCR4
3191 *
3192 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3193 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3194 * 05 TST1 Test Pin, 0=normal operation
3195 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3196 * 03..02 Reserved, must be 0
3197 * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
3198 *
3199 * 0101 0000
d12341f9 3200 */
1da177e4
LT		 3201 val = 0x50;
3202 write_reg(info, CHA + CCR4, val);
3203 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
3204 mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
3205 else
3206 mgslpc_set_rate(info, CHA, info->params.clock_speed);
d12341f9 3207
1da177e4
LT		 3208 /* RLCR Receive length check register
3209 *
3210 * 7 1=enable receive length check
3211 * 6..0 Max frame length = (RL + 1) * 32
d12341f9 3212 */
1da177e4 3213 write_reg(info, CHA + RLCR, 0);
d12341f9 3214
1da177e4
LT		 3215 /* XBCH Transmit Byte Count High
3216 *
3217 * 07 DMA mode, 0 = interrupt driven
3218 * 06 NRM, 0=ABM (ignored)
3219 * 05 CAS Carrier Auto Start
3220 * 04 XC Transmit Continuously (ignored)
3221 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3222 *
3223 * 0000 0000
d12341f9 3224 */
1da177e4
LT		 3225 val = 0x00;
3226 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3227 val |= BIT5;
3228 write_reg(info, CHA + XBCH, val);
3229 enable_auxclk(info);
3230 if (info->params.loopback || info->testing_irq)
3231 loopback_enable(info);
3232 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3233 {
3234 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3235 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3236 set_reg_bits(info, CHA + PVR, BIT3);
3237 } else
3238 clear_reg_bits(info, CHA + PVR, BIT3);
3239
3240 irq_enable(info, CHA,
3241 IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
3242 IRQ_UNDERRUN + IRQ_TXFIFO);
3243 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3244 wait_command_complete(info, CHA);
3245 read_reg16(info, CHA + ISR); /* clear pending IRQs */
d12341f9 3246
1da177e4
LT		 3247 /* Master clock mode enabled above to allow reset commands
3248 * to complete even if no data clocks are present.
3249 *
3250 * Disable master clock mode for normal communications because
3251 * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
3252 * IRQ when in master clock mode.
3253 *
3254 * Leave master clock mode enabled for IRQ test because the
3255 * timer IRQ used by the test can only happen in master clock mode.
d12341f9 3256 */
1da177e4
LT		 3257 if (!info->testing_irq)
3258 clear_reg_bits(info, CHA + CCR0, BIT6);
3259
3260 tx_set_idle(info);
3261
3262 tx_stop(info);
3263 rx_stop(info);
3264}
3265
cdaad343 3266static void rx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3267{
3268 if (debug_level >= DEBUG_LEVEL_ISR)
3269 printk("%s(%d):rx_stop(%s)\n",
3270 __FILE__,__LINE__, info->device_name );
d12341f9
JG		 3271
3272 /* MODE:03 RAC Receiver Active, 0=inactive */
1da177e4
LT		 3273 clear_reg_bits(info, CHA + MODE, BIT3);
3274
0fab6de0
JP		 3275 info->rx_enabled = false;
3276 info->rx_overflow = false;
1da177e4
LT		 3277}
3278
cdaad343 3279static void rx_start(MGSLPC_INFO *info)
1da177e4
LT		 3280{
3281 if (debug_level >= DEBUG_LEVEL_ISR)
3282 printk("%s(%d):rx_start(%s)\n",
3283 __FILE__,__LINE__, info->device_name );
3284
3285 rx_reset_buffers(info);
0fab6de0
JP		 3286 info->rx_enabled = false;
3287 info->rx_overflow = false;
1da177e4 3288
d12341f9 3289 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3290 set_reg_bits(info, CHA + MODE, BIT3);
3291
0fab6de0 3292 info->rx_enabled = true;
1da177e4
LT		 3293}
3294
eeb46134 3295static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3296{
3297 if (debug_level >= DEBUG_LEVEL_ISR)
3298 printk("%s(%d):tx_start(%s)\n",
3299 __FILE__,__LINE__, info->device_name );
d12341f9 3300
1da177e4
LT		 3301 if (info->tx_count) {
3302 /* If auto RTS enabled and RTS is inactive, then assert */
3303 /* RTS and set a flag indicating that the driver should */
3304 /* negate RTS when the transmission completes. */
0fab6de0 3305 info->drop_rts_on_tx_done = false;
1da177e4
LT		 3306
3307 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3308 get_signals(info);
3309 if (!(info->serial_signals & SerialSignal_RTS)) {
3310 info->serial_signals |= SerialSignal_RTS;
3311 set_signals(info);
0fab6de0 3312 info->drop_rts_on_tx_done = true;
1da177e4
LT		 3313 }
3314 }
3315
3316 if (info->params.mode == MGSL_MODE_ASYNC) {
3317 if (!info->tx_active) {
0fab6de0 3318 info->tx_active = true;
eeb46134 3319 tx_ready(info, tty);
1da177e4
LT		 3320 }
3321 } else {
0fab6de0 3322 info->tx_active = true;
eeb46134 3323 tx_ready(info, tty);
40565f19
JS		 3324 mod_timer(&info->tx_timer, jiffies +
3325 msecs_to_jiffies(5000));
1da177e4
LT		 3326 }
3327 }
3328
3329 if (!info->tx_enabled)
0fab6de0 3330 info->tx_enabled = true;
1da177e4
LT		 3331}
3332
cdaad343 3333static void tx_stop(MGSLPC_INFO *info)
1da177e4
LT		 3334{
3335 if (debug_level >= DEBUG_LEVEL_ISR)
3336 printk("%s(%d):tx_stop(%s)\n",
3337 __FILE__,__LINE__, info->device_name );
d12341f9
JG		 3338
3339 del_timer(&info->tx_timer);
1da177e4 3340
0fab6de0
JP		 3341 info->tx_enabled = false;
3342 info->tx_active = false;
1da177e4
LT		 3343}
3344
3345/* Reset the adapter to a known state and prepare it for further use.
3346 */
cdaad343 3347static void reset_device(MGSLPC_INFO *info)
1da177e4 3348{
d12341f9 3349 /* power up both channels (set BIT7) */
1da177e4
LT		 3350 write_reg(info, CHA + CCR0, 0x80);
3351 write_reg(info, CHB + CCR0, 0x80);
3352 write_reg(info, CHA + MODE, 0);
3353 write_reg(info, CHB + MODE, 0);
d12341f9
JG		 3354
3355 /* disable all interrupts */
1da177e4
LT		 3356 irq_disable(info, CHA, 0xffff);
3357 irq_disable(info, CHB, 0xffff);
3358 port_irq_disable(info, 0xff);
d12341f9 3359
1da177e4
LT		 3360 /* PCR Port Configuration Register
3361 *
3362 * 07..04 DEC[3..0] Serial I/F select outputs
3363 * 03 output, 1=AUTO CTS control enabled
3364 * 02 RI Ring Indicator input 0=active
3365 * 01 DSR input 0=active
3366 * 00 DTR output 0=active
3367 *
3368 * 0000 0110
d12341f9 3369 */
1da177e4 3370 write_reg(info, PCR, 0x06);
d12341f9 3371
1da177e4
LT		 3372 /* PVR Port Value Register
3373 *
3374 * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
3375 * 03 AUTO CTS output 1=enabled
3376 * 02 RI Ring Indicator input
3377 * 01 DSR input
3378 * 00 DTR output (1=inactive)
3379 *
3380 * 0000 0001
3381 */
3382// write_reg(info, PVR, PVR_DTR);
d12341f9 3383
1da177e4
LT		 3384 /* IPC Interrupt Port Configuration
3385 *
3386 * 07 VIS 1=Masked interrupts visible
3387 * 06..05 Reserved, 0
3388 * 04..03 SLA Slave address, 00 ignored
3389 * 02 CASM Cascading Mode, 1=daisy chain
3390 * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
3391 *
3392 * 0000 0101
d12341f9 3393 */
1da177e4
LT		 3394 write_reg(info, IPC, 0x05);
3395}
3396
cdaad343 3397static void async_mode(MGSLPC_INFO *info)
1da177e4
LT		 3398{
3399 unsigned char val;
3400
d12341f9 3401 /* disable all interrupts */
1da177e4
LT		 3402 irq_disable(info, CHA, 0xffff);
3403 irq_disable(info, CHB, 0xffff);
3404 port_irq_disable(info, 0xff);
d12341f9 3405
1da177e4
LT		 3406 /* MODE
3407 *
3408 * 07 Reserved, 0
3409 * 06 FRTS RTS State, 0=active
3410 * 05 FCTS Flow Control on CTS
3411 * 04 FLON Flow Control Enable
3412 * 03 RAC Receiver Active, 0 = inactive
3413 * 02 RTS 0=Auto RTS, 1=manual RTS
3414 * 01 TRS Timer Resolution, 1=512
3415 * 00 TLP Test Loop, 0 = no loop
3416 *
3417 * 0000 0110
d12341f9 3418 */
1da177e4
LT		 3419 val = 0x06;
3420 if (info->params.loopback)
3421 val |= BIT0;
d12341f9
JG		 3422
3423 /* preserve RTS state */
1da177e4
LT		 3424 if (!(info->serial_signals & SerialSignal_RTS))
3425 val |= BIT6;
3426 write_reg(info, CHA + MODE, val);
d12341f9 3427
1da177e4
LT		 3428 /* CCR0
3429 *
3430 * 07 PU Power Up, 1=active, 0=power down
3431 * 06 MCE Master Clock Enable, 1=enabled
3432 * 05 Reserved, 0
3433 * 04..02 SC[2..0] Encoding, 000=NRZ
3434 * 01..00 SM[1..0] Serial Mode, 11=Async
3435 *
3436 * 1000 0011
d12341f9 3437 */
1da177e4 3438 write_reg(info, CHA + CCR0, 0x83);
d12341f9 3439
1da177e4
LT		 3440 /* CCR1
3441 *
3442 * 07..05 Reserved, 0
3443 * 04 ODS Output Driver Select, 1=TxD is push-pull output
3444 * 03 BCR Bit Clock Rate, 1=16x
3445 * 02..00 CM[2..0] Clock Mode, 111=BRG
3446 *
3447 * 0001 1111
d12341f9 3448 */
1da177e4 3449 write_reg(info, CHA + CCR1, 0x1f);
d12341f9 3450
1da177e4
LT		 3451 /* CCR2 (channel A)
3452 *
3453 * 07..06 BGR[9..8] Baud rate bits 9..8
3454 * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
3455 * 04 SSEL Clock source select, 1=submode b
3456 * 03 TOE 0=TxCLK is input, 0=TxCLK is input
3457 * 02 RWX Read/Write Exchange 0=disabled
3458 * 01 Reserved, 0
3459 * 00 DIV, data inversion 0=disabled, 1=enabled
3460 *
3461 * 0001 0000
d12341f9 3462 */
1da177e4 3463 write_reg(info, CHA + CCR2, 0x10);
d12341f9 3464
1da177e4
LT		 3465 /* CCR3
3466 *
3467 * 07..01 Reserved, 0
3468 * 00 PSD DPLL Phase Shift Disable
3469 *
3470 * 0000 0000
d12341f9 3471 */
1da177e4 3472 write_reg(info, CHA + CCR3, 0);
d12341f9 3473
1da177e4
LT		 3474 /* CCR4
3475 *
3476 * 07 MCK4 Master Clock Divide by 4, 1=enabled
3477 * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
3478 * 05 TST1 Test Pin, 0=normal operation
3479 * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
3480 * 03..00 Reserved, must be 0
3481 *
3482 * 0101 0000
d12341f9 3483 */
1da177e4
LT		 3484 write_reg(info, CHA + CCR4, 0x50);
3485 mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
d12341f9 3486
1da177e4
LT		 3487 /* DAFO Data Format
3488 *
3489 * 07 Reserved, 0
3490 * 06 XBRK transmit break, 0=normal operation
3491 * 05 Stop bits (0=1, 1=2)
3492 * 04..03 PAR[1..0] Parity (01=odd, 10=even)
3493 * 02 PAREN Parity Enable
3494 * 01..00 CHL[1..0] Character Length (00=8, 01=7)
3495 *
d12341f9 3496 */
1da177e4
LT		 3497 val = 0x00;
3498 if (info->params.data_bits != 8)
3499 val |= BIT0; /* 7 bits */
3500 if (info->params.stop_bits != 1)
3501 val |= BIT5;
3502 if (info->params.parity != ASYNC_PARITY_NONE)
3503 {
3504 val |= BIT2; /* Parity enable */
3505 if (info->params.parity == ASYNC_PARITY_ODD)
3506 val |= BIT3;
3507 else
3508 val |= BIT4;
3509 }
3510 write_reg(info, CHA + DAFO, val);
d12341f9 3511
1da177e4
LT		 3512 /* RFC Rx FIFO Control
3513 *
3514 * 07 Reserved, 0
3515 * 06 DPS, 1=parity bit not stored in data byte
3516 * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
3517 * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
3518 * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
3519 * 01 Reserved, 0
3520 * 00 TCDE Terminate Char Detect Enable, 0=disabled
3521 *
3522 * 0101 1100
d12341f9 3523 */
1da177e4 3524 write_reg(info, CHA + RFC, 0x5c);
d12341f9 3525
1da177e4
LT		 3526 /* RLCR Receive length check register
3527 *
3528 * Max frame length = (RL + 1) * 32
d12341f9 3529 */
1da177e4 3530 write_reg(info, CHA + RLCR, 0);
d12341f9 3531
1da177e4
LT		 3532 /* XBCH Transmit Byte Count High
3533 *
3534 * 07 DMA mode, 0 = interrupt driven
3535 * 06 NRM, 0=ABM (ignored)
3536 * 05 CAS Carrier Auto Start
3537 * 04 XC Transmit Continuously (ignored)
3538 * 03..00 XBC[10..8] Transmit byte count bits 10..8
3539 *
3540 * 0000 0000
d12341f9 3541 */
1da177e4
LT		 3542 val = 0x00;
3543 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3544 val |= BIT5;
3545 write_reg(info, CHA + XBCH, val);
3546 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3547 irq_enable(info, CHA, IRQ_CTS);
d12341f9
JG		 3548
3549 /* MODE:03 RAC Receiver Active, 1=active */
1da177e4
LT		 3550 set_reg_bits(info, CHA + MODE, BIT3);
3551 enable_auxclk(info);
3552 if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
3553 irq_enable(info, CHB, IRQ_CTS);
d12341f9 3554 /* PVR[3] 1=AUTO CTS active */
1da177e4
LT		 3555 set_reg_bits(info, CHA + PVR, BIT3);
3556 } else
3557 clear_reg_bits(info, CHA + PVR, BIT3);
3558 irq_enable(info, CHA,
3559 IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
3560 IRQ_ALLSENT + IRQ_TXFIFO);
3561 issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
3562 wait_command_complete(info, CHA);
3563 read_reg16(info, CHA + ISR); /* clear pending IRQs */
3564}
3565
3566/* Set the HDLC idle mode for the transmitter.
3567 */
cdaad343 3568static void tx_set_idle(MGSLPC_INFO *info)
1da177e4 3569{
d12341f9 3570 /* Note: ESCC2 only supports flags and one idle modes */
1da177e4
LT		 3571 if (info->idle_mode == HDLC_TXIDLE_FLAGS)
3572 set_reg_bits(info, CHA + CCR1, BIT3);
3573 else
3574 clear_reg_bits(info, CHA + CCR1, BIT3);
3575}
3576
3577/* get state of the V24 status (input) signals.
3578 */
cdaad343 3579static void get_signals(MGSLPC_INFO *info)
1da177e4
LT		 3580{
3581 unsigned char status = 0;
d12341f9
JG		 3582
3583 /* preserve DTR and RTS */
1da177e4
LT		 3584 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
3585
3586 if (read_reg(info, CHB + VSTR) & BIT7)
3587 info->serial_signals |= SerialSignal_DCD;
3588 if (read_reg(info, CHB + STAR) & BIT1)
3589 info->serial_signals |= SerialSignal_CTS;
3590
3591 status = read_reg(info, CHA + PVR);
3592 if (!(status & PVR_RI))
3593 info->serial_signals |= SerialSignal_RI;
3594 if (!(status & PVR_DSR))
3595 info->serial_signals |= SerialSignal_DSR;
3596}
3597
3598/* Set the state of DTR and RTS based on contents of
3599 * serial_signals member of device extension.
3600 */
cdaad343 3601static void set_signals(MGSLPC_INFO *info)
1da177e4
LT		 3602{
3603 unsigned char val;
3604
3605 val = read_reg(info, CHA + MODE);
3606 if (info->params.mode == MGSL_MODE_ASYNC) {
3607 if (info->serial_signals & SerialSignal_RTS)
3608 val &= ~BIT6;
3609 else
3610 val |= BIT6;
3611 } else {
3612 if (info->serial_signals & SerialSignal_RTS)
3613 val |= BIT2;
3614 else
3615 val &= ~BIT2;
3616 }
3617 write_reg(info, CHA + MODE, val);
3618
3619 if (info->serial_signals & SerialSignal_DTR)
3620 clear_reg_bits(info, CHA + PVR, PVR_DTR);
3621 else
3622 set_reg_bits(info, CHA + PVR, PVR_DTR);
3623}
3624
cdaad343 3625static void rx_reset_buffers(MGSLPC_INFO *info)
1da177e4
LT		 3626{
3627 RXBUF *buf;
3628 int i;
3629
3630 info->rx_put = 0;
3631 info->rx_get = 0;
3632 info->rx_frame_count = 0;
3633 for (i=0 ; i < info->rx_buf_count ; i++) {
3634 buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
3635 buf->status = buf->count = 0;
3636 }
3637}
3638
3639/* Attempt to return a received HDLC frame
3640 * Only frames received without errors are returned.
3641 *
0fab6de0 3642 * Returns true if frame returned, otherwise false
1da177e4 3643 */
eeb46134 3644static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
1da177e4
LT		 3645{
3646 unsigned short status;
3647 RXBUF *buf;
3648 unsigned int framesize = 0;
3649 unsigned long flags;
0fab6de0 3650 bool return_frame = false;
d12341f9 3651
1da177e4 3652 if (info->rx_frame_count == 0)
0fab6de0 3653 return false;
1da177e4
LT		 3654
3655 buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
3656
3657 status = buf->status;
3658
3659 /* 07 VFR 1=valid frame
3660 * 06 RDO 1=data overrun
3661 * 05 CRC 1=OK, 0=error
3662 * 04 RAB 1=frame aborted
3663 */
3664 if ((status & 0xf0) != 0xA0) {
3665 if (!(status & BIT7) || (status & BIT4))
3666 info->icount.rxabort++;
3667 else if (status & BIT6)
3668 info->icount.rxover++;
3669 else if (!(status & BIT5)) {
3670 info->icount.rxcrc++;
3671 if (info->params.crc_type & HDLC_CRC_RETURN_EX)
0fab6de0 3672 return_frame = true;
1da177e4
LT		 3673 }
3674 framesize = 0;
af69c7f9 3675#if SYNCLINK_GENERIC_HDLC
1da177e4 3676 {
198191c4
KH		 3677 info->netdev->stats.rx_errors++;
3678 info->netdev->stats.rx_frame_errors++;
1da177e4
LT		 3679 }
3680#endif
3681 } else
0fab6de0 3682 return_frame = true;
1da177e4
LT		 3683
3684 if (return_frame)
3685 framesize = buf->count;
3686
3687 if (debug_level >= DEBUG_LEVEL_BH)
3688 printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
3689 __FILE__,__LINE__,info->device_name,status,framesize);
d12341f9 3690
1da177e4 3691 if (debug_level >= DEBUG_LEVEL_DATA)
d12341f9
JG		 3692 trace_block(info, buf->data, framesize, 0);
3693
1da177e4
LT		 3694 if (framesize) {
3695 if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
3696 framesize+1 > info->max_frame_size) ||
3697 framesize > info->max_frame_size)
3698 info->icount.rxlong++;
3699 else {
3700 if (status & BIT5)
3701 info->icount.rxok++;
3702
3703 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
3704 *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
3705 ++framesize;
3706 }
3707
af69c7f9 3708#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3709 if (info->netcount)
3710 hdlcdev_rx(info, buf->data, framesize);
3711 else
3712#endif
3713 ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
3714 }
3715 }
3716
3717 spin_lock_irqsave(&info->lock,flags);
3718 buf->status = buf->count = 0;
3719 info->rx_frame_count--;
3720 info->rx_get++;
3721 if (info->rx_get >= info->rx_buf_count)
3722 info->rx_get = 0;
3723 spin_unlock_irqrestore(&info->lock,flags);
3724
0fab6de0 3725 return true;
1da177e4
LT		 3726}
3727
0fab6de0 3728static bool register_test(MGSLPC_INFO *info)
1da177e4 3729{
d12341f9 3730 static unsigned char patterns[] =
1da177e4 3731 { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
fe971071 3732 static unsigned int count = ARRAY_SIZE(patterns);
1da177e4 3733 unsigned int i;
0fab6de0 3734 bool rc = true;
1da177e4
LT		 3735 unsigned long flags;
3736
3737 spin_lock_irqsave(&info->lock,flags);
3738 reset_device(info);
3739
3740 for (i = 0; i < count; i++) {
3741 write_reg(info, XAD1, patterns[i]);
3742 write_reg(info, XAD2, patterns[(i + 1) % count]);
fe971071 3743 if ((read_reg(info, XAD1) != patterns[i]) ||
1da177e4 3744 (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
0fab6de0 3745 rc = false;
1da177e4
LT		 3746 break;
3747 }
3748 }
3749
3750 spin_unlock_irqrestore(&info->lock,flags);
3751 return rc;
3752}
3753
0fab6de0 3754static bool irq_test(MGSLPC_INFO *info)
1da177e4
LT		 3755{
3756 unsigned long end_time;
3757 unsigned long flags;
3758
3759 spin_lock_irqsave(&info->lock,flags);
3760 reset_device(info);
3761
0fab6de0 3762 info->testing_irq = true;
1da177e4
LT		 3763 hdlc_mode(info);
3764
0fab6de0 3765 info->irq_occurred = false;
1da177e4
LT		 3766
3767 /* init hdlc mode */
3768
3769 irq_enable(info, CHA, IRQ_TIMER);
3770 write_reg(info, CHA + TIMR, 0); /* 512 cycles */
3771 issue_command(info, CHA, CMD_START_TIMER);
3772
3773 spin_unlock_irqrestore(&info->lock,flags);
3774
3775 end_time=100;
3776 while(end_time-- && !info->irq_occurred) {
3777 msleep_interruptible(10);
3778 }
d12341f9 3779
0fab6de0 3780 info->testing_irq = false;
1da177e4
LT		 3781
3782 spin_lock_irqsave(&info->lock,flags);
3783 reset_device(info);
3784 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 3785
0fab6de0 3786 return info->irq_occurred;
1da177e4
LT		 3787}
3788
cdaad343 3789static int adapter_test(MGSLPC_INFO *info)
1da177e4
LT		 3790{
3791 if (!register_test(info)) {
3792 info->init_error = DiagStatus_AddressFailure;
3793 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
3794 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
3795 return -ENODEV;
3796 }
3797
3798 if (!irq_test(info)) {
3799 info->init_error = DiagStatus_IrqFailure;
3800 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
3801 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
3802 return -ENODEV;
3803 }
3804
3805 if (debug_level >= DEBUG_LEVEL_INFO)
3806 printk("%s(%d):device %s passed diagnostics\n",
3807 __FILE__,__LINE__,info->device_name);
3808 return 0;
3809}
3810
cdaad343 3811static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
1da177e4
LT		 3812{
3813 int i;
3814 int linecount;
3815 if (xmit)
3816 printk("%s tx data:\n",info->device_name);
3817 else
3818 printk("%s rx data:\n",info->device_name);
d12341f9 3819
1da177e4
LT		 3820 while(count) {
3821 if (count > 16)
3822 linecount = 16;
3823 else
3824 linecount = count;
d12341f9 3825
1da177e4
LT		 3826 for(i=0;i<linecount;i++)
3827 printk("%02X ",(unsigned char)data[i]);
3828 for(;i<17;i++)
3829 printk(" ");
3830 for(i=0;i<linecount;i++) {
3831 if (data[i]>=040 && data[i]<=0176)
3832 printk("%c",data[i]);
3833 else
3834 printk(".");
3835 }
3836 printk("\n");
d12341f9 3837
1da177e4
LT		 3838 data += linecount;
3839 count -= linecount;
3840 }
3841}
3842
3843/* HDLC frame time out
3844 * update stats and do tx completion processing
3845 */
cdaad343 3846static void tx_timeout(unsigned long context)
1da177e4
LT		 3847{
3848 MGSLPC_INFO *info = (MGSLPC_INFO*)context;
3849 unsigned long flags;
d12341f9 3850
1da177e4
LT		 3851 if ( debug_level >= DEBUG_LEVEL_INFO )
3852 printk( "%s(%d):tx_timeout(%s)\n",
3853 __FILE__,__LINE__,info->device_name);
3854 if(info->tx_active &&
3855 info->params.mode == MGSL_MODE_HDLC) {
3856 info->icount.txtimeout++;
3857 }
3858 spin_lock_irqsave(&info->lock,flags);
0fab6de0 3859 info->tx_active = false;
1da177e4
LT		 3860 info->tx_count = info->tx_put = info->tx_get = 0;
3861
3862 spin_unlock_irqrestore(&info->lock,flags);
d12341f9 3863
af69c7f9 3864#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3865 if (info->netcount)
3866 hdlcdev_tx_done(info);
3867 else
3868#endif
eeb46134
AC		 3869 {
3870 struct tty_struct *tty = tty_port_tty_get(&info->port);
3871 bh_transmit(info, tty);
3872 tty_kref_put(tty);
3873 }
1da177e4
LT		 3874}
3875
af69c7f9 3876#if SYNCLINK_GENERIC_HDLC
1da177e4
LT		 3877
3878/**
3879 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
3880 * set encoding and frame check sequence (FCS) options
3881 *
3882 * dev pointer to network device structure
3883 * encoding serial encoding setting
3884 * parity FCS setting
3885 *
3886 * returns 0 if success, otherwise error code
3887 */
3888static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
3889 unsigned short parity)
3890{
3891 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3892 struct tty_struct *tty;
1da177e4
LT		 3893 unsigned char new_encoding;
3894 unsigned short new_crctype;
3895
3896 /* return error if TTY interface open */
eeb46134 3897 if (info->port.count)
1da177e4
LT		 3898 return -EBUSY;
3899
3900 switch (encoding)
3901 {
3902 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
3903 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
3904 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
3905 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
3906 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
3907 default: return -EINVAL;
3908 }
3909
3910 switch (parity)
3911 {
3912 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
3913 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
3914 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
3915 default: return -EINVAL;
3916 }
3917
3918 info->params.encoding = new_encoding;
53b3531b 3919 info->params.crc_type = new_crctype;
1da177e4
LT		 3920
3921 /* if network interface up, reprogram hardware */
eeb46134
AC		 3922 if (info->netcount) {
3923 tty = tty_port_tty_get(&info->port);
3924 mgslpc_program_hw(info, tty);
3925 tty_kref_put(tty);
3926 }
1da177e4
LT		 3927
3928 return 0;
3929}
3930
3931/**
3932 * called by generic HDLC layer to send frame
3933 *
3934 * skb socket buffer containing HDLC frame
3935 * dev pointer to network device structure
1da177e4 3936 */
4c5d502d
SH		 3937static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
3938 struct net_device *dev)
1da177e4
LT		 3939{
3940 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 3941 unsigned long flags;
3942
3943 if (debug_level >= DEBUG_LEVEL_INFO)
3944 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
3945
3946 /* stop sending until this frame completes */
3947 netif_stop_queue(dev);
3948
3949 /* copy data to device buffers */
d626f62b 3950 skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
1da177e4
LT		 3951 info->tx_get = 0;
3952 info->tx_put = info->tx_count = skb->len;
3953
3954 /* update network statistics */
198191c4
KH		 3955 dev->stats.tx_packets++;
3956 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 3957
3958 /* done with socket buffer, so free it */
3959 dev_kfree_skb(skb);
3960
3961 /* save start time for transmit timeout detection */
3962 dev->trans_start = jiffies;
3963
3964 /* start hardware transmitter if necessary */
3965 spin_lock_irqsave(&info->lock,flags);
eeb46134
AC		 3966 if (!info->tx_active) {
3967 struct tty_struct *tty = tty_port_tty_get(&info->port);
3968 tx_start(info, tty);
3969 tty_kref_put(tty);
3970 }
1da177e4
LT		 3971 spin_unlock_irqrestore(&info->lock,flags);
3972
4c5d502d 3973 return NETDEV_TX_OK;
1da177e4
LT		 3974}
3975
3976/**
3977 * called by network layer when interface enabled
3978 * claim resources and initialize hardware
3979 *
3980 * dev pointer to network device structure
3981 *
3982 * returns 0 if success, otherwise error code
3983 */
3984static int hdlcdev_open(struct net_device *dev)
3985{
3986 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 3987 struct tty_struct *tty;
1da177e4
LT		 3988 int rc;
3989 unsigned long flags;
3990
3991 if (debug_level >= DEBUG_LEVEL_INFO)
3992 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
3993
3994 /* generic HDLC layer open processing */
3995 if ((rc = hdlc_open(dev)))
3996 return rc;
3997
3998 /* arbitrate between network and tty opens */
3999 spin_lock_irqsave(&info->netlock, flags);
eeb46134 4000 if (info->port.count != 0 || info->netcount != 0) {
1da177e4
LT		 4001 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
4002 spin_unlock_irqrestore(&info->netlock, flags);
4003 return -EBUSY;
4004 }
4005 info->netcount=1;
4006 spin_unlock_irqrestore(&info->netlock, flags);
4007
eeb46134 4008 tty = tty_port_tty_get(&info->port);
1da177e4 4009 /* claim resources and init adapter */
eeb46134
AC		 4010 if ((rc = startup(info, tty)) != 0) {
4011 tty_kref_put(tty);
1da177e4
LT		 4012 spin_lock_irqsave(&info->netlock, flags);
4013 info->netcount=0;
4014 spin_unlock_irqrestore(&info->netlock, flags);
4015 return rc;
4016 }
1da177e4
LT		 4017 /* assert DTR and RTS, apply hardware settings */
4018 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
eeb46134
AC		 4019 mgslpc_program_hw(info, tty);
4020 tty_kref_put(tty);
1da177e4
LT		 4021
4022 /* enable network layer transmit */
4023 dev->trans_start = jiffies;
4024 netif_start_queue(dev);
4025
4026 /* inform generic HDLC layer of current DCD status */
4027 spin_lock_irqsave(&info->lock, flags);
4028 get_signals(info);
4029 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 4030 if (info->serial_signals & SerialSignal_DCD)
4031 netif_carrier_on(dev);
4032 else
4033 netif_carrier_off(dev);
1da177e4
LT		 4034 return 0;
4035}
4036
4037/**
4038 * called by network layer when interface is disabled
4039 * shutdown hardware and release resources
4040 *
4041 * dev pointer to network device structure
4042 *
4043 * returns 0 if success, otherwise error code
4044 */
4045static int hdlcdev_close(struct net_device *dev)
4046{
4047 MGSLPC_INFO *info = dev_to_port(dev);
eeb46134 4048 struct tty_struct *tty = tty_port_tty_get(&info->port);
1da177e4
LT		 4049 unsigned long flags;
4050
4051 if (debug_level >= DEBUG_LEVEL_INFO)
4052 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
4053
4054 netif_stop_queue(dev);
4055
4056 /* shutdown adapter and release resources */
eeb46134
AC		 4057 shutdown(info, tty);
4058 tty_kref_put(tty);
1da177e4
LT		 4059 hdlc_close(dev);
4060
4061 spin_lock_irqsave(&info->netlock, flags);
4062 info->netcount=0;
4063 spin_unlock_irqrestore(&info->netlock, flags);
4064
4065 return 0;
4066}
4067
4068/**
4069 * called by network layer to process IOCTL call to network device
4070 *
4071 * dev pointer to network device structure
4072 * ifr pointer to network interface request structure
4073 * cmd IOCTL command code
4074 *
4075 * returns 0 if success, otherwise error code
4076 */
4077static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4078{
4079 const size_t size = sizeof(sync_serial_settings);
4080 sync_serial_settings new_line;
4081 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
4082 MGSLPC_INFO *info = dev_to_port(dev);
4083 unsigned int flags;
4084
4085 if (debug_level >= DEBUG_LEVEL_INFO)
4086 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
4087
4088 /* return error if TTY interface open */
eeb46134 4089 if (info->port.count)
1da177e4
LT		 4090 return -EBUSY;
4091
4092 if (cmd != SIOCWANDEV)
4093 return hdlc_ioctl(dev, ifr, cmd);
4094
5b917a14
VK		 4095 memset(&new_line, 0, size);
4096
1da177e4
LT		 4097 switch(ifr->ifr_settings.type) {
4098 case IF_GET_IFACE: /* return current sync_serial_settings */
4099
4100 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
4101 if (ifr->ifr_settings.size < size) {
4102 ifr->ifr_settings.size = size; /* data size wanted */
4103 return -ENOBUFS;
4104 }
4105
4106 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4107 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4108 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4109 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4110
4111 switch (flags){
4112 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4113 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4114 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4115 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4116 default: new_line.clock_type = CLOCK_DEFAULT;
4117 }
4118
4119 new_line.clock_rate = info->params.clock_speed;
4120 new_line.loopback = info->params.loopback ? 1:0;
4121
4122 if (copy_to_user(line, &new_line, size))
4123 return -EFAULT;
4124 return 0;
4125
4126 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
4127
4128 if(!capable(CAP_NET_ADMIN))
4129 return -EPERM;
4130 if (copy_from_user(&new_line, line, size))
4131 return -EFAULT;
4132
4133 switch (new_line.clock_type)
4134 {
4135 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
4136 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
4137 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
4138 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
4139 case CLOCK_DEFAULT: flags = info->params.flags &
4140 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4141 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4142 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4143 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
4144 default: return -EINVAL;
4145 }
4146
4147 if (new_line.loopback != 0 && new_line.loopback != 1)
4148 return -EINVAL;
4149
4150 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
4151 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
4152 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
4153 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
4154 info->params.flags |= flags;
4155
4156 info->params.loopback = new_line.loopback;
4157
4158 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
4159 info->params.clock_speed = new_line.clock_rate;
4160 else
4161 info->params.clock_speed = 0;
4162
4163 /* if network interface up, reprogram hardware */
eeb46134
AC		 4164 if (info->netcount) {
4165 struct tty_struct *tty = tty_port_tty_get(&info->port);
4166 mgslpc_program_hw(info, tty);
4167 tty_kref_put(tty);
4168 }
1da177e4
LT		 4169 return 0;
4170
4171 default:
4172 return hdlc_ioctl(dev, ifr, cmd);
4173 }
4174}
4175
4176/**
4177 * called by network layer when transmit timeout is detected
4178 *
4179 * dev pointer to network device structure
4180 */
4181static void hdlcdev_tx_timeout(struct net_device *dev)
4182{
4183 MGSLPC_INFO *info = dev_to_port(dev);
1da177e4
LT		 4184 unsigned long flags;
4185
4186 if (debug_level >= DEBUG_LEVEL_INFO)
4187 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
4188
198191c4
KH		 4189 dev->stats.tx_errors++;
4190 dev->stats.tx_aborted_errors++;
1da177e4
LT		 4191
4192 spin_lock_irqsave(&info->lock,flags);
4193 tx_stop(info);
4194 spin_unlock_irqrestore(&info->lock,flags);
4195
4196 netif_wake_queue(dev);
4197}
4198
4199/**
4200 * called by device driver when transmit completes
4201 * reenable network layer transmit if stopped
4202 *
4203 * info pointer to device instance information
4204 */
4205static void hdlcdev_tx_done(MGSLPC_INFO *info)
4206{
4207 if (netif_queue_stopped(info->netdev))
4208 netif_wake_queue(info->netdev);
4209}
4210
4211/**
4212 * called by device driver when frame received
4213 * pass frame to network layer
4214 *
4215 * info pointer to device instance information
4216 * buf pointer to buffer contianing frame data
4217 * size count of data bytes in buf
4218 */
4219static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
4220{
4221 struct sk_buff *skb = dev_alloc_skb(size);
4222 struct net_device *dev = info->netdev;
1da177e4
LT		 4223
4224 if (debug_level >= DEBUG_LEVEL_INFO)
4225 printk("hdlcdev_rx(%s)\n",dev->name);
4226
4227 if (skb == NULL) {
4228 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
198191c4 4229 dev->stats.rx_dropped++;
1da177e4
LT		 4230 return;
4231 }
4232
198191c4 4233 memcpy(skb_put(skb, size), buf, size);
1da177e4 4234
198191c4 4235 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4 4236
198191c4
KH		 4237 dev->stats.rx_packets++;
4238 dev->stats.rx_bytes += size;
1da177e4
LT		 4239
4240 netif_rx(skb);
1da177e4
LT		 4241}
4242
991990a1
KH		 4243static const struct net_device_ops hdlcdev_ops = {
4244 .ndo_open = hdlcdev_open,
4245 .ndo_stop = hdlcdev_close,
4246 .ndo_change_mtu = hdlc_change_mtu,
4247 .ndo_start_xmit = hdlc_start_xmit,
4248 .ndo_do_ioctl = hdlcdev_ioctl,
4249 .ndo_tx_timeout = hdlcdev_tx_timeout,
4250};
4251
1da177e4
LT		 4252/**
4253 * called by device driver when adding device instance
4254 * do generic HDLC initialization
4255 *
4256 * info pointer to device instance information
4257 *
4258 * returns 0 if success, otherwise error code
4259 */
4260static int hdlcdev_init(MGSLPC_INFO *info)
4261{
4262 int rc;
4263 struct net_device *dev;
4264 hdlc_device *hdlc;
4265
4266 /* allocate and initialize network and HDLC layer objects */
4267
4268 if (!(dev = alloc_hdlcdev(info))) {
4269 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
4270 return -ENOMEM;
4271 }
4272
4273 /* for network layer reporting purposes only */
4274 dev->base_addr = info->io_base;
4275 dev->irq = info->irq_level;
4276
4277 /* network layer callbacks and settings */
991990a1
KH		 4278 dev->netdev_ops = &hdlcdev_ops;
4279 dev->watchdog_timeo = 10 * HZ;
1da177e4
LT		 4280 dev->tx_queue_len = 50;
4281
4282 /* generic HDLC layer callbacks and settings */
4283 hdlc = dev_to_hdlc(dev);
4284 hdlc->attach = hdlcdev_attach;
4285 hdlc->xmit = hdlcdev_xmit;
4286
4287 /* register objects with HDLC layer */
4288 if ((rc = register_hdlc_device(dev))) {
4289 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
4290 free_netdev(dev);
4291 return rc;
4292 }
4293
4294 info->netdev = dev;
4295 return 0;
4296}
4297
4298/**
4299 * called by device driver when removing device instance
4300 * do generic HDLC cleanup
4301 *
4302 * info pointer to device instance information
4303 */
4304static void hdlcdev_exit(MGSLPC_INFO *info)
4305{
4306 unregister_hdlc_device(info->netdev);
4307 free_netdev(info->netdev);
4308 info->netdev = NULL;
4309}
4310
4311#endif /* CONFIG_HDLC */
4312
Linux kernel - Deliverables
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