Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * RocketPort device driver for Linux | |
3 | * | |
4 | * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000. | |
5 | * | |
6 | * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of the | |
11 | * License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Kernel Synchronization: | |
25 | * | |
26 | * This driver has 2 kernel control paths - exception handlers (calls into the driver | |
27 | * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts | |
28 | * are not used. | |
29 | * | |
30 | * Critical data: | |
31 | * - rp_table[], accessed through passed "info" pointers, is a global (static) array of | |
32 | * serial port state information and the xmit_buf circular buffer. Protected by | |
33 | * a per port spinlock. | |
34 | * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there | |
35 | * is data to be transmitted. Protected by atomic bit operations. | |
36 | * - rp_num_ports, int indicating number of open ports, protected by atomic operations. | |
37 | * | |
38 | * rp_write() and rp_write_char() functions use a per port semaphore to protect against | |
39 | * simultaneous access to the same port by more than one process. | |
40 | */ | |
41 | ||
42 | /****** Defines ******/ | |
43 | #ifdef PCI_NUM_RESOURCES | |
44 | #define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start) | |
45 | #else | |
46 | #define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r]) | |
47 | #endif | |
48 | ||
49 | #define ROCKET_PARANOIA_CHECK | |
50 | #define ROCKET_DISABLE_SIMUSAGE | |
51 | ||
52 | #undef ROCKET_SOFT_FLOW | |
53 | #undef ROCKET_DEBUG_OPEN | |
54 | #undef ROCKET_DEBUG_INTR | |
55 | #undef ROCKET_DEBUG_WRITE | |
56 | #undef ROCKET_DEBUG_FLOW | |
57 | #undef ROCKET_DEBUG_THROTTLE | |
58 | #undef ROCKET_DEBUG_WAIT_UNTIL_SENT | |
59 | #undef ROCKET_DEBUG_RECEIVE | |
60 | #undef ROCKET_DEBUG_HANGUP | |
61 | #undef REV_PCI_ORDER | |
62 | #undef ROCKET_DEBUG_IO | |
63 | ||
64 | #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */ | |
65 | ||
66 | /****** Kernel includes ******/ | |
67 | ||
68 | #ifdef MODVERSIONS | |
69 | #include <config/modversions.h> | |
70 | #endif | |
71 | ||
72 | #include <linux/module.h> | |
73 | #include <linux/errno.h> | |
74 | #include <linux/major.h> | |
75 | #include <linux/kernel.h> | |
76 | #include <linux/signal.h> | |
77 | #include <linux/slab.h> | |
78 | #include <linux/mm.h> | |
79 | #include <linux/sched.h> | |
80 | #include <linux/timer.h> | |
81 | #include <linux/interrupt.h> | |
82 | #include <linux/tty.h> | |
83 | #include <linux/tty_driver.h> | |
84 | #include <linux/tty_flip.h> | |
85 | #include <linux/string.h> | |
86 | #include <linux/fcntl.h> | |
87 | #include <linux/ptrace.h> | |
88 | #include <linux/ioport.h> | |
89 | #include <linux/delay.h> | |
90 | #include <linux/wait.h> | |
91 | #include <linux/pci.h> | |
92 | #include <asm/uaccess.h> | |
93 | #include <asm/atomic.h> | |
94 | #include <linux/bitops.h> | |
95 | #include <linux/spinlock.h> | |
96 | #include <asm/semaphore.h> | |
97 | #include <linux/init.h> | |
98 | ||
99 | /****** RocketPort includes ******/ | |
100 | ||
101 | #include "rocket_int.h" | |
102 | #include "rocket.h" | |
103 | ||
104 | #define ROCKET_VERSION "2.09" | |
105 | #define ROCKET_DATE "12-June-2003" | |
106 | ||
107 | /****** RocketPort Local Variables ******/ | |
108 | ||
109 | static struct tty_driver *rocket_driver; | |
110 | ||
111 | static struct rocket_version driver_version = { | |
112 | ROCKET_VERSION, ROCKET_DATE | |
113 | }; | |
114 | ||
115 | static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */ | |
116 | static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */ | |
117 | /* eg. Bit 0 indicates port 0 has xmit data, ... */ | |
118 | static atomic_t rp_num_ports_open; /* Number of serial ports open */ | |
119 | static struct timer_list rocket_timer; | |
120 | ||
121 | static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */ | |
122 | static unsigned long board2; | |
123 | static unsigned long board3; | |
124 | static unsigned long board4; | |
125 | static unsigned long controller; | |
126 | static int support_low_speed; | |
127 | static unsigned long modem1; | |
128 | static unsigned long modem2; | |
129 | static unsigned long modem3; | |
130 | static unsigned long modem4; | |
131 | static unsigned long pc104_1[8]; | |
132 | static unsigned long pc104_2[8]; | |
133 | static unsigned long pc104_3[8]; | |
134 | static unsigned long pc104_4[8]; | |
135 | static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 }; | |
136 | ||
137 | static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */ | |
138 | static unsigned long rcktpt_io_addr[NUM_BOARDS]; | |
139 | static int rcktpt_type[NUM_BOARDS]; | |
140 | static int is_PCI[NUM_BOARDS]; | |
141 | static rocketModel_t rocketModel[NUM_BOARDS]; | |
142 | static int max_board; | |
143 | ||
144 | /* | |
145 | * The following arrays define the interrupt bits corresponding to each AIOP. | |
146 | * These bits are different between the ISA and regular PCI boards and the | |
147 | * Universal PCI boards. | |
148 | */ | |
149 | ||
150 | static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = { | |
151 | AIOP_INTR_BIT_0, | |
152 | AIOP_INTR_BIT_1, | |
153 | AIOP_INTR_BIT_2, | |
154 | AIOP_INTR_BIT_3 | |
155 | }; | |
156 | ||
157 | static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = { | |
158 | UPCI_AIOP_INTR_BIT_0, | |
159 | UPCI_AIOP_INTR_BIT_1, | |
160 | UPCI_AIOP_INTR_BIT_2, | |
161 | UPCI_AIOP_INTR_BIT_3 | |
162 | }; | |
163 | ||
f15313bf AB |
164 | static Byte_t RData[RDATASIZE] = { |
165 | 0x00, 0x09, 0xf6, 0x82, | |
166 | 0x02, 0x09, 0x86, 0xfb, | |
167 | 0x04, 0x09, 0x00, 0x0a, | |
168 | 0x06, 0x09, 0x01, 0x0a, | |
169 | 0x08, 0x09, 0x8a, 0x13, | |
170 | 0x0a, 0x09, 0xc5, 0x11, | |
171 | 0x0c, 0x09, 0x86, 0x85, | |
172 | 0x0e, 0x09, 0x20, 0x0a, | |
173 | 0x10, 0x09, 0x21, 0x0a, | |
174 | 0x12, 0x09, 0x41, 0xff, | |
175 | 0x14, 0x09, 0x82, 0x00, | |
176 | 0x16, 0x09, 0x82, 0x7b, | |
177 | 0x18, 0x09, 0x8a, 0x7d, | |
178 | 0x1a, 0x09, 0x88, 0x81, | |
179 | 0x1c, 0x09, 0x86, 0x7a, | |
180 | 0x1e, 0x09, 0x84, 0x81, | |
181 | 0x20, 0x09, 0x82, 0x7c, | |
182 | 0x22, 0x09, 0x0a, 0x0a | |
183 | }; | |
184 | ||
185 | static Byte_t RRegData[RREGDATASIZE] = { | |
186 | 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */ | |
187 | 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */ | |
188 | 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */ | |
189 | 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */ | |
190 | 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */ | |
191 | 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */ | |
192 | 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */ | |
193 | 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */ | |
194 | 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */ | |
195 | 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */ | |
196 | 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */ | |
197 | 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */ | |
198 | 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */ | |
199 | }; | |
200 | ||
201 | static CONTROLLER_T sController[CTL_SIZE] = { | |
202 | {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, | |
203 | {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}, | |
204 | {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, | |
205 | {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}, | |
206 | {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, | |
207 | {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}, | |
208 | {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0}, | |
209 | {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}} | |
210 | }; | |
211 | ||
212 | static Byte_t sBitMapClrTbl[8] = { | |
213 | 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f | |
214 | }; | |
215 | ||
216 | static Byte_t sBitMapSetTbl[8] = { | |
217 | 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 | |
218 | }; | |
219 | ||
220 | static int sClockPrescale = 0x14; | |
221 | ||
1da177e4 LT |
222 | /* |
223 | * Line number is the ttySIx number (x), the Minor number. We | |
224 | * assign them sequentially, starting at zero. The following | |
225 | * array keeps track of the line number assigned to a given board/aiop/channel. | |
226 | */ | |
227 | static unsigned char lineNumbers[MAX_RP_PORTS]; | |
228 | static unsigned long nextLineNumber; | |
229 | ||
230 | /***** RocketPort Static Prototypes *********/ | |
231 | static int __init init_ISA(int i); | |
232 | static void rp_wait_until_sent(struct tty_struct *tty, int timeout); | |
233 | static void rp_flush_buffer(struct tty_struct *tty); | |
234 | static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model); | |
235 | static unsigned char GetLineNumber(int ctrl, int aiop, int ch); | |
236 | static unsigned char SetLineNumber(int ctrl, int aiop, int ch); | |
237 | static void rp_start(struct tty_struct *tty); | |
f15313bf AB |
238 | static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum, |
239 | int ChanNum); | |
240 | static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode); | |
241 | static void sFlushRxFIFO(CHANNEL_T * ChP); | |
242 | static void sFlushTxFIFO(CHANNEL_T * ChP); | |
243 | static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags); | |
244 | static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags); | |
245 | static void sModemReset(CONTROLLER_T * CtlP, int chan, int on); | |
246 | static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on); | |
247 | static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data); | |
248 | static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum, | |
249 | ByteIO_t * AiopIOList, int AiopIOListSize, | |
250 | WordIO_t ConfigIO, int IRQNum, Byte_t Frequency, | |
251 | int PeriodicOnly, int altChanRingIndicator, | |
252 | int UPCIRingInd); | |
253 | static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO, | |
254 | ByteIO_t * AiopIOList, int AiopIOListSize, | |
255 | int IRQNum, Byte_t Frequency, int PeriodicOnly); | |
256 | static int sReadAiopID(ByteIO_t io); | |
257 | static int sReadAiopNumChan(WordIO_t io); | |
1da177e4 | 258 | |
1da177e4 LT |
259 | MODULE_AUTHOR("Theodore Ts'o"); |
260 | MODULE_DESCRIPTION("Comtrol RocketPort driver"); | |
261 | module_param(board1, ulong, 0); | |
262 | MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1"); | |
263 | module_param(board2, ulong, 0); | |
264 | MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2"); | |
265 | module_param(board3, ulong, 0); | |
266 | MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3"); | |
267 | module_param(board4, ulong, 0); | |
268 | MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4"); | |
269 | module_param(controller, ulong, 0); | |
270 | MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller"); | |
271 | module_param(support_low_speed, bool, 0); | |
272 | MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud"); | |
273 | module_param(modem1, ulong, 0); | |
274 | MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem"); | |
275 | module_param(modem2, ulong, 0); | |
276 | MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem"); | |
277 | module_param(modem3, ulong, 0); | |
278 | MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem"); | |
279 | module_param(modem4, ulong, 0); | |
280 | MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem"); | |
281 | module_param_array(pc104_1, ulong, NULL, 0); | |
282 | MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,..."); | |
283 | module_param_array(pc104_2, ulong, NULL, 0); | |
284 | MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,..."); | |
285 | module_param_array(pc104_3, ulong, NULL, 0); | |
286 | MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,..."); | |
287 | module_param_array(pc104_4, ulong, NULL, 0); | |
288 | MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,..."); | |
289 | ||
d269cdd0 | 290 | static int rp_init(void); |
1da177e4 LT |
291 | static void rp_cleanup_module(void); |
292 | ||
293 | module_init(rp_init); | |
294 | module_exit(rp_cleanup_module); | |
295 | ||
1da177e4 | 296 | |
1da177e4 | 297 | MODULE_LICENSE("Dual BSD/GPL"); |
1da177e4 LT |
298 | |
299 | /*************************************************************************/ | |
300 | /* Module code starts here */ | |
301 | ||
302 | static inline int rocket_paranoia_check(struct r_port *info, | |
303 | const char *routine) | |
304 | { | |
305 | #ifdef ROCKET_PARANOIA_CHECK | |
306 | if (!info) | |
307 | return 1; | |
308 | if (info->magic != RPORT_MAGIC) { | |
309 | printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n", | |
310 | routine); | |
311 | return 1; | |
312 | } | |
313 | #endif | |
314 | return 0; | |
315 | } | |
316 | ||
317 | ||
318 | /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals | |
319 | * that receive data is present on a serial port. Pulls data from FIFO, moves it into the | |
320 | * tty layer. | |
321 | */ | |
322 | static void rp_do_receive(struct r_port *info, | |
323 | struct tty_struct *tty, | |
324 | CHANNEL_t * cp, unsigned int ChanStatus) | |
325 | { | |
326 | unsigned int CharNStat; | |
327 | int ToRecv, wRecv, space = 0, count; | |
328 | unsigned char *cbuf; | |
329 | char *fbuf; | |
330 | struct tty_ldisc *ld; | |
331 | ||
332 | ld = tty_ldisc_ref(tty); | |
333 | ||
334 | ToRecv = sGetRxCnt(cp); | |
335 | if (ld) | |
336 | space = ld->receive_room(tty); | |
337 | if (space > 2 * TTY_FLIPBUF_SIZE) | |
338 | space = 2 * TTY_FLIPBUF_SIZE; | |
339 | cbuf = tty->flip.char_buf; | |
340 | fbuf = tty->flip.flag_buf; | |
341 | count = 0; | |
342 | #ifdef ROCKET_DEBUG_INTR | |
343 | printk(KERN_INFO "rp_do_receive(%d, %d)...", ToRecv, space); | |
344 | #endif | |
345 | ||
346 | /* | |
347 | * determine how many we can actually read in. If we can't | |
348 | * read any in then we have a software overrun condition. | |
349 | */ | |
350 | if (ToRecv > space) | |
351 | ToRecv = space; | |
352 | ||
353 | if (ToRecv <= 0) | |
a1287ba1 | 354 | goto done; |
1da177e4 LT |
355 | |
356 | /* | |
357 | * if status indicates there are errored characters in the | |
358 | * FIFO, then enter status mode (a word in FIFO holds | |
359 | * character and status). | |
360 | */ | |
361 | if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) { | |
362 | if (!(ChanStatus & STATMODE)) { | |
363 | #ifdef ROCKET_DEBUG_RECEIVE | |
364 | printk(KERN_INFO "Entering STATMODE..."); | |
365 | #endif | |
366 | ChanStatus |= STATMODE; | |
367 | sEnRxStatusMode(cp); | |
368 | } | |
369 | } | |
370 | ||
371 | /* | |
372 | * if we previously entered status mode, then read down the | |
373 | * FIFO one word at a time, pulling apart the character and | |
374 | * the status. Update error counters depending on status | |
375 | */ | |
376 | if (ChanStatus & STATMODE) { | |
377 | #ifdef ROCKET_DEBUG_RECEIVE | |
378 | printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask, | |
379 | info->read_status_mask); | |
380 | #endif | |
381 | while (ToRecv) { | |
382 | CharNStat = sInW(sGetTxRxDataIO(cp)); | |
383 | #ifdef ROCKET_DEBUG_RECEIVE | |
384 | printk(KERN_INFO "%x...", CharNStat); | |
385 | #endif | |
386 | if (CharNStat & STMBREAKH) | |
387 | CharNStat &= ~(STMFRAMEH | STMPARITYH); | |
388 | if (CharNStat & info->ignore_status_mask) { | |
389 | ToRecv--; | |
390 | continue; | |
391 | } | |
392 | CharNStat &= info->read_status_mask; | |
393 | if (CharNStat & STMBREAKH) | |
394 | *fbuf++ = TTY_BREAK; | |
395 | else if (CharNStat & STMPARITYH) | |
396 | *fbuf++ = TTY_PARITY; | |
397 | else if (CharNStat & STMFRAMEH) | |
398 | *fbuf++ = TTY_FRAME; | |
399 | else if (CharNStat & STMRCVROVRH) | |
400 | *fbuf++ = TTY_OVERRUN; | |
401 | else | |
402 | *fbuf++ = 0; | |
403 | *cbuf++ = CharNStat & 0xff; | |
404 | count++; | |
405 | ToRecv--; | |
406 | } | |
407 | ||
408 | /* | |
409 | * after we've emptied the FIFO in status mode, turn | |
410 | * status mode back off | |
411 | */ | |
412 | if (sGetRxCnt(cp) == 0) { | |
413 | #ifdef ROCKET_DEBUG_RECEIVE | |
414 | printk(KERN_INFO "Status mode off.\n"); | |
415 | #endif | |
416 | sDisRxStatusMode(cp); | |
417 | } | |
418 | } else { | |
419 | /* | |
420 | * we aren't in status mode, so read down the FIFO two | |
421 | * characters at time by doing repeated word IO | |
422 | * transfer. | |
423 | */ | |
424 | wRecv = ToRecv >> 1; | |
425 | if (wRecv) | |
426 | sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv); | |
427 | if (ToRecv & 1) | |
428 | cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp)); | |
429 | memset(fbuf, 0, ToRecv); | |
430 | cbuf += ToRecv; | |
431 | fbuf += ToRecv; | |
432 | count += ToRecv; | |
433 | } | |
434 | /* Push the data up to the tty layer */ | |
435 | ld->receive_buf(tty, tty->flip.char_buf, tty->flip.flag_buf, count); | |
a1287ba1 | 436 | done: |
1da177e4 LT |
437 | tty_ldisc_deref(ld); |
438 | } | |
439 | ||
440 | /* | |
441 | * Serial port transmit data function. Called from the timer polling loop as a | |
442 | * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready | |
443 | * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is | |
444 | * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks. | |
445 | */ | |
446 | static void rp_do_transmit(struct r_port *info) | |
447 | { | |
448 | int c; | |
449 | CHANNEL_t *cp = &info->channel; | |
450 | struct tty_struct *tty; | |
451 | unsigned long flags; | |
452 | ||
453 | #ifdef ROCKET_DEBUG_INTR | |
454 | printk(KERN_INFO "rp_do_transmit "); | |
455 | #endif | |
456 | if (!info) | |
457 | return; | |
458 | if (!info->tty) { | |
459 | printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n"); | |
460 | clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); | |
461 | return; | |
462 | } | |
463 | ||
464 | spin_lock_irqsave(&info->slock, flags); | |
465 | tty = info->tty; | |
466 | info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp); | |
467 | ||
468 | /* Loop sending data to FIFO until done or FIFO full */ | |
469 | while (1) { | |
470 | if (tty->stopped || tty->hw_stopped) | |
471 | break; | |
472 | c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail)); | |
473 | if (c <= 0 || info->xmit_fifo_room <= 0) | |
474 | break; | |
475 | sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2); | |
476 | if (c & 1) | |
477 | sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]); | |
478 | info->xmit_tail += c; | |
479 | info->xmit_tail &= XMIT_BUF_SIZE - 1; | |
480 | info->xmit_cnt -= c; | |
481 | info->xmit_fifo_room -= c; | |
482 | #ifdef ROCKET_DEBUG_INTR | |
483 | printk(KERN_INFO "tx %d chars...", c); | |
484 | #endif | |
485 | } | |
486 | ||
487 | if (info->xmit_cnt == 0) | |
488 | clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); | |
489 | ||
490 | if (info->xmit_cnt < WAKEUP_CHARS) { | |
491 | tty_wakeup(tty); | |
492 | wake_up_interruptible(&tty->write_wait); | |
493 | #ifdef ROCKETPORT_HAVE_POLL_WAIT | |
494 | wake_up_interruptible(&tty->poll_wait); | |
495 | #endif | |
496 | } | |
497 | ||
498 | spin_unlock_irqrestore(&info->slock, flags); | |
499 | ||
500 | #ifdef ROCKET_DEBUG_INTR | |
501 | printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head, | |
502 | info->xmit_tail, info->xmit_fifo_room); | |
503 | #endif | |
504 | } | |
505 | ||
506 | /* | |
507 | * Called when a serial port signals it has read data in it's RX FIFO. | |
508 | * It checks what interrupts are pending and services them, including | |
509 | * receiving serial data. | |
510 | */ | |
511 | static void rp_handle_port(struct r_port *info) | |
512 | { | |
513 | CHANNEL_t *cp; | |
514 | struct tty_struct *tty; | |
515 | unsigned int IntMask, ChanStatus; | |
516 | ||
517 | if (!info) | |
518 | return; | |
519 | ||
520 | if ((info->flags & ROCKET_INITIALIZED) == 0) { | |
521 | printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n"); | |
522 | return; | |
523 | } | |
524 | if (!info->tty) { | |
525 | printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n"); | |
526 | return; | |
527 | } | |
528 | cp = &info->channel; | |
529 | tty = info->tty; | |
530 | ||
531 | IntMask = sGetChanIntID(cp) & info->intmask; | |
532 | #ifdef ROCKET_DEBUG_INTR | |
533 | printk(KERN_INFO "rp_interrupt %02x...", IntMask); | |
534 | #endif | |
535 | ChanStatus = sGetChanStatus(cp); | |
536 | if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */ | |
537 | rp_do_receive(info, tty, cp, ChanStatus); | |
538 | } | |
539 | if (IntMask & DELTA_CD) { /* CD change */ | |
540 | #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP)) | |
541 | printk(KERN_INFO "ttyR%d CD now %s...", info->line, | |
542 | (ChanStatus & CD_ACT) ? "on" : "off"); | |
543 | #endif | |
544 | if (!(ChanStatus & CD_ACT) && info->cd_status) { | |
545 | #ifdef ROCKET_DEBUG_HANGUP | |
546 | printk(KERN_INFO "CD drop, calling hangup.\n"); | |
547 | #endif | |
548 | tty_hangup(tty); | |
549 | } | |
550 | info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0; | |
551 | wake_up_interruptible(&info->open_wait); | |
552 | } | |
553 | #ifdef ROCKET_DEBUG_INTR | |
554 | if (IntMask & DELTA_CTS) { /* CTS change */ | |
555 | printk(KERN_INFO "CTS change...\n"); | |
556 | } | |
557 | if (IntMask & DELTA_DSR) { /* DSR change */ | |
558 | printk(KERN_INFO "DSR change...\n"); | |
559 | } | |
560 | #endif | |
561 | } | |
562 | ||
563 | /* | |
564 | * The top level polling routine. Repeats every 1/100 HZ (10ms). | |
565 | */ | |
566 | static void rp_do_poll(unsigned long dummy) | |
567 | { | |
568 | CONTROLLER_t *ctlp; | |
569 | int ctrl, aiop, ch, line, i; | |
570 | unsigned int xmitmask; | |
571 | unsigned int CtlMask; | |
572 | unsigned char AiopMask; | |
573 | Word_t bit; | |
574 | ||
575 | /* Walk through all the boards (ctrl's) */ | |
576 | for (ctrl = 0; ctrl < max_board; ctrl++) { | |
577 | if (rcktpt_io_addr[ctrl] <= 0) | |
578 | continue; | |
579 | ||
580 | /* Get a ptr to the board's control struct */ | |
581 | ctlp = sCtlNumToCtlPtr(ctrl); | |
582 | ||
583 | /* Get the interupt status from the board */ | |
584 | #ifdef CONFIG_PCI | |
585 | if (ctlp->BusType == isPCI) | |
586 | CtlMask = sPCIGetControllerIntStatus(ctlp); | |
587 | else | |
588 | #endif | |
589 | CtlMask = sGetControllerIntStatus(ctlp); | |
590 | ||
591 | /* Check if any AIOP read bits are set */ | |
592 | for (aiop = 0; CtlMask; aiop++) { | |
593 | bit = ctlp->AiopIntrBits[aiop]; | |
594 | if (CtlMask & bit) { | |
595 | CtlMask &= ~bit; | |
596 | AiopMask = sGetAiopIntStatus(ctlp, aiop); | |
597 | ||
598 | /* Check if any port read bits are set */ | |
599 | for (ch = 0; AiopMask; AiopMask >>= 1, ch++) { | |
600 | if (AiopMask & 1) { | |
601 | ||
602 | /* Get the line number (/dev/ttyRx number). */ | |
603 | /* Read the data from the port. */ | |
604 | line = GetLineNumber(ctrl, aiop, ch); | |
605 | rp_handle_port(rp_table[line]); | |
606 | } | |
607 | } | |
608 | } | |
609 | } | |
610 | ||
611 | xmitmask = xmit_flags[ctrl]; | |
612 | ||
613 | /* | |
614 | * xmit_flags contains bit-significant flags, indicating there is data | |
615 | * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port | |
616 | * 1, ... (32 total possible). The variable i has the aiop and ch | |
617 | * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc). | |
618 | */ | |
619 | if (xmitmask) { | |
620 | for (i = 0; i < rocketModel[ctrl].numPorts; i++) { | |
621 | if (xmitmask & (1 << i)) { | |
622 | aiop = (i & 0x18) >> 3; | |
623 | ch = i & 0x07; | |
624 | line = GetLineNumber(ctrl, aiop, ch); | |
625 | rp_do_transmit(rp_table[line]); | |
626 | } | |
627 | } | |
628 | } | |
629 | } | |
630 | ||
631 | /* | |
632 | * Reset the timer so we get called at the next clock tick (10ms). | |
633 | */ | |
634 | if (atomic_read(&rp_num_ports_open)) | |
635 | mod_timer(&rocket_timer, jiffies + POLL_PERIOD); | |
636 | } | |
637 | ||
638 | /* | |
639 | * Initializes the r_port structure for a port, as well as enabling the port on | |
640 | * the board. | |
641 | * Inputs: board, aiop, chan numbers | |
642 | */ | |
643 | static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev) | |
644 | { | |
645 | unsigned rocketMode; | |
646 | struct r_port *info; | |
647 | int line; | |
648 | CONTROLLER_T *ctlp; | |
649 | ||
650 | /* Get the next available line number */ | |
651 | line = SetLineNumber(board, aiop, chan); | |
652 | ||
653 | ctlp = sCtlNumToCtlPtr(board); | |
654 | ||
655 | /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */ | |
656 | info = kmalloc(sizeof (struct r_port), GFP_KERNEL); | |
657 | if (!info) { | |
658 | printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line); | |
659 | return; | |
660 | } | |
661 | memset(info, 0, sizeof (struct r_port)); | |
662 | ||
663 | info->magic = RPORT_MAGIC; | |
664 | info->line = line; | |
665 | info->ctlp = ctlp; | |
666 | info->board = board; | |
667 | info->aiop = aiop; | |
668 | info->chan = chan; | |
669 | info->closing_wait = 3000; | |
670 | info->close_delay = 50; | |
671 | init_waitqueue_head(&info->open_wait); | |
672 | init_waitqueue_head(&info->close_wait); | |
673 | info->flags &= ~ROCKET_MODE_MASK; | |
674 | switch (pc104[board][line]) { | |
675 | case 422: | |
676 | info->flags |= ROCKET_MODE_RS422; | |
677 | break; | |
678 | case 485: | |
679 | info->flags |= ROCKET_MODE_RS485; | |
680 | break; | |
681 | case 232: | |
682 | default: | |
683 | info->flags |= ROCKET_MODE_RS232; | |
684 | break; | |
685 | } | |
686 | ||
687 | info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR; | |
688 | if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) { | |
689 | printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan); | |
690 | kfree(info); | |
691 | return; | |
692 | } | |
693 | ||
694 | rocketMode = info->flags & ROCKET_MODE_MASK; | |
695 | ||
696 | if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485)) | |
697 | sEnRTSToggle(&info->channel); | |
698 | else | |
699 | sDisRTSToggle(&info->channel); | |
700 | ||
701 | if (ctlp->boardType == ROCKET_TYPE_PC104) { | |
702 | switch (rocketMode) { | |
703 | case ROCKET_MODE_RS485: | |
704 | sSetInterfaceMode(&info->channel, InterfaceModeRS485); | |
705 | break; | |
706 | case ROCKET_MODE_RS422: | |
707 | sSetInterfaceMode(&info->channel, InterfaceModeRS422); | |
708 | break; | |
709 | case ROCKET_MODE_RS232: | |
710 | default: | |
711 | if (info->flags & ROCKET_RTS_TOGGLE) | |
712 | sSetInterfaceMode(&info->channel, InterfaceModeRS232T); | |
713 | else | |
714 | sSetInterfaceMode(&info->channel, InterfaceModeRS232); | |
715 | break; | |
716 | } | |
717 | } | |
718 | spin_lock_init(&info->slock); | |
719 | sema_init(&info->write_sem, 1); | |
720 | rp_table[line] = info; | |
721 | if (pci_dev) | |
722 | tty_register_device(rocket_driver, line, &pci_dev->dev); | |
723 | } | |
724 | ||
725 | /* | |
726 | * Configures a rocketport port according to its termio settings. Called from | |
727 | * user mode into the driver (exception handler). *info CD manipulation is spinlock protected. | |
728 | */ | |
729 | static void configure_r_port(struct r_port *info, | |
730 | struct termios *old_termios) | |
731 | { | |
732 | unsigned cflag; | |
733 | unsigned long flags; | |
734 | unsigned rocketMode; | |
735 | int bits, baud, divisor; | |
736 | CHANNEL_t *cp; | |
737 | ||
738 | if (!info->tty || !info->tty->termios) | |
739 | return; | |
740 | cp = &info->channel; | |
741 | cflag = info->tty->termios->c_cflag; | |
742 | ||
743 | /* Byte size and parity */ | |
744 | if ((cflag & CSIZE) == CS8) { | |
745 | sSetData8(cp); | |
746 | bits = 10; | |
747 | } else { | |
748 | sSetData7(cp); | |
749 | bits = 9; | |
750 | } | |
751 | if (cflag & CSTOPB) { | |
752 | sSetStop2(cp); | |
753 | bits++; | |
754 | } else { | |
755 | sSetStop1(cp); | |
756 | } | |
757 | ||
758 | if (cflag & PARENB) { | |
759 | sEnParity(cp); | |
760 | bits++; | |
761 | if (cflag & PARODD) { | |
762 | sSetOddParity(cp); | |
763 | } else { | |
764 | sSetEvenParity(cp); | |
765 | } | |
766 | } else { | |
767 | sDisParity(cp); | |
768 | } | |
769 | ||
770 | /* baud rate */ | |
771 | baud = tty_get_baud_rate(info->tty); | |
772 | if (!baud) | |
773 | baud = 9600; | |
774 | divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1; | |
775 | if ((divisor >= 8192 || divisor < 0) && old_termios) { | |
776 | info->tty->termios->c_cflag &= ~CBAUD; | |
777 | info->tty->termios->c_cflag |= | |
778 | (old_termios->c_cflag & CBAUD); | |
779 | baud = tty_get_baud_rate(info->tty); | |
780 | if (!baud) | |
781 | baud = 9600; | |
782 | divisor = (rp_baud_base[info->board] / baud) - 1; | |
783 | } | |
784 | if (divisor >= 8192 || divisor < 0) { | |
785 | baud = 9600; | |
786 | divisor = (rp_baud_base[info->board] / baud) - 1; | |
787 | } | |
788 | info->cps = baud / bits; | |
789 | sSetBaud(cp, divisor); | |
790 | ||
791 | if (cflag & CRTSCTS) { | |
792 | info->intmask |= DELTA_CTS; | |
793 | sEnCTSFlowCtl(cp); | |
794 | } else { | |
795 | info->intmask &= ~DELTA_CTS; | |
796 | sDisCTSFlowCtl(cp); | |
797 | } | |
798 | if (cflag & CLOCAL) { | |
799 | info->intmask &= ~DELTA_CD; | |
800 | } else { | |
801 | spin_lock_irqsave(&info->slock, flags); | |
802 | if (sGetChanStatus(cp) & CD_ACT) | |
803 | info->cd_status = 1; | |
804 | else | |
805 | info->cd_status = 0; | |
806 | info->intmask |= DELTA_CD; | |
807 | spin_unlock_irqrestore(&info->slock, flags); | |
808 | } | |
809 | ||
810 | /* | |
811 | * Handle software flow control in the board | |
812 | */ | |
813 | #ifdef ROCKET_SOFT_FLOW | |
814 | if (I_IXON(info->tty)) { | |
815 | sEnTxSoftFlowCtl(cp); | |
816 | if (I_IXANY(info->tty)) { | |
817 | sEnIXANY(cp); | |
818 | } else { | |
819 | sDisIXANY(cp); | |
820 | } | |
821 | sSetTxXONChar(cp, START_CHAR(info->tty)); | |
822 | sSetTxXOFFChar(cp, STOP_CHAR(info->tty)); | |
823 | } else { | |
824 | sDisTxSoftFlowCtl(cp); | |
825 | sDisIXANY(cp); | |
826 | sClrTxXOFF(cp); | |
827 | } | |
828 | #endif | |
829 | ||
830 | /* | |
831 | * Set up ignore/read mask words | |
832 | */ | |
833 | info->read_status_mask = STMRCVROVRH | 0xFF; | |
834 | if (I_INPCK(info->tty)) | |
835 | info->read_status_mask |= STMFRAMEH | STMPARITYH; | |
836 | if (I_BRKINT(info->tty) || I_PARMRK(info->tty)) | |
837 | info->read_status_mask |= STMBREAKH; | |
838 | ||
839 | /* | |
840 | * Characters to ignore | |
841 | */ | |
842 | info->ignore_status_mask = 0; | |
843 | if (I_IGNPAR(info->tty)) | |
844 | info->ignore_status_mask |= STMFRAMEH | STMPARITYH; | |
845 | if (I_IGNBRK(info->tty)) { | |
846 | info->ignore_status_mask |= STMBREAKH; | |
847 | /* | |
848 | * If we're ignoring parity and break indicators, | |
849 | * ignore overruns too. (For real raw support). | |
850 | */ | |
851 | if (I_IGNPAR(info->tty)) | |
852 | info->ignore_status_mask |= STMRCVROVRH; | |
853 | } | |
854 | ||
855 | rocketMode = info->flags & ROCKET_MODE_MASK; | |
856 | ||
857 | if ((info->flags & ROCKET_RTS_TOGGLE) | |
858 | || (rocketMode == ROCKET_MODE_RS485)) | |
859 | sEnRTSToggle(cp); | |
860 | else | |
861 | sDisRTSToggle(cp); | |
862 | ||
863 | sSetRTS(&info->channel); | |
864 | ||
865 | if (cp->CtlP->boardType == ROCKET_TYPE_PC104) { | |
866 | switch (rocketMode) { | |
867 | case ROCKET_MODE_RS485: | |
868 | sSetInterfaceMode(cp, InterfaceModeRS485); | |
869 | break; | |
870 | case ROCKET_MODE_RS422: | |
871 | sSetInterfaceMode(cp, InterfaceModeRS422); | |
872 | break; | |
873 | case ROCKET_MODE_RS232: | |
874 | default: | |
875 | if (info->flags & ROCKET_RTS_TOGGLE) | |
876 | sSetInterfaceMode(cp, InterfaceModeRS232T); | |
877 | else | |
878 | sSetInterfaceMode(cp, InterfaceModeRS232); | |
879 | break; | |
880 | } | |
881 | } | |
882 | } | |
883 | ||
884 | /* info->count is considered critical, protected by spinlocks. */ | |
885 | static int block_til_ready(struct tty_struct *tty, struct file *filp, | |
886 | struct r_port *info) | |
887 | { | |
888 | DECLARE_WAITQUEUE(wait, current); | |
889 | int retval; | |
890 | int do_clocal = 0, extra_count = 0; | |
891 | unsigned long flags; | |
892 | ||
893 | /* | |
894 | * If the device is in the middle of being closed, then block | |
895 | * until it's done, and then try again. | |
896 | */ | |
897 | if (tty_hung_up_p(filp)) | |
898 | return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS); | |
899 | if (info->flags & ROCKET_CLOSING) { | |
900 | interruptible_sleep_on(&info->close_wait); | |
901 | return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS); | |
902 | } | |
903 | ||
904 | /* | |
905 | * If non-blocking mode is set, or the port is not enabled, | |
906 | * then make the check up front and then exit. | |
907 | */ | |
908 | if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) { | |
909 | info->flags |= ROCKET_NORMAL_ACTIVE; | |
910 | return 0; | |
911 | } | |
912 | if (tty->termios->c_cflag & CLOCAL) | |
913 | do_clocal = 1; | |
914 | ||
915 | /* | |
916 | * Block waiting for the carrier detect and the line to become free. While we are in | |
917 | * this loop, info->count is dropped by one, so that rp_close() knows when to free things. | |
918 | * We restore it upon exit, either normal or abnormal. | |
919 | */ | |
920 | retval = 0; | |
921 | add_wait_queue(&info->open_wait, &wait); | |
922 | #ifdef ROCKET_DEBUG_OPEN | |
923 | printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count); | |
924 | #endif | |
925 | spin_lock_irqsave(&info->slock, flags); | |
926 | ||
927 | #ifdef ROCKET_DISABLE_SIMUSAGE | |
928 | info->flags |= ROCKET_NORMAL_ACTIVE; | |
929 | #else | |
930 | if (!tty_hung_up_p(filp)) { | |
931 | extra_count = 1; | |
932 | info->count--; | |
933 | } | |
934 | #endif | |
935 | info->blocked_open++; | |
936 | ||
937 | spin_unlock_irqrestore(&info->slock, flags); | |
938 | ||
939 | while (1) { | |
940 | if (tty->termios->c_cflag & CBAUD) { | |
941 | sSetDTR(&info->channel); | |
942 | sSetRTS(&info->channel); | |
943 | } | |
944 | set_current_state(TASK_INTERRUPTIBLE); | |
945 | if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) { | |
946 | if (info->flags & ROCKET_HUP_NOTIFY) | |
947 | retval = -EAGAIN; | |
948 | else | |
949 | retval = -ERESTARTSYS; | |
950 | break; | |
951 | } | |
952 | if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT))) | |
953 | break; | |
954 | if (signal_pending(current)) { | |
955 | retval = -ERESTARTSYS; | |
956 | break; | |
957 | } | |
958 | #ifdef ROCKET_DEBUG_OPEN | |
959 | printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n", | |
960 | info->line, info->count, info->flags); | |
961 | #endif | |
962 | schedule(); /* Don't hold spinlock here, will hang PC */ | |
963 | } | |
964 | current->state = TASK_RUNNING; | |
965 | remove_wait_queue(&info->open_wait, &wait); | |
966 | ||
967 | spin_lock_irqsave(&info->slock, flags); | |
968 | ||
969 | if (extra_count) | |
970 | info->count++; | |
971 | info->blocked_open--; | |
972 | ||
973 | spin_unlock_irqrestore(&info->slock, flags); | |
974 | ||
975 | #ifdef ROCKET_DEBUG_OPEN | |
976 | printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n", | |
977 | info->line, info->count); | |
978 | #endif | |
979 | if (retval) | |
980 | return retval; | |
981 | info->flags |= ROCKET_NORMAL_ACTIVE; | |
982 | return 0; | |
983 | } | |
984 | ||
985 | /* | |
986 | * Exception handler that opens a serial port. Creates xmit_buf storage, fills in | |
987 | * port's r_port struct. Initializes the port hardware. | |
988 | */ | |
989 | static int rp_open(struct tty_struct *tty, struct file *filp) | |
990 | { | |
991 | struct r_port *info; | |
992 | int line = 0, retval; | |
993 | CHANNEL_t *cp; | |
994 | unsigned long page; | |
995 | ||
996 | line = TTY_GET_LINE(tty); | |
997 | if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL)) | |
998 | return -ENXIO; | |
999 | ||
1000 | page = __get_free_page(GFP_KERNEL); | |
1001 | if (!page) | |
1002 | return -ENOMEM; | |
1003 | ||
1004 | if (info->flags & ROCKET_CLOSING) { | |
1005 | interruptible_sleep_on(&info->close_wait); | |
1006 | free_page(page); | |
1007 | return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS); | |
1008 | } | |
1009 | ||
1010 | /* | |
1011 | * We must not sleep from here until the port is marked fully in use. | |
1012 | */ | |
1013 | if (info->xmit_buf) | |
1014 | free_page(page); | |
1015 | else | |
1016 | info->xmit_buf = (unsigned char *) page; | |
1017 | ||
1018 | tty->driver_data = info; | |
1019 | info->tty = tty; | |
1020 | ||
1021 | if (info->count++ == 0) { | |
1022 | atomic_inc(&rp_num_ports_open); | |
1023 | ||
1024 | #ifdef ROCKET_DEBUG_OPEN | |
1025 | printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open)); | |
1026 | #endif | |
1027 | } | |
1028 | #ifdef ROCKET_DEBUG_OPEN | |
1029 | printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count); | |
1030 | #endif | |
1031 | ||
1032 | /* | |
1033 | * Info->count is now 1; so it's safe to sleep now. | |
1034 | */ | |
1035 | info->session = current->signal->session; | |
1036 | info->pgrp = process_group(current); | |
1037 | ||
1038 | if ((info->flags & ROCKET_INITIALIZED) == 0) { | |
1039 | cp = &info->channel; | |
1040 | sSetRxTrigger(cp, TRIG_1); | |
1041 | if (sGetChanStatus(cp) & CD_ACT) | |
1042 | info->cd_status = 1; | |
1043 | else | |
1044 | info->cd_status = 0; | |
1045 | sDisRxStatusMode(cp); | |
1046 | sFlushRxFIFO(cp); | |
1047 | sFlushTxFIFO(cp); | |
1048 | ||
1049 | sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN)); | |
1050 | sSetRxTrigger(cp, TRIG_1); | |
1051 | ||
1052 | sGetChanStatus(cp); | |
1053 | sDisRxStatusMode(cp); | |
1054 | sClrTxXOFF(cp); | |
1055 | ||
1056 | sDisCTSFlowCtl(cp); | |
1057 | sDisTxSoftFlowCtl(cp); | |
1058 | ||
1059 | sEnRxFIFO(cp); | |
1060 | sEnTransmit(cp); | |
1061 | ||
1062 | info->flags |= ROCKET_INITIALIZED; | |
1063 | ||
1064 | /* | |
1065 | * Set up the tty->alt_speed kludge | |
1066 | */ | |
1067 | if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI) | |
1068 | info->tty->alt_speed = 57600; | |
1069 | if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI) | |
1070 | info->tty->alt_speed = 115200; | |
1071 | if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI) | |
1072 | info->tty->alt_speed = 230400; | |
1073 | if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP) | |
1074 | info->tty->alt_speed = 460800; | |
1075 | ||
1076 | configure_r_port(info, NULL); | |
1077 | if (tty->termios->c_cflag & CBAUD) { | |
1078 | sSetDTR(cp); | |
1079 | sSetRTS(cp); | |
1080 | } | |
1081 | } | |
1082 | /* Starts (or resets) the maint polling loop */ | |
1083 | mod_timer(&rocket_timer, jiffies + POLL_PERIOD); | |
1084 | ||
1085 | retval = block_til_ready(tty, filp, info); | |
1086 | if (retval) { | |
1087 | #ifdef ROCKET_DEBUG_OPEN | |
1088 | printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval); | |
1089 | #endif | |
1090 | return retval; | |
1091 | } | |
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | /* | |
1096 | * Exception handler that closes a serial port. info->count is considered critical. | |
1097 | */ | |
1098 | static void rp_close(struct tty_struct *tty, struct file *filp) | |
1099 | { | |
1100 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1101 | unsigned long flags; | |
1102 | int timeout; | |
1103 | CHANNEL_t *cp; | |
1104 | ||
1105 | if (rocket_paranoia_check(info, "rp_close")) | |
1106 | return; | |
1107 | ||
1108 | #ifdef ROCKET_DEBUG_OPEN | |
1109 | printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count); | |
1110 | #endif | |
1111 | ||
1112 | if (tty_hung_up_p(filp)) | |
1113 | return; | |
1114 | spin_lock_irqsave(&info->slock, flags); | |
1115 | ||
1116 | if ((tty->count == 1) && (info->count != 1)) { | |
1117 | /* | |
1118 | * Uh, oh. tty->count is 1, which means that the tty | |
1119 | * structure will be freed. Info->count should always | |
1120 | * be one in these conditions. If it's greater than | |
1121 | * one, we've got real problems, since it means the | |
1122 | * serial port won't be shutdown. | |
1123 | */ | |
1124 | printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, " | |
1125 | "info->count is %d\n", info->count); | |
1126 | info->count = 1; | |
1127 | } | |
1128 | if (--info->count < 0) { | |
1129 | printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n", | |
1130 | info->line, info->count); | |
1131 | info->count = 0; | |
1132 | } | |
1133 | if (info->count) { | |
1134 | spin_unlock_irqrestore(&info->slock, flags); | |
1135 | return; | |
1136 | } | |
1137 | info->flags |= ROCKET_CLOSING; | |
1138 | spin_unlock_irqrestore(&info->slock, flags); | |
1139 | ||
1140 | cp = &info->channel; | |
1141 | ||
1142 | /* | |
1143 | * Notify the line discpline to only process XON/XOFF characters | |
1144 | */ | |
1145 | tty->closing = 1; | |
1146 | ||
1147 | /* | |
1148 | * If transmission was throttled by the application request, | |
1149 | * just flush the xmit buffer. | |
1150 | */ | |
1151 | if (tty->flow_stopped) | |
1152 | rp_flush_buffer(tty); | |
1153 | ||
1154 | /* | |
1155 | * Wait for the transmit buffer to clear | |
1156 | */ | |
1157 | if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE) | |
1158 | tty_wait_until_sent(tty, info->closing_wait); | |
1159 | /* | |
1160 | * Before we drop DTR, make sure the UART transmitter | |
1161 | * has completely drained; this is especially | |
1162 | * important if there is a transmit FIFO! | |
1163 | */ | |
1164 | timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps; | |
1165 | if (timeout == 0) | |
1166 | timeout = 1; | |
1167 | rp_wait_until_sent(tty, timeout); | |
1168 | clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); | |
1169 | ||
1170 | sDisTransmit(cp); | |
1171 | sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN)); | |
1172 | sDisCTSFlowCtl(cp); | |
1173 | sDisTxSoftFlowCtl(cp); | |
1174 | sClrTxXOFF(cp); | |
1175 | sFlushRxFIFO(cp); | |
1176 | sFlushTxFIFO(cp); | |
1177 | sClrRTS(cp); | |
1178 | if (C_HUPCL(tty)) | |
1179 | sClrDTR(cp); | |
1180 | ||
1181 | if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty)) | |
1182 | TTY_DRIVER_FLUSH_BUFFER(tty); | |
1183 | ||
1184 | tty_ldisc_flush(tty); | |
1185 | ||
1186 | clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); | |
1187 | ||
1188 | if (info->blocked_open) { | |
1189 | if (info->close_delay) { | |
1190 | msleep_interruptible(jiffies_to_msecs(info->close_delay)); | |
1191 | } | |
1192 | wake_up_interruptible(&info->open_wait); | |
1193 | } else { | |
1194 | if (info->xmit_buf) { | |
1195 | free_page((unsigned long) info->xmit_buf); | |
1196 | info->xmit_buf = NULL; | |
1197 | } | |
1198 | } | |
1199 | info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE); | |
1200 | tty->closing = 0; | |
1201 | wake_up_interruptible(&info->close_wait); | |
1202 | atomic_dec(&rp_num_ports_open); | |
1203 | ||
1204 | #ifdef ROCKET_DEBUG_OPEN | |
1205 | printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open)); | |
1206 | printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line); | |
1207 | #endif | |
1208 | ||
1209 | } | |
1210 | ||
1211 | static void rp_set_termios(struct tty_struct *tty, | |
1212 | struct termios *old_termios) | |
1213 | { | |
1214 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1215 | CHANNEL_t *cp; | |
1216 | unsigned cflag; | |
1217 | ||
1218 | if (rocket_paranoia_check(info, "rp_set_termios")) | |
1219 | return; | |
1220 | ||
1221 | cflag = tty->termios->c_cflag; | |
1222 | ||
1223 | if (cflag == old_termios->c_cflag) | |
1224 | return; | |
1225 | ||
1226 | /* | |
1227 | * This driver doesn't support CS5 or CS6 | |
1228 | */ | |
1229 | if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6)) | |
1230 | tty->termios->c_cflag = | |
1231 | ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE)); | |
1232 | ||
1233 | configure_r_port(info, old_termios); | |
1234 | ||
1235 | cp = &info->channel; | |
1236 | ||
1237 | /* Handle transition to B0 status */ | |
1238 | if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) { | |
1239 | sClrDTR(cp); | |
1240 | sClrRTS(cp); | |
1241 | } | |
1242 | ||
1243 | /* Handle transition away from B0 status */ | |
1244 | if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) { | |
1245 | if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS)) | |
1246 | sSetRTS(cp); | |
1247 | sSetDTR(cp); | |
1248 | } | |
1249 | ||
1250 | if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) { | |
1251 | tty->hw_stopped = 0; | |
1252 | rp_start(tty); | |
1253 | } | |
1254 | } | |
1255 | ||
1256 | static void rp_break(struct tty_struct *tty, int break_state) | |
1257 | { | |
1258 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1259 | unsigned long flags; | |
1260 | ||
1261 | if (rocket_paranoia_check(info, "rp_break")) | |
1262 | return; | |
1263 | ||
1264 | spin_lock_irqsave(&info->slock, flags); | |
1265 | if (break_state == -1) | |
1266 | sSendBreak(&info->channel); | |
1267 | else | |
1268 | sClrBreak(&info->channel); | |
1269 | spin_unlock_irqrestore(&info->slock, flags); | |
1270 | } | |
1271 | ||
1272 | /* | |
1273 | * sGetChanRI used to be a macro in rocket_int.h. When the functionality for | |
1274 | * the UPCI boards was added, it was decided to make this a function because | |
1275 | * the macro was getting too complicated. All cases except the first one | |
1276 | * (UPCIRingInd) are taken directly from the original macro. | |
1277 | */ | |
1278 | static int sGetChanRI(CHANNEL_T * ChP) | |
1279 | { | |
1280 | CONTROLLER_t *CtlP = ChP->CtlP; | |
1281 | int ChanNum = ChP->ChanNum; | |
1282 | int RingInd = 0; | |
1283 | ||
1284 | if (CtlP->UPCIRingInd) | |
1285 | RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]); | |
1286 | else if (CtlP->AltChanRingIndicator) | |
1287 | RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT; | |
1288 | else if (CtlP->boardType == ROCKET_TYPE_PC104) | |
1289 | RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]); | |
1290 | ||
1291 | return RingInd; | |
1292 | } | |
1293 | ||
1294 | /********************************************************************************************/ | |
1295 | /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */ | |
1296 | ||
1297 | /* | |
1298 | * Returns the state of the serial modem control lines. These next 2 functions | |
1299 | * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs. | |
1300 | */ | |
1301 | static int rp_tiocmget(struct tty_struct *tty, struct file *file) | |
1302 | { | |
1303 | struct r_port *info = (struct r_port *)tty->driver_data; | |
1304 | unsigned int control, result, ChanStatus; | |
1305 | ||
1306 | ChanStatus = sGetChanStatusLo(&info->channel); | |
1307 | control = info->channel.TxControl[3]; | |
1308 | result = ((control & SET_RTS) ? TIOCM_RTS : 0) | | |
1309 | ((control & SET_DTR) ? TIOCM_DTR : 0) | | |
1310 | ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) | | |
1311 | (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) | | |
1312 | ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) | | |
1313 | ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0); | |
1314 | ||
1315 | return result; | |
1316 | } | |
1317 | ||
1318 | /* | |
1319 | * Sets the modem control lines | |
1320 | */ | |
1321 | static int rp_tiocmset(struct tty_struct *tty, struct file *file, | |
1322 | unsigned int set, unsigned int clear) | |
1323 | { | |
1324 | struct r_port *info = (struct r_port *)tty->driver_data; | |
1325 | ||
1326 | if (set & TIOCM_RTS) | |
1327 | info->channel.TxControl[3] |= SET_RTS; | |
1328 | if (set & TIOCM_DTR) | |
1329 | info->channel.TxControl[3] |= SET_DTR; | |
1330 | if (clear & TIOCM_RTS) | |
1331 | info->channel.TxControl[3] &= ~SET_RTS; | |
1332 | if (clear & TIOCM_DTR) | |
1333 | info->channel.TxControl[3] &= ~SET_DTR; | |
1334 | ||
1335 | sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0])); | |
1336 | return 0; | |
1337 | } | |
1338 | ||
1339 | static int get_config(struct r_port *info, struct rocket_config __user *retinfo) | |
1340 | { | |
1341 | struct rocket_config tmp; | |
1342 | ||
1343 | if (!retinfo) | |
1344 | return -EFAULT; | |
1345 | memset(&tmp, 0, sizeof (tmp)); | |
1346 | tmp.line = info->line; | |
1347 | tmp.flags = info->flags; | |
1348 | tmp.close_delay = info->close_delay; | |
1349 | tmp.closing_wait = info->closing_wait; | |
1350 | tmp.port = rcktpt_io_addr[(info->line >> 5) & 3]; | |
1351 | ||
1352 | if (copy_to_user(retinfo, &tmp, sizeof (*retinfo))) | |
1353 | return -EFAULT; | |
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | static int set_config(struct r_port *info, struct rocket_config __user *new_info) | |
1358 | { | |
1359 | struct rocket_config new_serial; | |
1360 | ||
1361 | if (copy_from_user(&new_serial, new_info, sizeof (new_serial))) | |
1362 | return -EFAULT; | |
1363 | ||
1364 | if (!capable(CAP_SYS_ADMIN)) | |
1365 | { | |
1366 | if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) | |
1367 | return -EPERM; | |
1368 | info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK)); | |
1369 | configure_r_port(info, NULL); | |
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS)); | |
1374 | info->close_delay = new_serial.close_delay; | |
1375 | info->closing_wait = new_serial.closing_wait; | |
1376 | ||
1377 | if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI) | |
1378 | info->tty->alt_speed = 57600; | |
1379 | if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI) | |
1380 | info->tty->alt_speed = 115200; | |
1381 | if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI) | |
1382 | info->tty->alt_speed = 230400; | |
1383 | if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP) | |
1384 | info->tty->alt_speed = 460800; | |
1385 | ||
1386 | configure_r_port(info, NULL); | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | /* | |
1391 | * This function fills in a rocket_ports struct with information | |
1392 | * about what boards/ports are in the system. This info is passed | |
1393 | * to user space. See setrocket.c where the info is used to create | |
1394 | * the /dev/ttyRx ports. | |
1395 | */ | |
1396 | static int get_ports(struct r_port *info, struct rocket_ports __user *retports) | |
1397 | { | |
1398 | struct rocket_ports tmp; | |
1399 | int board; | |
1400 | ||
1401 | if (!retports) | |
1402 | return -EFAULT; | |
1403 | memset(&tmp, 0, sizeof (tmp)); | |
1404 | tmp.tty_major = rocket_driver->major; | |
1405 | ||
1406 | for (board = 0; board < 4; board++) { | |
1407 | tmp.rocketModel[board].model = rocketModel[board].model; | |
1408 | strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString); | |
1409 | tmp.rocketModel[board].numPorts = rocketModel[board].numPorts; | |
1410 | tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2; | |
1411 | tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber; | |
1412 | } | |
1413 | if (copy_to_user(retports, &tmp, sizeof (*retports))) | |
1414 | return -EFAULT; | |
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | static int reset_rm2(struct r_port *info, void __user *arg) | |
1419 | { | |
1420 | int reset; | |
1421 | ||
1422 | if (copy_from_user(&reset, arg, sizeof (int))) | |
1423 | return -EFAULT; | |
1424 | if (reset) | |
1425 | reset = 1; | |
1426 | ||
1427 | if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII && | |
1428 | rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII) | |
1429 | return -EINVAL; | |
1430 | ||
1431 | if (info->ctlp->BusType == isISA) | |
1432 | sModemReset(info->ctlp, info->chan, reset); | |
1433 | else | |
1434 | sPCIModemReset(info->ctlp, info->chan, reset); | |
1435 | ||
1436 | return 0; | |
1437 | } | |
1438 | ||
1439 | static int get_version(struct r_port *info, struct rocket_version __user *retvers) | |
1440 | { | |
1441 | if (copy_to_user(retvers, &driver_version, sizeof (*retvers))) | |
1442 | return -EFAULT; | |
1443 | return 0; | |
1444 | } | |
1445 | ||
1446 | /* IOCTL call handler into the driver */ | |
1447 | static int rp_ioctl(struct tty_struct *tty, struct file *file, | |
1448 | unsigned int cmd, unsigned long arg) | |
1449 | { | |
1450 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1451 | void __user *argp = (void __user *)arg; | |
1452 | ||
1453 | if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl")) | |
1454 | return -ENXIO; | |
1455 | ||
1456 | switch (cmd) { | |
1457 | case RCKP_GET_STRUCT: | |
1458 | if (copy_to_user(argp, info, sizeof (struct r_port))) | |
1459 | return -EFAULT; | |
1460 | return 0; | |
1461 | case RCKP_GET_CONFIG: | |
1462 | return get_config(info, argp); | |
1463 | case RCKP_SET_CONFIG: | |
1464 | return set_config(info, argp); | |
1465 | case RCKP_GET_PORTS: | |
1466 | return get_ports(info, argp); | |
1467 | case RCKP_RESET_RM2: | |
1468 | return reset_rm2(info, argp); | |
1469 | case RCKP_GET_VERSION: | |
1470 | return get_version(info, argp); | |
1471 | default: | |
1472 | return -ENOIOCTLCMD; | |
1473 | } | |
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static void rp_send_xchar(struct tty_struct *tty, char ch) | |
1478 | { | |
1479 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1480 | CHANNEL_t *cp; | |
1481 | ||
1482 | if (rocket_paranoia_check(info, "rp_send_xchar")) | |
1483 | return; | |
1484 | ||
1485 | cp = &info->channel; | |
1486 | if (sGetTxCnt(cp)) | |
1487 | sWriteTxPrioByte(cp, ch); | |
1488 | else | |
1489 | sWriteTxByte(sGetTxRxDataIO(cp), ch); | |
1490 | } | |
1491 | ||
1492 | static void rp_throttle(struct tty_struct *tty) | |
1493 | { | |
1494 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1495 | CHANNEL_t *cp; | |
1496 | ||
1497 | #ifdef ROCKET_DEBUG_THROTTLE | |
1498 | printk(KERN_INFO "throttle %s: %d....\n", tty->name, | |
1499 | tty->ldisc.chars_in_buffer(tty)); | |
1500 | #endif | |
1501 | ||
1502 | if (rocket_paranoia_check(info, "rp_throttle")) | |
1503 | return; | |
1504 | ||
1505 | cp = &info->channel; | |
1506 | if (I_IXOFF(tty)) | |
1507 | rp_send_xchar(tty, STOP_CHAR(tty)); | |
1508 | ||
1509 | sClrRTS(&info->channel); | |
1510 | } | |
1511 | ||
1512 | static void rp_unthrottle(struct tty_struct *tty) | |
1513 | { | |
1514 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1515 | CHANNEL_t *cp; | |
1516 | #ifdef ROCKET_DEBUG_THROTTLE | |
1517 | printk(KERN_INFO "unthrottle %s: %d....\n", tty->name, | |
1518 | tty->ldisc.chars_in_buffer(tty)); | |
1519 | #endif | |
1520 | ||
1521 | if (rocket_paranoia_check(info, "rp_throttle")) | |
1522 | return; | |
1523 | ||
1524 | cp = &info->channel; | |
1525 | if (I_IXOFF(tty)) | |
1526 | rp_send_xchar(tty, START_CHAR(tty)); | |
1527 | ||
1528 | sSetRTS(&info->channel); | |
1529 | } | |
1530 | ||
1531 | /* | |
1532 | * ------------------------------------------------------------ | |
1533 | * rp_stop() and rp_start() | |
1534 | * | |
1535 | * This routines are called before setting or resetting tty->stopped. | |
1536 | * They enable or disable transmitter interrupts, as necessary. | |
1537 | * ------------------------------------------------------------ | |
1538 | */ | |
1539 | static void rp_stop(struct tty_struct *tty) | |
1540 | { | |
1541 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1542 | ||
1543 | #ifdef ROCKET_DEBUG_FLOW | |
1544 | printk(KERN_INFO "stop %s: %d %d....\n", tty->name, | |
1545 | info->xmit_cnt, info->xmit_fifo_room); | |
1546 | #endif | |
1547 | ||
1548 | if (rocket_paranoia_check(info, "rp_stop")) | |
1549 | return; | |
1550 | ||
1551 | if (sGetTxCnt(&info->channel)) | |
1552 | sDisTransmit(&info->channel); | |
1553 | } | |
1554 | ||
1555 | static void rp_start(struct tty_struct *tty) | |
1556 | { | |
1557 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1558 | ||
1559 | #ifdef ROCKET_DEBUG_FLOW | |
1560 | printk(KERN_INFO "start %s: %d %d....\n", tty->name, | |
1561 | info->xmit_cnt, info->xmit_fifo_room); | |
1562 | #endif | |
1563 | ||
1564 | if (rocket_paranoia_check(info, "rp_stop")) | |
1565 | return; | |
1566 | ||
1567 | sEnTransmit(&info->channel); | |
1568 | set_bit((info->aiop * 8) + info->chan, | |
1569 | (void *) &xmit_flags[info->board]); | |
1570 | } | |
1571 | ||
1572 | /* | |
1573 | * rp_wait_until_sent() --- wait until the transmitter is empty | |
1574 | */ | |
1575 | static void rp_wait_until_sent(struct tty_struct *tty, int timeout) | |
1576 | { | |
1577 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1578 | CHANNEL_t *cp; | |
1579 | unsigned long orig_jiffies; | |
1580 | int check_time, exit_time; | |
1581 | int txcnt; | |
1582 | ||
1583 | if (rocket_paranoia_check(info, "rp_wait_until_sent")) | |
1584 | return; | |
1585 | ||
1586 | cp = &info->channel; | |
1587 | ||
1588 | orig_jiffies = jiffies; | |
1589 | #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT | |
1590 | printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout, | |
1591 | jiffies); | |
1592 | printk(KERN_INFO "cps=%d...", info->cps); | |
1593 | #endif | |
1594 | while (1) { | |
1595 | txcnt = sGetTxCnt(cp); | |
1596 | if (!txcnt) { | |
1597 | if (sGetChanStatusLo(cp) & TXSHRMT) | |
1598 | break; | |
1599 | check_time = (HZ / info->cps) / 5; | |
1600 | } else { | |
1601 | check_time = HZ * txcnt / info->cps; | |
1602 | } | |
1603 | if (timeout) { | |
1604 | exit_time = orig_jiffies + timeout - jiffies; | |
1605 | if (exit_time <= 0) | |
1606 | break; | |
1607 | if (exit_time < check_time) | |
1608 | check_time = exit_time; | |
1609 | } | |
1610 | if (check_time == 0) | |
1611 | check_time = 1; | |
1612 | #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT | |
1613 | printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time); | |
1614 | #endif | |
1615 | msleep_interruptible(jiffies_to_msecs(check_time)); | |
1616 | if (signal_pending(current)) | |
1617 | break; | |
1618 | } | |
1619 | current->state = TASK_RUNNING; | |
1620 | #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT | |
1621 | printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies); | |
1622 | #endif | |
1623 | } | |
1624 | ||
1625 | /* | |
1626 | * rp_hangup() --- called by tty_hangup() when a hangup is signaled. | |
1627 | */ | |
1628 | static void rp_hangup(struct tty_struct *tty) | |
1629 | { | |
1630 | CHANNEL_t *cp; | |
1631 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1632 | ||
1633 | if (rocket_paranoia_check(info, "rp_hangup")) | |
1634 | return; | |
1635 | ||
1636 | #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP)) | |
1637 | printk(KERN_INFO "rp_hangup of ttyR%d...", info->line); | |
1638 | #endif | |
1639 | rp_flush_buffer(tty); | |
1640 | if (info->flags & ROCKET_CLOSING) | |
1641 | return; | |
1642 | if (info->count) | |
1643 | atomic_dec(&rp_num_ports_open); | |
1644 | clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); | |
1645 | ||
1646 | info->count = 0; | |
1647 | info->flags &= ~ROCKET_NORMAL_ACTIVE; | |
1648 | info->tty = NULL; | |
1649 | ||
1650 | cp = &info->channel; | |
1651 | sDisRxFIFO(cp); | |
1652 | sDisTransmit(cp); | |
1653 | sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN)); | |
1654 | sDisCTSFlowCtl(cp); | |
1655 | sDisTxSoftFlowCtl(cp); | |
1656 | sClrTxXOFF(cp); | |
1657 | info->flags &= ~ROCKET_INITIALIZED; | |
1658 | ||
1659 | wake_up_interruptible(&info->open_wait); | |
1660 | } | |
1661 | ||
1662 | /* | |
1663 | * Exception handler - write char routine. The RocketPort driver uses a | |
1664 | * double-buffering strategy, with the twist that if the in-memory CPU | |
1665 | * buffer is empty, and there's space in the transmit FIFO, the | |
1666 | * writing routines will write directly to transmit FIFO. | |
1667 | * Write buffer and counters protected by spinlocks | |
1668 | */ | |
1669 | static void rp_put_char(struct tty_struct *tty, unsigned char ch) | |
1670 | { | |
1671 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1672 | CHANNEL_t *cp; | |
1673 | unsigned long flags; | |
1674 | ||
1675 | if (rocket_paranoia_check(info, "rp_put_char")) | |
1676 | return; | |
1677 | ||
1678 | /* Grab the port write semaphore, locking out other processes that try to write to this port */ | |
1679 | down(&info->write_sem); | |
1680 | ||
1681 | #ifdef ROCKET_DEBUG_WRITE | |
1682 | printk(KERN_INFO "rp_put_char %c...", ch); | |
1683 | #endif | |
1684 | ||
1685 | spin_lock_irqsave(&info->slock, flags); | |
1686 | cp = &info->channel; | |
1687 | ||
1688 | if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0) | |
1689 | info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp); | |
1690 | ||
1691 | if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) { | |
1692 | info->xmit_buf[info->xmit_head++] = ch; | |
1693 | info->xmit_head &= XMIT_BUF_SIZE - 1; | |
1694 | info->xmit_cnt++; | |
1695 | set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); | |
1696 | } else { | |
1697 | sOutB(sGetTxRxDataIO(cp), ch); | |
1698 | info->xmit_fifo_room--; | |
1699 | } | |
1700 | spin_unlock_irqrestore(&info->slock, flags); | |
1701 | up(&info->write_sem); | |
1702 | } | |
1703 | ||
1704 | /* | |
1705 | * Exception handler - write routine, called when user app writes to the device. | |
1706 | * A per port write semaphore is used to protect from another process writing to | |
1707 | * this port at the same time. This other process could be running on the other CPU | |
1708 | * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out). | |
1709 | * Spinlocks protect the info xmit members. | |
1710 | */ | |
1711 | static int rp_write(struct tty_struct *tty, | |
1712 | const unsigned char *buf, int count) | |
1713 | { | |
1714 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1715 | CHANNEL_t *cp; | |
1716 | const unsigned char *b; | |
1717 | int c, retval = 0; | |
1718 | unsigned long flags; | |
1719 | ||
1720 | if (count <= 0 || rocket_paranoia_check(info, "rp_write")) | |
1721 | return 0; | |
1722 | ||
1723 | down_interruptible(&info->write_sem); | |
1724 | ||
1725 | #ifdef ROCKET_DEBUG_WRITE | |
1726 | printk(KERN_INFO "rp_write %d chars...", count); | |
1727 | #endif | |
1728 | cp = &info->channel; | |
1729 | ||
1730 | if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count) | |
1731 | info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp); | |
1732 | ||
1733 | /* | |
1734 | * If the write queue for the port is empty, and there is FIFO space, stuff bytes | |
1735 | * into FIFO. Use the write queue for temp storage. | |
1736 | */ | |
1737 | if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) { | |
1738 | c = min(count, info->xmit_fifo_room); | |
1739 | b = buf; | |
1740 | ||
1741 | /* Push data into FIFO, 2 bytes at a time */ | |
1742 | sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2); | |
1743 | ||
1744 | /* If there is a byte remaining, write it */ | |
1745 | if (c & 1) | |
1746 | sOutB(sGetTxRxDataIO(cp), b[c - 1]); | |
1747 | ||
1748 | retval += c; | |
1749 | buf += c; | |
1750 | count -= c; | |
1751 | ||
1752 | spin_lock_irqsave(&info->slock, flags); | |
1753 | info->xmit_fifo_room -= c; | |
1754 | spin_unlock_irqrestore(&info->slock, flags); | |
1755 | } | |
1756 | ||
1757 | /* If count is zero, we wrote it all and are done */ | |
1758 | if (!count) | |
1759 | goto end; | |
1760 | ||
1761 | /* Write remaining data into the port's xmit_buf */ | |
1762 | while (1) { | |
1763 | if (info->tty == 0) /* Seemingly obligatory check... */ | |
1764 | goto end; | |
1765 | ||
1766 | c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head)); | |
1767 | if (c <= 0) | |
1768 | break; | |
1769 | ||
1770 | b = buf; | |
1771 | memcpy(info->xmit_buf + info->xmit_head, b, c); | |
1772 | ||
1773 | spin_lock_irqsave(&info->slock, flags); | |
1774 | info->xmit_head = | |
1775 | (info->xmit_head + c) & (XMIT_BUF_SIZE - 1); | |
1776 | info->xmit_cnt += c; | |
1777 | spin_unlock_irqrestore(&info->slock, flags); | |
1778 | ||
1779 | buf += c; | |
1780 | count -= c; | |
1781 | retval += c; | |
1782 | } | |
1783 | ||
1784 | if ((retval > 0) && !tty->stopped && !tty->hw_stopped) | |
1785 | set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]); | |
1786 | ||
1787 | end: | |
1788 | if (info->xmit_cnt < WAKEUP_CHARS) { | |
1789 | tty_wakeup(tty); | |
1790 | wake_up_interruptible(&tty->write_wait); | |
1791 | #ifdef ROCKETPORT_HAVE_POLL_WAIT | |
1792 | wake_up_interruptible(&tty->poll_wait); | |
1793 | #endif | |
1794 | } | |
1795 | up(&info->write_sem); | |
1796 | return retval; | |
1797 | } | |
1798 | ||
1799 | /* | |
1800 | * Return the number of characters that can be sent. We estimate | |
1801 | * only using the in-memory transmit buffer only, and ignore the | |
1802 | * potential space in the transmit FIFO. | |
1803 | */ | |
1804 | static int rp_write_room(struct tty_struct *tty) | |
1805 | { | |
1806 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1807 | int ret; | |
1808 | ||
1809 | if (rocket_paranoia_check(info, "rp_write_room")) | |
1810 | return 0; | |
1811 | ||
1812 | ret = XMIT_BUF_SIZE - info->xmit_cnt - 1; | |
1813 | if (ret < 0) | |
1814 | ret = 0; | |
1815 | #ifdef ROCKET_DEBUG_WRITE | |
1816 | printk(KERN_INFO "rp_write_room returns %d...", ret); | |
1817 | #endif | |
1818 | return ret; | |
1819 | } | |
1820 | ||
1821 | /* | |
1822 | * Return the number of characters in the buffer. Again, this only | |
1823 | * counts those characters in the in-memory transmit buffer. | |
1824 | */ | |
1825 | static int rp_chars_in_buffer(struct tty_struct *tty) | |
1826 | { | |
1827 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1828 | CHANNEL_t *cp; | |
1829 | ||
1830 | if (rocket_paranoia_check(info, "rp_chars_in_buffer")) | |
1831 | return 0; | |
1832 | ||
1833 | cp = &info->channel; | |
1834 | ||
1835 | #ifdef ROCKET_DEBUG_WRITE | |
1836 | printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt); | |
1837 | #endif | |
1838 | return info->xmit_cnt; | |
1839 | } | |
1840 | ||
1841 | /* | |
1842 | * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the | |
1843 | * r_port struct for the port. Note that spinlock are used to protect info members, | |
1844 | * do not call this function if the spinlock is already held. | |
1845 | */ | |
1846 | static void rp_flush_buffer(struct tty_struct *tty) | |
1847 | { | |
1848 | struct r_port *info = (struct r_port *) tty->driver_data; | |
1849 | CHANNEL_t *cp; | |
1850 | unsigned long flags; | |
1851 | ||
1852 | if (rocket_paranoia_check(info, "rp_flush_buffer")) | |
1853 | return; | |
1854 | ||
1855 | spin_lock_irqsave(&info->slock, flags); | |
1856 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | |
1857 | spin_unlock_irqrestore(&info->slock, flags); | |
1858 | ||
1859 | wake_up_interruptible(&tty->write_wait); | |
1860 | #ifdef ROCKETPORT_HAVE_POLL_WAIT | |
1861 | wake_up_interruptible(&tty->poll_wait); | |
1862 | #endif | |
1863 | tty_wakeup(tty); | |
1864 | ||
1865 | cp = &info->channel; | |
1866 | sFlushTxFIFO(cp); | |
1867 | } | |
1868 | ||
1869 | #ifdef CONFIG_PCI | |
1870 | ||
1871 | /* | |
1872 | * Called when a PCI card is found. Retrieves and stores model information, | |
1873 | * init's aiopic and serial port hardware. | |
1874 | * Inputs: i is the board number (0-n) | |
1875 | */ | |
f15313bf | 1876 | static __init int register_PCI(int i, struct pci_dev *dev) |
1da177e4 LT |
1877 | { |
1878 | int num_aiops, aiop, max_num_aiops, num_chan, chan; | |
1879 | unsigned int aiopio[MAX_AIOPS_PER_BOARD]; | |
1880 | char *str, *board_type; | |
1881 | CONTROLLER_t *ctlp; | |
1882 | ||
1883 | int fast_clock = 0; | |
1884 | int altChanRingIndicator = 0; | |
1885 | int ports_per_aiop = 8; | |
1886 | int ret; | |
1887 | unsigned int class_rev; | |
1888 | WordIO_t ConfigIO = 0; | |
1889 | ByteIO_t UPCIRingInd = 0; | |
1890 | ||
1891 | if (!dev || pci_enable_device(dev)) | |
1892 | return 0; | |
1893 | ||
1894 | rcktpt_io_addr[i] = pci_resource_start(dev, 0); | |
1895 | ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
1896 | ||
1897 | if (ret) { | |
1898 | printk(KERN_INFO " Error during register_PCI(), unable to read config dword \n"); | |
1899 | return 0; | |
1900 | } | |
1901 | ||
1902 | rcktpt_type[i] = ROCKET_TYPE_NORMAL; | |
1903 | rocketModel[i].loadrm2 = 0; | |
1904 | rocketModel[i].startingPortNumber = nextLineNumber; | |
1905 | ||
1906 | /* Depending on the model, set up some config variables */ | |
1907 | switch (dev->device) { | |
1908 | case PCI_DEVICE_ID_RP4QUAD: | |
1909 | str = "Quadcable"; | |
1910 | max_num_aiops = 1; | |
1911 | ports_per_aiop = 4; | |
1912 | rocketModel[i].model = MODEL_RP4QUAD; | |
1913 | strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable"); | |
1914 | rocketModel[i].numPorts = 4; | |
1915 | break; | |
1916 | case PCI_DEVICE_ID_RP8OCTA: | |
1917 | str = "Octacable"; | |
1918 | max_num_aiops = 1; | |
1919 | rocketModel[i].model = MODEL_RP8OCTA; | |
1920 | strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable"); | |
1921 | rocketModel[i].numPorts = 8; | |
1922 | break; | |
1923 | case PCI_DEVICE_ID_URP8OCTA: | |
1924 | str = "Octacable"; | |
1925 | max_num_aiops = 1; | |
1926 | rocketModel[i].model = MODEL_UPCI_RP8OCTA; | |
1927 | strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable"); | |
1928 | rocketModel[i].numPorts = 8; | |
1929 | break; | |
1930 | case PCI_DEVICE_ID_RP8INTF: | |
1931 | str = "8"; | |
1932 | max_num_aiops = 1; | |
1933 | rocketModel[i].model = MODEL_RP8INTF; | |
1934 | strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F"); | |
1935 | rocketModel[i].numPorts = 8; | |
1936 | break; | |
1937 | case PCI_DEVICE_ID_URP8INTF: | |
1938 | str = "8"; | |
1939 | max_num_aiops = 1; | |
1940 | rocketModel[i].model = MODEL_UPCI_RP8INTF; | |
1941 | strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F"); | |
1942 | rocketModel[i].numPorts = 8; | |
1943 | break; | |
1944 | case PCI_DEVICE_ID_RP8J: | |
1945 | str = "8J"; | |
1946 | max_num_aiops = 1; | |
1947 | rocketModel[i].model = MODEL_RP8J; | |
1948 | strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors"); | |
1949 | rocketModel[i].numPorts = 8; | |
1950 | break; | |
1951 | case PCI_DEVICE_ID_RP4J: | |
1952 | str = "4J"; | |
1953 | max_num_aiops = 1; | |
1954 | ports_per_aiop = 4; | |
1955 | rocketModel[i].model = MODEL_RP4J; | |
1956 | strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors"); | |
1957 | rocketModel[i].numPorts = 4; | |
1958 | break; | |
1959 | case PCI_DEVICE_ID_RP8SNI: | |
1960 | str = "8 (DB78 Custom)"; | |
1961 | max_num_aiops = 1; | |
1962 | rocketModel[i].model = MODEL_RP8SNI; | |
1963 | strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78"); | |
1964 | rocketModel[i].numPorts = 8; | |
1965 | break; | |
1966 | case PCI_DEVICE_ID_RP16SNI: | |
1967 | str = "16 (DB78 Custom)"; | |
1968 | max_num_aiops = 2; | |
1969 | rocketModel[i].model = MODEL_RP16SNI; | |
1970 | strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78"); | |
1971 | rocketModel[i].numPorts = 16; | |
1972 | break; | |
1973 | case PCI_DEVICE_ID_RP16INTF: | |
1974 | str = "16"; | |
1975 | max_num_aiops = 2; | |
1976 | rocketModel[i].model = MODEL_RP16INTF; | |
1977 | strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F"); | |
1978 | rocketModel[i].numPorts = 16; | |
1979 | break; | |
1980 | case PCI_DEVICE_ID_URP16INTF: | |
1981 | str = "16"; | |
1982 | max_num_aiops = 2; | |
1983 | rocketModel[i].model = MODEL_UPCI_RP16INTF; | |
1984 | strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F"); | |
1985 | rocketModel[i].numPorts = 16; | |
1986 | break; | |
1987 | case PCI_DEVICE_ID_CRP16INTF: | |
1988 | str = "16"; | |
1989 | max_num_aiops = 2; | |
1990 | rocketModel[i].model = MODEL_CPCI_RP16INTF; | |
1991 | strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F"); | |
1992 | rocketModel[i].numPorts = 16; | |
1993 | break; | |
1994 | case PCI_DEVICE_ID_RP32INTF: | |
1995 | str = "32"; | |
1996 | max_num_aiops = 4; | |
1997 | rocketModel[i].model = MODEL_RP32INTF; | |
1998 | strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F"); | |
1999 | rocketModel[i].numPorts = 32; | |
2000 | break; | |
2001 | case PCI_DEVICE_ID_URP32INTF: | |
2002 | str = "32"; | |
2003 | max_num_aiops = 4; | |
2004 | rocketModel[i].model = MODEL_UPCI_RP32INTF; | |
2005 | strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F"); | |
2006 | rocketModel[i].numPorts = 32; | |
2007 | break; | |
2008 | case PCI_DEVICE_ID_RPP4: | |
2009 | str = "Plus Quadcable"; | |
2010 | max_num_aiops = 1; | |
2011 | ports_per_aiop = 4; | |
2012 | altChanRingIndicator++; | |
2013 | fast_clock++; | |
2014 | rocketModel[i].model = MODEL_RPP4; | |
2015 | strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port"); | |
2016 | rocketModel[i].numPorts = 4; | |
2017 | break; | |
2018 | case PCI_DEVICE_ID_RPP8: | |
2019 | str = "Plus Octacable"; | |
2020 | max_num_aiops = 2; | |
2021 | ports_per_aiop = 4; | |
2022 | altChanRingIndicator++; | |
2023 | fast_clock++; | |
2024 | rocketModel[i].model = MODEL_RPP8; | |
2025 | strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port"); | |
2026 | rocketModel[i].numPorts = 8; | |
2027 | break; | |
2028 | case PCI_DEVICE_ID_RP2_232: | |
2029 | str = "Plus 2 (RS-232)"; | |
2030 | max_num_aiops = 1; | |
2031 | ports_per_aiop = 2; | |
2032 | altChanRingIndicator++; | |
2033 | fast_clock++; | |
2034 | rocketModel[i].model = MODEL_RP2_232; | |
2035 | strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232"); | |
2036 | rocketModel[i].numPorts = 2; | |
2037 | break; | |
2038 | case PCI_DEVICE_ID_RP2_422: | |
2039 | str = "Plus 2 (RS-422)"; | |
2040 | max_num_aiops = 1; | |
2041 | ports_per_aiop = 2; | |
2042 | altChanRingIndicator++; | |
2043 | fast_clock++; | |
2044 | rocketModel[i].model = MODEL_RP2_422; | |
2045 | strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422"); | |
2046 | rocketModel[i].numPorts = 2; | |
2047 | break; | |
2048 | case PCI_DEVICE_ID_RP6M: | |
2049 | ||
2050 | max_num_aiops = 1; | |
2051 | ports_per_aiop = 6; | |
2052 | str = "6-port"; | |
2053 | ||
2054 | /* If class_rev is 1, the rocketmodem flash must be loaded. If it is 2 it is a "socketed" version. */ | |
2055 | if ((class_rev & 0xFF) == 1) { | |
2056 | rcktpt_type[i] = ROCKET_TYPE_MODEMII; | |
2057 | rocketModel[i].loadrm2 = 1; | |
2058 | } else { | |
2059 | rcktpt_type[i] = ROCKET_TYPE_MODEM; | |
2060 | } | |
2061 | ||
2062 | rocketModel[i].model = MODEL_RP6M; | |
2063 | strcpy(rocketModel[i].modelString, "RocketModem 6 port"); | |
2064 | rocketModel[i].numPorts = 6; | |
2065 | break; | |
2066 | case PCI_DEVICE_ID_RP4M: | |
2067 | max_num_aiops = 1; | |
2068 | ports_per_aiop = 4; | |
2069 | str = "4-port"; | |
2070 | if ((class_rev & 0xFF) == 1) { | |
2071 | rcktpt_type[i] = ROCKET_TYPE_MODEMII; | |
2072 | rocketModel[i].loadrm2 = 1; | |
2073 | } else { | |
2074 | rcktpt_type[i] = ROCKET_TYPE_MODEM; | |
2075 | } | |
2076 | ||
2077 | rocketModel[i].model = MODEL_RP4M; | |
2078 | strcpy(rocketModel[i].modelString, "RocketModem 4 port"); | |
2079 | rocketModel[i].numPorts = 4; | |
2080 | break; | |
2081 | default: | |
2082 | str = "(unknown/unsupported)"; | |
2083 | max_num_aiops = 0; | |
2084 | break; | |
2085 | } | |
2086 | ||
2087 | /* | |
2088 | * Check for UPCI boards. | |
2089 | */ | |
2090 | ||
2091 | switch (dev->device) { | |
2092 | case PCI_DEVICE_ID_URP32INTF: | |
2093 | case PCI_DEVICE_ID_URP8INTF: | |
2094 | case PCI_DEVICE_ID_URP16INTF: | |
2095 | case PCI_DEVICE_ID_CRP16INTF: | |
2096 | case PCI_DEVICE_ID_URP8OCTA: | |
2097 | rcktpt_io_addr[i] = pci_resource_start(dev, 2); | |
2098 | ConfigIO = pci_resource_start(dev, 1); | |
2099 | if (dev->device == PCI_DEVICE_ID_URP8OCTA) { | |
2100 | UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND; | |
2101 | ||
2102 | /* | |
2103 | * Check for octa or quad cable. | |
2104 | */ | |
2105 | if (! | |
2106 | (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) & | |
2107 | PCI_GPIO_CTRL_8PORT)) { | |
2108 | str = "Quadcable"; | |
2109 | ports_per_aiop = 4; | |
2110 | rocketModel[i].numPorts = 4; | |
2111 | } | |
2112 | } | |
2113 | break; | |
2114 | case PCI_DEVICE_ID_UPCI_RM3_8PORT: | |
2115 | str = "8 ports"; | |
2116 | max_num_aiops = 1; | |
2117 | rocketModel[i].model = MODEL_UPCI_RM3_8PORT; | |
2118 | strcpy(rocketModel[i].modelString, "RocketModem III 8 port"); | |
2119 | rocketModel[i].numPorts = 8; | |
2120 | rcktpt_io_addr[i] = pci_resource_start(dev, 2); | |
2121 | UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND; | |
2122 | ConfigIO = pci_resource_start(dev, 1); | |
2123 | rcktpt_type[i] = ROCKET_TYPE_MODEMIII; | |
2124 | break; | |
2125 | case PCI_DEVICE_ID_UPCI_RM3_4PORT: | |
2126 | str = "4 ports"; | |
2127 | max_num_aiops = 1; | |
2128 | rocketModel[i].model = MODEL_UPCI_RM3_4PORT; | |
2129 | strcpy(rocketModel[i].modelString, "RocketModem III 4 port"); | |
2130 | rocketModel[i].numPorts = 4; | |
2131 | rcktpt_io_addr[i] = pci_resource_start(dev, 2); | |
2132 | UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND; | |
2133 | ConfigIO = pci_resource_start(dev, 1); | |
2134 | rcktpt_type[i] = ROCKET_TYPE_MODEMIII; | |
2135 | break; | |
2136 | default: | |
2137 | break; | |
2138 | } | |
2139 | ||
2140 | switch (rcktpt_type[i]) { | |
2141 | case ROCKET_TYPE_MODEM: | |
2142 | board_type = "RocketModem"; | |
2143 | break; | |
2144 | case ROCKET_TYPE_MODEMII: | |
2145 | board_type = "RocketModem II"; | |
2146 | break; | |
2147 | case ROCKET_TYPE_MODEMIII: | |
2148 | board_type = "RocketModem III"; | |
2149 | break; | |
2150 | default: | |
2151 | board_type = "RocketPort"; | |
2152 | break; | |
2153 | } | |
2154 | ||
2155 | if (fast_clock) { | |
2156 | sClockPrescale = 0x12; /* mod 2 (divide by 3) */ | |
2157 | rp_baud_base[i] = 921600; | |
2158 | } else { | |
2159 | /* | |
2160 | * If support_low_speed is set, use the slow clock | |
2161 | * prescale, which supports 50 bps | |
2162 | */ | |
2163 | if (support_low_speed) { | |
2164 | /* mod 9 (divide by 10) prescale */ | |
2165 | sClockPrescale = 0x19; | |
2166 | rp_baud_base[i] = 230400; | |
2167 | } else { | |
2168 | /* mod 4 (devide by 5) prescale */ | |
2169 | sClockPrescale = 0x14; | |
2170 | rp_baud_base[i] = 460800; | |
2171 | } | |
2172 | } | |
2173 | ||
2174 | for (aiop = 0; aiop < max_num_aiops; aiop++) | |
2175 | aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40); | |
2176 | ctlp = sCtlNumToCtlPtr(i); | |
2177 | num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd); | |
2178 | for (aiop = 0; aiop < max_num_aiops; aiop++) | |
2179 | ctlp->AiopNumChan[aiop] = ports_per_aiop; | |
2180 | ||
2181 | printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, " | |
2182 | "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev), | |
2183 | rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString); | |
2184 | printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n", | |
2185 | rocketModel[i].modelString, | |
2186 | rocketModel[i].startingPortNumber, | |
2187 | rocketModel[i].startingPortNumber + | |
2188 | rocketModel[i].numPorts - 1); | |
2189 | ||
2190 | if (num_aiops <= 0) { | |
2191 | rcktpt_io_addr[i] = 0; | |
2192 | return (0); | |
2193 | } | |
2194 | is_PCI[i] = 1; | |
2195 | ||
2196 | /* Reset the AIOPIC, init the serial ports */ | |
2197 | for (aiop = 0; aiop < num_aiops; aiop++) { | |
2198 | sResetAiopByNum(ctlp, aiop); | |
2199 | num_chan = ports_per_aiop; | |
2200 | for (chan = 0; chan < num_chan; chan++) | |
2201 | init_r_port(i, aiop, chan, dev); | |
2202 | } | |
2203 | ||
2204 | /* Rocket modems must be reset */ | |
2205 | if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || | |
2206 | (rcktpt_type[i] == ROCKET_TYPE_MODEMII) || | |
2207 | (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) { | |
2208 | num_chan = ports_per_aiop; | |
2209 | for (chan = 0; chan < num_chan; chan++) | |
2210 | sPCIModemReset(ctlp, chan, 1); | |
2211 | mdelay(500); | |
2212 | for (chan = 0; chan < num_chan; chan++) | |
2213 | sPCIModemReset(ctlp, chan, 0); | |
2214 | mdelay(500); | |
2215 | rmSpeakerReset(ctlp, rocketModel[i].model); | |
2216 | } | |
2217 | return (1); | |
2218 | } | |
2219 | ||
2220 | /* | |
2221 | * Probes for PCI cards, inits them if found | |
2222 | * Input: board_found = number of ISA boards already found, or the | |
2223 | * starting board number | |
2224 | * Returns: Number of PCI boards found | |
2225 | */ | |
2226 | static int __init init_PCI(int boards_found) | |
2227 | { | |
2228 | struct pci_dev *dev = NULL; | |
2229 | int count = 0; | |
2230 | ||
2231 | /* Work through the PCI device list, pulling out ours */ | |
2232 | while ((dev = pci_find_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) { | |
2233 | if (register_PCI(count + boards_found, dev)) | |
2234 | count++; | |
2235 | } | |
2236 | return (count); | |
2237 | } | |
2238 | ||
2239 | #endif /* CONFIG_PCI */ | |
2240 | ||
2241 | /* | |
2242 | * Probes for ISA cards | |
2243 | * Input: i = the board number to look for | |
2244 | * Returns: 1 if board found, 0 else | |
2245 | */ | |
2246 | static int __init init_ISA(int i) | |
2247 | { | |
2248 | int num_aiops, num_chan = 0, total_num_chan = 0; | |
2249 | int aiop, chan; | |
2250 | unsigned int aiopio[MAX_AIOPS_PER_BOARD]; | |
2251 | CONTROLLER_t *ctlp; | |
2252 | char *type_string; | |
2253 | ||
2254 | /* If io_addr is zero, no board configured */ | |
2255 | if (rcktpt_io_addr[i] == 0) | |
2256 | return (0); | |
2257 | ||
2258 | /* Reserve the IO region */ | |
2259 | if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) { | |
2260 | printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]); | |
2261 | rcktpt_io_addr[i] = 0; | |
2262 | return (0); | |
2263 | } | |
2264 | ||
2265 | ctlp = sCtlNumToCtlPtr(i); | |
2266 | ||
2267 | ctlp->boardType = rcktpt_type[i]; | |
2268 | ||
2269 | switch (rcktpt_type[i]) { | |
2270 | case ROCKET_TYPE_PC104: | |
2271 | type_string = "(PC104)"; | |
2272 | break; | |
2273 | case ROCKET_TYPE_MODEM: | |
2274 | type_string = "(RocketModem)"; | |
2275 | break; | |
2276 | case ROCKET_TYPE_MODEMII: | |
2277 | type_string = "(RocketModem II)"; | |
2278 | break; | |
2279 | default: | |
2280 | type_string = ""; | |
2281 | break; | |
2282 | } | |
2283 | ||
2284 | /* | |
2285 | * If support_low_speed is set, use the slow clock prescale, | |
2286 | * which supports 50 bps | |
2287 | */ | |
2288 | if (support_low_speed) { | |
2289 | sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */ | |
2290 | rp_baud_base[i] = 230400; | |
2291 | } else { | |
2292 | sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */ | |
2293 | rp_baud_base[i] = 460800; | |
2294 | } | |
2295 | ||
2296 | for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++) | |
2297 | aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400); | |
2298 | ||
2299 | num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0); | |
2300 | ||
2301 | if (ctlp->boardType == ROCKET_TYPE_PC104) { | |
2302 | sEnAiop(ctlp, 2); /* only one AIOPIC, but these */ | |
2303 | sEnAiop(ctlp, 3); /* CSels used for other stuff */ | |
2304 | } | |
2305 | ||
2306 | /* If something went wrong initing the AIOP's release the ISA IO memory */ | |
2307 | if (num_aiops <= 0) { | |
2308 | release_region(rcktpt_io_addr[i], 64); | |
2309 | rcktpt_io_addr[i] = 0; | |
2310 | return (0); | |
2311 | } | |
2312 | ||
2313 | rocketModel[i].startingPortNumber = nextLineNumber; | |
2314 | ||
2315 | for (aiop = 0; aiop < num_aiops; aiop++) { | |
2316 | sResetAiopByNum(ctlp, aiop); | |
2317 | sEnAiop(ctlp, aiop); | |
2318 | num_chan = sGetAiopNumChan(ctlp, aiop); | |
2319 | total_num_chan += num_chan; | |
2320 | for (chan = 0; chan < num_chan; chan++) | |
2321 | init_r_port(i, aiop, chan, NULL); | |
2322 | } | |
2323 | is_PCI[i] = 0; | |
2324 | if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) { | |
2325 | num_chan = sGetAiopNumChan(ctlp, 0); | |
2326 | total_num_chan = num_chan; | |
2327 | for (chan = 0; chan < num_chan; chan++) | |
2328 | sModemReset(ctlp, chan, 1); | |
2329 | mdelay(500); | |
2330 | for (chan = 0; chan < num_chan; chan++) | |
2331 | sModemReset(ctlp, chan, 0); | |
2332 | mdelay(500); | |
2333 | strcpy(rocketModel[i].modelString, "RocketModem ISA"); | |
2334 | } else { | |
2335 | strcpy(rocketModel[i].modelString, "RocketPort ISA"); | |
2336 | } | |
2337 | rocketModel[i].numPorts = total_num_chan; | |
2338 | rocketModel[i].model = MODEL_ISA; | |
2339 | ||
2340 | printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n", | |
2341 | i, rcktpt_io_addr[i], num_aiops, type_string); | |
2342 | ||
2343 | printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n", | |
2344 | rocketModel[i].modelString, | |
2345 | rocketModel[i].startingPortNumber, | |
2346 | rocketModel[i].startingPortNumber + | |
2347 | rocketModel[i].numPorts - 1); | |
2348 | ||
2349 | return (1); | |
2350 | } | |
2351 | ||
2352 | static struct tty_operations rocket_ops = { | |
2353 | .open = rp_open, | |
2354 | .close = rp_close, | |
2355 | .write = rp_write, | |
2356 | .put_char = rp_put_char, | |
2357 | .write_room = rp_write_room, | |
2358 | .chars_in_buffer = rp_chars_in_buffer, | |
2359 | .flush_buffer = rp_flush_buffer, | |
2360 | .ioctl = rp_ioctl, | |
2361 | .throttle = rp_throttle, | |
2362 | .unthrottle = rp_unthrottle, | |
2363 | .set_termios = rp_set_termios, | |
2364 | .stop = rp_stop, | |
2365 | .start = rp_start, | |
2366 | .hangup = rp_hangup, | |
2367 | .break_ctl = rp_break, | |
2368 | .send_xchar = rp_send_xchar, | |
2369 | .wait_until_sent = rp_wait_until_sent, | |
2370 | .tiocmget = rp_tiocmget, | |
2371 | .tiocmset = rp_tiocmset, | |
2372 | }; | |
2373 | ||
2374 | /* | |
2375 | * The module "startup" routine; it's run when the module is loaded. | |
2376 | */ | |
d269cdd0 | 2377 | static int __init rp_init(void) |
1da177e4 LT |
2378 | { |
2379 | int retval, pci_boards_found, isa_boards_found, i; | |
2380 | ||
2381 | printk(KERN_INFO "RocketPort device driver module, version %s, %s\n", | |
2382 | ROCKET_VERSION, ROCKET_DATE); | |
2383 | ||
2384 | rocket_driver = alloc_tty_driver(MAX_RP_PORTS); | |
2385 | if (!rocket_driver) | |
2386 | return -ENOMEM; | |
2387 | ||
2388 | /* | |
2389 | * Set up the timer channel. | |
2390 | */ | |
2391 | init_timer(&rocket_timer); | |
2392 | rocket_timer.function = rp_do_poll; | |
2393 | ||
2394 | /* | |
2395 | * Initialize the array of pointers to our own internal state | |
2396 | * structures. | |
2397 | */ | |
2398 | memset(rp_table, 0, sizeof (rp_table)); | |
2399 | memset(xmit_flags, 0, sizeof (xmit_flags)); | |
2400 | ||
2401 | for (i = 0; i < MAX_RP_PORTS; i++) | |
2402 | lineNumbers[i] = 0; | |
2403 | nextLineNumber = 0; | |
2404 | memset(rocketModel, 0, sizeof (rocketModel)); | |
2405 | ||
2406 | /* | |
2407 | * If board 1 is non-zero, there is at least one ISA configured. If controller is | |
2408 | * zero, use the default controller IO address of board1 + 0x40. | |
2409 | */ | |
2410 | if (board1) { | |
2411 | if (controller == 0) | |
2412 | controller = board1 + 0x40; | |
2413 | } else { | |
2414 | controller = 0; /* Used as a flag, meaning no ISA boards */ | |
2415 | } | |
2416 | ||
2417 | /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */ | |
2418 | if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) { | |
2419 | printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx. Driver exiting \n", controller); | |
2420 | return -EBUSY; | |
2421 | } | |
2422 | ||
2423 | /* Store ISA variable retrieved from command line or .conf file. */ | |
2424 | rcktpt_io_addr[0] = board1; | |
2425 | rcktpt_io_addr[1] = board2; | |
2426 | rcktpt_io_addr[2] = board3; | |
2427 | rcktpt_io_addr[3] = board4; | |
2428 | ||
2429 | rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL; | |
2430 | rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0]; | |
2431 | rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL; | |
2432 | rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1]; | |
2433 | rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL; | |
2434 | rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2]; | |
2435 | rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL; | |
2436 | rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3]; | |
2437 | ||
2438 | /* | |
2439 | * Set up the tty driver structure and then register this | |
2440 | * driver with the tty layer. | |
2441 | */ | |
2442 | ||
2443 | rocket_driver->owner = THIS_MODULE; | |
2444 | rocket_driver->flags = TTY_DRIVER_NO_DEVFS; | |
2445 | rocket_driver->devfs_name = "tts/R"; | |
2446 | rocket_driver->name = "ttyR"; | |
2447 | rocket_driver->driver_name = "Comtrol RocketPort"; | |
2448 | rocket_driver->major = TTY_ROCKET_MAJOR; | |
2449 | rocket_driver->minor_start = 0; | |
2450 | rocket_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
2451 | rocket_driver->subtype = SERIAL_TYPE_NORMAL; | |
2452 | rocket_driver->init_termios = tty_std_termios; | |
2453 | rocket_driver->init_termios.c_cflag = | |
2454 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
2455 | #ifdef ROCKET_SOFT_FLOW | |
2456 | rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS; | |
2457 | #endif | |
2458 | tty_set_operations(rocket_driver, &rocket_ops); | |
2459 | ||
2460 | retval = tty_register_driver(rocket_driver); | |
2461 | if (retval < 0) { | |
2462 | printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval); | |
2463 | put_tty_driver(rocket_driver); | |
2464 | return -1; | |
2465 | } | |
2466 | ||
2467 | #ifdef ROCKET_DEBUG_OPEN | |
2468 | printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major); | |
2469 | #endif | |
2470 | ||
2471 | /* | |
2472 | * OK, let's probe each of the controllers looking for boards. Any boards found | |
2473 | * will be initialized here. | |
2474 | */ | |
2475 | isa_boards_found = 0; | |
2476 | pci_boards_found = 0; | |
2477 | ||
2478 | for (i = 0; i < NUM_BOARDS; i++) { | |
2479 | if (init_ISA(i)) | |
2480 | isa_boards_found++; | |
2481 | } | |
2482 | ||
2483 | #ifdef CONFIG_PCI | |
2484 | if (isa_boards_found < NUM_BOARDS) | |
2485 | pci_boards_found = init_PCI(isa_boards_found); | |
2486 | #endif | |
2487 | ||
2488 | max_board = pci_boards_found + isa_boards_found; | |
2489 | ||
2490 | if (max_board == 0) { | |
2491 | printk(KERN_INFO "No rocketport ports found; unloading driver.\n"); | |
2492 | del_timer_sync(&rocket_timer); | |
2493 | tty_unregister_driver(rocket_driver); | |
2494 | put_tty_driver(rocket_driver); | |
2495 | return -ENXIO; | |
2496 | } | |
2497 | ||
2498 | return 0; | |
2499 | } | |
2500 | ||
1da177e4 LT |
2501 | |
2502 | static void rp_cleanup_module(void) | |
2503 | { | |
2504 | int retval; | |
2505 | int i; | |
2506 | ||
2507 | del_timer_sync(&rocket_timer); | |
2508 | ||
2509 | retval = tty_unregister_driver(rocket_driver); | |
2510 | if (retval) | |
2511 | printk(KERN_INFO "Error %d while trying to unregister " | |
2512 | "rocketport driver\n", -retval); | |
2513 | put_tty_driver(rocket_driver); | |
2514 | ||
735d5661 JJ |
2515 | for (i = 0; i < MAX_RP_PORTS; i++) |
2516 | kfree(rp_table[i]); | |
1da177e4 LT |
2517 | |
2518 | for (i = 0; i < NUM_BOARDS; i++) { | |
2519 | if (rcktpt_io_addr[i] <= 0 || is_PCI[i]) | |
2520 | continue; | |
2521 | release_region(rcktpt_io_addr[i], 64); | |
2522 | } | |
2523 | if (controller) | |
2524 | release_region(controller, 4); | |
2525 | } | |
1da177e4 | 2526 | |
1da177e4 LT |
2527 | /*************************************************************************** |
2528 | Function: sInitController | |
2529 | Purpose: Initialization of controller global registers and controller | |
2530 | structure. | |
2531 | Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize, | |
2532 | IRQNum,Frequency,PeriodicOnly) | |
2533 | CONTROLLER_T *CtlP; Ptr to controller structure | |
2534 | int CtlNum; Controller number | |
2535 | ByteIO_t MudbacIO; Mudbac base I/O address. | |
2536 | ByteIO_t *AiopIOList; List of I/O addresses for each AIOP. | |
2537 | This list must be in the order the AIOPs will be found on the | |
2538 | controller. Once an AIOP in the list is not found, it is | |
2539 | assumed that there are no more AIOPs on the controller. | |
2540 | int AiopIOListSize; Number of addresses in AiopIOList | |
2541 | int IRQNum; Interrupt Request number. Can be any of the following: | |
2542 | 0: Disable global interrupts | |
2543 | 3: IRQ 3 | |
2544 | 4: IRQ 4 | |
2545 | 5: IRQ 5 | |
2546 | 9: IRQ 9 | |
2547 | 10: IRQ 10 | |
2548 | 11: IRQ 11 | |
2549 | 12: IRQ 12 | |
2550 | 15: IRQ 15 | |
2551 | Byte_t Frequency: A flag identifying the frequency | |
2552 | of the periodic interrupt, can be any one of the following: | |
2553 | FREQ_DIS - periodic interrupt disabled | |
2554 | FREQ_137HZ - 137 Hertz | |
2555 | FREQ_69HZ - 69 Hertz | |
2556 | FREQ_34HZ - 34 Hertz | |
2557 | FREQ_17HZ - 17 Hertz | |
2558 | FREQ_9HZ - 9 Hertz | |
2559 | FREQ_4HZ - 4 Hertz | |
2560 | If IRQNum is set to 0 the Frequency parameter is | |
2561 | overidden, it is forced to a value of FREQ_DIS. | |
f15313bf | 2562 | int PeriodicOnly: 1 if all interrupts except the periodic |
1da177e4 | 2563 | interrupt are to be blocked. |
f15313bf | 2564 | 0 is both the periodic interrupt and |
1da177e4 LT |
2565 | other channel interrupts are allowed. |
2566 | If IRQNum is set to 0 the PeriodicOnly parameter is | |
f15313bf | 2567 | overidden, it is forced to a value of 0. |
1da177e4 LT |
2568 | Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller |
2569 | initialization failed. | |
2570 | ||
2571 | Comments: | |
2572 | If periodic interrupts are to be disabled but AIOP interrupts | |
f15313bf | 2573 | are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0. |
1da177e4 LT |
2574 | |
2575 | If interrupts are to be completely disabled set IRQNum to 0. | |
2576 | ||
f15313bf | 2577 | Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an |
1da177e4 LT |
2578 | invalid combination. |
2579 | ||
2580 | This function performs initialization of global interrupt modes, | |
2581 | but it does not actually enable global interrupts. To enable | |
2582 | and disable global interrupts use functions sEnGlobalInt() and | |
2583 | sDisGlobalInt(). Enabling of global interrupts is normally not | |
2584 | done until all other initializations are complete. | |
2585 | ||
2586 | Even if interrupts are globally enabled, they must also be | |
2587 | individually enabled for each channel that is to generate | |
2588 | interrupts. | |
2589 | ||
2590 | Warnings: No range checking on any of the parameters is done. | |
2591 | ||
2592 | No context switches are allowed while executing this function. | |
2593 | ||
2594 | After this function all AIOPs on the controller are disabled, | |
2595 | they can be enabled with sEnAiop(). | |
2596 | */ | |
f15313bf AB |
2597 | static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO, |
2598 | ByteIO_t * AiopIOList, int AiopIOListSize, | |
2599 | int IRQNum, Byte_t Frequency, int PeriodicOnly) | |
1da177e4 LT |
2600 | { |
2601 | int i; | |
2602 | ByteIO_t io; | |
2603 | int done; | |
2604 | ||
2605 | CtlP->AiopIntrBits = aiop_intr_bits; | |
2606 | CtlP->AltChanRingIndicator = 0; | |
2607 | CtlP->CtlNum = CtlNum; | |
2608 | CtlP->CtlID = CTLID_0001; /* controller release 1 */ | |
2609 | CtlP->BusType = isISA; | |
2610 | CtlP->MBaseIO = MudbacIO; | |
2611 | CtlP->MReg1IO = MudbacIO + 1; | |
2612 | CtlP->MReg2IO = MudbacIO + 2; | |
2613 | CtlP->MReg3IO = MudbacIO + 3; | |
2614 | #if 1 | |
2615 | CtlP->MReg2 = 0; /* interrupt disable */ | |
2616 | CtlP->MReg3 = 0; /* no periodic interrupts */ | |
2617 | #else | |
2618 | if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */ | |
2619 | CtlP->MReg2 = 0; /* interrupt disable */ | |
2620 | CtlP->MReg3 = 0; /* no periodic interrupts */ | |
2621 | } else { | |
2622 | CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */ | |
2623 | CtlP->MReg3 = Frequency; /* set frequency */ | |
2624 | if (PeriodicOnly) { /* periodic interrupt only */ | |
2625 | CtlP->MReg3 |= PERIODIC_ONLY; | |
2626 | } | |
2627 | } | |
2628 | #endif | |
2629 | sOutB(CtlP->MReg2IO, CtlP->MReg2); | |
2630 | sOutB(CtlP->MReg3IO, CtlP->MReg3); | |
2631 | sControllerEOI(CtlP); /* clear EOI if warm init */ | |
2632 | /* Init AIOPs */ | |
2633 | CtlP->NumAiop = 0; | |
2634 | for (i = done = 0; i < AiopIOListSize; i++) { | |
2635 | io = AiopIOList[i]; | |
2636 | CtlP->AiopIO[i] = (WordIO_t) io; | |
2637 | CtlP->AiopIntChanIO[i] = io + _INT_CHAN; | |
2638 | sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */ | |
2639 | sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */ | |
2640 | if (done) | |
2641 | continue; | |
2642 | sEnAiop(CtlP, i); /* enable the AIOP */ | |
2643 | CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */ | |
2644 | if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */ | |
2645 | done = 1; /* done looking for AIOPs */ | |
2646 | else { | |
2647 | CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */ | |
2648 | sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ | |
2649 | sOutB(io + _INDX_DATA, sClockPrescale); | |
2650 | CtlP->NumAiop++; /* bump count of AIOPs */ | |
2651 | } | |
2652 | sDisAiop(CtlP, i); /* disable AIOP */ | |
2653 | } | |
2654 | ||
2655 | if (CtlP->NumAiop == 0) | |
2656 | return (-1); | |
2657 | else | |
2658 | return (CtlP->NumAiop); | |
2659 | } | |
2660 | ||
2661 | /*************************************************************************** | |
2662 | Function: sPCIInitController | |
2663 | Purpose: Initialization of controller global registers and controller | |
2664 | structure. | |
2665 | Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize, | |
2666 | IRQNum,Frequency,PeriodicOnly) | |
2667 | CONTROLLER_T *CtlP; Ptr to controller structure | |
2668 | int CtlNum; Controller number | |
2669 | ByteIO_t *AiopIOList; List of I/O addresses for each AIOP. | |
2670 | This list must be in the order the AIOPs will be found on the | |
2671 | controller. Once an AIOP in the list is not found, it is | |
2672 | assumed that there are no more AIOPs on the controller. | |
2673 | int AiopIOListSize; Number of addresses in AiopIOList | |
2674 | int IRQNum; Interrupt Request number. Can be any of the following: | |
2675 | 0: Disable global interrupts | |
2676 | 3: IRQ 3 | |
2677 | 4: IRQ 4 | |
2678 | 5: IRQ 5 | |
2679 | 9: IRQ 9 | |
2680 | 10: IRQ 10 | |
2681 | 11: IRQ 11 | |
2682 | 12: IRQ 12 | |
2683 | 15: IRQ 15 | |
2684 | Byte_t Frequency: A flag identifying the frequency | |
2685 | of the periodic interrupt, can be any one of the following: | |
2686 | FREQ_DIS - periodic interrupt disabled | |
2687 | FREQ_137HZ - 137 Hertz | |
2688 | FREQ_69HZ - 69 Hertz | |
2689 | FREQ_34HZ - 34 Hertz | |
2690 | FREQ_17HZ - 17 Hertz | |
2691 | FREQ_9HZ - 9 Hertz | |
2692 | FREQ_4HZ - 4 Hertz | |
2693 | If IRQNum is set to 0 the Frequency parameter is | |
2694 | overidden, it is forced to a value of FREQ_DIS. | |
f15313bf | 2695 | int PeriodicOnly: 1 if all interrupts except the periodic |
1da177e4 | 2696 | interrupt are to be blocked. |
f15313bf | 2697 | 0 is both the periodic interrupt and |
1da177e4 LT |
2698 | other channel interrupts are allowed. |
2699 | If IRQNum is set to 0 the PeriodicOnly parameter is | |
f15313bf | 2700 | overidden, it is forced to a value of 0. |
1da177e4 LT |
2701 | Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller |
2702 | initialization failed. | |
2703 | ||
2704 | Comments: | |
2705 | If periodic interrupts are to be disabled but AIOP interrupts | |
f15313bf | 2706 | are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0. |
1da177e4 LT |
2707 | |
2708 | If interrupts are to be completely disabled set IRQNum to 0. | |
2709 | ||
f15313bf | 2710 | Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an |
1da177e4 LT |
2711 | invalid combination. |
2712 | ||
2713 | This function performs initialization of global interrupt modes, | |
2714 | but it does not actually enable global interrupts. To enable | |
2715 | and disable global interrupts use functions sEnGlobalInt() and | |
2716 | sDisGlobalInt(). Enabling of global interrupts is normally not | |
2717 | done until all other initializations are complete. | |
2718 | ||
2719 | Even if interrupts are globally enabled, they must also be | |
2720 | individually enabled for each channel that is to generate | |
2721 | interrupts. | |
2722 | ||
2723 | Warnings: No range checking on any of the parameters is done. | |
2724 | ||
2725 | No context switches are allowed while executing this function. | |
2726 | ||
2727 | After this function all AIOPs on the controller are disabled, | |
2728 | they can be enabled with sEnAiop(). | |
2729 | */ | |
f15313bf AB |
2730 | static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum, |
2731 | ByteIO_t * AiopIOList, int AiopIOListSize, | |
2732 | WordIO_t ConfigIO, int IRQNum, Byte_t Frequency, | |
2733 | int PeriodicOnly, int altChanRingIndicator, | |
2734 | int UPCIRingInd) | |
1da177e4 LT |
2735 | { |
2736 | int i; | |
2737 | ByteIO_t io; | |
2738 | ||
2739 | CtlP->AltChanRingIndicator = altChanRingIndicator; | |
2740 | CtlP->UPCIRingInd = UPCIRingInd; | |
2741 | CtlP->CtlNum = CtlNum; | |
2742 | CtlP->CtlID = CTLID_0001; /* controller release 1 */ | |
2743 | CtlP->BusType = isPCI; /* controller release 1 */ | |
2744 | ||
2745 | if (ConfigIO) { | |
2746 | CtlP->isUPCI = 1; | |
2747 | CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL; | |
2748 | CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL; | |
2749 | CtlP->AiopIntrBits = upci_aiop_intr_bits; | |
2750 | } else { | |
2751 | CtlP->isUPCI = 0; | |
2752 | CtlP->PCIIO = | |
2753 | (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC); | |
2754 | CtlP->AiopIntrBits = aiop_intr_bits; | |
2755 | } | |
2756 | ||
2757 | sPCIControllerEOI(CtlP); /* clear EOI if warm init */ | |
2758 | /* Init AIOPs */ | |
2759 | CtlP->NumAiop = 0; | |
2760 | for (i = 0; i < AiopIOListSize; i++) { | |
2761 | io = AiopIOList[i]; | |
2762 | CtlP->AiopIO[i] = (WordIO_t) io; | |
2763 | CtlP->AiopIntChanIO[i] = io + _INT_CHAN; | |
2764 | ||
2765 | CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */ | |
2766 | if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */ | |
2767 | break; /* done looking for AIOPs */ | |
2768 | ||
2769 | CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */ | |
2770 | sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ | |
2771 | sOutB(io + _INDX_DATA, sClockPrescale); | |
2772 | CtlP->NumAiop++; /* bump count of AIOPs */ | |
2773 | } | |
2774 | ||
2775 | if (CtlP->NumAiop == 0) | |
2776 | return (-1); | |
2777 | else | |
2778 | return (CtlP->NumAiop); | |
2779 | } | |
2780 | ||
2781 | /*************************************************************************** | |
2782 | Function: sReadAiopID | |
2783 | Purpose: Read the AIOP idenfication number directly from an AIOP. | |
2784 | Call: sReadAiopID(io) | |
2785 | ByteIO_t io: AIOP base I/O address | |
2786 | Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X | |
2787 | is replace by an identifying number. | |
2788 | Flag AIOPID_NULL if no valid AIOP is found | |
2789 | Warnings: No context switches are allowed while executing this function. | |
2790 | ||
2791 | */ | |
f15313bf | 2792 | static int sReadAiopID(ByteIO_t io) |
1da177e4 LT |
2793 | { |
2794 | Byte_t AiopID; /* ID byte from AIOP */ | |
2795 | ||
2796 | sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */ | |
2797 | sOutB(io + _CMD_REG, 0x0); | |
2798 | AiopID = sInW(io + _CHN_STAT0) & 0x07; | |
2799 | if (AiopID == 0x06) | |
2800 | return (1); | |
2801 | else /* AIOP does not exist */ | |
2802 | return (-1); | |
2803 | } | |
2804 | ||
2805 | /*************************************************************************** | |
2806 | Function: sReadAiopNumChan | |
2807 | Purpose: Read the number of channels available in an AIOP directly from | |
2808 | an AIOP. | |
2809 | Call: sReadAiopNumChan(io) | |
2810 | WordIO_t io: AIOP base I/O address | |
2811 | Return: int: The number of channels available | |
2812 | Comments: The number of channels is determined by write/reads from identical | |
2813 | offsets within the SRAM address spaces for channels 0 and 4. | |
2814 | If the channel 4 space is mirrored to channel 0 it is a 4 channel | |
2815 | AIOP, otherwise it is an 8 channel. | |
2816 | Warnings: No context switches are allowed while executing this function. | |
2817 | */ | |
f15313bf | 2818 | static int sReadAiopNumChan(WordIO_t io) |
1da177e4 LT |
2819 | { |
2820 | Word_t x; | |
2821 | static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 }; | |
2822 | ||
2823 | /* write to chan 0 SRAM */ | |
2824 | sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0])); | |
2825 | sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ | |
2826 | x = sInW(io + _INDX_DATA); | |
2827 | sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ | |
2828 | if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */ | |
2829 | return (8); | |
2830 | else | |
2831 | return (4); | |
2832 | } | |
2833 | ||
2834 | /*************************************************************************** | |
2835 | Function: sInitChan | |
2836 | Purpose: Initialization of a channel and channel structure | |
2837 | Call: sInitChan(CtlP,ChP,AiopNum,ChanNum) | |
2838 | CONTROLLER_T *CtlP; Ptr to controller structure | |
2839 | CHANNEL_T *ChP; Ptr to channel structure | |
2840 | int AiopNum; AIOP number within controller | |
2841 | int ChanNum; Channel number within AIOP | |
f15313bf | 2842 | Return: int: 1 if initialization succeeded, 0 if it fails because channel |
1da177e4 LT |
2843 | number exceeds number of channels available in AIOP. |
2844 | Comments: This function must be called before a channel can be used. | |
2845 | Warnings: No range checking on any of the parameters is done. | |
2846 | ||
2847 | No context switches are allowed while executing this function. | |
2848 | */ | |
f15313bf AB |
2849 | static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum, |
2850 | int ChanNum) | |
1da177e4 LT |
2851 | { |
2852 | int i; | |
2853 | WordIO_t AiopIO; | |
2854 | WordIO_t ChIOOff; | |
2855 | Byte_t *ChR; | |
2856 | Word_t ChOff; | |
2857 | static Byte_t R[4]; | |
2858 | int brd9600; | |
2859 | ||
2860 | if (ChanNum >= CtlP->AiopNumChan[AiopNum]) | |
f15313bf | 2861 | return 0; /* exceeds num chans in AIOP */ |
1da177e4 LT |
2862 | |
2863 | /* Channel, AIOP, and controller identifiers */ | |
2864 | ChP->CtlP = CtlP; | |
2865 | ChP->ChanID = CtlP->AiopID[AiopNum]; | |
2866 | ChP->AiopNum = AiopNum; | |
2867 | ChP->ChanNum = ChanNum; | |
2868 | ||
2869 | /* Global direct addresses */ | |
2870 | AiopIO = CtlP->AiopIO[AiopNum]; | |
2871 | ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG; | |
2872 | ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN; | |
2873 | ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK; | |
2874 | ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR; | |
2875 | ChP->IndexData = AiopIO + _INDX_DATA; | |
2876 | ||
2877 | /* Channel direct addresses */ | |
2878 | ChIOOff = AiopIO + ChP->ChanNum * 2; | |
2879 | ChP->TxRxData = ChIOOff + _TD0; | |
2880 | ChP->ChanStat = ChIOOff + _CHN_STAT0; | |
2881 | ChP->TxRxCount = ChIOOff + _FIFO_CNT0; | |
2882 | ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0; | |
2883 | ||
2884 | /* Initialize the channel from the RData array */ | |
2885 | for (i = 0; i < RDATASIZE; i += 4) { | |
2886 | R[0] = RData[i]; | |
2887 | R[1] = RData[i + 1] + 0x10 * ChanNum; | |
2888 | R[2] = RData[i + 2]; | |
2889 | R[3] = RData[i + 3]; | |
2890 | sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0])); | |
2891 | } | |
2892 | ||
2893 | ChR = ChP->R; | |
2894 | for (i = 0; i < RREGDATASIZE; i += 4) { | |
2895 | ChR[i] = RRegData[i]; | |
2896 | ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum; | |
2897 | ChR[i + 2] = RRegData[i + 2]; | |
2898 | ChR[i + 3] = RRegData[i + 3]; | |
2899 | } | |
2900 | ||
2901 | /* Indexed registers */ | |
2902 | ChOff = (Word_t) ChanNum *0x1000; | |
2903 | ||
2904 | if (sClockPrescale == 0x14) | |
2905 | brd9600 = 47; | |
2906 | else | |
2907 | brd9600 = 23; | |
2908 | ||
2909 | ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD); | |
2910 | ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8); | |
2911 | ChP->BaudDiv[2] = (Byte_t) brd9600; | |
2912 | ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8); | |
2913 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]); | |
2914 | ||
2915 | ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL); | |
2916 | ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8); | |
2917 | ChP->TxControl[2] = 0; | |
2918 | ChP->TxControl[3] = 0; | |
2919 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); | |
2920 | ||
2921 | ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL); | |
2922 | ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8); | |
2923 | ChP->RxControl[2] = 0; | |
2924 | ChP->RxControl[3] = 0; | |
2925 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); | |
2926 | ||
2927 | ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS); | |
2928 | ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8); | |
2929 | ChP->TxEnables[2] = 0; | |
2930 | ChP->TxEnables[3] = 0; | |
2931 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]); | |
2932 | ||
2933 | ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1); | |
2934 | ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8); | |
2935 | ChP->TxCompare[2] = 0; | |
2936 | ChP->TxCompare[3] = 0; | |
2937 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]); | |
2938 | ||
2939 | ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1); | |
2940 | ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8); | |
2941 | ChP->TxReplace1[2] = 0; | |
2942 | ChP->TxReplace1[3] = 0; | |
2943 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]); | |
2944 | ||
2945 | ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2); | |
2946 | ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8); | |
2947 | ChP->TxReplace2[2] = 0; | |
2948 | ChP->TxReplace2[3] = 0; | |
2949 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]); | |
2950 | ||
2951 | ChP->TxFIFOPtrs = ChOff + _TXF_OUTP; | |
2952 | ChP->TxFIFO = ChOff + _TX_FIFO; | |
2953 | ||
2954 | sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */ | |
2955 | sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */ | |
2956 | sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ | |
2957 | sOutW(ChP->IndexData, 0); | |
2958 | ChP->RxFIFOPtrs = ChOff + _RXF_OUTP; | |
2959 | ChP->RxFIFO = ChOff + _RX_FIFO; | |
2960 | ||
2961 | sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */ | |
2962 | sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */ | |
2963 | sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ | |
2964 | sOutW(ChP->IndexData, 0); | |
2965 | sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ | |
2966 | sOutW(ChP->IndexData, 0); | |
2967 | ChP->TxPrioCnt = ChOff + _TXP_CNT; | |
2968 | sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt); | |
2969 | sOutB(ChP->IndexData, 0); | |
2970 | ChP->TxPrioPtr = ChOff + _TXP_PNTR; | |
2971 | sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr); | |
2972 | sOutB(ChP->IndexData, 0); | |
2973 | ChP->TxPrioBuf = ChOff + _TXP_BUF; | |
2974 | sEnRxProcessor(ChP); /* start the Rx processor */ | |
2975 | ||
f15313bf | 2976 | return 1; |
1da177e4 LT |
2977 | } |
2978 | ||
2979 | /*************************************************************************** | |
2980 | Function: sStopRxProcessor | |
2981 | Purpose: Stop the receive processor from processing a channel. | |
2982 | Call: sStopRxProcessor(ChP) | |
2983 | CHANNEL_T *ChP; Ptr to channel structure | |
2984 | ||
2985 | Comments: The receive processor can be started again with sStartRxProcessor(). | |
2986 | This function causes the receive processor to skip over the | |
2987 | stopped channel. It does not stop it from processing other channels. | |
2988 | ||
2989 | Warnings: No context switches are allowed while executing this function. | |
2990 | ||
2991 | Do not leave the receive processor stopped for more than one | |
2992 | character time. | |
2993 | ||
2994 | After calling this function a delay of 4 uS is required to ensure | |
2995 | that the receive processor is no longer processing this channel. | |
2996 | */ | |
f15313bf | 2997 | static void sStopRxProcessor(CHANNEL_T * ChP) |
1da177e4 LT |
2998 | { |
2999 | Byte_t R[4]; | |
3000 | ||
3001 | R[0] = ChP->R[0]; | |
3002 | R[1] = ChP->R[1]; | |
3003 | R[2] = 0x0a; | |
3004 | R[3] = ChP->R[3]; | |
3005 | sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]); | |
3006 | } | |
3007 | ||
3008 | /*************************************************************************** | |
3009 | Function: sFlushRxFIFO | |
3010 | Purpose: Flush the Rx FIFO | |
3011 | Call: sFlushRxFIFO(ChP) | |
3012 | CHANNEL_T *ChP; Ptr to channel structure | |
3013 | Return: void | |
3014 | Comments: To prevent data from being enqueued or dequeued in the Tx FIFO | |
3015 | while it is being flushed the receive processor is stopped | |
3016 | and the transmitter is disabled. After these operations a | |
3017 | 4 uS delay is done before clearing the pointers to allow | |
3018 | the receive processor to stop. These items are handled inside | |
3019 | this function. | |
3020 | Warnings: No context switches are allowed while executing this function. | |
3021 | */ | |
f15313bf | 3022 | static void sFlushRxFIFO(CHANNEL_T * ChP) |
1da177e4 LT |
3023 | { |
3024 | int i; | |
3025 | Byte_t Ch; /* channel number within AIOP */ | |
f15313bf | 3026 | int RxFIFOEnabled; /* 1 if Rx FIFO enabled */ |
1da177e4 LT |
3027 | |
3028 | if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */ | |
3029 | return; /* don't need to flush */ | |
3030 | ||
f15313bf | 3031 | RxFIFOEnabled = 0; |
1da177e4 | 3032 | if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */ |
f15313bf | 3033 | RxFIFOEnabled = 1; |
1da177e4 LT |
3034 | sDisRxFIFO(ChP); /* disable it */ |
3035 | for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */ | |
3036 | sInB(ChP->IntChan); /* depends on bus i/o timing */ | |
3037 | } | |
3038 | sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */ | |
3039 | Ch = (Byte_t) sGetChanNum(ChP); | |
3040 | sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */ | |
3041 | sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */ | |
3042 | sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ | |
3043 | sOutW(ChP->IndexData, 0); | |
3044 | sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ | |
3045 | sOutW(ChP->IndexData, 0); | |
3046 | if (RxFIFOEnabled) | |
3047 | sEnRxFIFO(ChP); /* enable Rx FIFO */ | |
3048 | } | |
3049 | ||
3050 | /*************************************************************************** | |
3051 | Function: sFlushTxFIFO | |
3052 | Purpose: Flush the Tx FIFO | |
3053 | Call: sFlushTxFIFO(ChP) | |
3054 | CHANNEL_T *ChP; Ptr to channel structure | |
3055 | Return: void | |
3056 | Comments: To prevent data from being enqueued or dequeued in the Tx FIFO | |
3057 | while it is being flushed the receive processor is stopped | |
3058 | and the transmitter is disabled. After these operations a | |
3059 | 4 uS delay is done before clearing the pointers to allow | |
3060 | the receive processor to stop. These items are handled inside | |
3061 | this function. | |
3062 | Warnings: No context switches are allowed while executing this function. | |
3063 | */ | |
f15313bf | 3064 | static void sFlushTxFIFO(CHANNEL_T * ChP) |
1da177e4 LT |
3065 | { |
3066 | int i; | |
3067 | Byte_t Ch; /* channel number within AIOP */ | |
f15313bf | 3068 | int TxEnabled; /* 1 if transmitter enabled */ |
1da177e4 LT |
3069 | |
3070 | if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */ | |
3071 | return; /* don't need to flush */ | |
3072 | ||
f15313bf | 3073 | TxEnabled = 0; |
1da177e4 | 3074 | if (ChP->TxControl[3] & TX_ENABLE) { |
f15313bf | 3075 | TxEnabled = 1; |
1da177e4 LT |
3076 | sDisTransmit(ChP); /* disable transmitter */ |
3077 | } | |
3078 | sStopRxProcessor(ChP); /* stop Rx processor */ | |
3079 | for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */ | |
3080 | sInB(ChP->IntChan); /* depends on bus i/o timing */ | |
3081 | Ch = (Byte_t) sGetChanNum(ChP); | |
3082 | sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */ | |
3083 | sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */ | |
3084 | sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ | |
3085 | sOutW(ChP->IndexData, 0); | |
3086 | if (TxEnabled) | |
3087 | sEnTransmit(ChP); /* enable transmitter */ | |
3088 | sStartRxProcessor(ChP); /* restart Rx processor */ | |
3089 | } | |
3090 | ||
3091 | /*************************************************************************** | |
3092 | Function: sWriteTxPrioByte | |
3093 | Purpose: Write a byte of priority transmit data to a channel | |
3094 | Call: sWriteTxPrioByte(ChP,Data) | |
3095 | CHANNEL_T *ChP; Ptr to channel structure | |
3096 | Byte_t Data; The transmit data byte | |
3097 | ||
3098 | Return: int: 1 if the bytes is successfully written, otherwise 0. | |
3099 | ||
3100 | Comments: The priority byte is transmitted before any data in the Tx FIFO. | |
3101 | ||
3102 | Warnings: No context switches are allowed while executing this function. | |
3103 | */ | |
f15313bf | 3104 | static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data) |
1da177e4 LT |
3105 | { |
3106 | Byte_t DWBuf[4]; /* buffer for double word writes */ | |
3107 | Word_t *WordPtr; /* must be far because Win SS != DS */ | |
3108 | register DWordIO_t IndexAddr; | |
3109 | ||
3110 | if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */ | |
3111 | IndexAddr = ChP->IndexAddr; | |
3112 | sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */ | |
3113 | if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */ | |
3114 | return (0); /* nothing sent */ | |
3115 | ||
3116 | WordPtr = (Word_t *) (&DWBuf[0]); | |
3117 | *WordPtr = ChP->TxPrioBuf; /* data byte address */ | |
3118 | ||
3119 | DWBuf[2] = Data; /* data byte value */ | |
3120 | sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ | |
3121 | ||
3122 | *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */ | |
3123 | ||
3124 | DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */ | |
3125 | DWBuf[3] = 0; /* priority buffer pointer */ | |
3126 | sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ | |
3127 | } else { /* write it to Tx FIFO */ | |
3128 | ||
3129 | sWriteTxByte(sGetTxRxDataIO(ChP), Data); | |
3130 | } | |
3131 | return (1); /* 1 byte sent */ | |
3132 | } | |
3133 | ||
3134 | /*************************************************************************** | |
3135 | Function: sEnInterrupts | |
3136 | Purpose: Enable one or more interrupts for a channel | |
3137 | Call: sEnInterrupts(ChP,Flags) | |
3138 | CHANNEL_T *ChP; Ptr to channel structure | |
3139 | Word_t Flags: Interrupt enable flags, can be any combination | |
3140 | of the following flags: | |
3141 | TXINT_EN: Interrupt on Tx FIFO empty | |
3142 | RXINT_EN: Interrupt on Rx FIFO at trigger level (see | |
3143 | sSetRxTrigger()) | |
3144 | SRCINT_EN: Interrupt on SRC (Special Rx Condition) | |
3145 | MCINT_EN: Interrupt on modem input change | |
3146 | CHANINT_EN: Allow channel interrupt signal to the AIOP's | |
3147 | Interrupt Channel Register. | |
3148 | Return: void | |
3149 | Comments: If an interrupt enable flag is set in Flags, that interrupt will be | |
3150 | enabled. If an interrupt enable flag is not set in Flags, that | |
3151 | interrupt will not be changed. Interrupts can be disabled with | |
3152 | function sDisInterrupts(). | |
3153 | ||
3154 | This function sets the appropriate bit for the channel in the AIOP's | |
3155 | Interrupt Mask Register if the CHANINT_EN flag is set. This allows | |
3156 | this channel's bit to be set in the AIOP's Interrupt Channel Register. | |
3157 | ||
3158 | Interrupts must also be globally enabled before channel interrupts | |
3159 | will be passed on to the host. This is done with function | |
3160 | sEnGlobalInt(). | |
3161 | ||
3162 | In some cases it may be desirable to disable interrupts globally but | |
3163 | enable channel interrupts. This would allow the global interrupt | |
3164 | status register to be used to determine which AIOPs need service. | |
3165 | */ | |
f15313bf | 3166 | static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags) |
1da177e4 LT |
3167 | { |
3168 | Byte_t Mask; /* Interrupt Mask Register */ | |
3169 | ||
3170 | ChP->RxControl[2] |= | |
3171 | ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); | |
3172 | ||
3173 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); | |
3174 | ||
3175 | ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN); | |
3176 | ||
3177 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); | |
3178 | ||
3179 | if (Flags & CHANINT_EN) { | |
3180 | Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum]; | |
3181 | sOutB(ChP->IntMask, Mask); | |
3182 | } | |
3183 | } | |
3184 | ||
3185 | /*************************************************************************** | |
3186 | Function: sDisInterrupts | |
3187 | Purpose: Disable one or more interrupts for a channel | |
3188 | Call: sDisInterrupts(ChP,Flags) | |
3189 | CHANNEL_T *ChP; Ptr to channel structure | |
3190 | Word_t Flags: Interrupt flags, can be any combination | |
3191 | of the following flags: | |
3192 | TXINT_EN: Interrupt on Tx FIFO empty | |
3193 | RXINT_EN: Interrupt on Rx FIFO at trigger level (see | |
3194 | sSetRxTrigger()) | |
3195 | SRCINT_EN: Interrupt on SRC (Special Rx Condition) | |
3196 | MCINT_EN: Interrupt on modem input change | |
3197 | CHANINT_EN: Disable channel interrupt signal to the | |
3198 | AIOP's Interrupt Channel Register. | |
3199 | Return: void | |
3200 | Comments: If an interrupt flag is set in Flags, that interrupt will be | |
3201 | disabled. If an interrupt flag is not set in Flags, that | |
3202 | interrupt will not be changed. Interrupts can be enabled with | |
3203 | function sEnInterrupts(). | |
3204 | ||
3205 | This function clears the appropriate bit for the channel in the AIOP's | |
3206 | Interrupt Mask Register if the CHANINT_EN flag is set. This blocks | |
3207 | this channel's bit from being set in the AIOP's Interrupt Channel | |
3208 | Register. | |
3209 | */ | |
f15313bf | 3210 | static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags) |
1da177e4 LT |
3211 | { |
3212 | Byte_t Mask; /* Interrupt Mask Register */ | |
3213 | ||
3214 | ChP->RxControl[2] &= | |
3215 | ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); | |
3216 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); | |
3217 | ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN); | |
3218 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); | |
3219 | ||
3220 | if (Flags & CHANINT_EN) { | |
3221 | Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum]; | |
3222 | sOutB(ChP->IntMask, Mask); | |
3223 | } | |
3224 | } | |
3225 | ||
f15313bf | 3226 | static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode) |
1da177e4 LT |
3227 | { |
3228 | sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum); | |
3229 | } | |
3230 | ||
3231 | /* | |
3232 | * Not an official SSCI function, but how to reset RocketModems. | |
3233 | * ISA bus version | |
3234 | */ | |
f15313bf | 3235 | static void sModemReset(CONTROLLER_T * CtlP, int chan, int on) |
1da177e4 LT |
3236 | { |
3237 | ByteIO_t addr; | |
3238 | Byte_t val; | |
3239 | ||
3240 | addr = CtlP->AiopIO[0] + 0x400; | |
3241 | val = sInB(CtlP->MReg3IO); | |
3242 | /* if AIOP[1] is not enabled, enable it */ | |
3243 | if ((val & 2) == 0) { | |
3244 | val = sInB(CtlP->MReg2IO); | |
3245 | sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03)); | |
3246 | sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6)); | |
3247 | } | |
3248 | ||
3249 | sEnAiop(CtlP, 1); | |
3250 | if (!on) | |
3251 | addr += 8; | |
3252 | sOutB(addr + chan, 0); /* apply or remove reset */ | |
3253 | sDisAiop(CtlP, 1); | |
3254 | } | |
3255 | ||
3256 | /* | |
3257 | * Not an official SSCI function, but how to reset RocketModems. | |
3258 | * PCI bus version | |
3259 | */ | |
f15313bf | 3260 | static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on) |
1da177e4 LT |
3261 | { |
3262 | ByteIO_t addr; | |
3263 | ||
3264 | addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */ | |
3265 | if (!on) | |
3266 | addr += 8; | |
3267 | sOutB(addr + chan, 0); /* apply or remove reset */ | |
3268 | } | |
3269 | ||
3270 | /* Resets the speaker controller on RocketModem II and III devices */ | |
3271 | static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model) | |
3272 | { | |
3273 | ByteIO_t addr; | |
3274 | ||
3275 | /* RocketModem II speaker control is at the 8th port location of offset 0x40 */ | |
3276 | if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) { | |
3277 | addr = CtlP->AiopIO[0] + 0x4F; | |
3278 | sOutB(addr, 0); | |
3279 | } | |
3280 | ||
3281 | /* RocketModem III speaker control is at the 1st port location of offset 0x80 */ | |
3282 | if ((model == MODEL_UPCI_RM3_8PORT) | |
3283 | || (model == MODEL_UPCI_RM3_4PORT)) { | |
3284 | addr = CtlP->AiopIO[0] + 0x88; | |
3285 | sOutB(addr, 0); | |
3286 | } | |
3287 | } | |
3288 | ||
3289 | /* Returns the line number given the controller (board), aiop and channel number */ | |
3290 | static unsigned char GetLineNumber(int ctrl, int aiop, int ch) | |
3291 | { | |
3292 | return lineNumbers[(ctrl << 5) | (aiop << 3) | ch]; | |
3293 | } | |
3294 | ||
3295 | /* | |
3296 | * Stores the line number associated with a given controller (board), aiop | |
3297 | * and channel number. | |
3298 | * Returns: The line number assigned | |
3299 | */ | |
3300 | static unsigned char SetLineNumber(int ctrl, int aiop, int ch) | |
3301 | { | |
3302 | lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++; | |
3303 | return (nextLineNumber - 1); | |
3304 | } |