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rocket: Prepare for BKL pushdown
[deliverable/linux.git] / drivers / char / rocket.c
CommitLineData
1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
1da177e4
LT		 43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
58#define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
59
60/****** Kernel includes ******/
61
1da177e4
LT		 62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
75#include <linux/string.h>
76#include <linux/fcntl.h>
77#include <linux/ptrace.h>
69f545ea 78#include <linux/mutex.h>
1da177e4
LT		 79#include <linux/ioport.h>
80#include <linux/delay.h>
8cf5a8c5 81#include <linux/completion.h>
1da177e4
LT		 82#include <linux/wait.h>
83#include <linux/pci.h>
84#include <asm/uaccess.h>
85#include <asm/atomic.h>
457fb605 86#include <asm/unaligned.h>
1da177e4
LT		 87#include <linux/bitops.h>
88#include <linux/spinlock.h>
1da177e4
LT		 89#include <linux/init.h>
90
91/****** RocketPort includes ******/
92
93#include "rocket_int.h"
94#include "rocket.h"
95
96#define ROCKET_VERSION "2.09"
97#define ROCKET_DATE "12-June-2003"
98
99/****** RocketPort Local Variables ******/
100
40565f19
JS		 101static void rp_do_poll(unsigned long dummy);
102
1da177e4
LT		 103static struct tty_driver *rocket_driver;
104
105static struct rocket_version driver_version = {
106 ROCKET_VERSION, ROCKET_DATE
107};
108
109static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
110static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
111 /* eg. Bit 0 indicates port 0 has xmit data, ... */
112static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 113static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 114
115static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
116static unsigned long board2;
117static unsigned long board3;
118static unsigned long board4;
119static unsigned long controller;
120static int support_low_speed;
121static unsigned long modem1;
122static unsigned long modem2;
123static unsigned long modem3;
124static unsigned long modem4;
125static unsigned long pc104_1[8];
126static unsigned long pc104_2[8];
127static unsigned long pc104_3[8];
128static unsigned long pc104_4[8];
129static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
130
131static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
132static unsigned long rcktpt_io_addr[NUM_BOARDS];
133static int rcktpt_type[NUM_BOARDS];
134static int is_PCI[NUM_BOARDS];
135static rocketModel_t rocketModel[NUM_BOARDS];
136static int max_board;
137
138/*
139 * The following arrays define the interrupt bits corresponding to each AIOP.
140 * These bits are different between the ISA and regular PCI boards and the
141 * Universal PCI boards.
142 */
143
144static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
145 AIOP_INTR_BIT_0,
146 AIOP_INTR_BIT_1,
147 AIOP_INTR_BIT_2,
148 AIOP_INTR_BIT_3
149};
150
151static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
152 UPCI_AIOP_INTR_BIT_0,
153 UPCI_AIOP_INTR_BIT_1,
154 UPCI_AIOP_INTR_BIT_2,
155 UPCI_AIOP_INTR_BIT_3
156};
157
f15313bf
AB		 158static Byte_t RData[RDATASIZE] = {
159 0x00, 0x09, 0xf6, 0x82,
160 0x02, 0x09, 0x86, 0xfb,
161 0x04, 0x09, 0x00, 0x0a,
162 0x06, 0x09, 0x01, 0x0a,
163 0x08, 0x09, 0x8a, 0x13,
164 0x0a, 0x09, 0xc5, 0x11,
165 0x0c, 0x09, 0x86, 0x85,
166 0x0e, 0x09, 0x20, 0x0a,
167 0x10, 0x09, 0x21, 0x0a,
168 0x12, 0x09, 0x41, 0xff,
169 0x14, 0x09, 0x82, 0x00,
170 0x16, 0x09, 0x82, 0x7b,
171 0x18, 0x09, 0x8a, 0x7d,
172 0x1a, 0x09, 0x88, 0x81,
173 0x1c, 0x09, 0x86, 0x7a,
174 0x1e, 0x09, 0x84, 0x81,
175 0x20, 0x09, 0x82, 0x7c,
176 0x22, 0x09, 0x0a, 0x0a
177};
178
179static Byte_t RRegData[RREGDATASIZE] = {
180 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
181 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
182 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
183 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
184 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
185 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
186 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
187 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
188 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
189 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
190 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
191 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
192 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
193};
194
195static CONTROLLER_T sController[CTL_SIZE] = {
196 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
197 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
204};
205
206static Byte_t sBitMapClrTbl[8] = {
207 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
208};
209
210static Byte_t sBitMapSetTbl[8] = {
211 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
212};
213
214static int sClockPrescale = 0x14;
215
1da177e4
LT		 216/*
217 * Line number is the ttySIx number (x), the Minor number. We
218 * assign them sequentially, starting at zero. The following
219 * array keeps track of the line number assigned to a given board/aiop/channel.
220 */
221static unsigned char lineNumbers[MAX_RP_PORTS];
222static unsigned long nextLineNumber;
223
224/***** RocketPort Static Prototypes *********/
225static int __init init_ISA(int i);
226static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
227static void rp_flush_buffer(struct tty_struct *tty);
228static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
229static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
230static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
231static void rp_start(struct tty_struct *tty);
f15313bf
AB		 232static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
233 int ChanNum);
234static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
235static void sFlushRxFIFO(CHANNEL_T * ChP);
236static void sFlushTxFIFO(CHANNEL_T * ChP);
237static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
238static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
239static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
240static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
241static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
242static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
243 ByteIO_t * AiopIOList, int AiopIOListSize,
244 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
245 int PeriodicOnly, int altChanRingIndicator,
246 int UPCIRingInd);
247static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
248 ByteIO_t * AiopIOList, int AiopIOListSize,
249 int IRQNum, Byte_t Frequency, int PeriodicOnly);
250static int sReadAiopID(ByteIO_t io);
251static int sReadAiopNumChan(WordIO_t io);
1da177e4 252
1da177e4
LT		 253MODULE_AUTHOR("Theodore Ts'o");
254MODULE_DESCRIPTION("Comtrol RocketPort driver");
255module_param(board1, ulong, 0);
256MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
257module_param(board2, ulong, 0);
258MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
259module_param(board3, ulong, 0);
260MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
261module_param(board4, ulong, 0);
262MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
263module_param(controller, ulong, 0);
264MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
265module_param(support_low_speed, bool, 0);
266MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
267module_param(modem1, ulong, 0);
268MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
269module_param(modem2, ulong, 0);
270MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
271module_param(modem3, ulong, 0);
272MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
273module_param(modem4, ulong, 0);
274MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
275module_param_array(pc104_1, ulong, NULL, 0);
276MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
277module_param_array(pc104_2, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
279module_param_array(pc104_3, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
281module_param_array(pc104_4, ulong, NULL, 0);
282MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
283
d269cdd0 284static int rp_init(void);
1da177e4
LT		 285static void rp_cleanup_module(void);
286
287module_init(rp_init);
288module_exit(rp_cleanup_module);
289
1da177e4 290
1da177e4 291MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 292
293/*************************************************************************/
294/* Module code starts here */
295
296static inline int rocket_paranoia_check(struct r_port *info,
297 const char *routine)
298{
299#ifdef ROCKET_PARANOIA_CHECK
300 if (!info)
301 return 1;
302 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 303 printk(KERN_WARNING "Warning: bad magic number for rocketport "
304 "struct in %s\n", routine);
1da177e4
LT		 305 return 1;
306 }
307#endif
308 return 0;
309}
310
311
312/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
313 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
314 * tty layer.
315 */
316static void rp_do_receive(struct r_port *info,
317 struct tty_struct *tty,
318 CHANNEL_t * cp, unsigned int ChanStatus)
319{
320 unsigned int CharNStat;
cc44a817
PF		 321 int ToRecv, wRecv, space;
322 unsigned char *cbuf;
1da177e4
LT		 323
324 ToRecv = sGetRxCnt(cp);
1da177e4 325#ifdef ROCKET_DEBUG_INTR
68562b79 326 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 327#endif
cc44a817
PF		 328 if (ToRecv == 0)
329 return;
33f0f88f 330
1da177e4
LT		 331 /*
332 * if status indicates there are errored characters in the
333 * FIFO, then enter status mode (a word in FIFO holds
334 * character and status).
335 */
336 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
337 if (!(ChanStatus & STATMODE)) {
338#ifdef ROCKET_DEBUG_RECEIVE
68562b79 339 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 340#endif
341 ChanStatus |= STATMODE;
342 sEnRxStatusMode(cp);
343 }
344 }
345
346 /*
347 * if we previously entered status mode, then read down the
348 * FIFO one word at a time, pulling apart the character and
349 * the status. Update error counters depending on status
350 */
351 if (ChanStatus & STATMODE) {
352#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 353 printk(KERN_INFO "Ignore %x, read %x...\n",
354 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 355#endif
356 while (ToRecv) {
cc44a817
PF		 357 char flag;
358
1da177e4
LT		 359 CharNStat = sInW(sGetTxRxDataIO(cp));
360#ifdef ROCKET_DEBUG_RECEIVE
68562b79 361 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 362#endif
363 if (CharNStat & STMBREAKH)
364 CharNStat &= ~(STMFRAMEH | STMPARITYH);
365 if (CharNStat & info->ignore_status_mask) {
366 ToRecv--;
367 continue;
368 }
369 CharNStat &= info->read_status_mask;
370 if (CharNStat & STMBREAKH)
cc44a817 371 flag = TTY_BREAK;
1da177e4 372 else if (CharNStat & STMPARITYH)
cc44a817 373 flag = TTY_PARITY;
1da177e4 374 else if (CharNStat & STMFRAMEH)
cc44a817 375 flag = TTY_FRAME;
1da177e4 376 else if (CharNStat & STMRCVROVRH)
cc44a817 377 flag = TTY_OVERRUN;
1da177e4 378 else
cc44a817
PF		 379 flag = TTY_NORMAL;
380 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
1da177e4
LT		 381 ToRecv--;
382 }
383
384 /*
385 * after we've emptied the FIFO in status mode, turn
386 * status mode back off
387 */
388 if (sGetRxCnt(cp) == 0) {
389#ifdef ROCKET_DEBUG_RECEIVE
390 printk(KERN_INFO "Status mode off.\n");
391#endif
392 sDisRxStatusMode(cp);
393 }
394 } else {
395 /*
396 * we aren't in status mode, so read down the FIFO two
397 * characters at time by doing repeated word IO
398 * transfer.
399 */
cc44a817
PF		 400 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
401 if (space < ToRecv) {
402#ifdef ROCKET_DEBUG_RECEIVE
403 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
404#endif
405 if (space <= 0)
406 return;
407 ToRecv = space;
408 }
1da177e4
LT		 409 wRecv = ToRecv >> 1;
410 if (wRecv)
411 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
412 if (ToRecv & 1)
413 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 414 }
415 /* Push the data up to the tty layer */
cc44a817 416 tty_flip_buffer_push(tty);
1da177e4
LT		 417}
418
419/*
420 * Serial port transmit data function. Called from the timer polling loop as a
421 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
422 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
423 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
424 */
425static void rp_do_transmit(struct r_port *info)
426{
427 int c;
428 CHANNEL_t *cp = &info->channel;
429 struct tty_struct *tty;
430 unsigned long flags;
431
432#ifdef ROCKET_DEBUG_INTR
68562b79 433 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 434#endif
435 if (!info)
436 return;
437 if (!info->tty) {
68562b79
JS		 438 printk(KERN_WARNING "rp: WARNING %s called with "
439 "info->tty==NULL\n", __func__);
1da177e4
LT		 440 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
441 return;
442 }
443
444 spin_lock_irqsave(&info->slock, flags);
445 tty = info->tty;
446 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
447
448 /* Loop sending data to FIFO until done or FIFO full */
449 while (1) {
450 if (tty->stopped || tty->hw_stopped)
451 break;
452 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
453 if (c <= 0 || info->xmit_fifo_room <= 0)
454 break;
455 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
456 if (c & 1)
457 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
458 info->xmit_tail += c;
459 info->xmit_tail &= XMIT_BUF_SIZE - 1;
460 info->xmit_cnt -= c;
461 info->xmit_fifo_room -= c;
462#ifdef ROCKET_DEBUG_INTR
68562b79 463 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 464#endif
465 }
466
467 if (info->xmit_cnt == 0)
468 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
469
470 if (info->xmit_cnt < WAKEUP_CHARS) {
471 tty_wakeup(tty);
1da177e4
LT		 472#ifdef ROCKETPORT_HAVE_POLL_WAIT
473 wake_up_interruptible(&tty->poll_wait);
474#endif
475 }
476
477 spin_unlock_irqrestore(&info->slock, flags);
478
479#ifdef ROCKET_DEBUG_INTR
68562b79 480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 481 info->xmit_tail, info->xmit_fifo_room);
482#endif
483}
484
485/*
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
489 */
490static void rp_handle_port(struct r_port *info)
491{
492 CHANNEL_t *cp;
493 struct tty_struct *tty;
494 unsigned int IntMask, ChanStatus;
495
496 if (!info)
497 return;
498
499 if ((info->flags & ROCKET_INITIALIZED) == 0) {
68562b79
JS		 500 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
501 "info->flags & NOT_INIT\n");
1da177e4
LT		 502 return;
503 }
504 if (!info->tty) {
68562b79
JS		 505 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
506 "info->tty==NULL\n");
1da177e4
LT		 507 return;
508 }
509 cp = &info->channel;
510 tty = info->tty;
511
512 IntMask = sGetChanIntID(cp) & info->intmask;
513#ifdef ROCKET_DEBUG_INTR
68562b79 514 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 515#endif
516 ChanStatus = sGetChanStatus(cp);
517 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
518 rp_do_receive(info, tty, cp, ChanStatus);
519 }
520 if (IntMask & DELTA_CD) { /* CD change */
521#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 522 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 523 (ChanStatus & CD_ACT) ? "on" : "off");
524#endif
525 if (!(ChanStatus & CD_ACT) && info->cd_status) {
526#ifdef ROCKET_DEBUG_HANGUP
527 printk(KERN_INFO "CD drop, calling hangup.\n");
528#endif
529 tty_hangup(tty);
530 }
531 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
532 wake_up_interruptible(&info->open_wait);
533 }
534#ifdef ROCKET_DEBUG_INTR
535 if (IntMask & DELTA_CTS) { /* CTS change */
536 printk(KERN_INFO "CTS change...\n");
537 }
538 if (IntMask & DELTA_DSR) { /* DSR change */
539 printk(KERN_INFO "DSR change...\n");
540 }
541#endif
542}
543
544/*
545 * The top level polling routine. Repeats every 1/100 HZ (10ms).
546 */
547static void rp_do_poll(unsigned long dummy)
548{
549 CONTROLLER_t *ctlp;
6c0286b1
JS		 550 int ctrl, aiop, ch, line;
551 unsigned int xmitmask, i;
1da177e4
LT		 552 unsigned int CtlMask;
553 unsigned char AiopMask;
554 Word_t bit;
555
556 /* Walk through all the boards (ctrl's) */
557 for (ctrl = 0; ctrl < max_board; ctrl++) {
558 if (rcktpt_io_addr[ctrl] <= 0)
559 continue;
560
561 /* Get a ptr to the board's control struct */
562 ctlp = sCtlNumToCtlPtr(ctrl);
563
3a4fa0a2 564 /* Get the interrupt status from the board */
1da177e4
LT		 565#ifdef CONFIG_PCI
566 if (ctlp->BusType == isPCI)
567 CtlMask = sPCIGetControllerIntStatus(ctlp);
568 else
569#endif
570 CtlMask = sGetControllerIntStatus(ctlp);
571
572 /* Check if any AIOP read bits are set */
573 for (aiop = 0; CtlMask; aiop++) {
574 bit = ctlp->AiopIntrBits[aiop];
575 if (CtlMask & bit) {
576 CtlMask &= ~bit;
577 AiopMask = sGetAiopIntStatus(ctlp, aiop);
578
579 /* Check if any port read bits are set */
580 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
581 if (AiopMask & 1) {
582
583 /* Get the line number (/dev/ttyRx number). */
584 /* Read the data from the port. */
585 line = GetLineNumber(ctrl, aiop, ch);
586 rp_handle_port(rp_table[line]);
587 }
588 }
589 }
590 }
591
592 xmitmask = xmit_flags[ctrl];
593
594 /*
595 * xmit_flags contains bit-significant flags, indicating there is data
596 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
597 * 1, ... (32 total possible). The variable i has the aiop and ch
598 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
599 */
600 if (xmitmask) {
601 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
602 if (xmitmask & (1 << i)) {
603 aiop = (i & 0x18) >> 3;
604 ch = i & 0x07;
605 line = GetLineNumber(ctrl, aiop, ch);
606 rp_do_transmit(rp_table[line]);
607 }
608 }
609 }
610 }
611
612 /*
613 * Reset the timer so we get called at the next clock tick (10ms).
614 */
615 if (atomic_read(&rp_num_ports_open))
616 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
617}
618
619/*
620 * Initializes the r_port structure for a port, as well as enabling the port on
621 * the board.
622 * Inputs: board, aiop, chan numbers
623 */
624static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
625{
626 unsigned rocketMode;
627 struct r_port *info;
628 int line;
629 CONTROLLER_T *ctlp;
630
631 /* Get the next available line number */
632 line = SetLineNumber(board, aiop, chan);
633
634 ctlp = sCtlNumToCtlPtr(board);
635
636 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 637 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 638 if (!info) {
68562b79
JS		 639 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
640 line);
1da177e4
LT		 641 return;
642 }
1da177e4
LT		 643
644 info->magic = RPORT_MAGIC;
645 info->line = line;
646 info->ctlp = ctlp;
647 info->board = board;
648 info->aiop = aiop;
649 info->chan = chan;
650 info->closing_wait = 3000;
651 info->close_delay = 50;
652 init_waitqueue_head(&info->open_wait);
8cf5a8c5 653 init_completion(&info->close_wait);
1da177e4
LT		 654 info->flags &= ~ROCKET_MODE_MASK;
655 switch (pc104[board][line]) {
656 case 422:
657 info->flags |= ROCKET_MODE_RS422;
658 break;
659 case 485:
660 info->flags |= ROCKET_MODE_RS485;
661 break;
662 case 232:
663 default:
664 info->flags |= ROCKET_MODE_RS232;
665 break;
666 }
667
668 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
669 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 670 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
671 board, aiop, chan);
1da177e4
LT		 672 kfree(info);
673 return;
674 }
675
676 rocketMode = info->flags & ROCKET_MODE_MASK;
677
678 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
679 sEnRTSToggle(&info->channel);
680 else
681 sDisRTSToggle(&info->channel);
682
683 if (ctlp->boardType == ROCKET_TYPE_PC104) {
684 switch (rocketMode) {
685 case ROCKET_MODE_RS485:
686 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
687 break;
688 case ROCKET_MODE_RS422:
689 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
690 break;
691 case ROCKET_MODE_RS232:
692 default:
693 if (info->flags & ROCKET_RTS_TOGGLE)
694 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
695 else
696 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
697 break;
698 }
699 }
700 spin_lock_init(&info->slock);
69f545ea 701 mutex_init(&info->write_mtx);
1da177e4 702 rp_table[line] = info;
ac6aec2f
JS		 703 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
704 NULL);
1da177e4
LT		 705}
706
707/*
708 * Configures a rocketport port according to its termio settings. Called from
709 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
710 */
711static void configure_r_port(struct r_port *info,
606d099c 712 struct ktermios *old_termios)
1da177e4
LT		 713{
714 unsigned cflag;
715 unsigned long flags;
716 unsigned rocketMode;
717 int bits, baud, divisor;
718 CHANNEL_t *cp;
6df3526b 719 struct ktermios *t = info->tty->termios;
1da177e4 720
1da177e4 721 cp = &info->channel;
6df3526b 722 cflag = t->c_cflag;
1da177e4
LT		 723
724 /* Byte size and parity */
725 if ((cflag & CSIZE) == CS8) {
726 sSetData8(cp);
727 bits = 10;
728 } else {
729 sSetData7(cp);
730 bits = 9;
731 }
732 if (cflag & CSTOPB) {
733 sSetStop2(cp);
734 bits++;
735 } else {
736 sSetStop1(cp);
737 }
738
739 if (cflag & PARENB) {
740 sEnParity(cp);
741 bits++;
742 if (cflag & PARODD) {
743 sSetOddParity(cp);
744 } else {
745 sSetEvenParity(cp);
746 }
747 } else {
748 sDisParity(cp);
749 }
750
751 /* baud rate */
752 baud = tty_get_baud_rate(info->tty);
753 if (!baud)
754 baud = 9600;
755 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
756 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 757 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 758 if (!baud)
759 baud = 9600;
760 divisor = (rp_baud_base[info->board] / baud) - 1;
761 }
762 if (divisor >= 8192 || divisor < 0) {
763 baud = 9600;
764 divisor = (rp_baud_base[info->board] / baud) - 1;
765 }
766 info->cps = baud / bits;
767 sSetBaud(cp, divisor);
768
6df3526b
AC		 769 /* FIXME: Should really back compute a baud rate from the divisor */
770 tty_encode_baud_rate(info->tty, baud, baud);
771
1da177e4
LT		 772 if (cflag & CRTSCTS) {
773 info->intmask |= DELTA_CTS;
774 sEnCTSFlowCtl(cp);
775 } else {
776 info->intmask &= ~DELTA_CTS;
777 sDisCTSFlowCtl(cp);
778 }
779 if (cflag & CLOCAL) {
780 info->intmask &= ~DELTA_CD;
781 } else {
782 spin_lock_irqsave(&info->slock, flags);
783 if (sGetChanStatus(cp) & CD_ACT)
784 info->cd_status = 1;
785 else
786 info->cd_status = 0;
787 info->intmask |= DELTA_CD;
788 spin_unlock_irqrestore(&info->slock, flags);
789 }
790
791 /*
792 * Handle software flow control in the board
793 */
794#ifdef ROCKET_SOFT_FLOW
795 if (I_IXON(info->tty)) {
796 sEnTxSoftFlowCtl(cp);
797 if (I_IXANY(info->tty)) {
798 sEnIXANY(cp);
799 } else {
800 sDisIXANY(cp);
801 }
802 sSetTxXONChar(cp, START_CHAR(info->tty));
803 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
804 } else {
805 sDisTxSoftFlowCtl(cp);
806 sDisIXANY(cp);
807 sClrTxXOFF(cp);
808 }
809#endif
810
811 /*
812 * Set up ignore/read mask words
813 */
814 info->read_status_mask = STMRCVROVRH | 0xFF;
815 if (I_INPCK(info->tty))
816 info->read_status_mask |= STMFRAMEH | STMPARITYH;
817 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
818 info->read_status_mask |= STMBREAKH;
819
820 /*
821 * Characters to ignore
822 */
823 info->ignore_status_mask = 0;
824 if (I_IGNPAR(info->tty))
825 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
826 if (I_IGNBRK(info->tty)) {
827 info->ignore_status_mask |= STMBREAKH;
828 /*
829 * If we're ignoring parity and break indicators,
830 * ignore overruns too. (For real raw support).
831 */
832 if (I_IGNPAR(info->tty))
833 info->ignore_status_mask |= STMRCVROVRH;
834 }
835
836 rocketMode = info->flags & ROCKET_MODE_MASK;
837
838 if ((info->flags & ROCKET_RTS_TOGGLE)
839 || (rocketMode == ROCKET_MODE_RS485))
840 sEnRTSToggle(cp);
841 else
842 sDisRTSToggle(cp);
843
844 sSetRTS(&info->channel);
845
846 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
847 switch (rocketMode) {
848 case ROCKET_MODE_RS485:
849 sSetInterfaceMode(cp, InterfaceModeRS485);
850 break;
851 case ROCKET_MODE_RS422:
852 sSetInterfaceMode(cp, InterfaceModeRS422);
853 break;
854 case ROCKET_MODE_RS232:
855 default:
856 if (info->flags & ROCKET_RTS_TOGGLE)
857 sSetInterfaceMode(cp, InterfaceModeRS232T);
858 else
859 sSetInterfaceMode(cp, InterfaceModeRS232);
860 break;
861 }
862 }
863}
864
865/* info->count is considered critical, protected by spinlocks. */
866static int block_til_ready(struct tty_struct *tty, struct file *filp,
867 struct r_port *info)
868{
869 DECLARE_WAITQUEUE(wait, current);
870 int retval;
871 int do_clocal = 0, extra_count = 0;
872 unsigned long flags;
873
874 /*
875 * If the device is in the middle of being closed, then block
876 * until it's done, and then try again.
877 */
878 if (tty_hung_up_p(filp))
879 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
880 if (info->flags & ROCKET_CLOSING) {
8cf5a8c5
JS		 881 if (wait_for_completion_interruptible(&info->close_wait))
882 return -ERESTARTSYS;
1da177e4
LT		 883 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
884 }
885
886 /*
887 * If non-blocking mode is set, or the port is not enabled,
888 * then make the check up front and then exit.
889 */
890 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
891 info->flags |= ROCKET_NORMAL_ACTIVE;
892 return 0;
893 }
894 if (tty->termios->c_cflag & CLOCAL)
895 do_clocal = 1;
896
897 /*
898 * Block waiting for the carrier detect and the line to become free. While we are in
899 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
900 * We restore it upon exit, either normal or abnormal.
901 */
902 retval = 0;
903 add_wait_queue(&info->open_wait, &wait);
904#ifdef ROCKET_DEBUG_OPEN
905 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
906#endif
907 spin_lock_irqsave(&info->slock, flags);
908
909#ifdef ROCKET_DISABLE_SIMUSAGE
910 info->flags |= ROCKET_NORMAL_ACTIVE;
911#else
912 if (!tty_hung_up_p(filp)) {
913 extra_count = 1;
914 info->count--;
915 }
916#endif
917 info->blocked_open++;
918
919 spin_unlock_irqrestore(&info->slock, flags);
920
921 while (1) {
922 if (tty->termios->c_cflag & CBAUD) {
923 sSetDTR(&info->channel);
924 sSetRTS(&info->channel);
925 }
926 set_current_state(TASK_INTERRUPTIBLE);
927 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
928 if (info->flags & ROCKET_HUP_NOTIFY)
929 retval = -EAGAIN;
930 else
931 retval = -ERESTARTSYS;
932 break;
933 }
934 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
935 break;
936 if (signal_pending(current)) {
937 retval = -ERESTARTSYS;
938 break;
939 }
940#ifdef ROCKET_DEBUG_OPEN
941 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
942 info->line, info->count, info->flags);
943#endif
944 schedule(); /* Don't hold spinlock here, will hang PC */
945 }
cc0a8fbb 946 __set_current_state(TASK_RUNNING);
1da177e4
LT		 947 remove_wait_queue(&info->open_wait, &wait);
948
949 spin_lock_irqsave(&info->slock, flags);
950
951 if (extra_count)
952 info->count++;
953 info->blocked_open--;
954
955 spin_unlock_irqrestore(&info->slock, flags);
956
957#ifdef ROCKET_DEBUG_OPEN
958 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
959 info->line, info->count);
960#endif
961 if (retval)
962 return retval;
963 info->flags |= ROCKET_NORMAL_ACTIVE;
964 return 0;
965}
966
967/*
968 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
969 * port's r_port struct. Initializes the port hardware.
970 */
971static int rp_open(struct tty_struct *tty, struct file *filp)
972{
973 struct r_port *info;
974 int line = 0, retval;
975 CHANNEL_t *cp;
976 unsigned long page;
977
f6de0c98 978 line = tty->index;
1da177e4
LT		 979 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
980 return -ENXIO;
981
982 page = __get_free_page(GFP_KERNEL);
983 if (!page)
984 return -ENOMEM;
985
986 if (info->flags & ROCKET_CLOSING) {
8cf5a8c5 987 retval = wait_for_completion_interruptible(&info->close_wait);
1da177e4 988 free_page(page);
8cf5a8c5
JS		 989 if (retval)
990 return retval;
1da177e4
LT		 991 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
992 }
993
994 /*
995 * We must not sleep from here until the port is marked fully in use.
996 */
997 if (info->xmit_buf)
998 free_page(page);
999 else
1000 info->xmit_buf = (unsigned char *) page;
1001
1002 tty->driver_data = info;
1003 info->tty = tty;
1004
1005 if (info->count++ == 0) {
1006 atomic_inc(&rp_num_ports_open);
1007
1008#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1009 printk(KERN_INFO "rocket mod++ = %d...\n",
1010 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1011#endif
1012 }
1013#ifdef ROCKET_DEBUG_OPEN
1014 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1015#endif
1016
1017 /*
1018 * Info->count is now 1; so it's safe to sleep now.
1019 */
1da177e4
LT		 1020 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1021 cp = &info->channel;
1022 sSetRxTrigger(cp, TRIG_1);
1023 if (sGetChanStatus(cp) & CD_ACT)
1024 info->cd_status = 1;
1025 else
1026 info->cd_status = 0;
1027 sDisRxStatusMode(cp);
1028 sFlushRxFIFO(cp);
1029 sFlushTxFIFO(cp);
1030
1031 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1032 sSetRxTrigger(cp, TRIG_1);
1033
1034 sGetChanStatus(cp);
1035 sDisRxStatusMode(cp);
1036 sClrTxXOFF(cp);
1037
1038 sDisCTSFlowCtl(cp);
1039 sDisTxSoftFlowCtl(cp);
1040
1041 sEnRxFIFO(cp);
1042 sEnTransmit(cp);
1043
1044 info->flags |= ROCKET_INITIALIZED;
1045
1046 /*
1047 * Set up the tty->alt_speed kludge
1048 */
1049 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1050 info->tty->alt_speed = 57600;
1051 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1052 info->tty->alt_speed = 115200;
1053 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1054 info->tty->alt_speed = 230400;
1055 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1056 info->tty->alt_speed = 460800;
1057
1058 configure_r_port(info, NULL);
1059 if (tty->termios->c_cflag & CBAUD) {
1060 sSetDTR(cp);
1061 sSetRTS(cp);
1062 }
1063 }
1064 /* Starts (or resets) the maint polling loop */
1065 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1066
1067 retval = block_til_ready(tty, filp, info);
1068 if (retval) {
1069#ifdef ROCKET_DEBUG_OPEN
1070 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1071#endif
1072 return retval;
1073 }
1074 return 0;
1075}
1076
1077/*
1078 * Exception handler that closes a serial port. info->count is considered critical.
1079 */
1080static void rp_close(struct tty_struct *tty, struct file *filp)
1081{
1082 struct r_port *info = (struct r_port *) tty->driver_data;
1083 unsigned long flags;
1084 int timeout;
1085 CHANNEL_t *cp;
1086
1087 if (rocket_paranoia_check(info, "rp_close"))
1088 return;
1089
1090#ifdef ROCKET_DEBUG_OPEN
1091 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1092#endif
1093
1094 if (tty_hung_up_p(filp))
1095 return;
1096 spin_lock_irqsave(&info->slock, flags);
1097
1098 if ((tty->count == 1) && (info->count != 1)) {
1099 /*
1100 * Uh, oh. tty->count is 1, which means that the tty
1101 * structure will be freed. Info->count should always
1102 * be one in these conditions. If it's greater than
1103 * one, we've got real problems, since it means the
1104 * serial port won't be shutdown.
1105 */
68562b79
JS		 1106 printk(KERN_WARNING "rp_close: bad serial port count; "
1107 "tty->count is 1, info->count is %d\n", info->count);
1da177e4
LT		 1108 info->count = 1;
1109 }
1110 if (--info->count < 0) {
68562b79
JS		 1111 printk(KERN_WARNING "rp_close: bad serial port count for "
1112 "ttyR%d: %d\n", info->line, info->count);
1da177e4
LT		 1113 info->count = 0;
1114 }
1115 if (info->count) {
1116 spin_unlock_irqrestore(&info->slock, flags);
1117 return;
1118 }
1119 info->flags |= ROCKET_CLOSING;
1120 spin_unlock_irqrestore(&info->slock, flags);
1121
1122 cp = &info->channel;
1123
1124 /*
1125 * Notify the line discpline to only process XON/XOFF characters
1126 */
1127 tty->closing = 1;
1128
1129 /*
1130 * If transmission was throttled by the application request,
1131 * just flush the xmit buffer.
1132 */
1133 if (tty->flow_stopped)
1134 rp_flush_buffer(tty);
1135
1136 /*
1137 * Wait for the transmit buffer to clear
1138 */
1139 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1140 tty_wait_until_sent(tty, info->closing_wait);
1141 /*
1142 * Before we drop DTR, make sure the UART transmitter
1143 * has completely drained; this is especially
1144 * important if there is a transmit FIFO!
1145 */
1146 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1147 if (timeout == 0)
1148 timeout = 1;
1149 rp_wait_until_sent(tty, timeout);
1150 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1151
1152 sDisTransmit(cp);
1153 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1154 sDisCTSFlowCtl(cp);
1155 sDisTxSoftFlowCtl(cp);
1156 sClrTxXOFF(cp);
1157 sFlushRxFIFO(cp);
1158 sFlushTxFIFO(cp);
1159 sClrRTS(cp);
1160 if (C_HUPCL(tty))
1161 sClrDTR(cp);
1162
f6de0c98 1163 rp_flush_buffer(tty);
1da177e4
LT		 1164
1165 tty_ldisc_flush(tty);
1166
1167 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1168
1169 if (info->blocked_open) {
1170 if (info->close_delay) {
1171 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1172 }
1173 wake_up_interruptible(&info->open_wait);
1174 } else {
1175 if (info->xmit_buf) {
1176 free_page((unsigned long) info->xmit_buf);
1177 info->xmit_buf = NULL;
1178 }
1179 }
1180 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1181 tty->closing = 0;
8cf5a8c5 1182 complete_all(&info->close_wait);
1da177e4
LT		 1183 atomic_dec(&rp_num_ports_open);
1184
1185#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1186 printk(KERN_INFO "rocket mod-- = %d...\n",
1187 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1188 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1189#endif
1190
1191}
1192
1193static void rp_set_termios(struct tty_struct *tty,
606d099c 1194 struct ktermios *old_termios)
1da177e4
LT		 1195{
1196 struct r_port *info = (struct r_port *) tty->driver_data;
1197 CHANNEL_t *cp;
1198 unsigned cflag;
1199
1200 if (rocket_paranoia_check(info, "rp_set_termios"))
1201 return;
1202
1203 cflag = tty->termios->c_cflag;
1204
1da177e4
LT		 1205 /*
1206 * This driver doesn't support CS5 or CS6
1207 */
1208 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1209 tty->termios->c_cflag =
1210 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b
AC		 1211 /* Or CMSPAR */
1212 tty->termios->c_cflag &= ~CMSPAR;
1da177e4
LT		 1213
1214 configure_r_port(info, old_termios);
1215
1216 cp = &info->channel;
1217
1218 /* Handle transition to B0 status */
1219 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1220 sClrDTR(cp);
1221 sClrRTS(cp);
1222 }
1223
1224 /* Handle transition away from B0 status */
1225 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1226 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1227 sSetRTS(cp);
1228 sSetDTR(cp);
1229 }
1230
1231 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1232 tty->hw_stopped = 0;
1233 rp_start(tty);
1234 }
1235}
1236
1237static void rp_break(struct tty_struct *tty, int break_state)
1238{
1239 struct r_port *info = (struct r_port *) tty->driver_data;
1240 unsigned long flags;
1241
1242 if (rocket_paranoia_check(info, "rp_break"))
1243 return;
1244
1245 spin_lock_irqsave(&info->slock, flags);
1246 if (break_state == -1)
1247 sSendBreak(&info->channel);
1248 else
1249 sClrBreak(&info->channel);
1250 spin_unlock_irqrestore(&info->slock, flags);
1251}
1252
1253/*
1254 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1255 * the UPCI boards was added, it was decided to make this a function because
1256 * the macro was getting too complicated. All cases except the first one
1257 * (UPCIRingInd) are taken directly from the original macro.
1258 */
1259static int sGetChanRI(CHANNEL_T * ChP)
1260{
1261 CONTROLLER_t *CtlP = ChP->CtlP;
1262 int ChanNum = ChP->ChanNum;
1263 int RingInd = 0;
1264
1265 if (CtlP->UPCIRingInd)
1266 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1267 else if (CtlP->AltChanRingIndicator)
1268 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1269 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1270 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1271
1272 return RingInd;
1273}
1274
1275/********************************************************************************************/
1276/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1277
1278/*
1279 * Returns the state of the serial modem control lines. These next 2 functions
1280 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1281 */
1282static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1283{
1284 struct r_port *info = (struct r_port *)tty->driver_data;
1285 unsigned int control, result, ChanStatus;
1286
1287 ChanStatus = sGetChanStatusLo(&info->channel);
1288 control = info->channel.TxControl[3];
1289 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1290 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1291 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1292 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1293 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1294 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1295
1296 return result;
1297}
1298
1299/*
1300 * Sets the modem control lines
1301 */
1302static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1303 unsigned int set, unsigned int clear)
1304{
1305 struct r_port *info = (struct r_port *)tty->driver_data;
1306
1307 if (set & TIOCM_RTS)
1308 info->channel.TxControl[3] |= SET_RTS;
1309 if (set & TIOCM_DTR)
1310 info->channel.TxControl[3] |= SET_DTR;
1311 if (clear & TIOCM_RTS)
1312 info->channel.TxControl[3] &= ~SET_RTS;
1313 if (clear & TIOCM_DTR)
1314 info->channel.TxControl[3] &= ~SET_DTR;
1315
457fb605 1316 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1317 return 0;
1318}
1319
1320static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1321{
1322 struct rocket_config tmp;
1323
1324 if (!retinfo)
1325 return -EFAULT;
1326 memset(&tmp, 0, sizeof (tmp));
1327 tmp.line = info->line;
1328 tmp.flags = info->flags;
1329 tmp.close_delay = info->close_delay;
1330 tmp.closing_wait = info->closing_wait;
1331 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1332
1333 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1334 return -EFAULT;
1335 return 0;
1336}
1337
1338static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1339{
1340 struct rocket_config new_serial;
1341
1342 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1343 return -EFAULT;
1344
1345 if (!capable(CAP_SYS_ADMIN))
1346 {
1347 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1348 return -EPERM;
1349 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1350 configure_r_port(info, NULL);
1351 return 0;
1352 }
1353
1354 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1355 info->close_delay = new_serial.close_delay;
1356 info->closing_wait = new_serial.closing_wait;
1357
1358 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1359 info->tty->alt_speed = 57600;
1360 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1361 info->tty->alt_speed = 115200;
1362 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1363 info->tty->alt_speed = 230400;
1364 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1365 info->tty->alt_speed = 460800;
1366
1367 configure_r_port(info, NULL);
1368 return 0;
1369}
1370
1371/*
1372 * This function fills in a rocket_ports struct with information
1373 * about what boards/ports are in the system. This info is passed
1374 * to user space. See setrocket.c where the info is used to create
1375 * the /dev/ttyRx ports.
1376 */
1377static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1378{
1379 struct rocket_ports tmp;
1380 int board;
1381
1382 if (!retports)
1383 return -EFAULT;
1384 memset(&tmp, 0, sizeof (tmp));
1385 tmp.tty_major = rocket_driver->major;
1386
1387 for (board = 0; board < 4; board++) {
1388 tmp.rocketModel[board].model = rocketModel[board].model;
1389 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1390 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1391 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1392 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1393 }
1394 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1395 return -EFAULT;
1396 return 0;
1397}
1398
1399static int reset_rm2(struct r_port *info, void __user *arg)
1400{
1401 int reset;
1402
4129a645
AC		 1403 if (!capable(CAP_SYS_ADMIN))
1404 return -EPERM;
1405
1da177e4
LT		 1406 if (copy_from_user(&reset, arg, sizeof (int)))
1407 return -EFAULT;
1408 if (reset)
1409 reset = 1;
1410
1411 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1412 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1413 return -EINVAL;
1414
1415 if (info->ctlp->BusType == isISA)
1416 sModemReset(info->ctlp, info->chan, reset);
1417 else
1418 sPCIModemReset(info->ctlp, info->chan, reset);
1419
1420 return 0;
1421}
1422
1423static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1424{
1425 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1426 return -EFAULT;
1427 return 0;
1428}
1429
1430/* IOCTL call handler into the driver */
1431static int rp_ioctl(struct tty_struct *tty, struct file *file,
1432 unsigned int cmd, unsigned long arg)
1433{
1434 struct r_port *info = (struct r_port *) tty->driver_data;
1435 void __user *argp = (void __user *)arg;
bdf183aa 1436 int ret = 0;
1da177e4
LT		 1437
1438 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1439 return -ENXIO;
1440
bdf183aa
AC		 1441 lock_kernel();
1442
1da177e4
LT		 1443 switch (cmd) {
1444 case RCKP_GET_STRUCT:
1445 if (copy_to_user(argp, info, sizeof (struct r_port)))
bdf183aa
AC		 1446 ret = -EFAULT;
1447 break;
1da177e4 1448 case RCKP_GET_CONFIG:
bdf183aa
AC		 1449 ret = get_config(info, argp);
1450 break;
1da177e4 1451 case RCKP_SET_CONFIG:
bdf183aa
AC		 1452 ret = set_config(info, argp);
1453 break;
1da177e4 1454 case RCKP_GET_PORTS:
bdf183aa
AC		 1455 ret = get_ports(info, argp);
1456 break;
1da177e4 1457 case RCKP_RESET_RM2:
bdf183aa
AC		 1458 ret = reset_rm2(info, argp);
1459 break;
1da177e4 1460 case RCKP_GET_VERSION:
bdf183aa
AC		 1461 ret = get_version(info, argp);
1462 break;
1da177e4 1463 default:
bdf183aa 1464 ret = -ENOIOCTLCMD;
1da177e4 1465 }
bdf183aa
AC		 1466 unlock_kernel();
1467 return ret;
1da177e4
LT		 1468}
1469
1470static void rp_send_xchar(struct tty_struct *tty, char ch)
1471{
1472 struct r_port *info = (struct r_port *) tty->driver_data;
1473 CHANNEL_t *cp;
1474
1475 if (rocket_paranoia_check(info, "rp_send_xchar"))
1476 return;
1477
1478 cp = &info->channel;
1479 if (sGetTxCnt(cp))
1480 sWriteTxPrioByte(cp, ch);
1481 else
1482 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1483}
1484
1485static void rp_throttle(struct tty_struct *tty)
1486{
1487 struct r_port *info = (struct r_port *) tty->driver_data;
1488 CHANNEL_t *cp;
1489
1490#ifdef ROCKET_DEBUG_THROTTLE
1491 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1492 tty->ldisc.chars_in_buffer(tty));
1493#endif
1494
1495 if (rocket_paranoia_check(info, "rp_throttle"))
1496 return;
1497
1498 cp = &info->channel;
1499 if (I_IXOFF(tty))
1500 rp_send_xchar(tty, STOP_CHAR(tty));
1501
1502 sClrRTS(&info->channel);
1503}
1504
1505static void rp_unthrottle(struct tty_struct *tty)
1506{
1507 struct r_port *info = (struct r_port *) tty->driver_data;
1508 CHANNEL_t *cp;
1509#ifdef ROCKET_DEBUG_THROTTLE
1510 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1511 tty->ldisc.chars_in_buffer(tty));
1512#endif
1513
1514 if (rocket_paranoia_check(info, "rp_throttle"))
1515 return;
1516
1517 cp = &info->channel;
1518 if (I_IXOFF(tty))
1519 rp_send_xchar(tty, START_CHAR(tty));
1520
1521 sSetRTS(&info->channel);
1522}
1523
1524/*
1525 * ------------------------------------------------------------
1526 * rp_stop() and rp_start()
1527 *
1528 * This routines are called before setting or resetting tty->stopped.
1529 * They enable or disable transmitter interrupts, as necessary.
1530 * ------------------------------------------------------------
1531 */
1532static void rp_stop(struct tty_struct *tty)
1533{
1534 struct r_port *info = (struct r_port *) tty->driver_data;
1535
1536#ifdef ROCKET_DEBUG_FLOW
1537 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1538 info->xmit_cnt, info->xmit_fifo_room);
1539#endif
1540
1541 if (rocket_paranoia_check(info, "rp_stop"))
1542 return;
1543
1544 if (sGetTxCnt(&info->channel))
1545 sDisTransmit(&info->channel);
1546}
1547
1548static void rp_start(struct tty_struct *tty)
1549{
1550 struct r_port *info = (struct r_port *) tty->driver_data;
1551
1552#ifdef ROCKET_DEBUG_FLOW
1553 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1554 info->xmit_cnt, info->xmit_fifo_room);
1555#endif
1556
1557 if (rocket_paranoia_check(info, "rp_stop"))
1558 return;
1559
1560 sEnTransmit(&info->channel);
1561 set_bit((info->aiop * 8) + info->chan,
1562 (void *) &xmit_flags[info->board]);
1563}
1564
1565/*
1566 * rp_wait_until_sent() --- wait until the transmitter is empty
1567 */
1568static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1569{
1570 struct r_port *info = (struct r_port *) tty->driver_data;
1571 CHANNEL_t *cp;
1572 unsigned long orig_jiffies;
1573 int check_time, exit_time;
1574 int txcnt;
1575
1576 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1577 return;
1578
1579 cp = &info->channel;
1580
1581 orig_jiffies = jiffies;
1582#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79 1583 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1da177e4 1584 jiffies);
68562b79 1585 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4
LT		 1586#endif
1587 while (1) {
1588 txcnt = sGetTxCnt(cp);
1589 if (!txcnt) {
1590 if (sGetChanStatusLo(cp) & TXSHRMT)
1591 break;
1592 check_time = (HZ / info->cps) / 5;
1593 } else {
1594 check_time = HZ * txcnt / info->cps;
1595 }
1596 if (timeout) {
1597 exit_time = orig_jiffies + timeout - jiffies;
1598 if (exit_time <= 0)
1599 break;
1600 if (exit_time < check_time)
1601 check_time = exit_time;
1602 }
1603 if (check_time == 0)
1604 check_time = 1;
1605#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1606 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1607 jiffies, check_time);
1da177e4
LT		 1608#endif
1609 msleep_interruptible(jiffies_to_msecs(check_time));
1610 if (signal_pending(current))
1611 break;
1612 }
cc0a8fbb 1613 __set_current_state(TASK_RUNNING);
1da177e4
LT		 1614#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1615 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1616#endif
1617}
1618
1619/*
1620 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1621 */
1622static void rp_hangup(struct tty_struct *tty)
1623{
1624 CHANNEL_t *cp;
1625 struct r_port *info = (struct r_port *) tty->driver_data;
1626
1627 if (rocket_paranoia_check(info, "rp_hangup"))
1628 return;
1629
1630#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1631 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1632#endif
1633 rp_flush_buffer(tty);
1634 if (info->flags & ROCKET_CLOSING)
1635 return;
1636 if (info->count)
1637 atomic_dec(&rp_num_ports_open);
1638 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1639
1640 info->count = 0;
1641 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1642 info->tty = NULL;
1643
1644 cp = &info->channel;
1645 sDisRxFIFO(cp);
1646 sDisTransmit(cp);
1647 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1648 sDisCTSFlowCtl(cp);
1649 sDisTxSoftFlowCtl(cp);
1650 sClrTxXOFF(cp);
1651 info->flags &= ~ROCKET_INITIALIZED;
1652
1653 wake_up_interruptible(&info->open_wait);
1654}
1655
1656/*
1657 * Exception handler - write char routine. The RocketPort driver uses a
1658 * double-buffering strategy, with the twist that if the in-memory CPU
1659 * buffer is empty, and there's space in the transmit FIFO, the
1660 * writing routines will write directly to transmit FIFO.
1661 * Write buffer and counters protected by spinlocks
1662 */
1663static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1664{
1665 struct r_port *info = (struct r_port *) tty->driver_data;
1666 CHANNEL_t *cp;
1667 unsigned long flags;
1668
1669 if (rocket_paranoia_check(info, "rp_put_char"))
1670 return;
1671
69f545ea
MK		 1672 /*
1673 * Grab the port write mutex, locking out other processes that try to
1674 * write to this port
1675 */
1676 mutex_lock(&info->write_mtx);
1da177e4
LT		 1677
1678#ifdef ROCKET_DEBUG_WRITE
68562b79 1679 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1680#endif
1681
1682 spin_lock_irqsave(&info->slock, flags);
1683 cp = &info->channel;
1684
1685 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1686 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1687
1688 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1689 info->xmit_buf[info->xmit_head++] = ch;
1690 info->xmit_head &= XMIT_BUF_SIZE - 1;
1691 info->xmit_cnt++;
1692 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1693 } else {
1694 sOutB(sGetTxRxDataIO(cp), ch);
1695 info->xmit_fifo_room--;
1696 }
1697 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1698 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1699}
1700
1701/*
1702 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1703 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1704 * this port at the same time. This other process could be running on the other CPU
1705 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1706 * Spinlocks protect the info xmit members.
1707 */
1708static int rp_write(struct tty_struct *tty,
1709 const unsigned char *buf, int count)
1710{
1711 struct r_port *info = (struct r_port *) tty->driver_data;
1712 CHANNEL_t *cp;
1713 const unsigned char *b;
1714 int c, retval = 0;
1715 unsigned long flags;
1716
1717 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1718 return 0;
1719
1e3e8d91
SS		 1720 if (mutex_lock_interruptible(&info->write_mtx))
1721 return -ERESTARTSYS;
1da177e4
LT		 1722
1723#ifdef ROCKET_DEBUG_WRITE
68562b79 1724 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1725#endif
1726 cp = &info->channel;
1727
1728 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1729 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1730
1731 /*
1732 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1733 * into FIFO. Use the write queue for temp storage.
1734 */
1735 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1736 c = min(count, info->xmit_fifo_room);
1737 b = buf;
1738
1739 /* Push data into FIFO, 2 bytes at a time */
1740 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1741
1742 /* If there is a byte remaining, write it */
1743 if (c & 1)
1744 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1745
1746 retval += c;
1747 buf += c;
1748 count -= c;
1749
1750 spin_lock_irqsave(&info->slock, flags);
1751 info->xmit_fifo_room -= c;
1752 spin_unlock_irqrestore(&info->slock, flags);
1753 }
1754
1755 /* If count is zero, we wrote it all and are done */
1756 if (!count)
1757 goto end;
1758
1759 /* Write remaining data into the port's xmit_buf */
1760 while (1) {
457fb605 1761 if (!info->tty) /* Seemingly obligatory check... */
1da177e4
LT		 1762 goto end;
1763
1764 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1765 if (c <= 0)
1766 break;
1767
1768 b = buf;
1769 memcpy(info->xmit_buf + info->xmit_head, b, c);
1770
1771 spin_lock_irqsave(&info->slock, flags);
1772 info->xmit_head =
1773 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1774 info->xmit_cnt += c;
1775 spin_unlock_irqrestore(&info->slock, flags);
1776
1777 buf += c;
1778 count -= c;
1779 retval += c;
1780 }
1781
1782 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1783 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1784
1785end:
1786 if (info->xmit_cnt < WAKEUP_CHARS) {
1787 tty_wakeup(tty);
1da177e4
LT		 1788#ifdef ROCKETPORT_HAVE_POLL_WAIT
1789 wake_up_interruptible(&tty->poll_wait);
1790#endif
1791 }
69f545ea 1792 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1793 return retval;
1794}
1795
1796/*
1797 * Return the number of characters that can be sent. We estimate
1798 * only using the in-memory transmit buffer only, and ignore the
1799 * potential space in the transmit FIFO.
1800 */
1801static int rp_write_room(struct tty_struct *tty)
1802{
1803 struct r_port *info = (struct r_port *) tty->driver_data;
1804 int ret;
1805
1806 if (rocket_paranoia_check(info, "rp_write_room"))
1807 return 0;
1808
1809 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1810 if (ret < 0)
1811 ret = 0;
1812#ifdef ROCKET_DEBUG_WRITE
68562b79 1813 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1814#endif
1815 return ret;
1816}
1817
1818/*
1819 * Return the number of characters in the buffer. Again, this only
1820 * counts those characters in the in-memory transmit buffer.
1821 */
1822static int rp_chars_in_buffer(struct tty_struct *tty)
1823{
1824 struct r_port *info = (struct r_port *) tty->driver_data;
1825 CHANNEL_t *cp;
1826
1827 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1828 return 0;
1829
1830 cp = &info->channel;
1831
1832#ifdef ROCKET_DEBUG_WRITE
68562b79 1833 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1834#endif
1835 return info->xmit_cnt;
1836}
1837
1838/*
1839 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1840 * r_port struct for the port. Note that spinlock are used to protect info members,
1841 * do not call this function if the spinlock is already held.
1842 */
1843static void rp_flush_buffer(struct tty_struct *tty)
1844{
1845 struct r_port *info = (struct r_port *) tty->driver_data;
1846 CHANNEL_t *cp;
1847 unsigned long flags;
1848
1849 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1850 return;
1851
1852 spin_lock_irqsave(&info->slock, flags);
1853 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1854 spin_unlock_irqrestore(&info->slock, flags);
1855
1da177e4
LT		 1856#ifdef ROCKETPORT_HAVE_POLL_WAIT
1857 wake_up_interruptible(&tty->poll_wait);
1858#endif
1859 tty_wakeup(tty);
1860
1861 cp = &info->channel;
1862 sFlushTxFIFO(cp);
1863}
1864
1865#ifdef CONFIG_PCI
1866
8d5916d3
JS		 1867static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1868 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1869 { }
1870};
1871MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1872
1da177e4
LT		 1873/*
1874 * Called when a PCI card is found. Retrieves and stores model information,
1875 * init's aiopic and serial port hardware.
1876 * Inputs: i is the board number (0-n)
1877 */
f15313bf 1878static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1879{
1880 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1881 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1882 char *str, *board_type;
1883 CONTROLLER_t *ctlp;
1884
1885 int fast_clock = 0;
1886 int altChanRingIndicator = 0;
1887 int ports_per_aiop = 8;
1da177e4
LT		 1888 WordIO_t ConfigIO = 0;
1889 ByteIO_t UPCIRingInd = 0;
1890
1891 if (!dev || pci_enable_device(dev))
1892 return 0;
1893
1894 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1895
1896 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1897 rocketModel[i].loadrm2 = 0;
1898 rocketModel[i].startingPortNumber = nextLineNumber;
1899
1900 /* Depending on the model, set up some config variables */
1901 switch (dev->device) {
1902 case PCI_DEVICE_ID_RP4QUAD:
1903 str = "Quadcable";
1904 max_num_aiops = 1;
1905 ports_per_aiop = 4;
1906 rocketModel[i].model = MODEL_RP4QUAD;
1907 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1908 rocketModel[i].numPorts = 4;
1909 break;
1910 case PCI_DEVICE_ID_RP8OCTA:
1911 str = "Octacable";
1912 max_num_aiops = 1;
1913 rocketModel[i].model = MODEL_RP8OCTA;
1914 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1915 rocketModel[i].numPorts = 8;
1916 break;
1917 case PCI_DEVICE_ID_URP8OCTA:
1918 str = "Octacable";
1919 max_num_aiops = 1;
1920 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1921 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1922 rocketModel[i].numPorts = 8;
1923 break;
1924 case PCI_DEVICE_ID_RP8INTF:
1925 str = "8";
1926 max_num_aiops = 1;
1927 rocketModel[i].model = MODEL_RP8INTF;
1928 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1929 rocketModel[i].numPorts = 8;
1930 break;
1931 case PCI_DEVICE_ID_URP8INTF:
1932 str = "8";
1933 max_num_aiops = 1;
1934 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1935 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1936 rocketModel[i].numPorts = 8;
1937 break;
1938 case PCI_DEVICE_ID_RP8J:
1939 str = "8J";
1940 max_num_aiops = 1;
1941 rocketModel[i].model = MODEL_RP8J;
1942 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1943 rocketModel[i].numPorts = 8;
1944 break;
1945 case PCI_DEVICE_ID_RP4J:
1946 str = "4J";
1947 max_num_aiops = 1;
1948 ports_per_aiop = 4;
1949 rocketModel[i].model = MODEL_RP4J;
1950 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1951 rocketModel[i].numPorts = 4;
1952 break;
1953 case PCI_DEVICE_ID_RP8SNI:
1954 str = "8 (DB78 Custom)";
1955 max_num_aiops = 1;
1956 rocketModel[i].model = MODEL_RP8SNI;
1957 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1958 rocketModel[i].numPorts = 8;
1959 break;
1960 case PCI_DEVICE_ID_RP16SNI:
1961 str = "16 (DB78 Custom)";
1962 max_num_aiops = 2;
1963 rocketModel[i].model = MODEL_RP16SNI;
1964 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1965 rocketModel[i].numPorts = 16;
1966 break;
1967 case PCI_DEVICE_ID_RP16INTF:
1968 str = "16";
1969 max_num_aiops = 2;
1970 rocketModel[i].model = MODEL_RP16INTF;
1971 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1972 rocketModel[i].numPorts = 16;
1973 break;
1974 case PCI_DEVICE_ID_URP16INTF:
1975 str = "16";
1976 max_num_aiops = 2;
1977 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1978 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1979 rocketModel[i].numPorts = 16;
1980 break;
1981 case PCI_DEVICE_ID_CRP16INTF:
1982 str = "16";
1983 max_num_aiops = 2;
1984 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1985 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1986 rocketModel[i].numPorts = 16;
1987 break;
1988 case PCI_DEVICE_ID_RP32INTF:
1989 str = "32";
1990 max_num_aiops = 4;
1991 rocketModel[i].model = MODEL_RP32INTF;
1992 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1993 rocketModel[i].numPorts = 32;
1994 break;
1995 case PCI_DEVICE_ID_URP32INTF:
1996 str = "32";
1997 max_num_aiops = 4;
1998 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1999 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2000 rocketModel[i].numPorts = 32;
2001 break;
2002 case PCI_DEVICE_ID_RPP4:
2003 str = "Plus Quadcable";
2004 max_num_aiops = 1;
2005 ports_per_aiop = 4;
2006 altChanRingIndicator++;
2007 fast_clock++;
2008 rocketModel[i].model = MODEL_RPP4;
2009 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2010 rocketModel[i].numPorts = 4;
2011 break;
2012 case PCI_DEVICE_ID_RPP8:
2013 str = "Plus Octacable";
2014 max_num_aiops = 2;
2015 ports_per_aiop = 4;
2016 altChanRingIndicator++;
2017 fast_clock++;
2018 rocketModel[i].model = MODEL_RPP8;
2019 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2020 rocketModel[i].numPorts = 8;
2021 break;
2022 case PCI_DEVICE_ID_RP2_232:
2023 str = "Plus 2 (RS-232)";
2024 max_num_aiops = 1;
2025 ports_per_aiop = 2;
2026 altChanRingIndicator++;
2027 fast_clock++;
2028 rocketModel[i].model = MODEL_RP2_232;
2029 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2030 rocketModel[i].numPorts = 2;
2031 break;
2032 case PCI_DEVICE_ID_RP2_422:
2033 str = "Plus 2 (RS-422)";
2034 max_num_aiops = 1;
2035 ports_per_aiop = 2;
2036 altChanRingIndicator++;
2037 fast_clock++;
2038 rocketModel[i].model = MODEL_RP2_422;
2039 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2040 rocketModel[i].numPorts = 2;
2041 break;
2042 case PCI_DEVICE_ID_RP6M:
2043
2044 max_num_aiops = 1;
2045 ports_per_aiop = 6;
2046 str = "6-port";
2047
57fedc7a
JS		 2048 /* If revision is 1, the rocketmodem flash must be loaded.
2049 * If it is 2 it is a "socketed" version. */
2050 if (dev->revision == 1) {
1da177e4
LT		 2051 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2052 rocketModel[i].loadrm2 = 1;
2053 } else {
2054 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2055 }
2056
2057 rocketModel[i].model = MODEL_RP6M;
2058 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2059 rocketModel[i].numPorts = 6;
2060 break;
2061 case PCI_DEVICE_ID_RP4M:
2062 max_num_aiops = 1;
2063 ports_per_aiop = 4;
2064 str = "4-port";
57fedc7a 2065 if (dev->revision == 1) {
1da177e4
LT		 2066 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2067 rocketModel[i].loadrm2 = 1;
2068 } else {
2069 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2070 }
2071
2072 rocketModel[i].model = MODEL_RP4M;
2073 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2074 rocketModel[i].numPorts = 4;
2075 break;
2076 default:
2077 str = "(unknown/unsupported)";
2078 max_num_aiops = 0;
2079 break;
2080 }
2081
2082 /*
2083 * Check for UPCI boards.
2084 */
2085
2086 switch (dev->device) {
2087 case PCI_DEVICE_ID_URP32INTF:
2088 case PCI_DEVICE_ID_URP8INTF:
2089 case PCI_DEVICE_ID_URP16INTF:
2090 case PCI_DEVICE_ID_CRP16INTF:
2091 case PCI_DEVICE_ID_URP8OCTA:
2092 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2093 ConfigIO = pci_resource_start(dev, 1);
2094 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2095 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2096
2097 /*
2098 * Check for octa or quad cable.
2099 */
2100 if (!
2101 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2102 PCI_GPIO_CTRL_8PORT)) {
2103 str = "Quadcable";
2104 ports_per_aiop = 4;
2105 rocketModel[i].numPorts = 4;
2106 }
2107 }
2108 break;
2109 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2110 str = "8 ports";
2111 max_num_aiops = 1;
2112 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2113 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2114 rocketModel[i].numPorts = 8;
2115 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2116 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2117 ConfigIO = pci_resource_start(dev, 1);
2118 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2119 break;
2120 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2121 str = "4 ports";
2122 max_num_aiops = 1;
2123 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2124 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2125 rocketModel[i].numPorts = 4;
2126 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2127 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2128 ConfigIO = pci_resource_start(dev, 1);
2129 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2130 break;
2131 default:
2132 break;
2133 }
2134
2135 switch (rcktpt_type[i]) {
2136 case ROCKET_TYPE_MODEM:
2137 board_type = "RocketModem";
2138 break;
2139 case ROCKET_TYPE_MODEMII:
2140 board_type = "RocketModem II";
2141 break;
2142 case ROCKET_TYPE_MODEMIII:
2143 board_type = "RocketModem III";
2144 break;
2145 default:
2146 board_type = "RocketPort";
2147 break;
2148 }
2149
2150 if (fast_clock) {
2151 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2152 rp_baud_base[i] = 921600;
2153 } else {
2154 /*
2155 * If support_low_speed is set, use the slow clock
2156 * prescale, which supports 50 bps
2157 */
2158 if (support_low_speed) {
2159 /* mod 9 (divide by 10) prescale */
2160 sClockPrescale = 0x19;
2161 rp_baud_base[i] = 230400;
2162 } else {
2163 /* mod 4 (devide by 5) prescale */
2164 sClockPrescale = 0x14;
2165 rp_baud_base[i] = 460800;
2166 }
2167 }
2168
2169 for (aiop = 0; aiop < max_num_aiops; aiop++)
2170 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2171 ctlp = sCtlNumToCtlPtr(i);
2172 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2173 for (aiop = 0; aiop < max_num_aiops; aiop++)
2174 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2175
68562b79
JS		 2176 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2177 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2178 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2179 rocketModel[i].startingPortNumber,
2180 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2181
2182 if (num_aiops <= 0) {
2183 rcktpt_io_addr[i] = 0;
2184 return (0);
2185 }
2186 is_PCI[i] = 1;
2187
2188 /* Reset the AIOPIC, init the serial ports */
2189 for (aiop = 0; aiop < num_aiops; aiop++) {
2190 sResetAiopByNum(ctlp, aiop);
2191 num_chan = ports_per_aiop;
2192 for (chan = 0; chan < num_chan; chan++)
2193 init_r_port(i, aiop, chan, dev);
2194 }
2195
2196 /* Rocket modems must be reset */
2197 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2198 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2199 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2200 num_chan = ports_per_aiop;
2201 for (chan = 0; chan < num_chan; chan++)
2202 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2203 msleep(500);
1da177e4
LT		 2204 for (chan = 0; chan < num_chan; chan++)
2205 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2206 msleep(500);
1da177e4
LT		 2207 rmSpeakerReset(ctlp, rocketModel[i].model);
2208 }
2209 return (1);
2210}
2211
2212/*
2213 * Probes for PCI cards, inits them if found
2214 * Input: board_found = number of ISA boards already found, or the
2215 * starting board number
2216 * Returns: Number of PCI boards found
2217 */
2218static int __init init_PCI(int boards_found)
2219{
2220 struct pci_dev *dev = NULL;
2221 int count = 0;
2222
2223 /* Work through the PCI device list, pulling out ours */
606d099c 2224 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2225 if (register_PCI(count + boards_found, dev))
2226 count++;
2227 }
2228 return (count);
2229}
2230
2231#endif /* CONFIG_PCI */
2232
2233/*
2234 * Probes for ISA cards
2235 * Input: i = the board number to look for
2236 * Returns: 1 if board found, 0 else
2237 */
2238static int __init init_ISA(int i)
2239{
2240 int num_aiops, num_chan = 0, total_num_chan = 0;
2241 int aiop, chan;
2242 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2243 CONTROLLER_t *ctlp;
2244 char *type_string;
2245
2246 /* If io_addr is zero, no board configured */
2247 if (rcktpt_io_addr[i] == 0)
2248 return (0);
2249
2250 /* Reserve the IO region */
2251 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2252 printk(KERN_ERR "Unable to reserve IO region for configured "
2253 "ISA RocketPort at address 0x%lx, board not "
2254 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2255 rcktpt_io_addr[i] = 0;
2256 return (0);
2257 }
2258
2259 ctlp = sCtlNumToCtlPtr(i);
2260
2261 ctlp->boardType = rcktpt_type[i];
2262
2263 switch (rcktpt_type[i]) {
2264 case ROCKET_TYPE_PC104:
2265 type_string = "(PC104)";
2266 break;
2267 case ROCKET_TYPE_MODEM:
2268 type_string = "(RocketModem)";
2269 break;
2270 case ROCKET_TYPE_MODEMII:
2271 type_string = "(RocketModem II)";
2272 break;
2273 default:
2274 type_string = "";
2275 break;
2276 }
2277
2278 /*
2279 * If support_low_speed is set, use the slow clock prescale,
2280 * which supports 50 bps
2281 */
2282 if (support_low_speed) {
2283 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2284 rp_baud_base[i] = 230400;
2285 } else {
2286 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2287 rp_baud_base[i] = 460800;
2288 }
2289
2290 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2291 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2292
2293 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2294
2295 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2296 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2297 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2298 }
2299
2300 /* If something went wrong initing the AIOP's release the ISA IO memory */
2301 if (num_aiops <= 0) {
2302 release_region(rcktpt_io_addr[i], 64);
2303 rcktpt_io_addr[i] = 0;
2304 return (0);
2305 }
2306
2307 rocketModel[i].startingPortNumber = nextLineNumber;
2308
2309 for (aiop = 0; aiop < num_aiops; aiop++) {
2310 sResetAiopByNum(ctlp, aiop);
2311 sEnAiop(ctlp, aiop);
2312 num_chan = sGetAiopNumChan(ctlp, aiop);
2313 total_num_chan += num_chan;
2314 for (chan = 0; chan < num_chan; chan++)
2315 init_r_port(i, aiop, chan, NULL);
2316 }
2317 is_PCI[i] = 0;
2318 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2319 num_chan = sGetAiopNumChan(ctlp, 0);
2320 total_num_chan = num_chan;
2321 for (chan = 0; chan < num_chan; chan++)
2322 sModemReset(ctlp, chan, 1);
48a67f5d 2323 msleep(500);
1da177e4
LT		 2324 for (chan = 0; chan < num_chan; chan++)
2325 sModemReset(ctlp, chan, 0);
48a67f5d 2326 msleep(500);
1da177e4
LT		 2327 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2328 } else {
2329 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2330 }
2331 rocketModel[i].numPorts = total_num_chan;
2332 rocketModel[i].model = MODEL_ISA;
2333
2334 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2335 i, rcktpt_io_addr[i], num_aiops, type_string);
2336
2337 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2338 rocketModel[i].modelString,
2339 rocketModel[i].startingPortNumber,
2340 rocketModel[i].startingPortNumber +
2341 rocketModel[i].numPorts - 1);
2342
2343 return (1);
2344}
2345
b68e31d0 2346static const struct tty_operations rocket_ops = {
1da177e4
LT		 2347 .open = rp_open,
2348 .close = rp_close,
2349 .write = rp_write,
2350 .put_char = rp_put_char,
2351 .write_room = rp_write_room,
2352 .chars_in_buffer = rp_chars_in_buffer,
2353 .flush_buffer = rp_flush_buffer,
2354 .ioctl = rp_ioctl,
2355 .throttle = rp_throttle,
2356 .unthrottle = rp_unthrottle,
2357 .set_termios = rp_set_termios,
2358 .stop = rp_stop,
2359 .start = rp_start,
2360 .hangup = rp_hangup,
2361 .break_ctl = rp_break,
2362 .send_xchar = rp_send_xchar,
2363 .wait_until_sent = rp_wait_until_sent,
2364 .tiocmget = rp_tiocmget,
2365 .tiocmset = rp_tiocmset,
2366};
2367
2368/*
2369 * The module "startup" routine; it's run when the module is loaded.
2370 */
d269cdd0 2371static int __init rp_init(void)
1da177e4 2372{
4384a3fa 2373 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2374
2375 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2376 ROCKET_VERSION, ROCKET_DATE);
2377
2378 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2379 if (!rocket_driver)
4384a3fa 2380 goto err;
1da177e4 2381
1da177e4
LT		 2382 /*
2383 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2384 * zero, use the default controller IO address of board1 + 0x40.
2385 */
2386 if (board1) {
2387 if (controller == 0)
2388 controller = board1 + 0x40;
2389 } else {
2390 controller = 0; /* Used as a flag, meaning no ISA boards */
2391 }
2392
2393 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2394 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2395 printk(KERN_ERR "Unable to reserve IO region for first "
2396 "configured ISA RocketPort controller 0x%lx. "
2397 "Driver exiting\n", controller);
2398 ret = -EBUSY;
2399 goto err_tty;
1da177e4
LT		 2400 }
2401
2402 /* Store ISA variable retrieved from command line or .conf file. */
2403 rcktpt_io_addr[0] = board1;
2404 rcktpt_io_addr[1] = board2;
2405 rcktpt_io_addr[2] = board3;
2406 rcktpt_io_addr[3] = board4;
2407
2408 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2409 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2410 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2411 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2412 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2413 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2414 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2415 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2416
2417 /*
2418 * Set up the tty driver structure and then register this
2419 * driver with the tty layer.
2420 */
2421
2422 rocket_driver->owner = THIS_MODULE;
331b8319 2423 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2424 rocket_driver->name = "ttyR";
2425 rocket_driver->driver_name = "Comtrol RocketPort";
2426 rocket_driver->major = TTY_ROCKET_MAJOR;
2427 rocket_driver->minor_start = 0;
2428 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2429 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2430 rocket_driver->init_termios = tty_std_termios;
2431 rocket_driver->init_termios.c_cflag =
2432 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2433 rocket_driver->init_termios.c_ispeed = 9600;
2434 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2435#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2436 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2437#endif
2438 tty_set_operations(rocket_driver, &rocket_ops);
2439
4384a3fa
JS		 2440 ret = tty_register_driver(rocket_driver);
2441 if (ret < 0) {
2442 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2443 goto err_tty;
1da177e4
LT		 2444 }
2445
2446#ifdef ROCKET_DEBUG_OPEN
2447 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2448#endif
2449
2450 /*
2451 * OK, let's probe each of the controllers looking for boards. Any boards found
2452 * will be initialized here.
2453 */
2454 isa_boards_found = 0;
2455 pci_boards_found = 0;
2456
2457 for (i = 0; i < NUM_BOARDS; i++) {
2458 if (init_ISA(i))
2459 isa_boards_found++;
2460 }
2461
2462#ifdef CONFIG_PCI
2463 if (isa_boards_found < NUM_BOARDS)
2464 pci_boards_found = init_PCI(isa_boards_found);
2465#endif
2466
2467 max_board = pci_boards_found + isa_boards_found;
2468
2469 if (max_board == 0) {
4384a3fa
JS		 2470 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2471 ret = -ENXIO;
2472 goto err_ttyu;
1da177e4
LT		 2473 }
2474
2475 return 0;
4384a3fa
JS		 2476err_ttyu:
2477 tty_unregister_driver(rocket_driver);
2478err_tty:
2479 put_tty_driver(rocket_driver);
2480err:
2481 return ret;
1da177e4
LT		 2482}
2483
1da177e4
LT		 2484
2485static void rp_cleanup_module(void)
2486{
2487 int retval;
2488 int i;
2489
2490 del_timer_sync(&rocket_timer);
2491
2492 retval = tty_unregister_driver(rocket_driver);
2493 if (retval)
68562b79 2494 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2495 "rocketport driver\n", -retval);
1da177e4 2496
735d5661 2497 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2498 if (rp_table[i]) {
2499 tty_unregister_device(rocket_driver, i);
2500 kfree(rp_table[i]);
2501 }
2502
2503 put_tty_driver(rocket_driver);
1da177e4
LT		 2504
2505 for (i = 0; i < NUM_BOARDS; i++) {
2506 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2507 continue;
2508 release_region(rcktpt_io_addr[i], 64);
2509 }
2510 if (controller)
2511 release_region(controller, 4);
2512}
1da177e4 2513
1da177e4
LT		 2514/***************************************************************************
2515Function: sInitController
2516Purpose: Initialization of controller global registers and controller
2517 structure.
2518Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2519 IRQNum,Frequency,PeriodicOnly)
2520 CONTROLLER_T *CtlP; Ptr to controller structure
2521 int CtlNum; Controller number
2522 ByteIO_t MudbacIO; Mudbac base I/O address.
2523 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2524 This list must be in the order the AIOPs will be found on the
2525 controller. Once an AIOP in the list is not found, it is
2526 assumed that there are no more AIOPs on the controller.
2527 int AiopIOListSize; Number of addresses in AiopIOList
2528 int IRQNum; Interrupt Request number. Can be any of the following:
2529 0: Disable global interrupts
2530 3: IRQ 3
2531 4: IRQ 4
2532 5: IRQ 5
2533 9: IRQ 9
2534 10: IRQ 10
2535 11: IRQ 11
2536 12: IRQ 12
2537 15: IRQ 15
2538 Byte_t Frequency: A flag identifying the frequency
2539 of the periodic interrupt, can be any one of the following:
2540 FREQ_DIS - periodic interrupt disabled
2541 FREQ_137HZ - 137 Hertz
2542 FREQ_69HZ - 69 Hertz
2543 FREQ_34HZ - 34 Hertz
2544 FREQ_17HZ - 17 Hertz
2545 FREQ_9HZ - 9 Hertz
2546 FREQ_4HZ - 4 Hertz
2547 If IRQNum is set to 0 the Frequency parameter is
2548 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2549 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2550 interrupt are to be blocked.
f15313bf 2551 0 is both the periodic interrupt and
1da177e4
LT		 2552 other channel interrupts are allowed.
2553 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2554 overidden, it is forced to a value of 0.
1da177e4
LT		 2555Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2556 initialization failed.
2557
2558Comments:
2559 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2560 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2561
2562 If interrupts are to be completely disabled set IRQNum to 0.
2563
f15313bf 2564 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2565 invalid combination.
2566
2567 This function performs initialization of global interrupt modes,
2568 but it does not actually enable global interrupts. To enable
2569 and disable global interrupts use functions sEnGlobalInt() and
2570 sDisGlobalInt(). Enabling of global interrupts is normally not
2571 done until all other initializations are complete.
2572
2573 Even if interrupts are globally enabled, they must also be
2574 individually enabled for each channel that is to generate
2575 interrupts.
2576
2577Warnings: No range checking on any of the parameters is done.
2578
2579 No context switches are allowed while executing this function.
2580
2581 After this function all AIOPs on the controller are disabled,
2582 they can be enabled with sEnAiop().
2583*/
f15313bf
AB		 2584static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2585 ByteIO_t * AiopIOList, int AiopIOListSize,
2586 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2587{
2588 int i;
2589 ByteIO_t io;
2590 int done;
2591
2592 CtlP->AiopIntrBits = aiop_intr_bits;
2593 CtlP->AltChanRingIndicator = 0;
2594 CtlP->CtlNum = CtlNum;
2595 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2596 CtlP->BusType = isISA;
2597 CtlP->MBaseIO = MudbacIO;
2598 CtlP->MReg1IO = MudbacIO + 1;
2599 CtlP->MReg2IO = MudbacIO + 2;
2600 CtlP->MReg3IO = MudbacIO + 3;
2601#if 1
2602 CtlP->MReg2 = 0; /* interrupt disable */
2603 CtlP->MReg3 = 0; /* no periodic interrupts */
2604#else
2605 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2606 CtlP->MReg2 = 0; /* interrupt disable */
2607 CtlP->MReg3 = 0; /* no periodic interrupts */
2608 } else {
2609 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2610 CtlP->MReg3 = Frequency; /* set frequency */
2611 if (PeriodicOnly) { /* periodic interrupt only */
2612 CtlP->MReg3 |= PERIODIC_ONLY;
2613 }
2614 }
2615#endif
2616 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2617 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2618 sControllerEOI(CtlP); /* clear EOI if warm init */
2619 /* Init AIOPs */
2620 CtlP->NumAiop = 0;
2621 for (i = done = 0; i < AiopIOListSize; i++) {
2622 io = AiopIOList[i];
2623 CtlP->AiopIO[i] = (WordIO_t) io;
2624 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2625 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2626 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2627 if (done)
2628 continue;
2629 sEnAiop(CtlP, i); /* enable the AIOP */
2630 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2631 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2632 done = 1; /* done looking for AIOPs */
2633 else {
2634 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2635 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2636 sOutB(io + _INDX_DATA, sClockPrescale);
2637 CtlP->NumAiop++; /* bump count of AIOPs */
2638 }
2639 sDisAiop(CtlP, i); /* disable AIOP */
2640 }
2641
2642 if (CtlP->NumAiop == 0)
2643 return (-1);
2644 else
2645 return (CtlP->NumAiop);
2646}
2647
2648/***************************************************************************
2649Function: sPCIInitController
2650Purpose: Initialization of controller global registers and controller
2651 structure.
2652Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2653 IRQNum,Frequency,PeriodicOnly)
2654 CONTROLLER_T *CtlP; Ptr to controller structure
2655 int CtlNum; Controller number
2656 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2657 This list must be in the order the AIOPs will be found on the
2658 controller. Once an AIOP in the list is not found, it is
2659 assumed that there are no more AIOPs on the controller.
2660 int AiopIOListSize; Number of addresses in AiopIOList
2661 int IRQNum; Interrupt Request number. Can be any of the following:
2662 0: Disable global interrupts
2663 3: IRQ 3
2664 4: IRQ 4
2665 5: IRQ 5
2666 9: IRQ 9
2667 10: IRQ 10
2668 11: IRQ 11
2669 12: IRQ 12
2670 15: IRQ 15
2671 Byte_t Frequency: A flag identifying the frequency
2672 of the periodic interrupt, can be any one of the following:
2673 FREQ_DIS - periodic interrupt disabled
2674 FREQ_137HZ - 137 Hertz
2675 FREQ_69HZ - 69 Hertz
2676 FREQ_34HZ - 34 Hertz
2677 FREQ_17HZ - 17 Hertz
2678 FREQ_9HZ - 9 Hertz
2679 FREQ_4HZ - 4 Hertz
2680 If IRQNum is set to 0 the Frequency parameter is
2681 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2682 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2683 interrupt are to be blocked.
f15313bf 2684 0 is both the periodic interrupt and
1da177e4
LT		 2685 other channel interrupts are allowed.
2686 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2687 overidden, it is forced to a value of 0.
1da177e4
LT		 2688Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2689 initialization failed.
2690
2691Comments:
2692 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2693 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2694
2695 If interrupts are to be completely disabled set IRQNum to 0.
2696
f15313bf 2697 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2698 invalid combination.
2699
2700 This function performs initialization of global interrupt modes,
2701 but it does not actually enable global interrupts. To enable
2702 and disable global interrupts use functions sEnGlobalInt() and
2703 sDisGlobalInt(). Enabling of global interrupts is normally not
2704 done until all other initializations are complete.
2705
2706 Even if interrupts are globally enabled, they must also be
2707 individually enabled for each channel that is to generate
2708 interrupts.
2709
2710Warnings: No range checking on any of the parameters is done.
2711
2712 No context switches are allowed while executing this function.
2713
2714 After this function all AIOPs on the controller are disabled,
2715 they can be enabled with sEnAiop().
2716*/
f15313bf
AB		 2717static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2718 ByteIO_t * AiopIOList, int AiopIOListSize,
2719 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2720 int PeriodicOnly, int altChanRingIndicator,
2721 int UPCIRingInd)
1da177e4
LT		 2722{
2723 int i;
2724 ByteIO_t io;
2725
2726 CtlP->AltChanRingIndicator = altChanRingIndicator;
2727 CtlP->UPCIRingInd = UPCIRingInd;
2728 CtlP->CtlNum = CtlNum;
2729 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2730 CtlP->BusType = isPCI; /* controller release 1 */
2731
2732 if (ConfigIO) {
2733 CtlP->isUPCI = 1;
2734 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2735 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2736 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2737 } else {
2738 CtlP->isUPCI = 0;
2739 CtlP->PCIIO =
2740 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2741 CtlP->AiopIntrBits = aiop_intr_bits;
2742 }
2743
2744 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2745 /* Init AIOPs */
2746 CtlP->NumAiop = 0;
2747 for (i = 0; i < AiopIOListSize; i++) {
2748 io = AiopIOList[i];
2749 CtlP->AiopIO[i] = (WordIO_t) io;
2750 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2751
2752 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2753 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2754 break; /* done looking for AIOPs */
2755
2756 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2757 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2758 sOutB(io + _INDX_DATA, sClockPrescale);
2759 CtlP->NumAiop++; /* bump count of AIOPs */
2760 }
2761
2762 if (CtlP->NumAiop == 0)
2763 return (-1);
2764 else
2765 return (CtlP->NumAiop);
2766}
2767
2768/***************************************************************************
2769Function: sReadAiopID
2770Purpose: Read the AIOP idenfication number directly from an AIOP.
2771Call: sReadAiopID(io)
2772 ByteIO_t io: AIOP base I/O address
2773Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2774 is replace by an identifying number.
2775 Flag AIOPID_NULL if no valid AIOP is found
2776Warnings: No context switches are allowed while executing this function.
2777
2778*/
f15313bf 2779static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2780{
2781 Byte_t AiopID; /* ID byte from AIOP */
2782
2783 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2784 sOutB(io + _CMD_REG, 0x0);
2785 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2786 if (AiopID == 0x06)
2787 return (1);
2788 else /* AIOP does not exist */
2789 return (-1);
2790}
2791
2792/***************************************************************************
2793Function: sReadAiopNumChan
2794Purpose: Read the number of channels available in an AIOP directly from
2795 an AIOP.
2796Call: sReadAiopNumChan(io)
2797 WordIO_t io: AIOP base I/O address
2798Return: int: The number of channels available
2799Comments: The number of channels is determined by write/reads from identical
2800 offsets within the SRAM address spaces for channels 0 and 4.
2801 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2802 AIOP, otherwise it is an 8 channel.
2803Warnings: No context switches are allowed while executing this function.
2804*/
f15313bf 2805static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2806{
2807 Word_t x;
2808 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2809
2810 /* write to chan 0 SRAM */
457fb605 2811 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2812 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2813 x = sInW(io + _INDX_DATA);
2814 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2815 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2816 return (8);
2817 else
2818 return (4);
2819}
2820
2821/***************************************************************************
2822Function: sInitChan
2823Purpose: Initialization of a channel and channel structure
2824Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2825 CONTROLLER_T *CtlP; Ptr to controller structure
2826 CHANNEL_T *ChP; Ptr to channel structure
2827 int AiopNum; AIOP number within controller
2828 int ChanNum; Channel number within AIOP
f15313bf 2829Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2830 number exceeds number of channels available in AIOP.
2831Comments: This function must be called before a channel can be used.
2832Warnings: No range checking on any of the parameters is done.
2833
2834 No context switches are allowed while executing this function.
2835*/
f15313bf
AB		 2836static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2837 int ChanNum)
1da177e4
LT		 2838{
2839 int i;
2840 WordIO_t AiopIO;
2841 WordIO_t ChIOOff;
2842 Byte_t *ChR;
2843 Word_t ChOff;
2844 static Byte_t R[4];
2845 int brd9600;
2846
2847 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2848 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2849
2850 /* Channel, AIOP, and controller identifiers */
2851 ChP->CtlP = CtlP;
2852 ChP->ChanID = CtlP->AiopID[AiopNum];
2853 ChP->AiopNum = AiopNum;
2854 ChP->ChanNum = ChanNum;
2855
2856 /* Global direct addresses */
2857 AiopIO = CtlP->AiopIO[AiopNum];
2858 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2859 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2860 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2861 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2862 ChP->IndexData = AiopIO + _INDX_DATA;
2863
2864 /* Channel direct addresses */
2865 ChIOOff = AiopIO + ChP->ChanNum * 2;
2866 ChP->TxRxData = ChIOOff + _TD0;
2867 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2868 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2869 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2870
2871 /* Initialize the channel from the RData array */
2872 for (i = 0; i < RDATASIZE; i += 4) {
2873 R[0] = RData[i];
2874 R[1] = RData[i + 1] + 0x10 * ChanNum;
2875 R[2] = RData[i + 2];
2876 R[3] = RData[i + 3];
457fb605 2877 out32(ChP->IndexAddr, R);
1da177e4
LT		 2878 }
2879
2880 ChR = ChP->R;
2881 for (i = 0; i < RREGDATASIZE; i += 4) {
2882 ChR[i] = RRegData[i];
2883 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2884 ChR[i + 2] = RRegData[i + 2];
2885 ChR[i + 3] = RRegData[i + 3];
2886 }
2887
2888 /* Indexed registers */
2889 ChOff = (Word_t) ChanNum *0x1000;
2890
2891 if (sClockPrescale == 0x14)
2892 brd9600 = 47;
2893 else
2894 brd9600 = 23;
2895
2896 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2897 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2898 ChP->BaudDiv[2] = (Byte_t) brd9600;
2899 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2900 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2901
2902 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2903 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2904 ChP->TxControl[2] = 0;
2905 ChP->TxControl[3] = 0;
457fb605 2906 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2907
2908 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2909 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2910 ChP->RxControl[2] = 0;
2911 ChP->RxControl[3] = 0;
457fb605 2912 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2913
2914 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2915 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2916 ChP->TxEnables[2] = 0;
2917 ChP->TxEnables[3] = 0;
457fb605 2918 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2919
2920 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2921 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2922 ChP->TxCompare[2] = 0;
2923 ChP->TxCompare[3] = 0;
457fb605 2924 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2925
2926 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2927 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2928 ChP->TxReplace1[2] = 0;
2929 ChP->TxReplace1[3] = 0;
457fb605 2930 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2931
2932 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2933 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2934 ChP->TxReplace2[2] = 0;
2935 ChP->TxReplace2[3] = 0;
457fb605 2936 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2937
2938 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2939 ChP->TxFIFO = ChOff + _TX_FIFO;
2940
2941 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2942 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2943 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2944 sOutW(ChP->IndexData, 0);
2945 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2946 ChP->RxFIFO = ChOff + _RX_FIFO;
2947
2948 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2949 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2950 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2951 sOutW(ChP->IndexData, 0);
2952 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2953 sOutW(ChP->IndexData, 0);
2954 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2955 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2956 sOutB(ChP->IndexData, 0);
2957 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2958 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2959 sOutB(ChP->IndexData, 0);
2960 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2961 sEnRxProcessor(ChP); /* start the Rx processor */
2962
f15313bf 2963 return 1;
1da177e4
LT		 2964}
2965
2966/***************************************************************************
2967Function: sStopRxProcessor
2968Purpose: Stop the receive processor from processing a channel.
2969Call: sStopRxProcessor(ChP)
2970 CHANNEL_T *ChP; Ptr to channel structure
2971
2972Comments: The receive processor can be started again with sStartRxProcessor().
2973 This function causes the receive processor to skip over the
2974 stopped channel. It does not stop it from processing other channels.
2975
2976Warnings: No context switches are allowed while executing this function.
2977
2978 Do not leave the receive processor stopped for more than one
2979 character time.
2980
2981 After calling this function a delay of 4 uS is required to ensure
2982 that the receive processor is no longer processing this channel.
2983*/
f15313bf 2984static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2985{
2986 Byte_t R[4];
2987
2988 R[0] = ChP->R[0];
2989 R[1] = ChP->R[1];
2990 R[2] = 0x0a;
2991 R[3] = ChP->R[3];
457fb605 2992 out32(ChP->IndexAddr, R);
1da177e4
LT		 2993}
2994
2995/***************************************************************************
2996Function: sFlushRxFIFO
2997Purpose: Flush the Rx FIFO
2998Call: sFlushRxFIFO(ChP)
2999 CHANNEL_T *ChP; Ptr to channel structure
3000Return: void
3001Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3002 while it is being flushed the receive processor is stopped
3003 and the transmitter is disabled. After these operations a
3004 4 uS delay is done before clearing the pointers to allow
3005 the receive processor to stop. These items are handled inside
3006 this function.
3007Warnings: No context switches are allowed while executing this function.
3008*/
f15313bf 3009static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 3010{
3011 int i;
3012 Byte_t Ch; /* channel number within AIOP */
f15313bf 3013 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 3014
3015 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3016 return; /* don't need to flush */
3017
f15313bf 3018 RxFIFOEnabled = 0;
1da177e4 3019 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 3020 RxFIFOEnabled = 1;
1da177e4
LT		 3021 sDisRxFIFO(ChP); /* disable it */
3022 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3023 sInB(ChP->IntChan); /* depends on bus i/o timing */
3024 }
3025 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3026 Ch = (Byte_t) sGetChanNum(ChP);
3027 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3028 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3029 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3030 sOutW(ChP->IndexData, 0);
3031 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3032 sOutW(ChP->IndexData, 0);
3033 if (RxFIFOEnabled)
3034 sEnRxFIFO(ChP); /* enable Rx FIFO */
3035}
3036
3037/***************************************************************************
3038Function: sFlushTxFIFO
3039Purpose: Flush the Tx FIFO
3040Call: sFlushTxFIFO(ChP)
3041 CHANNEL_T *ChP; Ptr to channel structure
3042Return: void
3043Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3044 while it is being flushed the receive processor is stopped
3045 and the transmitter is disabled. After these operations a
3046 4 uS delay is done before clearing the pointers to allow
3047 the receive processor to stop. These items are handled inside
3048 this function.
3049Warnings: No context switches are allowed while executing this function.
3050*/
f15313bf 3051static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 3052{
3053 int i;
3054 Byte_t Ch; /* channel number within AIOP */
f15313bf 3055 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 3056
3057 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3058 return; /* don't need to flush */
3059
f15313bf 3060 TxEnabled = 0;
1da177e4 3061 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 3062 TxEnabled = 1;
1da177e4
LT		 3063 sDisTransmit(ChP); /* disable transmitter */
3064 }
3065 sStopRxProcessor(ChP); /* stop Rx processor */
3066 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3067 sInB(ChP->IntChan); /* depends on bus i/o timing */
3068 Ch = (Byte_t) sGetChanNum(ChP);
3069 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3070 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3071 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3072 sOutW(ChP->IndexData, 0);
3073 if (TxEnabled)
3074 sEnTransmit(ChP); /* enable transmitter */
3075 sStartRxProcessor(ChP); /* restart Rx processor */
3076}
3077
3078/***************************************************************************
3079Function: sWriteTxPrioByte
3080Purpose: Write a byte of priority transmit data to a channel
3081Call: sWriteTxPrioByte(ChP,Data)
3082 CHANNEL_T *ChP; Ptr to channel structure
3083 Byte_t Data; The transmit data byte
3084
3085Return: int: 1 if the bytes is successfully written, otherwise 0.
3086
3087Comments: The priority byte is transmitted before any data in the Tx FIFO.
3088
3089Warnings: No context switches are allowed while executing this function.
3090*/
f15313bf 3091static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 3092{
3093 Byte_t DWBuf[4]; /* buffer for double word writes */
3094 Word_t *WordPtr; /* must be far because Win SS != DS */
3095 register DWordIO_t IndexAddr;
3096
3097 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3098 IndexAddr = ChP->IndexAddr;
3099 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3100 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3101 return (0); /* nothing sent */
3102
3103 WordPtr = (Word_t *) (&DWBuf[0]);
3104 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3105
3106 DWBuf[2] = Data; /* data byte value */
457fb605 3107 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3108
3109 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3110
3111 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3112 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 3113 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3114 } else { /* write it to Tx FIFO */
3115
3116 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3117 }
3118 return (1); /* 1 byte sent */
3119}
3120
3121/***************************************************************************
3122Function: sEnInterrupts
3123Purpose: Enable one or more interrupts for a channel
3124Call: sEnInterrupts(ChP,Flags)
3125 CHANNEL_T *ChP; Ptr to channel structure
3126 Word_t Flags: Interrupt enable flags, can be any combination
3127 of the following flags:
3128 TXINT_EN: Interrupt on Tx FIFO empty
3129 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3130 sSetRxTrigger())
3131 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3132 MCINT_EN: Interrupt on modem input change
3133 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3134 Interrupt Channel Register.
3135Return: void
3136Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3137 enabled. If an interrupt enable flag is not set in Flags, that
3138 interrupt will not be changed. Interrupts can be disabled with
3139 function sDisInterrupts().
3140
3141 This function sets the appropriate bit for the channel in the AIOP's
3142 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3143 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3144
3145 Interrupts must also be globally enabled before channel interrupts
3146 will be passed on to the host. This is done with function
3147 sEnGlobalInt().
3148
3149 In some cases it may be desirable to disable interrupts globally but
3150 enable channel interrupts. This would allow the global interrupt
3151 status register to be used to determine which AIOPs need service.
3152*/
f15313bf 3153static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3154{
3155 Byte_t Mask; /* Interrupt Mask Register */
3156
3157 ChP->RxControl[2] |=
3158 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3159
457fb605 3160 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3161
3162 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3163
457fb605 3164 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3165
3166 if (Flags & CHANINT_EN) {
3167 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3168 sOutB(ChP->IntMask, Mask);
3169 }
3170}
3171
3172/***************************************************************************
3173Function: sDisInterrupts
3174Purpose: Disable one or more interrupts for a channel
3175Call: sDisInterrupts(ChP,Flags)
3176 CHANNEL_T *ChP; Ptr to channel structure
3177 Word_t Flags: Interrupt flags, can be any combination
3178 of the following flags:
3179 TXINT_EN: Interrupt on Tx FIFO empty
3180 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3181 sSetRxTrigger())
3182 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3183 MCINT_EN: Interrupt on modem input change
3184 CHANINT_EN: Disable channel interrupt signal to the
3185 AIOP's Interrupt Channel Register.
3186Return: void
3187Comments: If an interrupt flag is set in Flags, that interrupt will be
3188 disabled. If an interrupt flag is not set in Flags, that
3189 interrupt will not be changed. Interrupts can be enabled with
3190 function sEnInterrupts().
3191
3192 This function clears the appropriate bit for the channel in the AIOP's
3193 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3194 this channel's bit from being set in the AIOP's Interrupt Channel
3195 Register.
3196*/
f15313bf 3197static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3198{
3199 Byte_t Mask; /* Interrupt Mask Register */
3200
3201 ChP->RxControl[2] &=
3202 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3203 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3204 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3205 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3206
3207 if (Flags & CHANINT_EN) {
3208 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3209 sOutB(ChP->IntMask, Mask);
3210 }
3211}
3212
f15313bf 3213static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3214{
3215 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3216}
3217
3218/*
3219 * Not an official SSCI function, but how to reset RocketModems.
3220 * ISA bus version
3221 */
f15313bf 3222static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3223{
3224 ByteIO_t addr;
3225 Byte_t val;
3226
3227 addr = CtlP->AiopIO[0] + 0x400;
3228 val = sInB(CtlP->MReg3IO);
3229 /* if AIOP[1] is not enabled, enable it */
3230 if ((val & 2) == 0) {
3231 val = sInB(CtlP->MReg2IO);
3232 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3233 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3234 }
3235
3236 sEnAiop(CtlP, 1);
3237 if (!on)
3238 addr += 8;
3239 sOutB(addr + chan, 0); /* apply or remove reset */
3240 sDisAiop(CtlP, 1);
3241}
3242
3243/*
3244 * Not an official SSCI function, but how to reset RocketModems.
3245 * PCI bus version
3246 */
f15313bf 3247static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3248{
3249 ByteIO_t addr;
3250
3251 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3252 if (!on)
3253 addr += 8;
3254 sOutB(addr + chan, 0); /* apply or remove reset */
3255}
3256
3257/* Resets the speaker controller on RocketModem II and III devices */
3258static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3259{
3260 ByteIO_t addr;
3261
3262 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3263 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3264 addr = CtlP->AiopIO[0] + 0x4F;
3265 sOutB(addr, 0);
3266 }
3267
3268 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3269 if ((model == MODEL_UPCI_RM3_8PORT)
3270 || (model == MODEL_UPCI_RM3_4PORT)) {
3271 addr = CtlP->AiopIO[0] + 0x88;
3272 sOutB(addr, 0);
3273 }
3274}
3275
3276/* Returns the line number given the controller (board), aiop and channel number */
3277static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3278{
3279 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3280}
3281
3282/*
3283 * Stores the line number associated with a given controller (board), aiop
3284 * and channel number.
3285 * Returns: The line number assigned
3286 */
3287static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3288{
3289 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3290 return (nextLineNumber - 1);
3291}
Linux kernel - Deliverables
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