[deliverable/linux.git] / drivers / char / tpm / tpm_crb.c

/*
 * Copyright (C) 2014 Intel Corporation
 *
 * Authors:
 * Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
 *
 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
 *
 * This device driver implements the TPM interface as defined in
 * the TCG CRB 2.0 TPM specification.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2
 * of the License.
 */

#include <linux/acpi.h>
#include <linux/highmem.h>
#include <linux/rculist.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include "tpm.h"

#define ACPI_SIG_TPM2 "TPM2"

static const u8 CRB_ACPI_START_UUID[] = {
	/* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
	/* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
};

enum crb_defaults {
	CRB_ACPI_START_REVISION_ID = 1,
	CRB_ACPI_START_INDEX = 1,
};

struct acpi_tpm2 {
	struct acpi_table_header hdr;
	u16 platform_class;
	u16 reserved;
	u64 control_area_pa;
	u32 start_method;
} __packed;

enum crb_ca_request {
	CRB_CA_REQ_GO_IDLE	= BIT(0),
	CRB_CA_REQ_CMD_READY	= BIT(1),
};

enum crb_ca_status {
	CRB_CA_STS_ERROR	= BIT(0),
	CRB_CA_STS_TPM_IDLE	= BIT(1),
};

enum crb_start {
	CRB_START_INVOKE	= BIT(0),
};

enum crb_cancel {
	CRB_CANCEL_INVOKE	= BIT(0),
};

struct crb_control_area {
	u32 req;
	u32 sts;
	u32 cancel;
	u32 start;
	u32 int_enable;
	u32 int_sts;
	u32 cmd_size;
	u32 cmd_pa_low;
	u32 cmd_pa_high;
	u32 rsp_size;
	u64 rsp_pa;
} __packed;

enum crb_status {
	CRB_STS_COMPLETE	= BIT(0),
};

enum crb_flags {
	CRB_FL_ACPI_START	= BIT(0),
	CRB_FL_CRB_START	= BIT(1),
};

struct crb_priv {
	unsigned int flags;
	struct crb_control_area __iomem *cca;
	u8 __iomem *cmd;
	u8 __iomem *rsp;
};

static SIMPLE_DEV_PM_OPS(crb_pm, tpm_pm_suspend, tpm_pm_resume);

static u8 crb_status(struct tpm_chip *chip)
{
	struct crb_priv *priv = chip->vendor.priv;
	u8 sts = 0;

	if ((le32_to_cpu(ioread32(&priv->cca->start)) & CRB_START_INVOKE) !=
	    CRB_START_INVOKE)
		sts |= CRB_STS_COMPLETE;

	return sts;
}

static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
{
	struct crb_priv *priv = chip->vendor.priv;
	unsigned int expected;

	/* sanity check */
	if (count < 6)
		return -EIO;

	if (le32_to_cpu(ioread32(&priv->cca->sts)) & CRB_CA_STS_ERROR)
		return -EIO;

	memcpy_fromio(buf, priv->rsp, 6);
	expected = be32_to_cpup((__be32 *) &buf[2]);

	if (expected > count)
		return -EIO;

	memcpy_fromio(&buf[6], &priv->rsp[6], expected - 6);

	return expected;
}

static int crb_do_acpi_start(struct tpm_chip *chip)
{
	union acpi_object *obj;
	int rc;

	obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
				CRB_ACPI_START_UUID,
				CRB_ACPI_START_REVISION_ID,
				CRB_ACPI_START_INDEX,
				NULL);
	if (!obj)
		return -ENXIO;
	rc = obj->integer.value == 0 ? 0 : -ENXIO;
	ACPI_FREE(obj);
	return rc;
}

static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
{
	struct crb_priv *priv = chip->vendor.priv;
	int rc = 0;

	if (len > le32_to_cpu(ioread32(&priv->cca->cmd_size))) {
		dev_err(&chip->dev,
			"invalid command count value %x %zx\n",
			(unsigned int) len,
			(size_t) le32_to_cpu(ioread32(&priv->cca->cmd_size)));
		return -E2BIG;
	}

	memcpy_toio(priv->cmd, buf, len);

	/* Make sure that cmd is populated before issuing start. */
	wmb();

	if (priv->flags & CRB_FL_CRB_START)
		iowrite32(cpu_to_le32(CRB_START_INVOKE), &priv->cca->start);

	if (priv->flags & CRB_FL_ACPI_START)
		rc = crb_do_acpi_start(chip);

	return rc;
}

static void crb_cancel(struct tpm_chip *chip)
{
	struct crb_priv *priv = chip->vendor.priv;

	iowrite32(cpu_to_le32(CRB_CANCEL_INVOKE), &priv->cca->cancel);

	/* Make sure that cmd is populated before issuing cancel. */
	wmb();

	if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
		dev_err(&chip->dev, "ACPI Start failed\n");

	iowrite32(0, &priv->cca->cancel);
}

static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
{
	struct crb_priv *priv = chip->vendor.priv;
	u32 cancel = le32_to_cpu(ioread32(&priv->cca->cancel));

	return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
}

static const struct tpm_class_ops tpm_crb = {
	.status = crb_status,
	.recv = crb_recv,
	.send = crb_send,
	.cancel = crb_cancel,
	.req_canceled = crb_req_canceled,
	.req_complete_mask = CRB_STS_COMPLETE,
	.req_complete_val = CRB_STS_COMPLETE,
};

static int crb_acpi_add(struct acpi_device *device)
{
	struct tpm_chip *chip;
	struct acpi_tpm2 *buf;
	struct crb_priv *priv;
	struct device *dev = &device->dev;
	acpi_status status;
	u32 sm;
	u64 pa;
	int rc;

	status = acpi_get_table(ACPI_SIG_TPM2, 1,
				(struct acpi_table_header **) &buf);
	if (ACPI_FAILURE(status)) {
		dev_err(dev, "failed to get TPM2 ACPI table\n");
		return -ENODEV;
	}

	/* Should the FIFO driver handle this? */
	if (buf->start_method == TPM2_START_FIFO)
		return -ENODEV;

	chip = tpmm_chip_alloc(dev, &tpm_crb);
	if (IS_ERR(chip))
		return PTR_ERR(chip);

	chip->flags = TPM_CHIP_FLAG_TPM2;

	if (buf->hdr.length < sizeof(struct acpi_tpm2)) {
		dev_err(dev, "TPM2 ACPI table has wrong size");
		return -EINVAL;
	}

	priv = (struct crb_priv *) devm_kzalloc(dev, sizeof(struct crb_priv),
						GFP_KERNEL);
	if (!priv) {
		dev_err(dev, "failed to devm_kzalloc for private data\n");
		return -ENOMEM;
	}

	sm = le32_to_cpu(buf->start_method);

	/* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
	 * report only ACPI start but in practice seems to require both
	 * ACPI start and CRB start.
	 */
	if (sm == TPM2_START_CRB || sm == TPM2_START_FIFO ||
	    !strcmp(acpi_device_hid(device), "MSFT0101"))
		priv->flags |= CRB_FL_CRB_START;

	if (sm == TPM2_START_ACPI || sm == TPM2_START_CRB_WITH_ACPI)
		priv->flags |= CRB_FL_ACPI_START;

	priv->cca = (struct crb_control_area __iomem *)
		devm_ioremap_nocache(dev, buf->control_area_pa, 0x1000);
	if (!priv->cca) {
		dev_err(dev, "ioremap of the control area failed\n");
		return -ENOMEM;
	}

	pa = ((u64) le32_to_cpu(ioread32(&priv->cca->cmd_pa_high)) << 32) |
		(u64) le32_to_cpu(ioread32(&priv->cca->cmd_pa_low));
	priv->cmd = devm_ioremap_nocache(dev, pa,
					 ioread32(&priv->cca->cmd_size));
	if (!priv->cmd) {
		dev_err(dev, "ioremap of the command buffer failed\n");
		return -ENOMEM;
	}

	memcpy_fromio(&pa, &priv->cca->rsp_pa, 8);
	pa = le64_to_cpu(pa);
	priv->rsp = devm_ioremap_nocache(dev, pa,
					 ioread32(&priv->cca->rsp_size));
	if (!priv->rsp) {
		dev_err(dev, "ioremap of the response buffer failed\n");
		return -ENOMEM;
	}

	chip->vendor.priv = priv;

	rc = tpm_get_timeouts(chip);
	if (rc)
		return rc;

	chip->acpi_dev_handle = device->handle;

	rc = tpm2_do_selftest(chip);
	if (rc)
		return rc;

	return tpm_chip_register(chip);
}

static int crb_acpi_remove(struct acpi_device *device)
{
	struct device *dev = &device->dev;
	struct tpm_chip *chip = dev_get_drvdata(dev);

	tpm_chip_unregister(chip);

	if (chip->flags & TPM_CHIP_FLAG_TPM2)
		tpm2_shutdown(chip, TPM2_SU_CLEAR);

	return 0;
}

static struct acpi_device_id crb_device_ids[] = {
	{"MSFT0101", 0},
	{"", 0},
};
MODULE_DEVICE_TABLE(acpi, crb_device_ids);

static struct acpi_driver crb_acpi_driver = {
	.name = "tpm_crb",
	.ids = crb_device_ids,
	.ops = {
		.add = crb_acpi_add,
		.remove = crb_acpi_remove,
	},
	.drv = {
		.pm = &crb_pm,
	},
};

module_acpi_driver(crb_acpi_driver);
MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
MODULE_DESCRIPTION("TPM2 Driver");
MODULE_VERSION("0.1");
MODULE_LICENSE("GPL");
Commit	Line	Data
30fc8d13 JS	1	/*
	2	* Copyright (C) 2014 Intel Corporation
	3	*
	4	* Authors:
	5	* Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
	6	*
	7	* Maintained by: <tpmdd-devel@lists.sourceforge.net>
	8	*
	9	* This device driver implements the TPM interface as defined in
	10	* the TCG CRB 2.0 TPM specification.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License
	14	* as published by the Free Software Foundation; version 2
	15	* of the License.
	16	*/
	17
	18	#include <linux/acpi.h>
	19	#include <linux/highmem.h>
	20	#include <linux/rculist.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include "tpm.h"
	24
	25	#define ACPI_SIG_TPM2 "TPM2"
	26
	27	static const u8 CRB_ACPI_START_UUID[] = {
	28	/* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
	29	/* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
	30	};
	31
	32	enum crb_defaults {
	33	CRB_ACPI_START_REVISION_ID = 1,
	34	CRB_ACPI_START_INDEX = 1,
	35	};
	36
30fc8d13 JS	37	struct acpi_tpm2 {
	38	struct acpi_table_header hdr;
	39	u16 platform_class;
	40	u16 reserved;
	41	u64 control_area_pa;
	42	u32 start_method;
	43	} __packed;
	44
	45	enum crb_ca_request {
	46	CRB_CA_REQ_GO_IDLE = BIT(0),
	47	CRB_CA_REQ_CMD_READY = BIT(1),
	48	};
	49
	50	enum crb_ca_status {
	51	CRB_CA_STS_ERROR = BIT(0),
	52	CRB_CA_STS_TPM_IDLE = BIT(1),
	53	};
	54
	55	enum crb_start {
	56	CRB_START_INVOKE = BIT(0),
	57	};
	58
	59	enum crb_cancel {
	60	CRB_CANCEL_INVOKE = BIT(0),
	61	};
	62
	63	struct crb_control_area {
	64	u32 req;
	65	u32 sts;
	66	u32 cancel;
	67	u32 start;
	68	u32 int_enable;
	69	u32 int_sts;
	70	u32 cmd_size;
149789ce JS	71	u32 cmd_pa_low;
149789ce JS	72	u32 cmd_pa_high;
30fc8d13 JS	73	u32 rsp_size;
	74	u64 rsp_pa;
	75	} __packed;
	76
	77	enum crb_status {
	78	CRB_STS_COMPLETE = BIT(0),
	79	};
	80
	81	enum crb_flags {
	82	CRB_FL_ACPI_START = BIT(0),
	83	CRB_FL_CRB_START = BIT(1),
	84	};
	85
	86	struct crb_priv {
	87	unsigned int flags;
	88	struct crb_control_area __iomem *cca;
	89	u8 __iomem *cmd;
	90	u8 __iomem *rsp;
	91	};
	92
74d6b3ce	93	static SIMPLE_DEV_PM_OPS(crb_pm, tpm_pm_suspend, tpm_pm_resume);
30fc8d13 JS	94
	95	static u8 crb_status(struct tpm_chip *chip)
	96	{
	97	struct crb_priv *priv = chip->vendor.priv;
	98	u8 sts = 0;
	99
	100	if ((le32_to_cpu(ioread32(&priv->cca->start)) & CRB_START_INVOKE) !=
	101	CRB_START_INVOKE)
	102	sts \|= CRB_STS_COMPLETE;
	103
	104	return sts;
	105	}
	106
	107	static int crb_recv(struct tpm_chip chip, u8 buf, size_t count)
	108	{
	109	struct crb_priv *priv = chip->vendor.priv;
	110	unsigned int expected;
	111
	112	/* sanity check */
	113	if (count < 6)
	114	return -EIO;
	115
	116	if (le32_to_cpu(ioread32(&priv->cca->sts)) & CRB_CA_STS_ERROR)
	117	return -EIO;
	118
	119	memcpy_fromio(buf, priv->rsp, 6);
	120	expected = be32_to_cpup((__be32 *) &buf[2]);
	121
	122	if (expected > count)
	123	return -EIO;
	124
	125	memcpy_fromio(&buf[6], &priv->rsp[6], expected - 6);
	126
	127	return expected;
	128	}
	129
	130	static int crb_do_acpi_start(struct tpm_chip *chip)
	131	{
	132	union acpi_object *obj;
	133	int rc;
	134
	135	obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
	136	CRB_ACPI_START_UUID,
	137	CRB_ACPI_START_REVISION_ID,
	138	CRB_ACPI_START_INDEX,
	139	NULL);
	140	if (!obj)
	141	return -ENXIO;
	142	rc = obj->integer.value == 0 ? 0 : -ENXIO;
	143	ACPI_FREE(obj);
	144	return rc;
	145	}
	146
	147	static int crb_send(struct tpm_chip chip, u8 buf, size_t len)
	148	{
	149	struct crb_priv *priv = chip->vendor.priv;
	150	int rc = 0;
	151
	152	if (len > le32_to_cpu(ioread32(&priv->cca->cmd_size))) {
	153	dev_err(&chip->dev,
	154	"invalid command count value %x %zx\n",
	155	(unsigned int) len,
	156	(size_t) le32_to_cpu(ioread32(&priv->cca->cmd_size)));
	157	return -E2BIG;
158	}
159
160	memcpy_toio(priv->cmd, buf, len);
161
162	/* Make sure that cmd is populated before issuing start. */
163	wmb();
164
165	if (priv->flags & CRB_FL_CRB_START)
166	iowrite32(cpu_to_le32(CRB_START_INVOKE), &priv->cca->start);
167
168	if (priv->flags & CRB_FL_ACPI_START)
169	rc = crb_do_acpi_start(chip);
170
171	return rc;
172	}
173
174	static void crb_cancel(struct tpm_chip *chip)
175	{
176	struct crb_priv *priv = chip->vendor.priv;
177
178	iowrite32(cpu_to_le32(CRB_CANCEL_INVOKE), &priv->cca->cancel);
179
180	/* Make sure that cmd is populated before issuing cancel. */
181	wmb();
182
183	if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
184	dev_err(&chip->dev, "ACPI Start failed\n");
185
186	iowrite32(0, &priv->cca->cancel);
187	}
188
189	static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
190	{
191	struct crb_priv *priv = chip->vendor.priv;
192	u32 cancel = le32_to_cpu(ioread32(&priv->cca->cancel));
193
194	return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
195	}
196
197	static const struct tpm_class_ops tpm_crb = {
198	.status = crb_status,
199	.recv = crb_recv,
200	.send = crb_send,
201	.cancel = crb_cancel,
202	.req_canceled = crb_req_canceled,
203	.req_complete_mask = CRB_STS_COMPLETE,
204	.req_complete_val = CRB_STS_COMPLETE,
205	};
206
207	static int crb_acpi_add(struct acpi_device *device)
208	{
209	struct tpm_chip *chip;
210	struct acpi_tpm2 *buf;
211	struct crb_priv *priv;
212	struct device *dev = &device->dev;
213	acpi_status status;
214	u32 sm;
215	u64 pa;
216	int rc;
217
30fc8d13 JS	218	status = acpi_get_table(ACPI_SIG_TPM2, 1,
	219	(struct acpi_table_header **) &buf);
	220	if (ACPI_FAILURE(status)) {
	221	dev_err(dev, "failed to get TPM2 ACPI table\n");
	222	return -ENODEV;
	223	}
	224
399235dc JS	225	/* Should the FIFO driver handle this? */
	226	if (buf->start_method == TPM2_START_FIFO)
	227	return -ENODEV;
	228
	229	chip = tpmm_chip_alloc(dev, &tpm_crb);
	230	if (IS_ERR(chip))
	231	return PTR_ERR(chip);
	232
	233	chip->flags = TPM_CHIP_FLAG_TPM2;
b371616b	234
30fc8d13 JS	235	if (buf->hdr.length < sizeof(struct acpi_tpm2)) {
	236	dev_err(dev, "TPM2 ACPI table has wrong size");
	237	return -EINVAL;
	238	}
	239
	240	priv = (struct crb_priv *) devm_kzalloc(dev, sizeof(struct crb_priv),
	241	GFP_KERNEL);
	242	if (!priv) {
	243	dev_err(dev, "failed to devm_kzalloc for private data\n");
	244	return -ENOMEM;
	245	}
	246
	247	sm = le32_to_cpu(buf->start_method);
	248
	249	/* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
	250	* report only ACPI start but in practice seems to require both
	251	* ACPI start and CRB start.
	252	*/
399235dc	253	if (sm == TPM2_START_CRB \|\| sm == TPM2_START_FIFO \|\|
30fc8d13 JS	254	!strcmp(acpi_device_hid(device), "MSFT0101"))
	255	priv->flags \|= CRB_FL_CRB_START;
	256
399235dc	257	if (sm == TPM2_START_ACPI \|\| sm == TPM2_START_CRB_WITH_ACPI)
30fc8d13 JS	258	priv->flags \|= CRB_FL_ACPI_START;
	259
	260	priv->cca = (struct crb_control_area __iomem *)
	261	devm_ioremap_nocache(dev, buf->control_area_pa, 0x1000);
	262	if (!priv->cca) {
	263	dev_err(dev, "ioremap of the control area failed\n");
	264	return -ENOMEM;
	265	}
	266
149789ce JS	267	pa = ((u64) le32_to_cpu(ioread32(&priv->cca->cmd_pa_high)) << 32) \|
149789ce JS	268	(u64) le32_to_cpu(ioread32(&priv->cca->cmd_pa_low));
49afd728	269	priv->cmd = devm_ioremap_nocache(dev, pa,
30fc8d13 JS	270	ioread32(&priv->cca->cmd_size));
	271	if (!priv->cmd) {
	272	dev_err(dev, "ioremap of the command buffer failed\n");
	273	return -ENOMEM;
	274	}
	275
	276	memcpy_fromio(&pa, &priv->cca->rsp_pa, 8);
	277	pa = le64_to_cpu(pa);
49afd728	278	priv->rsp = devm_ioremap_nocache(dev, pa,
30fc8d13 JS	279	ioread32(&priv->cca->rsp_size));
	280	if (!priv->rsp) {
	281	dev_err(dev, "ioremap of the response buffer failed\n");
	282	return -ENOMEM;
	283	}
	284
	285	chip->vendor.priv = priv;
	286
25112048 JG	287	rc = tpm_get_timeouts(chip);
	288	if (rc)
	289	return rc;
30fc8d13 JS	290
	291	chip->acpi_dev_handle = device->handle;
	292
	293	rc = tpm2_do_selftest(chip);
	294	if (rc)
	295	return rc;
	296
	297	return tpm_chip_register(chip);
	298	}
	299
	300	static int crb_acpi_remove(struct acpi_device *device)
	301	{
	302	struct device *dev = &device->dev;
	303	struct tpm_chip *chip = dev_get_drvdata(dev);
	304
	305	tpm_chip_unregister(chip);
74d6b3ce JS	306
	307	if (chip->flags & TPM_CHIP_FLAG_TPM2)
	308	tpm2_shutdown(chip, TPM2_SU_CLEAR);
	309
30fc8d13 JS	310	return 0;
	311	}
	312
	313	static struct acpi_device_id crb_device_ids[] = {
	314	{"MSFT0101", 0},
	315	{"", 0},
	316	};
	317	MODULE_DEVICE_TABLE(acpi, crb_device_ids);
	318
	319	static struct acpi_driver crb_acpi_driver = {
	320	.name = "tpm_crb",
	321	.ids = crb_device_ids,
	322	.ops = {
	323	.add = crb_acpi_add,
	324	.remove = crb_acpi_remove,
	325	},
	326	.drv = {
	327	.pm = &crb_pm,
	328	},
	329	};
	330
	331	module_acpi_driver(crb_acpi_driver);
	332	MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
	333	MODULE_DESCRIPTION("TPM2 Driver");
	334	MODULE_VERSION("0.1");
	335	MODULE_LICENSE("GPL");