[deliverable/linux.git] / drivers / char / tpm / tpm_nsc.c

/*
 * Copyright (C) 2004 IBM Corporation
 *
 * Authors:
 * Leendert van Doorn <leendert@watson.ibm.com>
 * Dave Safford <safford@watson.ibm.com>
 * Reiner Sailer <sailer@watson.ibm.com>
 * Kylene Hall <kjhall@us.ibm.com>
 *
 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
 *
 * Device driver for TCG/TCPA TPM (trusted platform module).
 * Specifications at www.trustedcomputinggroup.org	 
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation, version 2 of the
 * License.
 * 
 */

#include <linux/platform_device.h>
#include <linux/slab.h>
#include "tpm.h"

/* National definitions */
enum tpm_nsc_addr{
	TPM_NSC_IRQ = 0x07,
	TPM_NSC_BASE0_HI = 0x60,
	TPM_NSC_BASE0_LO = 0x61,
	TPM_NSC_BASE1_HI = 0x62,
	TPM_NSC_BASE1_LO = 0x63
};

enum tpm_nsc_index {
	NSC_LDN_INDEX = 0x07,
	NSC_SID_INDEX = 0x20,
	NSC_LDC_INDEX = 0x30,
	NSC_DIO_INDEX = 0x60,
	NSC_CIO_INDEX = 0x62,
	NSC_IRQ_INDEX = 0x70,
	NSC_ITS_INDEX = 0x71
};

enum tpm_nsc_status_loc {
	NSC_STATUS = 0x01,
	NSC_COMMAND = 0x01,
	NSC_DATA = 0x00
};

/* status bits */
enum tpm_nsc_status {
	NSC_STATUS_OBF = 0x01,	/* output buffer full */
	NSC_STATUS_IBF = 0x02,	/* input buffer full */
	NSC_STATUS_F0 = 0x04,	/* F0 */
	NSC_STATUS_A2 = 0x08,	/* A2 */
	NSC_STATUS_RDY = 0x10,	/* ready to receive command */
	NSC_STATUS_IBR = 0x20	/* ready to receive data */
};

/* command bits */
enum tpm_nsc_cmd_mode {
	NSC_COMMAND_NORMAL = 0x01,	/* normal mode */
	NSC_COMMAND_EOC = 0x03,
	NSC_COMMAND_CANCEL = 0x22
};
/*
 * Wait for a certain status to appear
 */
static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
{
	unsigned long stop;

	/* status immediately available check */
	*data = inb(chip->vendor.base + NSC_STATUS);
	if ((*data & mask) == val)
		return 0;

	/* wait for status */
	stop = jiffies + 10 * HZ;
	do {
		msleep(TPM_TIMEOUT);
		*data = inb(chip->vendor.base + 1);
		if ((*data & mask) == val)
			return 0;
	}
	while (time_before(jiffies, stop));

	return -EBUSY;
}

static int nsc_wait_for_ready(struct tpm_chip *chip)
{
	int status;
	unsigned long stop;

	/* status immediately available check */
	status = inb(chip->vendor.base + NSC_STATUS);
	if (status & NSC_STATUS_OBF)
		status = inb(chip->vendor.base + NSC_DATA);
	if (status & NSC_STATUS_RDY)
		return 0;

	/* wait for status */
	stop = jiffies + 100;
	do {
		msleep(TPM_TIMEOUT);
		status = inb(chip->vendor.base + NSC_STATUS);
		if (status & NSC_STATUS_OBF)
			status = inb(chip->vendor.base + NSC_DATA);
		if (status & NSC_STATUS_RDY)
			return 0;
	}
	while (time_before(jiffies, stop));

	dev_info(chip->pdev, "wait for ready failed\n");
	return -EBUSY;
}


static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
{
	u8 *buffer = buf;
	u8 data, *p;
	u32 size;
	__be32 *native_size;

	if (count < 6)
		return -EIO;

	if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
		dev_err(chip->pdev, "F0 timeout\n");
		return -EIO;
	}
	if ((data =
	     inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
		dev_err(chip->pdev, "not in normal mode (0x%x)\n",
			data);
		return -EIO;
	}

	/* read the whole packet */
	for (p = buffer; p < &buffer[count]; p++) {
		if (wait_for_stat
		    (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
			dev_err(chip->pdev,
				"OBF timeout (while reading data)\n");
			return -EIO;
		}
		if (data & NSC_STATUS_F0)
			break;
		*p = inb(chip->vendor.base + NSC_DATA);
	}

	if ((data & NSC_STATUS_F0) == 0 &&
	(wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
		dev_err(chip->pdev, "F0 not set\n");
		return -EIO;
	}
	if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) {
		dev_err(chip->pdev,
			"expected end of command(0x%x)\n", data);
		return -EIO;
	}

	native_size = (__force __be32 *) (buf + 2);
	size = be32_to_cpu(*native_size);

	if (count < size)
		return -EIO;

	return size;
}

static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
{
	u8 data;
	int i;

	/*
	 * If we hit the chip with back to back commands it locks up
	 * and never set IBF. Hitting it with this "hammer" seems to
	 * fix it. Not sure why this is needed, we followed the flow
	 * chart in the manual to the letter.
	 */
	outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);

	if (nsc_wait_for_ready(chip) != 0)
		return -EIO;

	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
		dev_err(chip->pdev, "IBF timeout\n");
		return -EIO;
	}

	outb(NSC_COMMAND_NORMAL, chip->vendor.base + NSC_COMMAND);
	if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
		dev_err(chip->pdev, "IBR timeout\n");
		return -EIO;
	}

	for (i = 0; i < count; i++) {
		if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
			dev_err(chip->pdev,
				"IBF timeout (while writing data)\n");
			return -EIO;
		}
		outb(buf[i], chip->vendor.base + NSC_DATA);
	}

	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
		dev_err(chip->pdev, "IBF timeout\n");
		return -EIO;
	}
	outb(NSC_COMMAND_EOC, chip->vendor.base + NSC_COMMAND);

	return count;
}

static void tpm_nsc_cancel(struct tpm_chip *chip)
{
	outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
}

static u8 tpm_nsc_status(struct tpm_chip *chip)
{
	return inb(chip->vendor.base + NSC_STATUS);
}

static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status)
{
	return (status == NSC_STATUS_RDY);
}

static const struct tpm_class_ops tpm_nsc = {
	.recv = tpm_nsc_recv,
	.send = tpm_nsc_send,
	.cancel = tpm_nsc_cancel,
	.status = tpm_nsc_status,
	.req_complete_mask = NSC_STATUS_OBF,
	.req_complete_val = NSC_STATUS_OBF,
	.req_canceled = tpm_nsc_req_canceled,
};

static struct platform_device *pdev = NULL;

static void tpm_nsc_remove(struct device *dev)
{
	struct tpm_chip *chip = dev_get_drvdata(dev);

	tpm_chip_unregister(chip);
	release_region(chip->vendor.base, 2);
}

static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume);

static struct platform_driver nsc_drv = {
	.driver          = {
		.name    = "tpm_nsc",
		.pm      = &tpm_nsc_pm,
	},
};

static int __init init_nsc(void)
{
	int rc = 0;
	int lo, hi, err;
	int nscAddrBase = TPM_ADDR;
	struct tpm_chip *chip;
	unsigned long base;

	/* verify that it is a National part (SID) */
	if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
		nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
			(tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
		if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
			return -ENODEV;
	}

	err = platform_driver_register(&nsc_drv);
	if (err)
		return err;

	hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
	lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
	base = (hi<<8) | lo;

	/* enable the DPM module */
	tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);

	pdev = platform_device_alloc("tpm_nscl0", -1);
	if (!pdev) {
		rc = -ENOMEM;
		goto err_unreg_drv;
	}

	pdev->num_resources = 0;
	pdev->dev.driver = &nsc_drv.driver;
	pdev->dev.release = tpm_nsc_remove;

	if ((rc = platform_device_add(pdev)) < 0)
		goto err_put_dev;

	if (request_region(base, 2, "tpm_nsc0") == NULL ) {
		rc = -EBUSY;
		goto err_del_dev;
	}

	chip = tpmm_chip_alloc(&pdev->dev, &tpm_nsc);
	if (IS_ERR(chip)) {
		rc = -ENODEV;
		goto err_rel_reg;
	}

	rc = tpm_chip_register(chip);
	if (rc)
		goto err_rel_reg;

	dev_dbg(&pdev->dev, "NSC TPM detected\n");
	dev_dbg(&pdev->dev,
		"NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
		tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
		tpm_read_index(nscAddrBase,0x27));
	dev_dbg(&pdev->dev,
		"NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
		tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
		tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
	dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
		(tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
	dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
		(tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
	dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
		tpm_read_index(nscAddrBase,0x70));
	dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
		tpm_read_index(nscAddrBase,0x71));
	dev_dbg(&pdev->dev,
		"NSC DMA channel select0 0x%x, select1 0x%x\n",
		tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
	dev_dbg(&pdev->dev,
		"NSC Config "
		"0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
		tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
		tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
		tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
		tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
		tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));

	dev_info(&pdev->dev,
		 "NSC TPM revision %d\n",
		 tpm_read_index(nscAddrBase, 0x27) & 0x1F);

	chip->vendor.base = base;

	return 0;

err_rel_reg:
	release_region(base, 2);
err_del_dev:
	platform_device_del(pdev);
err_put_dev:
	platform_device_put(pdev);
err_unreg_drv:
	platform_driver_unregister(&nsc_drv);
	return rc;
}

static void __exit cleanup_nsc(void)
{
	if (pdev) {
		tpm_nsc_remove(&pdev->dev);
		platform_device_unregister(pdev);
	}

	platform_driver_unregister(&nsc_drv);
}

module_init(init_nsc);
module_exit(cleanup_nsc);

MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
MODULE_DESCRIPTION("TPM Driver");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 IBM Corporation
	3	*
	4	* Authors:
	5	* Leendert van Doorn <leendert@watson.ibm.com>
	6	* Dave Safford <safford@watson.ibm.com>
	7	* Reiner Sailer <sailer@watson.ibm.com>
	8	* Kylene Hall <kjhall@us.ibm.com>
	9	*
8e81cc13	10	* Maintained by: <tpmdd-devel@lists.sourceforge.net>
1da177e4 LT	11	*
	12	* Device driver for TCG/TCPA TPM (trusted platform module).
	13	* Specifications at www.trustedcomputinggroup.org
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation, version 2 of the
	18	* License.
	19	*
	20	*/
	21
faba278f	22	#include <linux/platform_device.h>
5a0e3ad6	23	#include <linux/slab.h>
1da177e4 LT	24	#include "tpm.h"
	25
	26	/* National definitions */
e1a23c66	27	enum tpm_nsc_addr{
e1a23c66 KH	28	TPM_NSC_IRQ = 0x07,
	29	TPM_NSC_BASE0_HI = 0x60,
	30	TPM_NSC_BASE0_LO = 0x61,
	31	TPM_NSC_BASE1_HI = 0x62,
	32	TPM_NSC_BASE1_LO = 0x63
3122a88a	33	};
1da177e4	34
3122a88a KH	35	enum tpm_nsc_index {
	36	NSC_LDN_INDEX = 0x07,
	37	NSC_SID_INDEX = 0x20,
	38	NSC_LDC_INDEX = 0x30,
	39	NSC_DIO_INDEX = 0x60,
	40	NSC_CIO_INDEX = 0x62,
	41	NSC_IRQ_INDEX = 0x70,
	42	NSC_ITS_INDEX = 0x71
	43	};
1da177e4	44
3122a88a KH	45	enum tpm_nsc_status_loc {
	46	NSC_STATUS = 0x01,
	47	NSC_COMMAND = 0x01,
	48	NSC_DATA = 0x00
	49	};
1da177e4 LT	50
1da177e4 LT	51	/* status bits */
e1a23c66	52	enum tpm_nsc_status {
3122a88a KH	53	NSC_STATUS_OBF = 0x01, /* output buffer full */
	54	NSC_STATUS_IBF = 0x02, /* input buffer full */
	55	NSC_STATUS_F0 = 0x04, /* F0 */
	56	NSC_STATUS_A2 = 0x08, /* A2 */
	57	NSC_STATUS_RDY = 0x10, /* ready to receive command */
	58	NSC_STATUS_IBR = 0x20 /* ready to receive data */
	59	};
daacdfa6	60
1da177e4	61	/* command bits */
3122a88a KH	62	enum tpm_nsc_cmd_mode {
	63	NSC_COMMAND_NORMAL = 0x01, /* normal mode */
	64	NSC_COMMAND_EOC = 0x03,
	65	NSC_COMMAND_CANCEL = 0x22
	66	};
1da177e4 LT	67	/*
	68	* Wait for a certain status to appear
	69	*/
	70	static int wait_for_stat(struct tpm_chip chip, u8 mask, u8 val, u8 data)
	71	{
700d8bdc	72	unsigned long stop;
1da177e4 LT	73
1da177e4 LT	74	/* status immediately available check */
90dda520	75	*data = inb(chip->vendor.base + NSC_STATUS);
1da177e4 LT	76	if ((*data & mask) == val)
	77	return 0;
	78
	79	/* wait for status */
700d8bdc	80	stop = jiffies + 10 * HZ;
1da177e4	81	do {
700d8bdc	82	msleep(TPM_TIMEOUT);
90dda520	83	*data = inb(chip->vendor.base + 1);
700d8bdc	84	if ((*data & mask) == val)
1da177e4	85	return 0;
1da177e4	86	}
700d8bdc	87	while (time_before(jiffies, stop));
1da177e4 LT	88
	89	return -EBUSY;
	90	}
	91
	92	static int nsc_wait_for_ready(struct tpm_chip *chip)
	93	{
	94	int status;
700d8bdc	95	unsigned long stop;
1da177e4 LT	96
1da177e4 LT	97	/* status immediately available check */
90dda520	98	status = inb(chip->vendor.base + NSC_STATUS);
1da177e4	99	if (status & NSC_STATUS_OBF)
90dda520	100	status = inb(chip->vendor.base + NSC_DATA);
1da177e4 LT	101	if (status & NSC_STATUS_RDY)
	102	return 0;
	103
	104	/* wait for status */
700d8bdc	105	stop = jiffies + 100;
1da177e4	106	do {
700d8bdc	107	msleep(TPM_TIMEOUT);
90dda520	108	status = inb(chip->vendor.base + NSC_STATUS);
1da177e4	109	if (status & NSC_STATUS_OBF)
90dda520	110	status = inb(chip->vendor.base + NSC_DATA);
700d8bdc	111	if (status & NSC_STATUS_RDY)
1da177e4	112	return 0;
1da177e4	113	}
700d8bdc	114	while (time_before(jiffies, stop));
1da177e4	115
71ed848f	116	dev_info(chip->pdev, "wait for ready failed\n");
1da177e4 LT	117	return -EBUSY;
	118	}
	119
	120
	121	static int tpm_nsc_recv(struct tpm_chip chip, u8 buf, size_t count)
	122	{
	123	u8 *buffer = buf;
	124	u8 data, *p;
	125	u32 size;
	126	__be32 *native_size;
	127
	128	if (count < 6)
	129	return -EIO;
	130
	131	if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
71ed848f	132	dev_err(chip->pdev, "F0 timeout\n");
1da177e4 LT	133	return -EIO;
	134	}
	135	if ((data =
90dda520	136	inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
71ed848f	137	dev_err(chip->pdev, "not in normal mode (0x%x)\n",
1da177e4 LT	138	data);
	139	return -EIO;
	140	}
	141
	142	/* read the whole packet */
	143	for (p = buffer; p < &buffer[count]; p++) {
	144	if (wait_for_stat
	145	(chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
71ed848f	146	dev_err(chip->pdev,
1da177e4 LT	147	"OBF timeout (while reading data)\n");
	148	return -EIO;
	149	}
	150	if (data & NSC_STATUS_F0)
	151	break;
90dda520	152	*p = inb(chip->vendor.base + NSC_DATA);
1da177e4 LT	153	}
1da177e4 LT	154
daacdfa6 KJH	155	if ((data & NSC_STATUS_F0) == 0 &&
daacdfa6 KJH	156	(wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
71ed848f	157	dev_err(chip->pdev, "F0 not set\n");
1da177e4 LT	158	return -EIO;
1da177e4 LT	159	}
90dda520	160	if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) {
71ed848f	161	dev_err(chip->pdev,
1da177e4 LT	162	"expected end of command(0x%x)\n", data);
	163	return -EIO;
	164	}
	165
	166	native_size = (__force __be32 *) (buf + 2);
	167	size = be32_to_cpu(*native_size);
	168
	169	if (count < size)
	170	return -EIO;
	171
	172	return size;
	173	}
	174
	175	static int tpm_nsc_send(struct tpm_chip chip, u8 buf, size_t count)
	176	{
	177	u8 data;
	178	int i;
	179
	180	/*
	181	* If we hit the chip with back to back commands it locks up
	182	* and never set IBF. Hitting it with this "hammer" seems to
	183	* fix it. Not sure why this is needed, we followed the flow
	184	* chart in the manual to the letter.
	185	*/
90dda520	186	outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
1da177e4 LT	187
	188	if (nsc_wait_for_ready(chip) != 0)
	189	return -EIO;
	190
	191	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
71ed848f	192	dev_err(chip->pdev, "IBF timeout\n");
1da177e4 LT	193	return -EIO;
	194	}
	195
90dda520	196	outb(NSC_COMMAND_NORMAL, chip->vendor.base + NSC_COMMAND);
1da177e4	197	if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
71ed848f	198	dev_err(chip->pdev, "IBR timeout\n");
1da177e4 LT	199	return -EIO;
	200	}
	201
	202	for (i = 0; i < count; i++) {
	203	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
71ed848f	204	dev_err(chip->pdev,
1da177e4 LT	205	"IBF timeout (while writing data)\n");
	206	return -EIO;
	207	}
90dda520	208	outb(buf[i], chip->vendor.base + NSC_DATA);
1da177e4 LT	209	}
	210
	211	if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
71ed848f	212	dev_err(chip->pdev, "IBF timeout\n");
1da177e4 LT	213	return -EIO;
1da177e4 LT	214	}
90dda520	215	outb(NSC_COMMAND_EOC, chip->vendor.base + NSC_COMMAND);
1da177e4 LT	216
	217	return count;
	218	}
	219
	220	static void tpm_nsc_cancel(struct tpm_chip *chip)
	221	{
90dda520	222	outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
1da177e4 LT	223	}
1da177e4 LT	224
b4ed3e3c KJH	225	static u8 tpm_nsc_status(struct tpm_chip *chip)
b4ed3e3c KJH	226	{
90dda520	227	return inb(chip->vendor.base + NSC_STATUS);
b4ed3e3c KJH	228	}
b4ed3e3c KJH	229
1f866057 SB	230	static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status)
	231	{
	232	return (status == NSC_STATUS_RDY);
	233	}
	234
01ad1fa7	235	static const struct tpm_class_ops tpm_nsc = {
1da177e4 LT	236	.recv = tpm_nsc_recv,
	237	.send = tpm_nsc_send,
	238	.cancel = tpm_nsc_cancel,
b4ed3e3c	239	.status = tpm_nsc_status,
1da177e4 LT	240	.req_complete_mask = NSC_STATUS_OBF,
1da177e4 LT	241	.req_complete_val = NSC_STATUS_OBF,
1f866057	242	.req_canceled = tpm_nsc_req_canceled,
1da177e4 LT	243	};
1da177e4 LT	244
570302a3 KJH	245	static struct platform_device *pdev = NULL;
570302a3 KJH	246
4821cd11	247	static void tpm_nsc_remove(struct device *dev)
570302a3 KJH	248	{
570302a3 KJH	249	struct tpm_chip *chip = dev_get_drvdata(dev);
afb5abc2 JS	250
	251	tpm_chip_unregister(chip);
	252	release_region(chip->vendor.base, 2);
570302a3 KJH	253	}
570302a3 KJH	254
ca9a2054	255	static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume);
09f50c95 DS	256
09f50c95 DS	257	static struct platform_driver nsc_drv = {
09f50c95 DS	258	.driver = {
09f50c95 DS	259	.name = "tpm_nsc",
ca9a2054	260	.pm = &tpm_nsc_pm,
09f50c95	261	},
570302a3 KJH	262	};
	263
	264	static int __init init_nsc(void)
1da177e4 LT	265	{
1da177e4 LT	266	int rc = 0;
f33d9bd5	267	int lo, hi, err;
daacdfa6	268	int nscAddrBase = TPM_ADDR;
e0dd03ca KJH	269	struct tpm_chip *chip;
e0dd03ca KJH	270	unsigned long base;
daacdfa6	271
1da177e4	272	/* verify that it is a National part (SID) */
daacdfa6 KJH	273	if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
	274	nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)\|
	275	(tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
570302a3 KJH	276	if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
570302a3 KJH	277	return -ENODEV;
1da177e4 LT	278	}
1da177e4 LT	279
09f50c95	280	err = platform_driver_register(&nsc_drv);
f33d9bd5 JG	281	if (err)
f33d9bd5 JG	282	return err;
e2a8f7a1	283
daacdfa6 KJH	284	hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
daacdfa6 KJH	285	lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
e0dd03ca	286	base = (hi<<8) \| lo;
daacdfa6	287
570302a3 KJH	288	/* enable the DPM module */
	289	tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
	290
09f50c95	291	pdev = platform_device_alloc("tpm_nscl0", -1);
e2a8f7a1 KJH	292	if (!pdev) {
	293	rc = -ENOMEM;
	294	goto err_unreg_drv;
	295	}
570302a3	296
570302a3	297	pdev->num_resources = 0;
09f50c95	298	pdev->dev.driver = &nsc_drv.driver;
570302a3	299	pdev->dev.release = tpm_nsc_remove;
570302a3	300
29412f0f SB	301	if ((rc = platform_device_add(pdev)) < 0)
29412f0f SB	302	goto err_put_dev;
570302a3	303
e0dd03ca	304	if (request_region(base, 2, "tpm_nsc0") == NULL ) {
e2a8f7a1	305	rc = -EBUSY;
29412f0f	306	goto err_del_dev;
570302a3 KJH	307	}
570302a3 KJH	308
afb5abc2 JS	309	chip = tpmm_chip_alloc(&pdev->dev, &tpm_nsc);
afb5abc2 JS	310	if (IS_ERR(chip)) {
e0dd03ca	311	rc = -ENODEV;
e2a8f7a1	312	goto err_rel_reg;
e0dd03ca	313	}
570302a3	314
afb5abc2 JS	315	rc = tpm_chip_register(chip);
	316	if (rc)
	317	goto err_rel_reg;
	318
570302a3 KJH	319	dev_dbg(&pdev->dev, "NSC TPM detected\n");
570302a3 KJH	320	dev_dbg(&pdev->dev,
1da177e4	321	"NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
daacdfa6 KJH	322	tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
daacdfa6 KJH	323	tpm_read_index(nscAddrBase,0x27));
570302a3	324	dev_dbg(&pdev->dev,
1da177e4	325	"NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
daacdfa6 KJH	326	tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
daacdfa6 KJH	327	tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
570302a3	328	dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
daacdfa6	329	(tpm_read_index(nscAddrBase,0x60) << 8) \| tpm_read_index(nscAddrBase,0x61));
570302a3	330	dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
daacdfa6	331	(tpm_read_index(nscAddrBase,0x62) << 8) \| tpm_read_index(nscAddrBase,0x63));
570302a3	332	dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
daacdfa6	333	tpm_read_index(nscAddrBase,0x70));
570302a3	334	dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
daacdfa6	335	tpm_read_index(nscAddrBase,0x71));
570302a3	336	dev_dbg(&pdev->dev,
1da177e4	337	"NSC DMA channel select0 0x%x, select1 0x%x\n",
daacdfa6	338	tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
570302a3	339	dev_dbg(&pdev->dev,
1da177e4 LT	340	"NSC Config "
1da177e4 LT	341	"0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
daacdfa6 KJH	342	tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
	343	tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
	344	tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
	345	tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
	346	tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
1da177e4	347
570302a3	348	dev_info(&pdev->dev,
daacdfa6 KJH	349	"NSC TPM revision %d\n",
daacdfa6 KJH	350	tpm_read_index(nscAddrBase, 0x27) & 0x1F);
1da177e4	351
e0dd03ca KJH	352	chip->vendor.base = base;
e0dd03ca KJH	353
1da177e4	354	return 0;
e2a8f7a1 KJH	355
e2a8f7a1 KJH	356	err_rel_reg:
e0dd03ca	357	release_region(base, 2);
29412f0f SB	358	err_del_dev:
	359	platform_device_del(pdev);
	360	err_put_dev:
	361	platform_device_put(pdev);
e2a8f7a1	362	err_unreg_drv:
09f50c95	363	platform_driver_unregister(&nsc_drv);
e2a8f7a1	364	return rc;
1da177e4 LT	365	}
	366
	367	static void __exit cleanup_nsc(void)
	368	{
570302a3 KJH	369	if (pdev) {
	370	tpm_nsc_remove(&pdev->dev);
	371	platform_device_unregister(pdev);
570302a3 KJH	372	}
570302a3 KJH	373
09f50c95	374	platform_driver_unregister(&nsc_drv);
1da177e4 LT	375	}
	376
	377	module_init(init_nsc);
	378	module_exit(cleanup_nsc);
	379
	380	MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
	381	MODULE_DESCRIPTION("TPM Driver");
	382	MODULE_VERSION("2.0");
	383	MODULE_LICENSE("GPL");