Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2004 IBM Corporation | |
3 | * | |
4 | * Authors: | |
5 | * Leendert van Doorn <leendert@watson.ibm.com> | |
6 | * Dave Safford <safford@watson.ibm.com> | |
7 | * Reiner Sailer <sailer@watson.ibm.com> | |
8 | * Kylene Hall <kjhall@us.ibm.com> | |
9 | * | |
8e81cc13 | 10 | * Maintained by: <tpmdd-devel@lists.sourceforge.net> |
1da177e4 LT |
11 | * |
12 | * Device driver for TCG/TCPA TPM (trusted platform module). | |
13 | * Specifications at www.trustedcomputinggroup.org | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation, version 2 of the | |
18 | * License. | |
19 | * | |
20 | */ | |
21 | ||
faba278f | 22 | #include <linux/platform_device.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
1da177e4 LT |
24 | #include "tpm.h" |
25 | ||
26 | /* National definitions */ | |
e1a23c66 | 27 | enum tpm_nsc_addr{ |
e1a23c66 KH |
28 | TPM_NSC_IRQ = 0x07, |
29 | TPM_NSC_BASE0_HI = 0x60, | |
30 | TPM_NSC_BASE0_LO = 0x61, | |
31 | TPM_NSC_BASE1_HI = 0x62, | |
32 | TPM_NSC_BASE1_LO = 0x63 | |
3122a88a | 33 | }; |
1da177e4 | 34 | |
3122a88a KH |
35 | enum tpm_nsc_index { |
36 | NSC_LDN_INDEX = 0x07, | |
37 | NSC_SID_INDEX = 0x20, | |
38 | NSC_LDC_INDEX = 0x30, | |
39 | NSC_DIO_INDEX = 0x60, | |
40 | NSC_CIO_INDEX = 0x62, | |
41 | NSC_IRQ_INDEX = 0x70, | |
42 | NSC_ITS_INDEX = 0x71 | |
43 | }; | |
1da177e4 | 44 | |
3122a88a KH |
45 | enum tpm_nsc_status_loc { |
46 | NSC_STATUS = 0x01, | |
47 | NSC_COMMAND = 0x01, | |
48 | NSC_DATA = 0x00 | |
49 | }; | |
1da177e4 LT |
50 | |
51 | /* status bits */ | |
e1a23c66 | 52 | enum tpm_nsc_status { |
3122a88a KH |
53 | NSC_STATUS_OBF = 0x01, /* output buffer full */ |
54 | NSC_STATUS_IBF = 0x02, /* input buffer full */ | |
55 | NSC_STATUS_F0 = 0x04, /* F0 */ | |
56 | NSC_STATUS_A2 = 0x08, /* A2 */ | |
57 | NSC_STATUS_RDY = 0x10, /* ready to receive command */ | |
58 | NSC_STATUS_IBR = 0x20 /* ready to receive data */ | |
59 | }; | |
daacdfa6 | 60 | |
1da177e4 | 61 | /* command bits */ |
3122a88a KH |
62 | enum tpm_nsc_cmd_mode { |
63 | NSC_COMMAND_NORMAL = 0x01, /* normal mode */ | |
64 | NSC_COMMAND_EOC = 0x03, | |
65 | NSC_COMMAND_CANCEL = 0x22 | |
66 | }; | |
1da177e4 LT |
67 | /* |
68 | * Wait for a certain status to appear | |
69 | */ | |
70 | static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data) | |
71 | { | |
700d8bdc | 72 | unsigned long stop; |
1da177e4 LT |
73 | |
74 | /* status immediately available check */ | |
90dda520 | 75 | *data = inb(chip->vendor.base + NSC_STATUS); |
1da177e4 LT |
76 | if ((*data & mask) == val) |
77 | return 0; | |
78 | ||
79 | /* wait for status */ | |
700d8bdc | 80 | stop = jiffies + 10 * HZ; |
1da177e4 | 81 | do { |
700d8bdc | 82 | msleep(TPM_TIMEOUT); |
90dda520 | 83 | *data = inb(chip->vendor.base + 1); |
700d8bdc | 84 | if ((*data & mask) == val) |
1da177e4 | 85 | return 0; |
1da177e4 | 86 | } |
700d8bdc | 87 | while (time_before(jiffies, stop)); |
1da177e4 LT |
88 | |
89 | return -EBUSY; | |
90 | } | |
91 | ||
92 | static int nsc_wait_for_ready(struct tpm_chip *chip) | |
93 | { | |
94 | int status; | |
700d8bdc | 95 | unsigned long stop; |
1da177e4 LT |
96 | |
97 | /* status immediately available check */ | |
90dda520 | 98 | status = inb(chip->vendor.base + NSC_STATUS); |
1da177e4 | 99 | if (status & NSC_STATUS_OBF) |
90dda520 | 100 | status = inb(chip->vendor.base + NSC_DATA); |
1da177e4 LT |
101 | if (status & NSC_STATUS_RDY) |
102 | return 0; | |
103 | ||
104 | /* wait for status */ | |
700d8bdc | 105 | stop = jiffies + 100; |
1da177e4 | 106 | do { |
700d8bdc | 107 | msleep(TPM_TIMEOUT); |
90dda520 | 108 | status = inb(chip->vendor.base + NSC_STATUS); |
1da177e4 | 109 | if (status & NSC_STATUS_OBF) |
90dda520 | 110 | status = inb(chip->vendor.base + NSC_DATA); |
700d8bdc | 111 | if (status & NSC_STATUS_RDY) |
1da177e4 | 112 | return 0; |
1da177e4 | 113 | } |
700d8bdc | 114 | while (time_before(jiffies, stop)); |
1da177e4 | 115 | |
e659a3fe | 116 | dev_info(chip->dev, "wait for ready failed\n"); |
1da177e4 LT |
117 | return -EBUSY; |
118 | } | |
119 | ||
120 | ||
121 | static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count) | |
122 | { | |
123 | u8 *buffer = buf; | |
124 | u8 data, *p; | |
125 | u32 size; | |
126 | __be32 *native_size; | |
127 | ||
128 | if (count < 6) | |
129 | return -EIO; | |
130 | ||
131 | if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) { | |
e659a3fe | 132 | dev_err(chip->dev, "F0 timeout\n"); |
1da177e4 LT |
133 | return -EIO; |
134 | } | |
135 | if ((data = | |
90dda520 | 136 | inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) { |
e659a3fe | 137 | dev_err(chip->dev, "not in normal mode (0x%x)\n", |
1da177e4 LT |
138 | data); |
139 | return -EIO; | |
140 | } | |
141 | ||
142 | /* read the whole packet */ | |
143 | for (p = buffer; p < &buffer[count]; p++) { | |
144 | if (wait_for_stat | |
145 | (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) { | |
e659a3fe | 146 | dev_err(chip->dev, |
1da177e4 LT |
147 | "OBF timeout (while reading data)\n"); |
148 | return -EIO; | |
149 | } | |
150 | if (data & NSC_STATUS_F0) | |
151 | break; | |
90dda520 | 152 | *p = inb(chip->vendor.base + NSC_DATA); |
1da177e4 LT |
153 | } |
154 | ||
daacdfa6 KJH |
155 | if ((data & NSC_STATUS_F0) == 0 && |
156 | (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) { | |
e659a3fe | 157 | dev_err(chip->dev, "F0 not set\n"); |
1da177e4 LT |
158 | return -EIO; |
159 | } | |
90dda520 | 160 | if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) { |
e659a3fe | 161 | dev_err(chip->dev, |
1da177e4 LT |
162 | "expected end of command(0x%x)\n", data); |
163 | return -EIO; | |
164 | } | |
165 | ||
166 | native_size = (__force __be32 *) (buf + 2); | |
167 | size = be32_to_cpu(*native_size); | |
168 | ||
169 | if (count < size) | |
170 | return -EIO; | |
171 | ||
172 | return size; | |
173 | } | |
174 | ||
175 | static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count) | |
176 | { | |
177 | u8 data; | |
178 | int i; | |
179 | ||
180 | /* | |
181 | * If we hit the chip with back to back commands it locks up | |
182 | * and never set IBF. Hitting it with this "hammer" seems to | |
183 | * fix it. Not sure why this is needed, we followed the flow | |
184 | * chart in the manual to the letter. | |
185 | */ | |
90dda520 | 186 | outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND); |
1da177e4 LT |
187 | |
188 | if (nsc_wait_for_ready(chip) != 0) | |
189 | return -EIO; | |
190 | ||
191 | if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { | |
e659a3fe | 192 | dev_err(chip->dev, "IBF timeout\n"); |
1da177e4 LT |
193 | return -EIO; |
194 | } | |
195 | ||
90dda520 | 196 | outb(NSC_COMMAND_NORMAL, chip->vendor.base + NSC_COMMAND); |
1da177e4 | 197 | if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) { |
e659a3fe | 198 | dev_err(chip->dev, "IBR timeout\n"); |
1da177e4 LT |
199 | return -EIO; |
200 | } | |
201 | ||
202 | for (i = 0; i < count; i++) { | |
203 | if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { | |
e659a3fe | 204 | dev_err(chip->dev, |
1da177e4 LT |
205 | "IBF timeout (while writing data)\n"); |
206 | return -EIO; | |
207 | } | |
90dda520 | 208 | outb(buf[i], chip->vendor.base + NSC_DATA); |
1da177e4 LT |
209 | } |
210 | ||
211 | if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { | |
e659a3fe | 212 | dev_err(chip->dev, "IBF timeout\n"); |
1da177e4 LT |
213 | return -EIO; |
214 | } | |
90dda520 | 215 | outb(NSC_COMMAND_EOC, chip->vendor.base + NSC_COMMAND); |
1da177e4 LT |
216 | |
217 | return count; | |
218 | } | |
219 | ||
220 | static void tpm_nsc_cancel(struct tpm_chip *chip) | |
221 | { | |
90dda520 | 222 | outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND); |
1da177e4 LT |
223 | } |
224 | ||
b4ed3e3c KJH |
225 | static u8 tpm_nsc_status(struct tpm_chip *chip) |
226 | { | |
90dda520 | 227 | return inb(chip->vendor.base + NSC_STATUS); |
b4ed3e3c KJH |
228 | } |
229 | ||
1f866057 SB |
230 | static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status) |
231 | { | |
232 | return (status == NSC_STATUS_RDY); | |
233 | } | |
234 | ||
01ad1fa7 | 235 | static const struct tpm_class_ops tpm_nsc = { |
1da177e4 LT |
236 | .recv = tpm_nsc_recv, |
237 | .send = tpm_nsc_send, | |
238 | .cancel = tpm_nsc_cancel, | |
b4ed3e3c | 239 | .status = tpm_nsc_status, |
1da177e4 LT |
240 | .req_complete_mask = NSC_STATUS_OBF, |
241 | .req_complete_val = NSC_STATUS_OBF, | |
1f866057 | 242 | .req_canceled = tpm_nsc_req_canceled, |
1da177e4 LT |
243 | }; |
244 | ||
570302a3 KJH |
245 | static struct platform_device *pdev = NULL; |
246 | ||
4821cd11 | 247 | static void tpm_nsc_remove(struct device *dev) |
570302a3 KJH |
248 | { |
249 | struct tpm_chip *chip = dev_get_drvdata(dev); | |
250 | if ( chip ) { | |
90dda520 | 251 | release_region(chip->vendor.base, 2); |
570302a3 KJH |
252 | tpm_remove_hardware(chip->dev); |
253 | } | |
254 | } | |
255 | ||
ca9a2054 | 256 | static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume); |
09f50c95 DS |
257 | |
258 | static struct platform_driver nsc_drv = { | |
09f50c95 DS |
259 | .driver = { |
260 | .name = "tpm_nsc", | |
261 | .owner = THIS_MODULE, | |
ca9a2054 | 262 | .pm = &tpm_nsc_pm, |
09f50c95 | 263 | }, |
570302a3 KJH |
264 | }; |
265 | ||
266 | static int __init init_nsc(void) | |
1da177e4 LT |
267 | { |
268 | int rc = 0; | |
f33d9bd5 | 269 | int lo, hi, err; |
daacdfa6 | 270 | int nscAddrBase = TPM_ADDR; |
e0dd03ca KJH |
271 | struct tpm_chip *chip; |
272 | unsigned long base; | |
daacdfa6 | 273 | |
1da177e4 | 274 | /* verify that it is a National part (SID) */ |
daacdfa6 KJH |
275 | if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) { |
276 | nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)| | |
277 | (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE); | |
570302a3 KJH |
278 | if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6) |
279 | return -ENODEV; | |
1da177e4 LT |
280 | } |
281 | ||
09f50c95 | 282 | err = platform_driver_register(&nsc_drv); |
f33d9bd5 JG |
283 | if (err) |
284 | return err; | |
e2a8f7a1 | 285 | |
daacdfa6 KJH |
286 | hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI); |
287 | lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO); | |
e0dd03ca | 288 | base = (hi<<8) | lo; |
daacdfa6 | 289 | |
570302a3 KJH |
290 | /* enable the DPM module */ |
291 | tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01); | |
292 | ||
09f50c95 | 293 | pdev = platform_device_alloc("tpm_nscl0", -1); |
e2a8f7a1 KJH |
294 | if (!pdev) { |
295 | rc = -ENOMEM; | |
296 | goto err_unreg_drv; | |
297 | } | |
570302a3 | 298 | |
570302a3 | 299 | pdev->num_resources = 0; |
09f50c95 | 300 | pdev->dev.driver = &nsc_drv.driver; |
570302a3 | 301 | pdev->dev.release = tpm_nsc_remove; |
570302a3 | 302 | |
29412f0f SB |
303 | if ((rc = platform_device_add(pdev)) < 0) |
304 | goto err_put_dev; | |
570302a3 | 305 | |
e0dd03ca | 306 | if (request_region(base, 2, "tpm_nsc0") == NULL ) { |
e2a8f7a1 | 307 | rc = -EBUSY; |
29412f0f | 308 | goto err_del_dev; |
570302a3 KJH |
309 | } |
310 | ||
e0dd03ca KJH |
311 | if (!(chip = tpm_register_hardware(&pdev->dev, &tpm_nsc))) { |
312 | rc = -ENODEV; | |
e2a8f7a1 | 313 | goto err_rel_reg; |
e0dd03ca | 314 | } |
570302a3 KJH |
315 | |
316 | dev_dbg(&pdev->dev, "NSC TPM detected\n"); | |
317 | dev_dbg(&pdev->dev, | |
1da177e4 | 318 | "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n", |
daacdfa6 KJH |
319 | tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20), |
320 | tpm_read_index(nscAddrBase,0x27)); | |
570302a3 | 321 | dev_dbg(&pdev->dev, |
1da177e4 | 322 | "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n", |
daacdfa6 KJH |
323 | tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25), |
324 | tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28)); | |
570302a3 | 325 | dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n", |
daacdfa6 | 326 | (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61)); |
570302a3 | 327 | dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n", |
daacdfa6 | 328 | (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63)); |
570302a3 | 329 | dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n", |
daacdfa6 | 330 | tpm_read_index(nscAddrBase,0x70)); |
570302a3 | 331 | dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n", |
daacdfa6 | 332 | tpm_read_index(nscAddrBase,0x71)); |
570302a3 | 333 | dev_dbg(&pdev->dev, |
1da177e4 | 334 | "NSC DMA channel select0 0x%x, select1 0x%x\n", |
daacdfa6 | 335 | tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75)); |
570302a3 | 336 | dev_dbg(&pdev->dev, |
1da177e4 LT |
337 | "NSC Config " |
338 | "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", | |
daacdfa6 KJH |
339 | tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1), |
340 | tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3), | |
341 | tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5), | |
342 | tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7), | |
343 | tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9)); | |
1da177e4 | 344 | |
570302a3 | 345 | dev_info(&pdev->dev, |
daacdfa6 KJH |
346 | "NSC TPM revision %d\n", |
347 | tpm_read_index(nscAddrBase, 0x27) & 0x1F); | |
1da177e4 | 348 | |
e0dd03ca KJH |
349 | chip->vendor.base = base; |
350 | ||
1da177e4 | 351 | return 0; |
e2a8f7a1 KJH |
352 | |
353 | err_rel_reg: | |
e0dd03ca | 354 | release_region(base, 2); |
29412f0f SB |
355 | err_del_dev: |
356 | platform_device_del(pdev); | |
357 | err_put_dev: | |
358 | platform_device_put(pdev); | |
e2a8f7a1 | 359 | err_unreg_drv: |
09f50c95 | 360 | platform_driver_unregister(&nsc_drv); |
e2a8f7a1 | 361 | return rc; |
1da177e4 LT |
362 | } |
363 | ||
364 | static void __exit cleanup_nsc(void) | |
365 | { | |
570302a3 KJH |
366 | if (pdev) { |
367 | tpm_nsc_remove(&pdev->dev); | |
368 | platform_device_unregister(pdev); | |
570302a3 KJH |
369 | } |
370 | ||
09f50c95 | 371 | platform_driver_unregister(&nsc_drv); |
1da177e4 LT |
372 | } |
373 | ||
374 | module_init(init_nsc); | |
375 | module_exit(cleanup_nsc); | |
376 | ||
377 | MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); | |
378 | MODULE_DESCRIPTION("TPM Driver"); | |
379 | MODULE_VERSION("2.0"); | |
380 | MODULE_LICENSE("GPL"); |