Commit | Line | Data |
---|---|---|
27084efe LD |
1 | /* |
2 | * Copyright (C) 2005, 2006 IBM Corporation | |
399235dc | 3 | * Copyright (C) 2014, 2015 Intel Corporation |
27084efe LD |
4 | * |
5 | * Authors: | |
6 | * Leendert van Doorn <leendert@watson.ibm.com> | |
7 | * Kylene Hall <kjhall@us.ibm.com> | |
8 | * | |
8e81cc13 KY |
9 | * Maintained by: <tpmdd-devel@lists.sourceforge.net> |
10 | * | |
27084efe LD |
11 | * Device driver for TCG/TCPA TPM (trusted platform module). |
12 | * Specifications at www.trustedcomputinggroup.org | |
13 | * | |
14 | * This device driver implements the TPM interface as defined in | |
15 | * the TCG TPM Interface Spec version 1.2, revision 1.0. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License as | |
19 | * published by the Free Software Foundation, version 2 of the | |
20 | * License. | |
21 | */ | |
57135568 KJH |
22 | #include <linux/init.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
27084efe | 25 | #include <linux/pnp.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
27084efe LD |
27 | #include <linux/interrupt.h> |
28 | #include <linux/wait.h> | |
3f0d3d01 | 29 | #include <linux/acpi.h> |
20b87bbf | 30 | #include <linux/freezer.h> |
399235dc | 31 | #include <acpi/actbl2.h> |
27084efe LD |
32 | #include "tpm.h" |
33 | ||
27084efe LD |
34 | enum tis_access { |
35 | TPM_ACCESS_VALID = 0x80, | |
36 | TPM_ACCESS_ACTIVE_LOCALITY = 0x20, | |
37 | TPM_ACCESS_REQUEST_PENDING = 0x04, | |
38 | TPM_ACCESS_REQUEST_USE = 0x02, | |
39 | }; | |
40 | ||
41 | enum tis_status { | |
42 | TPM_STS_VALID = 0x80, | |
43 | TPM_STS_COMMAND_READY = 0x40, | |
44 | TPM_STS_GO = 0x20, | |
45 | TPM_STS_DATA_AVAIL = 0x10, | |
46 | TPM_STS_DATA_EXPECT = 0x08, | |
47 | }; | |
48 | ||
49 | enum tis_int_flags { | |
50 | TPM_GLOBAL_INT_ENABLE = 0x80000000, | |
51 | TPM_INTF_BURST_COUNT_STATIC = 0x100, | |
52 | TPM_INTF_CMD_READY_INT = 0x080, | |
53 | TPM_INTF_INT_EDGE_FALLING = 0x040, | |
54 | TPM_INTF_INT_EDGE_RISING = 0x020, | |
55 | TPM_INTF_INT_LEVEL_LOW = 0x010, | |
56 | TPM_INTF_INT_LEVEL_HIGH = 0x008, | |
57 | TPM_INTF_LOCALITY_CHANGE_INT = 0x004, | |
58 | TPM_INTF_STS_VALID_INT = 0x002, | |
59 | TPM_INTF_DATA_AVAIL_INT = 0x001, | |
60 | }; | |
61 | ||
36b20020 | 62 | enum tis_defaults { |
2a7362f5 | 63 | TIS_MEM_BASE = 0xFED40000, |
b09d5300 | 64 | TIS_MEM_LEN = 0x5000, |
cb535425 KJH |
65 | TIS_SHORT_TIMEOUT = 750, /* ms */ |
66 | TIS_LONG_TIMEOUT = 2000, /* 2 sec */ | |
36b20020 KJH |
67 | }; |
68 | ||
399235dc JS |
69 | struct tpm_info { |
70 | unsigned long start; | |
71 | unsigned long len; | |
72 | unsigned int irq; | |
73 | }; | |
74 | ||
75 | static struct tpm_info tis_default_info = { | |
76 | .start = TIS_MEM_BASE, | |
77 | .len = TIS_MEM_LEN, | |
78 | .irq = 0, | |
79 | }; | |
aec04cbd JS |
80 | |
81 | /* Some timeout values are needed before it is known whether the chip is | |
82 | * TPM 1.0 or TPM 2.0. | |
83 | */ | |
84 | #define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A) | |
85 | #define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B) | |
86 | #define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C) | |
87 | #define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D) | |
88 | ||
27084efe LD |
89 | #define TPM_ACCESS(l) (0x0000 | ((l) << 12)) |
90 | #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) | |
91 | #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12)) | |
92 | #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12)) | |
93 | #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) | |
94 | #define TPM_STS(l) (0x0018 | ((l) << 12)) | |
aec04cbd | 95 | #define TPM_STS3(l) (0x001b | ((l) << 12)) |
27084efe LD |
96 | #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) |
97 | ||
98 | #define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) | |
99 | #define TPM_RID(l) (0x0F04 | ((l) << 12)) | |
100 | ||
448e9c55 | 101 | struct priv_data { |
7ab4032f | 102 | bool irq_probing; |
448e9c55 SD |
103 | bool irq_tested; |
104 | }; | |
105 | ||
1560ffe6 | 106 | #if defined(CONFIG_PNP) && defined(CONFIG_ACPI) |
399235dc | 107 | static int has_hid(struct acpi_device *dev, const char *hid) |
3f0d3d01 | 108 | { |
3f0d3d01 MG |
109 | struct acpi_hardware_id *id; |
110 | ||
399235dc JS |
111 | list_for_each_entry(id, &dev->pnp.ids, list) |
112 | if (!strcmp(hid, id->id)) | |
3f0d3d01 | 113 | return 1; |
3f0d3d01 MG |
114 | |
115 | return 0; | |
116 | } | |
399235dc JS |
117 | |
118 | static inline int is_itpm(struct acpi_device *dev) | |
119 | { | |
120 | return has_hid(dev, "INTC0102"); | |
121 | } | |
122 | ||
123 | static inline int is_fifo(struct acpi_device *dev) | |
124 | { | |
125 | struct acpi_table_tpm2 *tbl; | |
126 | acpi_status st; | |
127 | ||
128 | /* TPM 1.2 FIFO */ | |
129 | if (!has_hid(dev, "MSFT0101")) | |
130 | return 1; | |
131 | ||
132 | st = acpi_get_table(ACPI_SIG_TPM2, 1, | |
133 | (struct acpi_table_header **) &tbl); | |
134 | if (ACPI_FAILURE(st)) { | |
135 | dev_err(&dev->dev, "failed to get TPM2 ACPI table\n"); | |
136 | return 0; | |
137 | } | |
138 | ||
139 | if (le32_to_cpu(tbl->start_method) != TPM2_START_FIFO) | |
140 | return 0; | |
141 | ||
142 | /* TPM 2.0 FIFO */ | |
143 | return 1; | |
144 | } | |
1560ffe6 | 145 | #else |
399235dc | 146 | static inline int is_itpm(struct acpi_device *dev) |
1560ffe6 RD |
147 | { |
148 | return 0; | |
149 | } | |
399235dc JS |
150 | |
151 | static inline int is_fifo(struct acpi_device *dev) | |
152 | { | |
153 | return 1; | |
154 | } | |
3f0d3d01 MG |
155 | #endif |
156 | ||
7240b983 JG |
157 | /* Before we attempt to access the TPM we must see that the valid bit is set. |
158 | * The specification says that this bit is 0 at reset and remains 0 until the | |
159 | * 'TPM has gone through its self test and initialization and has established | |
160 | * correct values in the other bits.' */ | |
161 | static int wait_startup(struct tpm_chip *chip, int l) | |
162 | { | |
163 | unsigned long stop = jiffies + chip->vendor.timeout_a; | |
164 | do { | |
165 | if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
166 | TPM_ACCESS_VALID) | |
167 | return 0; | |
168 | msleep(TPM_TIMEOUT); | |
169 | } while (time_before(jiffies, stop)); | |
170 | return -1; | |
171 | } | |
172 | ||
27084efe LD |
173 | static int check_locality(struct tpm_chip *chip, int l) |
174 | { | |
175 | if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
176 | (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) == | |
177 | (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) | |
178 | return chip->vendor.locality = l; | |
179 | ||
180 | return -1; | |
181 | } | |
182 | ||
183 | static void release_locality(struct tpm_chip *chip, int l, int force) | |
184 | { | |
185 | if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) & | |
186 | (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) == | |
187 | (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) | |
188 | iowrite8(TPM_ACCESS_ACTIVE_LOCALITY, | |
189 | chip->vendor.iobase + TPM_ACCESS(l)); | |
190 | } | |
191 | ||
192 | static int request_locality(struct tpm_chip *chip, int l) | |
193 | { | |
20b87bbf | 194 | unsigned long stop, timeout; |
27084efe LD |
195 | long rc; |
196 | ||
197 | if (check_locality(chip, l) >= 0) | |
198 | return l; | |
199 | ||
200 | iowrite8(TPM_ACCESS_REQUEST_USE, | |
201 | chip->vendor.iobase + TPM_ACCESS(l)); | |
202 | ||
20b87bbf SB |
203 | stop = jiffies + chip->vendor.timeout_a; |
204 | ||
27084efe | 205 | if (chip->vendor.irq) { |
20b87bbf SB |
206 | again: |
207 | timeout = stop - jiffies; | |
208 | if ((long)timeout <= 0) | |
209 | return -1; | |
36b20020 | 210 | rc = wait_event_interruptible_timeout(chip->vendor.int_queue, |
27084efe LD |
211 | (check_locality |
212 | (chip, l) >= 0), | |
20b87bbf | 213 | timeout); |
27084efe LD |
214 | if (rc > 0) |
215 | return l; | |
20b87bbf SB |
216 | if (rc == -ERESTARTSYS && freezing(current)) { |
217 | clear_thread_flag(TIF_SIGPENDING); | |
218 | goto again; | |
219 | } | |
27084efe LD |
220 | } else { |
221 | /* wait for burstcount */ | |
27084efe LD |
222 | do { |
223 | if (check_locality(chip, l) >= 0) | |
224 | return l; | |
225 | msleep(TPM_TIMEOUT); | |
226 | } | |
227 | while (time_before(jiffies, stop)); | |
228 | } | |
229 | return -1; | |
230 | } | |
231 | ||
232 | static u8 tpm_tis_status(struct tpm_chip *chip) | |
233 | { | |
234 | return ioread8(chip->vendor.iobase + | |
235 | TPM_STS(chip->vendor.locality)); | |
236 | } | |
237 | ||
238 | static void tpm_tis_ready(struct tpm_chip *chip) | |
239 | { | |
240 | /* this causes the current command to be aborted */ | |
241 | iowrite8(TPM_STS_COMMAND_READY, | |
242 | chip->vendor.iobase + TPM_STS(chip->vendor.locality)); | |
243 | } | |
244 | ||
245 | static int get_burstcount(struct tpm_chip *chip) | |
246 | { | |
247 | unsigned long stop; | |
248 | int burstcnt; | |
249 | ||
250 | /* wait for burstcount */ | |
251 | /* which timeout value, spec has 2 answers (c & d) */ | |
36b20020 | 252 | stop = jiffies + chip->vendor.timeout_d; |
27084efe LD |
253 | do { |
254 | burstcnt = ioread8(chip->vendor.iobase + | |
255 | TPM_STS(chip->vendor.locality) + 1); | |
256 | burstcnt += ioread8(chip->vendor.iobase + | |
257 | TPM_STS(chip->vendor.locality) + | |
258 | 2) << 8; | |
259 | if (burstcnt) | |
260 | return burstcnt; | |
261 | msleep(TPM_TIMEOUT); | |
262 | } while (time_before(jiffies, stop)); | |
263 | return -EBUSY; | |
264 | } | |
265 | ||
cb535425 | 266 | static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count) |
27084efe LD |
267 | { |
268 | int size = 0, burstcnt; | |
269 | while (size < count && | |
fd048866 RA |
270 | wait_for_tpm_stat(chip, |
271 | TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
272 | chip->vendor.timeout_c, | |
78f09cc2 | 273 | &chip->vendor.read_queue, true) |
27084efe LD |
274 | == 0) { |
275 | burstcnt = get_burstcount(chip); | |
276 | for (; burstcnt > 0 && size < count; burstcnt--) | |
277 | buf[size++] = ioread8(chip->vendor.iobase + | |
278 | TPM_DATA_FIFO(chip->vendor. | |
279 | locality)); | |
280 | } | |
281 | return size; | |
282 | } | |
283 | ||
cb535425 | 284 | static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) |
27084efe LD |
285 | { |
286 | int size = 0; | |
287 | int expected, status; | |
288 | ||
289 | if (count < TPM_HEADER_SIZE) { | |
290 | size = -EIO; | |
291 | goto out; | |
292 | } | |
293 | ||
294 | /* read first 10 bytes, including tag, paramsize, and result */ | |
295 | if ((size = | |
296 | recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) { | |
71ed848f | 297 | dev_err(chip->pdev, "Unable to read header\n"); |
27084efe LD |
298 | goto out; |
299 | } | |
300 | ||
301 | expected = be32_to_cpu(*(__be32 *) (buf + 2)); | |
302 | if (expected > count) { | |
303 | size = -EIO; | |
304 | goto out; | |
305 | } | |
306 | ||
307 | if ((size += | |
308 | recv_data(chip, &buf[TPM_HEADER_SIZE], | |
309 | expected - TPM_HEADER_SIZE)) < expected) { | |
71ed848f | 310 | dev_err(chip->pdev, "Unable to read remainder of result\n"); |
27084efe LD |
311 | size = -ETIME; |
312 | goto out; | |
313 | } | |
314 | ||
fd048866 | 315 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
78f09cc2 | 316 | &chip->vendor.int_queue, false); |
27084efe LD |
317 | status = tpm_tis_status(chip); |
318 | if (status & TPM_STS_DATA_AVAIL) { /* retry? */ | |
71ed848f | 319 | dev_err(chip->pdev, "Error left over data\n"); |
27084efe LD |
320 | size = -EIO; |
321 | goto out; | |
322 | } | |
323 | ||
324 | out: | |
325 | tpm_tis_ready(chip); | |
326 | release_locality(chip, chip->vendor.locality, 0); | |
327 | return size; | |
328 | } | |
329 | ||
90ab5ee9 | 330 | static bool itpm; |
3507d612 RA |
331 | module_param(itpm, bool, 0444); |
332 | MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)"); | |
333 | ||
27084efe LD |
334 | /* |
335 | * If interrupts are used (signaled by an irq set in the vendor structure) | |
336 | * tpm.c can skip polling for the data to be available as the interrupt is | |
337 | * waited for here | |
338 | */ | |
9519de3f | 339 | static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len) |
27084efe LD |
340 | { |
341 | int rc, status, burstcnt; | |
342 | size_t count = 0; | |
27084efe LD |
343 | |
344 | if (request_locality(chip, 0) < 0) | |
345 | return -EBUSY; | |
346 | ||
347 | status = tpm_tis_status(chip); | |
348 | if ((status & TPM_STS_COMMAND_READY) == 0) { | |
349 | tpm_tis_ready(chip); | |
fd048866 | 350 | if (wait_for_tpm_stat |
27084efe | 351 | (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b, |
78f09cc2 | 352 | &chip->vendor.int_queue, false) < 0) { |
27084efe LD |
353 | rc = -ETIME; |
354 | goto out_err; | |
355 | } | |
356 | } | |
357 | ||
358 | while (count < len - 1) { | |
359 | burstcnt = get_burstcount(chip); | |
360 | for (; burstcnt > 0 && count < len - 1; burstcnt--) { | |
361 | iowrite8(buf[count], chip->vendor.iobase + | |
362 | TPM_DATA_FIFO(chip->vendor.locality)); | |
363 | count++; | |
364 | } | |
365 | ||
fd048866 | 366 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
78f09cc2 | 367 | &chip->vendor.int_queue, false); |
27084efe | 368 | status = tpm_tis_status(chip); |
3507d612 | 369 | if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) { |
27084efe LD |
370 | rc = -EIO; |
371 | goto out_err; | |
372 | } | |
373 | } | |
374 | ||
375 | /* write last byte */ | |
376 | iowrite8(buf[count], | |
9519de3f | 377 | chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality)); |
fd048866 | 378 | wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c, |
78f09cc2 | 379 | &chip->vendor.int_queue, false); |
27084efe LD |
380 | status = tpm_tis_status(chip); |
381 | if ((status & TPM_STS_DATA_EXPECT) != 0) { | |
382 | rc = -EIO; | |
383 | goto out_err; | |
384 | } | |
385 | ||
9519de3f SB |
386 | return 0; |
387 | ||
388 | out_err: | |
389 | tpm_tis_ready(chip); | |
390 | release_locality(chip, chip->vendor.locality, 0); | |
391 | return rc; | |
392 | } | |
393 | ||
448e9c55 SD |
394 | static void disable_interrupts(struct tpm_chip *chip) |
395 | { | |
396 | u32 intmask; | |
397 | ||
398 | intmask = | |
399 | ioread32(chip->vendor.iobase + | |
400 | TPM_INT_ENABLE(chip->vendor.locality)); | |
401 | intmask &= ~TPM_GLOBAL_INT_ENABLE; | |
402 | iowrite32(intmask, | |
403 | chip->vendor.iobase + | |
404 | TPM_INT_ENABLE(chip->vendor.locality)); | |
727f28b8 | 405 | devm_free_irq(chip->pdev, chip->vendor.irq, chip); |
448e9c55 SD |
406 | chip->vendor.irq = 0; |
407 | } | |
408 | ||
9519de3f SB |
409 | /* |
410 | * If interrupts are used (signaled by an irq set in the vendor structure) | |
411 | * tpm.c can skip polling for the data to be available as the interrupt is | |
412 | * waited for here | |
413 | */ | |
448e9c55 | 414 | static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len) |
9519de3f SB |
415 | { |
416 | int rc; | |
417 | u32 ordinal; | |
aec04cbd | 418 | unsigned long dur; |
9519de3f SB |
419 | |
420 | rc = tpm_tis_send_data(chip, buf, len); | |
421 | if (rc < 0) | |
422 | return rc; | |
423 | ||
27084efe LD |
424 | /* go and do it */ |
425 | iowrite8(TPM_STS_GO, | |
426 | chip->vendor.iobase + TPM_STS(chip->vendor.locality)); | |
427 | ||
428 | if (chip->vendor.irq) { | |
429 | ordinal = be32_to_cpu(*((__be32 *) (buf + 6))); | |
aec04cbd JS |
430 | |
431 | if (chip->flags & TPM_CHIP_FLAG_TPM2) | |
432 | dur = tpm2_calc_ordinal_duration(chip, ordinal); | |
433 | else | |
434 | dur = tpm_calc_ordinal_duration(chip, ordinal); | |
435 | ||
fd048866 | 436 | if (wait_for_tpm_stat |
aec04cbd | 437 | (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur, |
78f09cc2 | 438 | &chip->vendor.read_queue, false) < 0) { |
27084efe LD |
439 | rc = -ETIME; |
440 | goto out_err; | |
441 | } | |
442 | } | |
443 | return len; | |
444 | out_err: | |
445 | tpm_tis_ready(chip); | |
446 | release_locality(chip, chip->vendor.locality, 0); | |
447 | return rc; | |
448 | } | |
449 | ||
448e9c55 SD |
450 | static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len) |
451 | { | |
452 | int rc, irq; | |
453 | struct priv_data *priv = chip->vendor.priv; | |
454 | ||
455 | if (!chip->vendor.irq || priv->irq_tested) | |
456 | return tpm_tis_send_main(chip, buf, len); | |
457 | ||
458 | /* Verify receipt of the expected IRQ */ | |
459 | irq = chip->vendor.irq; | |
460 | chip->vendor.irq = 0; | |
461 | rc = tpm_tis_send_main(chip, buf, len); | |
462 | chip->vendor.irq = irq; | |
463 | if (!priv->irq_tested) | |
464 | msleep(1); | |
465 | if (!priv->irq_tested) { | |
466 | disable_interrupts(chip); | |
7ab4032f JG |
467 | if (!priv->irq_probing) |
468 | dev_err(chip->pdev, FW_BUG | |
469 | "TPM interrupt not working, polling instead\n"); | |
448e9c55 SD |
470 | } |
471 | priv->irq_tested = true; | |
472 | return rc; | |
473 | } | |
474 | ||
8e54caf4 JG |
475 | struct tis_vendor_timeout_override { |
476 | u32 did_vid; | |
477 | unsigned long timeout_us[4]; | |
478 | }; | |
479 | ||
480 | static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = { | |
481 | /* Atmel 3204 */ | |
482 | { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000), | |
483 | (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } }, | |
484 | }; | |
485 | ||
486 | static bool tpm_tis_update_timeouts(struct tpm_chip *chip, | |
487 | unsigned long *timeout_cap) | |
488 | { | |
489 | int i; | |
490 | u32 did_vid; | |
491 | ||
492 | did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0)); | |
493 | ||
494 | for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) { | |
495 | if (vendor_timeout_overrides[i].did_vid != did_vid) | |
496 | continue; | |
497 | memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us, | |
498 | sizeof(vendor_timeout_overrides[i].timeout_us)); | |
499 | return true; | |
500 | } | |
501 | ||
502 | return false; | |
503 | } | |
504 | ||
9519de3f SB |
505 | /* |
506 | * Early probing for iTPM with STS_DATA_EXPECT flaw. | |
507 | * Try sending command without itpm flag set and if that | |
508 | * fails, repeat with itpm flag set. | |
509 | */ | |
510 | static int probe_itpm(struct tpm_chip *chip) | |
511 | { | |
512 | int rc = 0; | |
513 | u8 cmd_getticks[] = { | |
514 | 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a, | |
515 | 0x00, 0x00, 0x00, 0xf1 | |
516 | }; | |
517 | size_t len = sizeof(cmd_getticks); | |
968de8e2 | 518 | bool rem_itpm = itpm; |
4e401fb0 SB |
519 | u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0)); |
520 | ||
521 | /* probe only iTPMS */ | |
522 | if (vendor != TPM_VID_INTEL) | |
523 | return 0; | |
9519de3f | 524 | |
73249695 | 525 | itpm = false; |
9519de3f SB |
526 | |
527 | rc = tpm_tis_send_data(chip, cmd_getticks, len); | |
528 | if (rc == 0) | |
529 | goto out; | |
530 | ||
531 | tpm_tis_ready(chip); | |
532 | release_locality(chip, chip->vendor.locality, 0); | |
533 | ||
73249695 | 534 | itpm = true; |
9519de3f SB |
535 | |
536 | rc = tpm_tis_send_data(chip, cmd_getticks, len); | |
537 | if (rc == 0) { | |
71ed848f | 538 | dev_info(chip->pdev, "Detected an iTPM.\n"); |
9519de3f SB |
539 | rc = 1; |
540 | } else | |
541 | rc = -EFAULT; | |
542 | ||
543 | out: | |
544 | itpm = rem_itpm; | |
545 | tpm_tis_ready(chip); | |
546 | release_locality(chip, chip->vendor.locality, 0); | |
547 | ||
548 | return rc; | |
549 | } | |
550 | ||
1f866057 SB |
551 | static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status) |
552 | { | |
553 | switch (chip->vendor.manufacturer_id) { | |
554 | case TPM_VID_WINBOND: | |
555 | return ((status == TPM_STS_VALID) || | |
556 | (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY))); | |
557 | case TPM_VID_STM: | |
558 | return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)); | |
559 | default: | |
560 | return (status == TPM_STS_COMMAND_READY); | |
561 | } | |
562 | } | |
563 | ||
01ad1fa7 | 564 | static const struct tpm_class_ops tpm_tis = { |
27084efe LD |
565 | .status = tpm_tis_status, |
566 | .recv = tpm_tis_recv, | |
567 | .send = tpm_tis_send, | |
568 | .cancel = tpm_tis_ready, | |
8e54caf4 | 569 | .update_timeouts = tpm_tis_update_timeouts, |
27084efe LD |
570 | .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID, |
571 | .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID, | |
1f866057 | 572 | .req_canceled = tpm_tis_req_canceled, |
27084efe LD |
573 | }; |
574 | ||
a6f97b29 | 575 | static irqreturn_t tis_int_handler(int dummy, void *dev_id) |
27084efe | 576 | { |
06efcad0 | 577 | struct tpm_chip *chip = dev_id; |
27084efe LD |
578 | u32 interrupt; |
579 | int i; | |
580 | ||
581 | interrupt = ioread32(chip->vendor.iobase + | |
582 | TPM_INT_STATUS(chip->vendor.locality)); | |
583 | ||
584 | if (interrupt == 0) | |
585 | return IRQ_NONE; | |
586 | ||
448e9c55 | 587 | ((struct priv_data *)chip->vendor.priv)->irq_tested = true; |
27084efe LD |
588 | if (interrupt & TPM_INTF_DATA_AVAIL_INT) |
589 | wake_up_interruptible(&chip->vendor.read_queue); | |
590 | if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT) | |
591 | for (i = 0; i < 5; i++) | |
592 | if (check_locality(chip, i) >= 0) | |
593 | break; | |
594 | if (interrupt & | |
595 | (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT | | |
596 | TPM_INTF_CMD_READY_INT)) | |
597 | wake_up_interruptible(&chip->vendor.int_queue); | |
598 | ||
599 | /* Clear interrupts handled with TPM_EOI */ | |
600 | iowrite32(interrupt, | |
601 | chip->vendor.iobase + | |
602 | TPM_INT_STATUS(chip->vendor.locality)); | |
cab091ea | 603 | ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality)); |
27084efe LD |
604 | return IRQ_HANDLED; |
605 | } | |
606 | ||
73249695 | 607 | static bool interrupts = true; |
57135568 KJH |
608 | module_param(interrupts, bool, 0444); |
609 | MODULE_PARM_DESC(interrupts, "Enable interrupts"); | |
610 | ||
afb5abc2 JS |
611 | static void tpm_tis_remove(struct tpm_chip *chip) |
612 | { | |
74d6b3ce JS |
613 | if (chip->flags & TPM_CHIP_FLAG_TPM2) |
614 | tpm2_shutdown(chip, TPM2_SU_CLEAR); | |
615 | ||
afb5abc2 JS |
616 | iowrite32(~TPM_GLOBAL_INT_ENABLE & |
617 | ioread32(chip->vendor.iobase + | |
618 | TPM_INT_ENABLE(chip->vendor. | |
619 | locality)), | |
620 | chip->vendor.iobase + | |
621 | TPM_INT_ENABLE(chip->vendor.locality)); | |
622 | release_locality(chip, chip->vendor.locality, 1); | |
623 | } | |
624 | ||
399235dc JS |
625 | static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info, |
626 | acpi_handle acpi_dev_handle) | |
27084efe LD |
627 | { |
628 | u32 vendor, intfcaps, intmask; | |
968de8e2 | 629 | int rc, i, irq_s, irq_e, probe; |
14b5c1c9 | 630 | int irq_r = -1; |
27084efe | 631 | struct tpm_chip *chip; |
448e9c55 | 632 | struct priv_data *priv; |
27084efe | 633 | |
448e9c55 SD |
634 | priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL); |
635 | if (priv == NULL) | |
636 | return -ENOMEM; | |
afb5abc2 JS |
637 | |
638 | chip = tpmm_chip_alloc(dev, &tpm_tis); | |
639 | if (IS_ERR(chip)) | |
640 | return PTR_ERR(chip); | |
641 | ||
448e9c55 | 642 | chip->vendor.priv = priv; |
aec04cbd | 643 | #ifdef CONFIG_ACPI |
0dc55365 | 644 | chip->acpi_dev_handle = acpi_dev_handle; |
aec04cbd | 645 | #endif |
27084efe | 646 | |
399235dc | 647 | chip->vendor.iobase = devm_ioremap(dev, tpm_info->start, tpm_info->len); |
afb5abc2 JS |
648 | if (!chip->vendor.iobase) |
649 | return -EIO; | |
27084efe | 650 | |
aec04cbd JS |
651 | /* Maximum timeouts */ |
652 | chip->vendor.timeout_a = TIS_TIMEOUT_A_MAX; | |
653 | chip->vendor.timeout_b = TIS_TIMEOUT_B_MAX; | |
654 | chip->vendor.timeout_c = TIS_TIMEOUT_C_MAX; | |
655 | chip->vendor.timeout_d = TIS_TIMEOUT_D_MAX; | |
ec579358 | 656 | |
7240b983 JG |
657 | if (wait_startup(chip, 0) != 0) { |
658 | rc = -ENODEV; | |
659 | goto out_err; | |
660 | } | |
661 | ||
036bb38f JG |
662 | /* Take control of the TPM's interrupt hardware and shut it off */ |
663 | intmask = ioread32(chip->vendor.iobase + | |
664 | TPM_INT_ENABLE(chip->vendor.locality)); | |
665 | intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT | | |
666 | TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT; | |
667 | intmask &= ~TPM_GLOBAL_INT_ENABLE; | |
668 | iowrite32(intmask, | |
669 | chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality)); | |
670 | ||
05a462af MS |
671 | if (request_locality(chip, 0) != 0) { |
672 | rc = -ENODEV; | |
673 | goto out_err; | |
674 | } | |
675 | ||
4d5f2051 JS |
676 | rc = tpm2_probe(chip); |
677 | if (rc) | |
678 | goto out_err; | |
aec04cbd | 679 | |
27084efe | 680 | vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0)); |
3e3a5e90 | 681 | chip->vendor.manufacturer_id = vendor; |
27084efe | 682 | |
aec04cbd JS |
683 | dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n", |
684 | (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2", | |
27084efe LD |
685 | vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0))); |
686 | ||
9519de3f | 687 | if (!itpm) { |
968de8e2 SB |
688 | probe = probe_itpm(chip); |
689 | if (probe < 0) { | |
9519de3f SB |
690 | rc = -ENODEV; |
691 | goto out_err; | |
692 | } | |
73249695 | 693 | itpm = !!probe; |
9519de3f SB |
694 | } |
695 | ||
3507d612 RA |
696 | if (itpm) |
697 | dev_info(dev, "Intel iTPM workaround enabled\n"); | |
698 | ||
699 | ||
27084efe LD |
700 | /* Figure out the capabilities */ |
701 | intfcaps = | |
702 | ioread32(chip->vendor.iobase + | |
703 | TPM_INTF_CAPS(chip->vendor.locality)); | |
9e323d3e | 704 | dev_dbg(dev, "TPM interface capabilities (0x%x):\n", |
27084efe LD |
705 | intfcaps); |
706 | if (intfcaps & TPM_INTF_BURST_COUNT_STATIC) | |
9e323d3e | 707 | dev_dbg(dev, "\tBurst Count Static\n"); |
27084efe | 708 | if (intfcaps & TPM_INTF_CMD_READY_INT) |
9e323d3e | 709 | dev_dbg(dev, "\tCommand Ready Int Support\n"); |
27084efe | 710 | if (intfcaps & TPM_INTF_INT_EDGE_FALLING) |
9e323d3e | 711 | dev_dbg(dev, "\tInterrupt Edge Falling\n"); |
27084efe | 712 | if (intfcaps & TPM_INTF_INT_EDGE_RISING) |
9e323d3e | 713 | dev_dbg(dev, "\tInterrupt Edge Rising\n"); |
27084efe | 714 | if (intfcaps & TPM_INTF_INT_LEVEL_LOW) |
9e323d3e | 715 | dev_dbg(dev, "\tInterrupt Level Low\n"); |
27084efe | 716 | if (intfcaps & TPM_INTF_INT_LEVEL_HIGH) |
9e323d3e | 717 | dev_dbg(dev, "\tInterrupt Level High\n"); |
27084efe | 718 | if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT) |
9e323d3e | 719 | dev_dbg(dev, "\tLocality Change Int Support\n"); |
27084efe | 720 | if (intfcaps & TPM_INTF_STS_VALID_INT) |
9e323d3e | 721 | dev_dbg(dev, "\tSts Valid Int Support\n"); |
27084efe | 722 | if (intfcaps & TPM_INTF_DATA_AVAIL_INT) |
9e323d3e | 723 | dev_dbg(dev, "\tData Avail Int Support\n"); |
27084efe | 724 | |
25112048 JG |
725 | /* Very early on issue a command to the TPM in polling mode to make |
726 | * sure it works. May as well use that command to set the proper | |
727 | * timeouts for the driver. | |
728 | */ | |
729 | if (tpm_get_timeouts(chip)) { | |
730 | dev_err(dev, "Could not get TPM timeouts and durations\n"); | |
731 | rc = -ENODEV; | |
732 | goto out_err; | |
733 | } | |
734 | ||
27084efe LD |
735 | /* INTERRUPT Setup */ |
736 | init_waitqueue_head(&chip->vendor.read_queue); | |
737 | init_waitqueue_head(&chip->vendor.int_queue); | |
738 | ||
7917ff9a | 739 | if (interrupts) |
399235dc | 740 | chip->vendor.irq = tpm_info->irq; |
7917ff9a | 741 | if (interrupts && !chip->vendor.irq) { |
a7b66822 | 742 | irq_s = |
57135568 KJH |
743 | ioread8(chip->vendor.iobase + |
744 | TPM_INT_VECTOR(chip->vendor.locality)); | |
14b5c1c9 | 745 | irq_r = irq_s; |
a7b66822 SB |
746 | if (irq_s) { |
747 | irq_e = irq_s; | |
748 | } else { | |
749 | irq_s = 3; | |
750 | irq_e = 15; | |
751 | } | |
57135568 | 752 | |
a7b66822 | 753 | for (i = irq_s; i <= irq_e && chip->vendor.irq == 0; i++) { |
57135568 | 754 | iowrite8(i, chip->vendor.iobase + |
a7b66822 | 755 | TPM_INT_VECTOR(chip->vendor.locality)); |
afb5abc2 | 756 | if (devm_request_irq |
7ab4032f | 757 | (dev, i, tis_int_handler, IRQF_SHARED, |
313d21ee | 758 | chip->devname, chip) != 0) { |
71ed848f | 759 | dev_info(chip->pdev, |
57135568 KJH |
760 | "Unable to request irq: %d for probe\n", |
761 | i); | |
762 | continue; | |
763 | } | |
7ab4032f | 764 | chip->vendor.irq = i; |
27084efe | 765 | |
57135568 KJH |
766 | /* Clear all existing */ |
767 | iowrite32(ioread32 | |
768 | (chip->vendor.iobase + | |
769 | TPM_INT_STATUS(chip->vendor.locality)), | |
770 | chip->vendor.iobase + | |
771 | TPM_INT_STATUS(chip->vendor.locality)); | |
772 | ||
773 | /* Turn on */ | |
774 | iowrite32(intmask | TPM_GLOBAL_INT_ENABLE, | |
775 | chip->vendor.iobase + | |
776 | TPM_INT_ENABLE(chip->vendor.locality)); | |
777 | ||
7ab4032f JG |
778 | priv->irq_tested = false; |
779 | priv->irq_probing = true; | |
a7b66822 | 780 | |
57135568 | 781 | /* Generate Interrupts */ |
aec04cbd | 782 | if (chip->flags & TPM_CHIP_FLAG_TPM2) |
4d5f2051 | 783 | tpm2_gen_interrupt(chip); |
aec04cbd JS |
784 | else |
785 | tpm_gen_interrupt(chip); | |
57135568 | 786 | |
7ab4032f | 787 | priv->irq_probing = false; |
2aef9da6 | 788 | |
7ab4032f JG |
789 | /* tpm_tis_send will either confirm the interrupt is |
790 | * working or it will call disable_irq which undoes | |
791 | * all of the above. | |
792 | */ | |
793 | if (chip->vendor.irq) | |
794 | break; | |
27084efe | 795 | } |
7ab4032f JG |
796 | if (!chip->vendor.irq) |
797 | iowrite8(irq_r, chip->vendor.iobase + | |
798 | TPM_INT_VECTOR(chip->vendor.locality)); | |
27084efe | 799 | } |
7ab4032f | 800 | if (chip->vendor.irq && !priv->irq_tested) { |
27084efe LD |
801 | iowrite8(chip->vendor.irq, |
802 | chip->vendor.iobase + | |
803 | TPM_INT_VECTOR(chip->vendor.locality)); | |
afb5abc2 JS |
804 | if (devm_request_irq |
805 | (dev, chip->vendor.irq, tis_int_handler, IRQF_SHARED, | |
313d21ee | 806 | chip->devname, chip) != 0) { |
71ed848f | 807 | dev_info(chip->pdev, |
57135568 KJH |
808 | "Unable to request irq: %d for use\n", |
809 | chip->vendor.irq); | |
27084efe LD |
810 | chip->vendor.irq = 0; |
811 | } else { | |
812 | /* Clear all existing */ | |
813 | iowrite32(ioread32 | |
814 | (chip->vendor.iobase + | |
815 | TPM_INT_STATUS(chip->vendor.locality)), | |
816 | chip->vendor.iobase + | |
817 | TPM_INT_STATUS(chip->vendor.locality)); | |
818 | ||
819 | /* Turn on */ | |
820 | iowrite32(intmask | TPM_GLOBAL_INT_ENABLE, | |
821 | chip->vendor.iobase + | |
822 | TPM_INT_ENABLE(chip->vendor.locality)); | |
823 | } | |
7ab4032f | 824 | } |
27084efe | 825 | |
25112048 JG |
826 | if (tpm_get_timeouts(chip)) { |
827 | dev_err(dev, "Could not get TPM timeouts and durations\n"); | |
828 | rc = -ENODEV; | |
829 | goto out_err; | |
830 | } | |
aec04cbd | 831 | |
25112048 | 832 | if (chip->flags & TPM_CHIP_FLAG_TPM2) { |
aec04cbd JS |
833 | rc = tpm2_do_selftest(chip); |
834 | if (rc == TPM2_RC_INITIALIZE) { | |
835 | dev_warn(dev, "Firmware has not started TPM\n"); | |
836 | rc = tpm2_startup(chip, TPM2_SU_CLEAR); | |
837 | if (!rc) | |
838 | rc = tpm2_do_selftest(chip); | |
839 | } | |
448e9c55 | 840 | |
aec04cbd JS |
841 | if (rc) { |
842 | dev_err(dev, "TPM self test failed\n"); | |
843 | if (rc > 0) | |
844 | rc = -ENODEV; | |
845 | goto out_err; | |
846 | } | |
847 | } else { | |
aec04cbd JS |
848 | if (tpm_do_selftest(chip)) { |
849 | dev_err(dev, "TPM self test failed\n"); | |
850 | rc = -ENODEV; | |
851 | goto out_err; | |
852 | } | |
448e9c55 SD |
853 | } |
854 | ||
afb5abc2 | 855 | return tpm_chip_register(chip); |
27084efe | 856 | out_err: |
afb5abc2 | 857 | tpm_tis_remove(chip); |
27084efe LD |
858 | return rc; |
859 | } | |
96854310 | 860 | |
19b94d2d | 861 | #ifdef CONFIG_PM_SLEEP |
96854310 SB |
862 | static void tpm_tis_reenable_interrupts(struct tpm_chip *chip) |
863 | { | |
864 | u32 intmask; | |
865 | ||
866 | /* reenable interrupts that device may have lost or | |
867 | BIOS/firmware may have disabled */ | |
868 | iowrite8(chip->vendor.irq, chip->vendor.iobase + | |
869 | TPM_INT_VECTOR(chip->vendor.locality)); | |
870 | ||
871 | intmask = | |
872 | ioread32(chip->vendor.iobase + | |
873 | TPM_INT_ENABLE(chip->vendor.locality)); | |
874 | ||
875 | intmask |= TPM_INTF_CMD_READY_INT | |
876 | | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT | |
877 | | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE; | |
878 | ||
879 | iowrite32(intmask, | |
880 | chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality)); | |
881 | } | |
96854310 | 882 | |
a2fa3fb0 SK |
883 | static int tpm_tis_resume(struct device *dev) |
884 | { | |
885 | struct tpm_chip *chip = dev_get_drvdata(dev); | |
74d6b3ce | 886 | int ret; |
a2fa3fb0 SK |
887 | |
888 | if (chip->vendor.irq) | |
889 | tpm_tis_reenable_interrupts(chip); | |
890 | ||
74d6b3ce JS |
891 | ret = tpm_pm_resume(dev); |
892 | if (ret) | |
893 | return ret; | |
aec04cbd | 894 | |
74d6b3ce JS |
895 | /* TPM 1.2 requires self-test on resume. This function actually returns |
896 | * an error code but for unknown reason it isn't handled. | |
897 | */ | |
898 | if (!(chip->flags & TPM_CHIP_FLAG_TPM2)) | |
899 | tpm_do_selftest(chip); | |
a2fa3fb0 | 900 | |
74d6b3ce | 901 | return 0; |
a2fa3fb0 SK |
902 | } |
903 | #endif | |
904 | ||
905 | static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume); | |
906 | ||
7f2ab000 | 907 | #ifdef CONFIG_PNP |
afc6d369 | 908 | static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev, |
9e323d3e KJH |
909 | const struct pnp_device_id *pnp_id) |
910 | { | |
399235dc | 911 | struct tpm_info tpm_info = tis_default_info; |
0dc55365 | 912 | acpi_handle acpi_dev_handle = NULL; |
7917ff9a | 913 | |
399235dc JS |
914 | tpm_info.start = pnp_mem_start(pnp_dev, 0); |
915 | tpm_info.len = pnp_mem_len(pnp_dev, 0); | |
9e323d3e | 916 | |
7917ff9a | 917 | if (pnp_irq_valid(pnp_dev, 0)) |
399235dc | 918 | tpm_info.irq = pnp_irq(pnp_dev, 0); |
7917ff9a | 919 | else |
73249695 | 920 | interrupts = false; |
7917ff9a | 921 | |
961be7ef | 922 | #ifdef CONFIG_ACPI |
399235dc JS |
923 | if (pnp_acpi_device(pnp_dev)) { |
924 | if (is_itpm(pnp_acpi_device(pnp_dev))) | |
925 | itpm = true; | |
926 | ||
0dc55365 | 927 | acpi_dev_handle = pnp_acpi_device(pnp_dev)->handle; |
399235dc | 928 | } |
961be7ef | 929 | #endif |
0dc55365 | 930 | |
399235dc | 931 | return tpm_tis_init(&pnp_dev->dev, &tpm_info, acpi_dev_handle); |
9e323d3e KJH |
932 | } |
933 | ||
0bbed20e | 934 | static struct pnp_device_id tpm_pnp_tbl[] = { |
27084efe | 935 | {"PNP0C31", 0}, /* TPM */ |
93e1b7d4 KJH |
936 | {"ATM1200", 0}, /* Atmel */ |
937 | {"IFX0102", 0}, /* Infineon */ | |
938 | {"BCM0101", 0}, /* Broadcom */ | |
061991ec | 939 | {"BCM0102", 0}, /* Broadcom */ |
93e1b7d4 | 940 | {"NSC1200", 0}, /* National */ |
fb0e7e11 | 941 | {"ICO0102", 0}, /* Intel */ |
93e1b7d4 KJH |
942 | /* Add new here */ |
943 | {"", 0}, /* User Specified */ | |
944 | {"", 0} /* Terminator */ | |
27084efe | 945 | }; |
31bde71c | 946 | MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl); |
27084efe | 947 | |
39af33fc | 948 | static void tpm_tis_pnp_remove(struct pnp_dev *dev) |
253115b7 RA |
949 | { |
950 | struct tpm_chip *chip = pnp_get_drvdata(dev); | |
399235dc | 951 | |
afb5abc2 JS |
952 | tpm_chip_unregister(chip); |
953 | tpm_tis_remove(chip); | |
253115b7 RA |
954 | } |
955 | ||
27084efe LD |
956 | static struct pnp_driver tis_pnp_driver = { |
957 | .name = "tpm_tis", | |
958 | .id_table = tpm_pnp_tbl, | |
959 | .probe = tpm_tis_pnp_init, | |
253115b7 | 960 | .remove = tpm_tis_pnp_remove, |
a2fa3fb0 SK |
961 | .driver = { |
962 | .pm = &tpm_tis_pm, | |
963 | }, | |
27084efe LD |
964 | }; |
965 | ||
93e1b7d4 KJH |
966 | #define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2 |
967 | module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id, | |
968 | sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444); | |
969 | MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe"); | |
7f2ab000 | 970 | #endif |
7a192ec3 | 971 | |
399235dc JS |
972 | #ifdef CONFIG_ACPI |
973 | static int tpm_check_resource(struct acpi_resource *ares, void *data) | |
974 | { | |
975 | struct tpm_info *tpm_info = (struct tpm_info *) data; | |
976 | struct resource res; | |
977 | ||
978 | if (acpi_dev_resource_interrupt(ares, 0, &res)) { | |
979 | tpm_info->irq = res.start; | |
980 | } else if (acpi_dev_resource_memory(ares, &res)) { | |
981 | tpm_info->start = res.start; | |
982 | tpm_info->len = resource_size(&res); | |
983 | } | |
984 | ||
985 | return 1; | |
986 | } | |
987 | ||
988 | static int tpm_tis_acpi_init(struct acpi_device *acpi_dev) | |
989 | { | |
990 | struct list_head resources; | |
991 | struct tpm_info tpm_info = tis_default_info; | |
992 | int ret; | |
993 | ||
994 | if (!is_fifo(acpi_dev)) | |
995 | return -ENODEV; | |
996 | ||
997 | INIT_LIST_HEAD(&resources); | |
998 | ret = acpi_dev_get_resources(acpi_dev, &resources, tpm_check_resource, | |
999 | &tpm_info); | |
1000 | if (ret < 0) | |
1001 | return ret; | |
1002 | ||
1003 | acpi_dev_free_resource_list(&resources); | |
1004 | ||
1005 | if (!tpm_info.irq) | |
1006 | interrupts = false; | |
1007 | ||
1008 | if (is_itpm(acpi_dev)) | |
1009 | itpm = true; | |
1010 | ||
1011 | return tpm_tis_init(&acpi_dev->dev, &tpm_info, acpi_dev->handle); | |
1012 | } | |
1013 | ||
1014 | static int tpm_tis_acpi_remove(struct acpi_device *dev) | |
1015 | { | |
1016 | struct tpm_chip *chip = dev_get_drvdata(&dev->dev); | |
1017 | ||
1018 | tpm_chip_unregister(chip); | |
1019 | tpm_tis_remove(chip); | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
1024 | static struct acpi_device_id tpm_acpi_tbl[] = { | |
1025 | {"MSFT0101", 0}, /* TPM 2.0 */ | |
1026 | /* Add new here */ | |
1027 | {"", 0}, /* User Specified */ | |
1028 | {"", 0} /* Terminator */ | |
1029 | }; | |
1030 | MODULE_DEVICE_TABLE(acpi, tpm_acpi_tbl); | |
1031 | ||
1032 | static struct acpi_driver tis_acpi_driver = { | |
1033 | .name = "tpm_tis", | |
1034 | .ids = tpm_acpi_tbl, | |
1035 | .ops = { | |
1036 | .add = tpm_tis_acpi_init, | |
1037 | .remove = tpm_tis_acpi_remove, | |
1038 | }, | |
1039 | .drv = { | |
1040 | .pm = &tpm_tis_pm, | |
1041 | }, | |
1042 | }; | |
1043 | #endif | |
1044 | ||
7a192ec3 ML |
1045 | static struct platform_driver tis_drv = { |
1046 | .driver = { | |
afb5abc2 | 1047 | .name = "tpm_tis", |
b633f050 | 1048 | .pm = &tpm_tis_pm, |
7a192ec3 | 1049 | }, |
9e323d3e KJH |
1050 | }; |
1051 | ||
1052 | static struct platform_device *pdev; | |
1053 | ||
90ab5ee9 | 1054 | static bool force; |
9e323d3e KJH |
1055 | module_param(force, bool, 0444); |
1056 | MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry"); | |
27084efe LD |
1057 | static int __init init_tis(void) |
1058 | { | |
9e323d3e | 1059 | int rc; |
7f2ab000 | 1060 | #ifdef CONFIG_PNP |
399235dc JS |
1061 | if (!force) { |
1062 | rc = pnp_register_driver(&tis_pnp_driver); | |
1063 | if (rc) | |
1064 | return rc; | |
1065 | } | |
1066 | #endif | |
1067 | #ifdef CONFIG_ACPI | |
1068 | if (!force) { | |
1069 | rc = acpi_bus_register_driver(&tis_acpi_driver); | |
1070 | if (rc) { | |
1071 | #ifdef CONFIG_PNP | |
1072 | pnp_unregister_driver(&tis_pnp_driver); | |
7f2ab000 | 1073 | #endif |
399235dc JS |
1074 | return rc; |
1075 | } | |
1076 | } | |
1077 | #endif | |
1078 | if (!force) | |
1079 | return 0; | |
9e323d3e | 1080 | |
7f2ab000 RA |
1081 | rc = platform_driver_register(&tis_drv); |
1082 | if (rc < 0) | |
9e323d3e | 1083 | return rc; |
4fba3c3b WY |
1084 | pdev = platform_device_register_simple("tpm_tis", -1, NULL, 0); |
1085 | if (IS_ERR(pdev)) { | |
1086 | rc = PTR_ERR(pdev); | |
1087 | goto err_dev; | |
9e323d3e | 1088 | } |
399235dc | 1089 | rc = tpm_tis_init(&pdev->dev, &tis_default_info, NULL); |
4fba3c3b WY |
1090 | if (rc) |
1091 | goto err_init; | |
1092 | return 0; | |
1093 | err_init: | |
1094 | platform_device_unregister(pdev); | |
1095 | err_dev: | |
1096 | platform_driver_unregister(&tis_drv); | |
7f2ab000 | 1097 | return rc; |
27084efe LD |
1098 | } |
1099 | ||
1100 | static void __exit cleanup_tis(void) | |
1101 | { | |
27084efe | 1102 | struct tpm_chip *chip; |
399235dc | 1103 | #if defined(CONFIG_PNP) || defined(CONFIG_ACPI) |
7f2ab000 | 1104 | if (!force) { |
399235dc JS |
1105 | #ifdef CONFIG_ACPI |
1106 | acpi_bus_unregister_driver(&tis_acpi_driver); | |
1107 | #endif | |
1108 | #ifdef CONFIG_PNP | |
9e323d3e | 1109 | pnp_unregister_driver(&tis_pnp_driver); |
399235dc | 1110 | #endif |
7f2ab000 RA |
1111 | return; |
1112 | } | |
1113 | #endif | |
afb5abc2 JS |
1114 | chip = dev_get_drvdata(&pdev->dev); |
1115 | tpm_chip_unregister(chip); | |
1116 | tpm_tis_remove(chip); | |
7f2ab000 RA |
1117 | platform_device_unregister(pdev); |
1118 | platform_driver_unregister(&tis_drv); | |
27084efe LD |
1119 | } |
1120 | ||
1121 | module_init(init_tis); | |
1122 | module_exit(cleanup_tis); | |
1123 | MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); | |
1124 | MODULE_DESCRIPTION("TPM Driver"); | |
1125 | MODULE_VERSION("2.0"); | |
1126 | MODULE_LICENSE("GPL"); |