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[WATCHDOG] sc1200wdt.c pnp unregister fix.
[deliverable/linux.git] / drivers / char / watchdog / iTCO_wdt.c
CommitLineData
9e0ea345
WVS		 1/*
2 * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
3 *
4 * (c) Copyright 2006 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * 82801AA (ICH) : document number 290655-003, 290677-014,
18 * 82801AB (ICHO) : document number 290655-003, 290677-014,
19 * 82801BA (ICH2) : document number 290687-002, 298242-027,
20 * 82801BAM (ICH2-M) : document number 290687-002, 298242-027,
21 * 82801CA (ICH3-S) : document number 290733-003, 290739-013,
22 * 82801CAM (ICH3-M) : document number 290716-001, 290718-007,
23 * 82801DB (ICH4) : document number 290744-001, 290745-020,
24 * 82801DBM (ICH4-M) : document number 252337-001, 252663-005,
25 * 82801E (C-ICH) : document number 273599-001, 273645-002,
26 * 82801EB (ICH5) : document number 252516-001, 252517-003,
27 * 82801ER (ICH5R) : document number 252516-001, 252517-003,
28 * 82801FB (ICH6) : document number 301473-002, 301474-007,
29 * 82801FR (ICH6R) : document number 301473-002, 301474-007,
30 * 82801FBM (ICH6-M) : document number 301473-002, 301474-007,
31 * 82801FW (ICH6W) : document number 301473-001, 301474-007,
32 * 82801FRW (ICH6RW) : document number 301473-001, 301474-007,
33 * 82801GB (ICH7) : document number 307013-002, 307014-009,
34 * 82801GR (ICH7R) : document number 307013-002, 307014-009,
35 * 82801GDH (ICH7DH) : document number 307013-002, 307014-009,
36 * 82801GBM (ICH7-M) : document number 307013-002, 307014-009,
37 * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009,
a8edd74e
WVS		 38 * 82801HB (ICH8) : document number 313056-002, 313057-004,
39 * 82801HR (ICH8R) : document number 313056-002, 313057-004,
40 * 82801HH (ICH8DH) : document number 313056-002, 313057-004,
41 * 82801HO (ICH8DO) : document number 313056-002, 313057-004,
9e0ea345
WVS		 42 * 6300ESB (6300ESB) : document number 300641-003
43 */
44
45/*
46 * Includes, defines, variables, module parameters, ...
47 */
48
49/* Module and version information */
50#define DRV_NAME "iTCO_wdt"
51#define DRV_VERSION "1.00"
a8edd74e 52#define DRV_RELDATE "08-Oct-2006"
9e0ea345
WVS		 53#define PFX DRV_NAME ": "
54
55/* Includes */
3836cc0f
WVS		 56#include <linux/module.h> /* For module specific items */
57#include <linux/moduleparam.h> /* For new moduleparam's */
58#include <linux/types.h> /* For standard types (like size_t) */
59#include <linux/errno.h> /* For the -ENODEV/... values */
60#include <linux/kernel.h> /* For printk/panic/... */
61#include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */
62#include <linux/watchdog.h> /* For the watchdog specific items */
3836cc0f
WVS		 63#include <linux/init.h> /* For __init/__exit/... */
64#include <linux/fs.h> /* For file operations */
65#include <linux/platform_device.h> /* For platform_driver framework */
66#include <linux/pci.h> /* For pci functions */
67#include <linux/ioport.h> /* For io-port access */
68#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
69
70#include <asm/uaccess.h> /* For copy_to_user/put_user/... */
71#include <asm/io.h> /* For inb/outb/... */
9e0ea345
WVS		 72
73/* TCO related info */
74enum iTCO_chipsets {
75 TCO_ICH = 0, /* ICH */
76 TCO_ICH0, /* ICH0 */
77 TCO_ICH2, /* ICH2 */
78 TCO_ICH2M, /* ICH2-M */
79 TCO_ICH3, /* ICH3-S */
80 TCO_ICH3M, /* ICH3-M */
81 TCO_ICH4, /* ICH4 */
82 TCO_ICH4M, /* ICH4-M */
83 TCO_CICH, /* C-ICH */
84 TCO_ICH5, /* ICH5 & ICH5R */
85 TCO_6300ESB, /* 6300ESB */
86 TCO_ICH6, /* ICH6 & ICH6R */
87 TCO_ICH6M, /* ICH6-M */
88 TCO_ICH6W, /* ICH6W & ICH6RW */
89 TCO_ICH7, /* ICH7 & ICH7R */
90 TCO_ICH7M, /* ICH7-M */
91 TCO_ICH7MDH, /* ICH7-M DH */
a8edd74e
WVS		 92 TCO_ICH8, /* ICH8 & ICH8R */
93 TCO_ICH8DH, /* ICH8DH */
94 TCO_ICH8DO, /* ICH8DO */
9e0ea345
WVS		 95};
96
97static struct {
98 char *name;
99 unsigned int iTCO_version;
100} iTCO_chipset_info[] __devinitdata = {
101 {"ICH", 1},
102 {"ICH0", 1},
103 {"ICH2", 1},
104 {"ICH2-M", 1},
105 {"ICH3-S", 1},
106 {"ICH3-M", 1},
107 {"ICH4", 1},
108 {"ICH4-M", 1},
109 {"C-ICH", 1},
110 {"ICH5 or ICH5R", 1},
111 {"6300ESB", 1},
112 {"ICH6 or ICH6R", 2},
113 {"ICH6-M", 2},
114 {"ICH6W or ICH6RW", 2},
115 {"ICH7 or ICH7R", 2},
116 {"ICH7-M", 2},
117 {"ICH7-M DH", 2},
bcbf25bd 118 {"ICH8 or ICH8R", 2},
a8edd74e
WVS		 119 {"ICH8DH", 2},
120 {"ICH8DO", 2},
9e0ea345
WVS		 121 {NULL,0}
122};
123
124/*
125 * This data only exists for exporting the supported PCI ids
126 * via MODULE_DEVICE_TABLE. We do not actually register a
127 * pci_driver, because the I/O Controller Hub has also other
128 * functions that probably will be registered by other drivers.
129 */
130static struct pci_device_id iTCO_wdt_pci_tbl[] = {
131 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH },
132 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH0 },
133 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH2 },
134 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH2M },
135 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH3 },
136 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH3M },
137 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH4 },
138 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH4M },
139 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_CICH },
140 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH5 },
141 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_6300ESB },
142 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6 },
143 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6M },
144 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH6W },
145 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7 },
146 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7M },
147 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH7MDH },
bcbf25bd 148 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8 },
a8edd74e
WVS		 149 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8DH },
150 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, TCO_ICH8DO },
9e0ea345
WVS		 151 { 0, }, /* End of list */
152};
153MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl);
154
155/* Address definitions for the TCO */
156#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */
157#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */
158
159#define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */
160#define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
161#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
162#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
163#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
164#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
165#define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
166#define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
167#define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
168
169/* internal variables */
170static unsigned long is_active;
171static char expect_release;
172static struct { /* this is private data for the iTCO_wdt device */
173 unsigned int iTCO_version; /* TCO version/generation */
174 unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
175 unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */
176 spinlock_t io_lock; /* the lock for io operations */
177 struct pci_dev *pdev; /* the PCI-device */
178} iTCO_wdt_private;
179
3836cc0f
WVS		 180static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */
181
9e0ea345
WVS		 182/* module parameters */
183#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
184static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
185module_param(heartbeat, int, 0);
186MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
187
188static int nowayout = WATCHDOG_NOWAYOUT;
189module_param(nowayout, int, 0);
190MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=CONFIG_WATCHDOG_NOWAYOUT)");
191
192/*
193 * Some TCO specific functions
194 */
195
196static inline unsigned int seconds_to_ticks(int seconds)
197{
198 /* the internal timer is stored as ticks which decrement
199 * every 0.6 seconds */
200 return (seconds * 10) / 6;
201}
202
203static void iTCO_wdt_set_NO_REBOOT_bit(void)
204{
205 u32 val32;
206
207 /* Set the NO_REBOOT bit: this disables reboots */
208 if (iTCO_wdt_private.iTCO_version == 2) {
209 val32 = readl(iTCO_wdt_private.gcs);
210 val32 |= 0x00000020;
211 writel(val32, iTCO_wdt_private.gcs);
212 } else if (iTCO_wdt_private.iTCO_version == 1) {
213 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
214 val32 |= 0x00000002;
215 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
216 }
217}
218
219static int iTCO_wdt_unset_NO_REBOOT_bit(void)
220{
221 int ret = 0;
222 u32 val32;
223
224 /* Unset the NO_REBOOT bit: this enables reboots */
225 if (iTCO_wdt_private.iTCO_version == 2) {
226 val32 = readl(iTCO_wdt_private.gcs);
227 val32 &= 0xffffffdf;
228 writel(val32, iTCO_wdt_private.gcs);
229
230 val32 = readl(iTCO_wdt_private.gcs);
231 if (val32 & 0x00000020)
232 ret = -EIO;
233 } else if (iTCO_wdt_private.iTCO_version == 1) {
234 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
235 val32 &= 0xfffffffd;
236 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
237
238 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
239 if (val32 & 0x00000002)
240 ret = -EIO;
241 }
242
243 return ret; /* returns: 0 = OK, -EIO = Error */
244}
245
246static int iTCO_wdt_start(void)
247{
248 unsigned int val;
249
250 spin_lock(&iTCO_wdt_private.io_lock);
251
252 /* disable chipset's NO_REBOOT bit */
253 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
254 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
255 return -EIO;
256 }
257
258 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
259 val = inw(TCO1_CNT);
260 val &= 0xf7ff;
261 outw(val, TCO1_CNT);
262 val = inw(TCO1_CNT);
263 spin_unlock(&iTCO_wdt_private.io_lock);
264
265 if (val & 0x0800)
266 return -1;
267 return 0;
268}
269
270static int iTCO_wdt_stop(void)
271{
272 unsigned int val;
273
274 spin_lock(&iTCO_wdt_private.io_lock);
275
276 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
277 val = inw(TCO1_CNT);
278 val |= 0x0800;
279 outw(val, TCO1_CNT);
280 val = inw(TCO1_CNT);
281
282 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
283 iTCO_wdt_set_NO_REBOOT_bit();
284
285 spin_unlock(&iTCO_wdt_private.io_lock);
286
287 if ((val & 0x0800) == 0)
288 return -1;
289 return 0;
290}
291
292static int iTCO_wdt_keepalive(void)
293{
294 spin_lock(&iTCO_wdt_private.io_lock);
295
296 /* Reload the timer by writing to the TCO Timer Counter register */
297 if (iTCO_wdt_private.iTCO_version == 2) {
298 outw(0x01, TCO_RLD);
299 } else if (iTCO_wdt_private.iTCO_version == 1) {
300 outb(0x01, TCO_RLD);
301 }
302
303 spin_unlock(&iTCO_wdt_private.io_lock);
304 return 0;
305}
306
307static int iTCO_wdt_set_heartbeat(int t)
308{
309 unsigned int val16;
310 unsigned char val8;
311 unsigned int tmrval;
312
313 tmrval = seconds_to_ticks(t);
314 /* from the specs: */
315 /* "Values of 0h-3h are ignored and should not be attempted" */
316 if (tmrval < 0x04)
317 return -EINVAL;
318 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
319 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
320 return -EINVAL;
321
322 /* Write new heartbeat to watchdog */
323 if (iTCO_wdt_private.iTCO_version == 2) {
324 spin_lock(&iTCO_wdt_private.io_lock);
325 val16 = inw(TCOv2_TMR);
326 val16 &= 0xfc00;
327 val16 |= tmrval;
328 outw(val16, TCOv2_TMR);
329 val16 = inw(TCOv2_TMR);
330 spin_unlock(&iTCO_wdt_private.io_lock);
331
332 if ((val16 & 0x3ff) != tmrval)
333 return -EINVAL;
334 } else if (iTCO_wdt_private.iTCO_version == 1) {
335 spin_lock(&iTCO_wdt_private.io_lock);
336 val8 = inb(TCOv1_TMR);
337 val8 &= 0xc0;
338 val8 |= (tmrval & 0xff);
339 outb(val8, TCOv1_TMR);
340 val8 = inb(TCOv1_TMR);
341 spin_unlock(&iTCO_wdt_private.io_lock);
342
343 if ((val8 & 0x3f) != tmrval)
344 return -EINVAL;
345 }
346
347 heartbeat = t;
348 return 0;
349}
350
351static int iTCO_wdt_get_timeleft (int *time_left)
352{
353 unsigned int val16;
354 unsigned char val8;
355
356 /* read the TCO Timer */
357 if (iTCO_wdt_private.iTCO_version == 2) {
358 spin_lock(&iTCO_wdt_private.io_lock);
359 val16 = inw(TCO_RLD);
360 val16 &= 0x3ff;
361 spin_unlock(&iTCO_wdt_private.io_lock);
362
363 *time_left = (val16 * 6) / 10;
364 } else if (iTCO_wdt_private.iTCO_version == 1) {
365 spin_lock(&iTCO_wdt_private.io_lock);
366 val8 = inb(TCO_RLD);
367 val8 &= 0x3f;
368 spin_unlock(&iTCO_wdt_private.io_lock);
369
370 *time_left = (val8 * 6) / 10;
80060362
JG		 371 } else
372 return -EINVAL;
9e0ea345
WVS		 373 return 0;
374}
375
376/*
377 * /dev/watchdog handling
378 */
379
380static int iTCO_wdt_open (struct inode *inode, struct file *file)
381{
382 /* /dev/watchdog can only be opened once */
383 if (test_and_set_bit(0, &is_active))
384 return -EBUSY;
385
386 /*
387 * Reload and activate timer
388 */
389 iTCO_wdt_keepalive();
390 iTCO_wdt_start();
391 return nonseekable_open(inode, file);
392}
393
394static int iTCO_wdt_release (struct inode *inode, struct file *file)
395{
396 /*
397 * Shut off the timer.
398 */
399 if (expect_release == 42) {
400 iTCO_wdt_stop();
401 } else {
402 printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n");
403 iTCO_wdt_keepalive();
404 }
405 clear_bit(0, &is_active);
406 expect_release = 0;
407 return 0;
408}
409
410static ssize_t iTCO_wdt_write (struct file *file, const char __user *data,
411 size_t len, loff_t * ppos)
412{
413 /* See if we got the magic character 'V' and reload the timer */
414 if (len) {
415 if (!nowayout) {
416 size_t i;
417
418 /* note: just in case someone wrote the magic character
419 * five months ago... */
420 expect_release = 0;
421
422 /* scan to see whether or not we got the magic character */
423 for (i = 0; i != len; i++) {
424 char c;
425 if (get_user(c, data+i))
426 return -EFAULT;
427 if (c == 'V')
428 expect_release = 42;
429 }
430 }
431
432 /* someone wrote to us, we should reload the timer */
433 iTCO_wdt_keepalive();
434 }
435 return len;
436}
437
438static int iTCO_wdt_ioctl (struct inode *inode, struct file *file,
439 unsigned int cmd, unsigned long arg)
440{
441 int new_options, retval = -EINVAL;
442 int new_heartbeat;
9e0ea345
WVS		 443 void __user *argp = (void __user *)arg;
444 int __user *p = argp;
445 static struct watchdog_info ident = {
446 .options = WDIOF_SETTIMEOUT |
447 WDIOF_KEEPALIVEPING |
448 WDIOF_MAGICCLOSE,
449 .firmware_version = 0,
450 .identity = DRV_NAME,
451 };
452
453 switch (cmd) {
454 case WDIOC_GETSUPPORT:
455 return copy_to_user(argp, &ident,
456 sizeof (ident)) ? -EFAULT : 0;
457
458 case WDIOC_GETSTATUS:
459 case WDIOC_GETBOOTSTATUS:
460 return put_user(0, p);
461
462 case WDIOC_KEEPALIVE:
463 iTCO_wdt_keepalive();
464 return 0;
465
466 case WDIOC_SETOPTIONS:
467 {
468 if (get_user(new_options, p))
469 return -EFAULT;
470
471 if (new_options & WDIOS_DISABLECARD) {
472 iTCO_wdt_stop();
473 retval = 0;
474 }
475
476 if (new_options & WDIOS_ENABLECARD) {
477 iTCO_wdt_keepalive();
478 iTCO_wdt_start();
479 retval = 0;
480 }
481
482 return retval;
483 }
484
485 case WDIOC_SETTIMEOUT:
486 {
487 if (get_user(new_heartbeat, p))
488 return -EFAULT;
489
490 if (iTCO_wdt_set_heartbeat(new_heartbeat))
491 return -EINVAL;
492
493 iTCO_wdt_keepalive();
494 /* Fall */
495 }
496
497 case WDIOC_GETTIMEOUT:
498 return put_user(heartbeat, p);
499
500 case WDIOC_GETTIMELEFT:
501 {
80060362
JG		 502 int time_left;
503
9e0ea345
WVS		 504 if (iTCO_wdt_get_timeleft(&time_left))
505 return -EINVAL;
506
507 return put_user(time_left, p);
508 }
509
510 default:
f311896a 511 return -ENOTTY;
9e0ea345
WVS		 512 }
513}
514
9e0ea345
WVS		 515/*
516 * Kernel Interfaces
517 */
518
519static struct file_operations iTCO_wdt_fops = {
520 .owner = THIS_MODULE,
521 .llseek = no_llseek,
522 .write = iTCO_wdt_write,
523 .ioctl = iTCO_wdt_ioctl,
524 .open = iTCO_wdt_open,
525 .release = iTCO_wdt_release,
526};
527
528static struct miscdevice iTCO_wdt_miscdev = {
529 .minor = WATCHDOG_MINOR,
530 .name = "watchdog",
531 .fops = &iTCO_wdt_fops,
532};
533
9e0ea345
WVS		 534/*
535 * Init & exit routines
536 */
537
3836cc0f 538static int iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device_id *ent, struct platform_device *dev)
9e0ea345
WVS		 539{
540 int ret;
541 u32 base_address;
542 unsigned long RCBA;
543 unsigned long val32;
544
545 /*
546 * Find the ACPI/PM base I/O address which is the base
547 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
548 * ACPIBASE is bits [15:7] from 0x40-0x43
549 */
550 pci_read_config_dword(pdev, 0x40, &base_address);
551 base_address &= 0x00007f80;
552 if (base_address == 0x00000000) {
553 /* Something's wrong here, ACPIBASE has to be set */
554 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
4802c653 555 pci_dev_put(pdev);
9e0ea345
WVS		 556 return -ENODEV;
557 }
558 iTCO_wdt_private.iTCO_version = iTCO_chipset_info[ent->driver_data].iTCO_version;
559 iTCO_wdt_private.ACPIBASE = base_address;
560 iTCO_wdt_private.pdev = pdev;
561
562 /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */
563 /* To get access to it you have to read RCBA from PCI Config space 0xf0
564 and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */
565 if (iTCO_wdt_private.iTCO_version == 2) {
566 pci_read_config_dword(pdev, 0xf0, &base_address);
567 RCBA = base_address & 0xffffc000;
568 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4);
569 }
570
571 /* Check chipset's NO_REBOOT bit */
572 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
573 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
574 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
575 goto out;
576 }
577
578 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
579 iTCO_wdt_set_NO_REBOOT_bit();
580
581 /* Set the TCO_EN bit in SMI_EN register */
582 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
583 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
584 SMI_EN );
585 ret = -EIO;
586 goto out;
587 }
588 val32 = inl(SMI_EN);
589 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
590 outl(val32, SMI_EN);
591 release_region(SMI_EN, 4);
592
593 /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */
594 if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) {
595 printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n",
596 TCOBASE);
597 ret = -EIO;
598 goto out;
599 }
600
601 printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
602 iTCO_chipset_info[ent->driver_data].name,
603 iTCO_chipset_info[ent->driver_data].iTCO_version,
604 TCOBASE);
605
606 /* Clear out the (probably old) status */
607 outb(0, TCO1_STS);
608 outb(3, TCO2_STS);
609
610 /* Make sure the watchdog is not running */
611 iTCO_wdt_stop();
612
613 /* Check that the heartbeat value is within it's range ; if not reset to the default */
614 if (iTCO_wdt_set_heartbeat(heartbeat)) {
615 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
616 printk(KERN_INFO PFX "heartbeat value must be 2<heartbeat<39 (TCO v1) or 613 (TCO v2), using %d\n",
617 heartbeat);
618 }
619
9e0ea345
WVS		 620 ret = misc_register(&iTCO_wdt_miscdev);
621 if (ret != 0) {
622 printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n",
623 WATCHDOG_MINOR, ret);
1bef84be 624 goto unreg_region;
9e0ea345
WVS		 625 }
626
627 printk (KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
628 heartbeat, nowayout);
629
630 return 0;
631
9e0ea345
WVS		 632unreg_region:
633 release_region (TCOBASE, 0x20);
634out:
635 if (iTCO_wdt_private.iTCO_version == 2)
636 iounmap(iTCO_wdt_private.gcs);
4802c653 637 pci_dev_put(iTCO_wdt_private.pdev);
1bef84be 638 iTCO_wdt_private.ACPIBASE = 0;
9e0ea345
WVS		 639 return ret;
640}
641
3836cc0f 642static void iTCO_wdt_cleanup(void)
9e0ea345
WVS		 643{
644 /* Stop the timer before we leave */
645 if (!nowayout)
646 iTCO_wdt_stop();
647
648 /* Deregister */
649 misc_deregister(&iTCO_wdt_miscdev);
9e0ea345
WVS		 650 release_region(TCOBASE, 0x20);
651 if (iTCO_wdt_private.iTCO_version == 2)
652 iounmap(iTCO_wdt_private.gcs);
4802c653 653 pci_dev_put(iTCO_wdt_private.pdev);
1bef84be 654 iTCO_wdt_private.ACPIBASE = 0;
9e0ea345
WVS		 655}
656
3836cc0f 657static int iTCO_wdt_probe(struct platform_device *dev)
9e0ea345
WVS		 658{
659 int found = 0;
660 struct pci_dev *pdev = NULL;
661 const struct pci_device_id *ent;
662
663 spin_lock_init(&iTCO_wdt_private.io_lock);
664
665 for_each_pci_dev(pdev) {
666 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
667 if (ent) {
3836cc0f 668 if (!(iTCO_wdt_init(pdev, ent, dev))) {
9e0ea345
WVS		 669 found++;
670 break;
671 }
672 }
673 }
674
675 if (!found) {
676 printk(KERN_INFO PFX "No card detected\n");
677 return -ENODEV;
678 }
679
680 return 0;
681}
682
3836cc0f 683static int iTCO_wdt_remove(struct platform_device *dev)
9e0ea345
WVS		 684{
685 if (iTCO_wdt_private.ACPIBASE)
686 iTCO_wdt_cleanup();
687
3836cc0f
WVS		 688 return 0;
689}
690
691static void iTCO_wdt_shutdown(struct platform_device *dev)
692{
693 iTCO_wdt_stop();
694}
695
696#define iTCO_wdt_suspend NULL
697#define iTCO_wdt_resume NULL
698
699static struct platform_driver iTCO_wdt_driver = {
700 .probe = iTCO_wdt_probe,
701 .remove = iTCO_wdt_remove,
702 .shutdown = iTCO_wdt_shutdown,
703 .suspend = iTCO_wdt_suspend,
704 .resume = iTCO_wdt_resume,
705 .driver = {
706 .owner = THIS_MODULE,
707 .name = DRV_NAME,
708 },
709};
710
711static int __init iTCO_wdt_init_module(void)
712{
713 int err;
714
715 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n",
716 DRV_VERSION, DRV_RELDATE);
717
718 err = platform_driver_register(&iTCO_wdt_driver);
719 if (err)
720 return err;
721
722 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0);
723 if (IS_ERR(iTCO_wdt_platform_device)) {
724 err = PTR_ERR(iTCO_wdt_platform_device);
725 goto unreg_platform_driver;
726 }
727
728 return 0;
729
730unreg_platform_driver:
731 platform_driver_unregister(&iTCO_wdt_driver);
732 return err;
733}
734
735static void __exit iTCO_wdt_cleanup_module(void)
736{
737 platform_device_unregister(iTCO_wdt_platform_device);
738 platform_driver_unregister(&iTCO_wdt_driver);
9e0ea345
WVS		 739 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
740}
741
742module_init(iTCO_wdt_init_module);
743module_exit(iTCO_wdt_cleanup_module);
744
745MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
746MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
3836cc0f 747MODULE_VERSION(DRV_VERSION);
9e0ea345
WVS		 748MODULE_LICENSE("GPL");
749MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Linux kernel - Deliverables
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