Commit | Line | Data |
---|---|---|
19fbbbbc ML |
1 | /* |
2 | * Driver for TI Dual PLL CDCE925 clock synthesizer | |
3 | * | |
4 | * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1 | |
5 | * and Y4/Y5 to PLL2. PLL frequency is set on a first-come-first-serve | |
6 | * basis. Clients can directly request any frequency that the chip can | |
7 | * deliver using the standard clk framework. In addition, the device can | |
8 | * be configured and activated via the devicetree. | |
9 | * | |
10 | * Copyright (C) 2014, Topic Embedded Products | |
11 | * Licenced under GPL | |
12 | */ | |
a826a1a4 | 13 | #include <linux/clk.h> |
19fbbbbc ML |
14 | #include <linux/clk-provider.h> |
15 | #include <linux/delay.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/regmap.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/gcd.h> | |
21 | ||
22 | /* The chip has 2 PLLs which can be routed through dividers to 5 outputs. | |
23 | * Model this as 2 PLL clocks which are parents to the outputs. | |
24 | */ | |
25 | #define NUMBER_OF_PLLS 2 | |
26 | #define NUMBER_OF_OUTPUTS 5 | |
27 | ||
28 | #define CDCE925_REG_GLOBAL1 0x01 | |
29 | #define CDCE925_REG_Y1SPIPDIVH 0x02 | |
30 | #define CDCE925_REG_PDIVL 0x03 | |
31 | #define CDCE925_REG_XCSEL 0x05 | |
32 | /* PLL parameters start at 0x10, steps of 0x10 */ | |
33 | #define CDCE925_OFFSET_PLL 0x10 | |
34 | /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ | |
35 | #define CDCE925_PLL_MUX_OUTPUTS 0x14 | |
36 | #define CDCE925_PLL_MULDIV 0x18 | |
37 | ||
38 | #define CDCE925_PLL_FREQUENCY_MIN 80000000ul | |
39 | #define CDCE925_PLL_FREQUENCY_MAX 230000000ul | |
40 | struct clk_cdce925_chip; | |
41 | ||
42 | struct clk_cdce925_output { | |
43 | struct clk_hw hw; | |
44 | struct clk_cdce925_chip *chip; | |
45 | u8 index; | |
46 | u16 pdiv; /* 1..127 for Y2-Y5; 1..1023 for Y1 */ | |
47 | }; | |
48 | #define to_clk_cdce925_output(_hw) \ | |
49 | container_of(_hw, struct clk_cdce925_output, hw) | |
50 | ||
51 | struct clk_cdce925_pll { | |
52 | struct clk_hw hw; | |
53 | struct clk_cdce925_chip *chip; | |
54 | u8 index; | |
55 | u16 m; /* 1..511 */ | |
56 | u16 n; /* 1..4095 */ | |
57 | }; | |
58 | #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw) | |
59 | ||
60 | struct clk_cdce925_chip { | |
61 | struct regmap *regmap; | |
62 | struct i2c_client *i2c_client; | |
63 | struct clk_cdce925_pll pll[NUMBER_OF_PLLS]; | |
64 | struct clk_cdce925_output clk[NUMBER_OF_OUTPUTS]; | |
19fbbbbc ML |
65 | }; |
66 | ||
67 | /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ | |
68 | ||
69 | static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, | |
70 | u16 n, u16 m) | |
71 | { | |
72 | if ((!m || !n) || (m == n)) | |
73 | return parent_rate; /* In bypass mode runs at same frequency */ | |
74 | return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); | |
75 | } | |
76 | ||
77 | static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, | |
78 | unsigned long parent_rate) | |
79 | { | |
80 | /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */ | |
81 | struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); | |
82 | ||
83 | return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); | |
84 | } | |
85 | ||
86 | static void cdce925_pll_find_rate(unsigned long rate, | |
87 | unsigned long parent_rate, u16 *n, u16 *m) | |
88 | { | |
89 | unsigned long un; | |
90 | unsigned long um; | |
91 | unsigned long g; | |
92 | ||
93 | if (rate <= parent_rate) { | |
94 | /* Can always deliver parent_rate in bypass mode */ | |
95 | rate = parent_rate; | |
96 | *n = 0; | |
97 | *m = 0; | |
98 | } else { | |
99 | /* In PLL mode, need to apply min/max range */ | |
100 | if (rate < CDCE925_PLL_FREQUENCY_MIN) | |
101 | rate = CDCE925_PLL_FREQUENCY_MIN; | |
102 | else if (rate > CDCE925_PLL_FREQUENCY_MAX) | |
103 | rate = CDCE925_PLL_FREQUENCY_MAX; | |
104 | ||
105 | g = gcd(rate, parent_rate); | |
106 | um = parent_rate / g; | |
107 | un = rate / g; | |
108 | /* When outside hw range, reduce to fit (rounding errors) */ | |
109 | while ((un > 4095) || (um > 511)) { | |
110 | un >>= 1; | |
111 | um >>= 1; | |
112 | } | |
113 | if (un == 0) | |
114 | un = 1; | |
115 | if (um == 0) | |
116 | um = 1; | |
117 | ||
118 | *n = un; | |
119 | *m = um; | |
120 | } | |
121 | } | |
122 | ||
123 | static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
124 | unsigned long *parent_rate) | |
125 | { | |
126 | u16 n, m; | |
127 | ||
128 | cdce925_pll_find_rate(rate, *parent_rate, &n, &m); | |
129 | return (long)cdce925_pll_calculate_rate(*parent_rate, n, m); | |
130 | } | |
131 | ||
132 | static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, | |
133 | unsigned long parent_rate) | |
134 | { | |
135 | struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); | |
136 | ||
137 | if (!rate || (rate == parent_rate)) { | |
138 | data->m = 0; /* Bypass mode */ | |
139 | data->n = 0; | |
140 | return 0; | |
141 | } | |
142 | ||
143 | if ((rate < CDCE925_PLL_FREQUENCY_MIN) || | |
144 | (rate > CDCE925_PLL_FREQUENCY_MAX)) { | |
145 | pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate); | |
146 | return -EINVAL; | |
147 | } | |
148 | ||
149 | if (rate < parent_rate) { | |
150 | pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__, | |
151 | rate, parent_rate); | |
152 | return -EINVAL; | |
153 | } | |
154 | ||
155 | cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); | |
156 | return 0; | |
157 | } | |
158 | ||
159 | ||
160 | /* calculate p = max(0, 4 - int(log2 (n/m))) */ | |
161 | static u8 cdce925_pll_calc_p(u16 n, u16 m) | |
162 | { | |
163 | u8 p; | |
164 | u16 r = n / m; | |
165 | ||
166 | if (r >= 16) | |
167 | return 0; | |
168 | p = 4; | |
169 | while (r > 1) { | |
170 | r >>= 1; | |
171 | --p; | |
172 | } | |
173 | return p; | |
174 | } | |
175 | ||
176 | /* Returns VCO range bits for VCO1_0_RANGE */ | |
177 | static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) | |
178 | { | |
179 | struct clk *parent = clk_get_parent(hw->clk); | |
180 | unsigned long rate = clk_get_rate(parent); | |
181 | ||
182 | rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); | |
183 | if (rate >= 175000000) | |
184 | return 0x3; | |
185 | if (rate >= 150000000) | |
186 | return 0x02; | |
187 | if (rate >= 125000000) | |
188 | return 0x01; | |
189 | return 0x00; | |
190 | } | |
191 | ||
192 | /* I2C clock, hence everything must happen in (un)prepare because this | |
193 | * may sleep */ | |
194 | static int cdce925_pll_prepare(struct clk_hw *hw) | |
195 | { | |
196 | struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); | |
197 | u16 n = data->n; | |
198 | u16 m = data->m; | |
199 | u16 r; | |
200 | u8 q; | |
201 | u8 p; | |
202 | u16 nn; | |
203 | u8 pll[4]; /* Bits are spread out over 4 byte registers */ | |
204 | u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; | |
205 | unsigned i; | |
206 | ||
207 | if ((!m || !n) || (m == n)) { | |
208 | /* Set PLL mux to bypass mode, leave the rest as is */ | |
209 | regmap_update_bits(data->chip->regmap, | |
210 | reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); | |
211 | } else { | |
212 | /* According to data sheet: */ | |
213 | /* p = max(0, 4 - int(log2 (n/m))) */ | |
214 | p = cdce925_pll_calc_p(n, m); | |
215 | /* nn = n * 2^p */ | |
216 | nn = n * BIT(p); | |
217 | /* q = int(nn/m) */ | |
218 | q = nn / m; | |
219 | if ((q < 16) || (1 > 64)) { | |
220 | pr_debug("%s invalid q=%d\n", __func__, q); | |
221 | return -EINVAL; | |
222 | } | |
223 | r = nn - (m*q); | |
224 | if (r > 511) { | |
225 | pr_debug("%s invalid r=%d\n", __func__, r); | |
226 | return -EINVAL; | |
227 | } | |
228 | pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__, | |
229 | n, m, p, q, r); | |
230 | /* encode into register bits */ | |
231 | pll[0] = n >> 4; | |
232 | pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); | |
233 | pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); | |
234 | pll[3] = ((q & 0x07) << 5) | (p << 2) | | |
235 | cdce925_pll_calc_range_bits(hw, n, m); | |
236 | /* Write to registers */ | |
237 | for (i = 0; i < ARRAY_SIZE(pll); ++i) | |
238 | regmap_write(data->chip->regmap, | |
239 | reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); | |
240 | /* Enable PLL */ | |
241 | regmap_update_bits(data->chip->regmap, | |
242 | reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); | |
243 | } | |
244 | ||
245 | return 0; | |
246 | } | |
247 | ||
248 | static void cdce925_pll_unprepare(struct clk_hw *hw) | |
249 | { | |
250 | struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); | |
251 | u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; | |
252 | ||
253 | regmap_update_bits(data->chip->regmap, | |
254 | reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); | |
255 | } | |
256 | ||
257 | static const struct clk_ops cdce925_pll_ops = { | |
258 | .prepare = cdce925_pll_prepare, | |
259 | .unprepare = cdce925_pll_unprepare, | |
260 | .recalc_rate = cdce925_pll_recalc_rate, | |
261 | .round_rate = cdce925_pll_round_rate, | |
262 | .set_rate = cdce925_pll_set_rate, | |
263 | }; | |
264 | ||
265 | ||
266 | static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) | |
267 | { | |
268 | switch (data->index) { | |
269 | case 0: | |
270 | regmap_update_bits(data->chip->regmap, | |
271 | CDCE925_REG_Y1SPIPDIVH, | |
272 | 0x03, (pdiv >> 8) & 0x03); | |
273 | regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); | |
274 | break; | |
275 | case 1: | |
276 | regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); | |
277 | break; | |
278 | case 2: | |
279 | regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); | |
280 | break; | |
281 | case 3: | |
282 | regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); | |
283 | break; | |
284 | case 4: | |
285 | regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); | |
286 | break; | |
287 | } | |
288 | } | |
289 | ||
290 | static void cdce925_clk_activate(struct clk_cdce925_output *data) | |
291 | { | |
292 | switch (data->index) { | |
293 | case 0: | |
294 | regmap_update_bits(data->chip->regmap, | |
295 | CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c); | |
296 | break; | |
297 | case 1: | |
298 | case 2: | |
299 | regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); | |
300 | break; | |
301 | case 3: | |
302 | case 4: | |
303 | regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); | |
304 | break; | |
305 | } | |
306 | } | |
307 | ||
308 | static int cdce925_clk_prepare(struct clk_hw *hw) | |
309 | { | |
310 | struct clk_cdce925_output *data = to_clk_cdce925_output(hw); | |
311 | ||
312 | cdce925_clk_set_pdiv(data, data->pdiv); | |
313 | cdce925_clk_activate(data); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static void cdce925_clk_unprepare(struct clk_hw *hw) | |
318 | { | |
319 | struct clk_cdce925_output *data = to_clk_cdce925_output(hw); | |
320 | ||
321 | /* Disable clock by setting divider to "0" */ | |
322 | cdce925_clk_set_pdiv(data, 0); | |
323 | } | |
324 | ||
325 | static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, | |
326 | unsigned long parent_rate) | |
327 | { | |
328 | struct clk_cdce925_output *data = to_clk_cdce925_output(hw); | |
329 | ||
330 | if (data->pdiv) | |
331 | return parent_rate / data->pdiv; | |
332 | return 0; | |
333 | } | |
334 | ||
335 | static u16 cdce925_calc_divider(unsigned long rate, | |
336 | unsigned long parent_rate) | |
337 | { | |
338 | unsigned long divider; | |
339 | ||
340 | if (!rate) | |
341 | return 0; | |
342 | if (rate >= parent_rate) | |
343 | return 1; | |
344 | ||
345 | divider = DIV_ROUND_CLOSEST(parent_rate, rate); | |
346 | if (divider > 0x7F) | |
347 | divider = 0x7F; | |
348 | ||
349 | return (u16)divider; | |
350 | } | |
351 | ||
352 | static unsigned long cdce925_clk_best_parent_rate( | |
353 | struct clk_hw *hw, unsigned long rate) | |
354 | { | |
355 | struct clk *pll = clk_get_parent(hw->clk); | |
356 | struct clk *root = clk_get_parent(pll); | |
357 | unsigned long root_rate = clk_get_rate(root); | |
358 | unsigned long best_rate_error = rate; | |
359 | u16 pdiv_min; | |
360 | u16 pdiv_max; | |
361 | u16 pdiv_best; | |
362 | u16 pdiv_now; | |
363 | ||
364 | if (root_rate % rate == 0) | |
365 | return root_rate; /* Don't need the PLL, use bypass */ | |
366 | ||
367 | pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate)); | |
368 | pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate); | |
369 | ||
370 | if (pdiv_min > pdiv_max) | |
371 | return 0; /* No can do? */ | |
372 | ||
373 | pdiv_best = pdiv_min; | |
374 | for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) { | |
375 | unsigned long target_rate = rate * pdiv_now; | |
376 | long pll_rate = clk_round_rate(pll, target_rate); | |
377 | unsigned long actual_rate; | |
378 | unsigned long rate_error; | |
379 | ||
380 | if (pll_rate <= 0) | |
381 | continue; | |
382 | actual_rate = pll_rate / pdiv_now; | |
383 | rate_error = abs((long)actual_rate - (long)rate); | |
384 | if (rate_error < best_rate_error) { | |
385 | pdiv_best = pdiv_now; | |
386 | best_rate_error = rate_error; | |
387 | } | |
388 | /* TODO: Consider PLL frequency based on smaller n/m values | |
389 | * and pick the better one if the error is equal */ | |
390 | } | |
391 | ||
392 | return rate * pdiv_best; | |
393 | } | |
394 | ||
395 | static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
396 | unsigned long *parent_rate) | |
397 | { | |
398 | unsigned long l_parent_rate = *parent_rate; | |
399 | u16 divider = cdce925_calc_divider(rate, l_parent_rate); | |
400 | ||
401 | if (l_parent_rate / divider != rate) { | |
402 | l_parent_rate = cdce925_clk_best_parent_rate(hw, rate); | |
403 | divider = cdce925_calc_divider(rate, l_parent_rate); | |
404 | *parent_rate = l_parent_rate; | |
405 | } | |
406 | ||
407 | if (divider) | |
408 | return (long)(l_parent_rate / divider); | |
409 | return 0; | |
410 | } | |
411 | ||
412 | static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, | |
413 | unsigned long parent_rate) | |
414 | { | |
415 | struct clk_cdce925_output *data = to_clk_cdce925_output(hw); | |
416 | ||
417 | data->pdiv = cdce925_calc_divider(rate, parent_rate); | |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | static const struct clk_ops cdce925_clk_ops = { | |
423 | .prepare = cdce925_clk_prepare, | |
424 | .unprepare = cdce925_clk_unprepare, | |
425 | .recalc_rate = cdce925_clk_recalc_rate, | |
426 | .round_rate = cdce925_clk_round_rate, | |
427 | .set_rate = cdce925_clk_set_rate, | |
428 | }; | |
429 | ||
430 | ||
431 | static u16 cdce925_y1_calc_divider(unsigned long rate, | |
432 | unsigned long parent_rate) | |
433 | { | |
434 | unsigned long divider; | |
435 | ||
436 | if (!rate) | |
437 | return 0; | |
438 | if (rate >= parent_rate) | |
439 | return 1; | |
440 | ||
441 | divider = DIV_ROUND_CLOSEST(parent_rate, rate); | |
442 | if (divider > 0x3FF) /* Y1 has 10-bit divider */ | |
443 | divider = 0x3FF; | |
444 | ||
445 | return (u16)divider; | |
446 | } | |
447 | ||
448 | static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, | |
449 | unsigned long *parent_rate) | |
450 | { | |
451 | unsigned long l_parent_rate = *parent_rate; | |
452 | u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); | |
453 | ||
454 | if (divider) | |
455 | return (long)(l_parent_rate / divider); | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, | |
460 | unsigned long parent_rate) | |
461 | { | |
462 | struct clk_cdce925_output *data = to_clk_cdce925_output(hw); | |
463 | ||
464 | data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | static const struct clk_ops cdce925_clk_y1_ops = { | |
470 | .prepare = cdce925_clk_prepare, | |
471 | .unprepare = cdce925_clk_unprepare, | |
472 | .recalc_rate = cdce925_clk_recalc_rate, | |
473 | .round_rate = cdce925_clk_y1_round_rate, | |
474 | .set_rate = cdce925_clk_y1_set_rate, | |
475 | }; | |
476 | ||
477 | ||
478 | static struct regmap_config cdce925_regmap_config = { | |
479 | .name = "configuration0", | |
480 | .reg_bits = 8, | |
481 | .val_bits = 8, | |
482 | .cache_type = REGCACHE_RBTREE, | |
483 | .max_register = 0x2F, | |
484 | }; | |
485 | ||
486 | #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 | |
487 | #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 | |
488 | ||
489 | static int cdce925_regmap_i2c_write( | |
490 | void *context, const void *data, size_t count) | |
491 | { | |
492 | struct device *dev = context; | |
493 | struct i2c_client *i2c = to_i2c_client(dev); | |
494 | int ret; | |
495 | u8 reg_data[2]; | |
496 | ||
497 | if (count != 2) | |
498 | return -ENOTSUPP; | |
499 | ||
500 | /* First byte is command code */ | |
501 | reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; | |
502 | reg_data[1] = ((u8 *)data)[1]; | |
503 | ||
504 | dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, | |
505 | reg_data[0], reg_data[1]); | |
506 | ||
507 | ret = i2c_master_send(i2c, reg_data, count); | |
508 | if (likely(ret == count)) | |
509 | return 0; | |
510 | else if (ret < 0) | |
511 | return ret; | |
512 | else | |
513 | return -EIO; | |
514 | } | |
515 | ||
516 | static int cdce925_regmap_i2c_read(void *context, | |
517 | const void *reg, size_t reg_size, void *val, size_t val_size) | |
518 | { | |
519 | struct device *dev = context; | |
520 | struct i2c_client *i2c = to_i2c_client(dev); | |
521 | struct i2c_msg xfer[2]; | |
522 | int ret; | |
523 | u8 reg_data[2]; | |
524 | ||
525 | if (reg_size != 1) | |
526 | return -ENOTSUPP; | |
527 | ||
528 | xfer[0].addr = i2c->addr; | |
529 | xfer[0].flags = 0; | |
530 | xfer[0].buf = reg_data; | |
531 | if (val_size == 1) { | |
532 | reg_data[0] = | |
533 | CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; | |
534 | xfer[0].len = 1; | |
535 | } else { | |
536 | reg_data[0] = | |
537 | CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; | |
538 | reg_data[1] = val_size; | |
539 | xfer[0].len = 2; | |
540 | } | |
541 | ||
542 | xfer[1].addr = i2c->addr; | |
543 | xfer[1].flags = I2C_M_RD; | |
544 | xfer[1].len = val_size; | |
545 | xfer[1].buf = val; | |
546 | ||
547 | ret = i2c_transfer(i2c->adapter, xfer, 2); | |
548 | if (likely(ret == 2)) { | |
b41c7bfa | 549 | dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, |
19fbbbbc ML |
550 | reg_size, val_size, reg_data[0], *((u8 *)val)); |
551 | return 0; | |
552 | } else if (ret < 0) | |
553 | return ret; | |
554 | else | |
555 | return -EIO; | |
556 | } | |
557 | ||
a85d1171 SB |
558 | static struct clk_hw * |
559 | of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data) | |
560 | { | |
561 | struct clk_cdce925_chip *data = _data; | |
562 | unsigned int idx = clkspec->args[0]; | |
563 | ||
564 | if (idx >= ARRAY_SIZE(data->clk)) { | |
565 | pr_err("%s: invalid index %u\n", __func__, idx); | |
566 | return ERR_PTR(-EINVAL); | |
567 | } | |
568 | ||
569 | return &data->clk[idx].hw; | |
570 | } | |
571 | ||
19fbbbbc ML |
572 | /* The CDCE925 uses a funky way to read/write registers. Bulk mode is |
573 | * just weird, so just use the single byte mode exclusively. */ | |
574 | static struct regmap_bus regmap_cdce925_bus = { | |
575 | .write = cdce925_regmap_i2c_write, | |
576 | .read = cdce925_regmap_i2c_read, | |
577 | }; | |
578 | ||
579 | static int cdce925_probe(struct i2c_client *client, | |
580 | const struct i2c_device_id *id) | |
581 | { | |
582 | struct clk_cdce925_chip *data; | |
583 | struct device_node *node = client->dev.of_node; | |
584 | const char *parent_name; | |
585 | const char *pll_clk_name[NUMBER_OF_PLLS] = {NULL,}; | |
586 | struct clk_init_data init; | |
19fbbbbc ML |
587 | u32 value; |
588 | int i; | |
589 | int err; | |
590 | struct device_node *np_output; | |
591 | char child_name[6]; | |
592 | ||
593 | dev_dbg(&client->dev, "%s\n", __func__); | |
594 | data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); | |
595 | if (!data) | |
596 | return -ENOMEM; | |
597 | ||
598 | data->i2c_client = client; | |
599 | data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, | |
600 | &client->dev, &cdce925_regmap_config); | |
601 | if (IS_ERR(data->regmap)) { | |
602 | dev_err(&client->dev, "failed to allocate register map\n"); | |
603 | return PTR_ERR(data->regmap); | |
604 | } | |
605 | i2c_set_clientdata(client, data); | |
606 | ||
607 | parent_name = of_clk_get_parent_name(node, 0); | |
608 | if (!parent_name) { | |
609 | dev_err(&client->dev, "missing parent clock\n"); | |
610 | return -ENODEV; | |
611 | } | |
612 | dev_dbg(&client->dev, "parent is: %s\n", parent_name); | |
613 | ||
614 | if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) | |
615 | regmap_write(data->regmap, | |
616 | CDCE925_REG_XCSEL, (value << 3) & 0xF8); | |
617 | /* PWDN bit */ | |
618 | regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); | |
619 | ||
620 | /* Set input source for Y1 to be the XTAL */ | |
621 | regmap_update_bits(data->regmap, 0x02, BIT(7), 0); | |
622 | ||
623 | init.ops = &cdce925_pll_ops; | |
624 | init.flags = 0; | |
625 | init.parent_names = &parent_name; | |
626 | init.num_parents = parent_name ? 1 : 0; | |
627 | ||
628 | /* Register PLL clocks */ | |
629 | for (i = 0; i < NUMBER_OF_PLLS; ++i) { | |
630 | pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d", | |
631 | client->dev.of_node->name, i); | |
632 | init.name = pll_clk_name[i]; | |
633 | data->pll[i].chip = data; | |
634 | data->pll[i].hw.init = &init; | |
635 | data->pll[i].index = i; | |
a85d1171 SB |
636 | err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); |
637 | if (err) { | |
19fbbbbc | 638 | dev_err(&client->dev, "Failed register PLL %d\n", i); |
19fbbbbc ML |
639 | goto error; |
640 | } | |
641 | sprintf(child_name, "PLL%d", i+1); | |
642 | np_output = of_get_child_by_name(node, child_name); | |
643 | if (!np_output) | |
644 | continue; | |
645 | if (!of_property_read_u32(np_output, | |
646 | "clock-frequency", &value)) { | |
a85d1171 | 647 | err = clk_set_rate(data->pll[i].hw.clk, value); |
19fbbbbc ML |
648 | if (err) |
649 | dev_err(&client->dev, | |
650 | "unable to set PLL frequency %ud\n", | |
651 | value); | |
652 | } | |
653 | if (!of_property_read_u32(np_output, | |
654 | "spread-spectrum", &value)) { | |
655 | u8 flag = of_property_read_bool(np_output, | |
656 | "spread-spectrum-center") ? 0x80 : 0x00; | |
657 | regmap_update_bits(data->regmap, | |
658 | 0x16 + (i*CDCE925_OFFSET_PLL), | |
659 | 0x80, flag); | |
660 | regmap_update_bits(data->regmap, | |
661 | 0x12 + (i*CDCE925_OFFSET_PLL), | |
662 | 0x07, value & 0x07); | |
663 | } | |
664 | } | |
665 | ||
666 | /* Register output clock Y1 */ | |
667 | init.ops = &cdce925_clk_y1_ops; | |
668 | init.flags = 0; | |
669 | init.num_parents = 1; | |
670 | init.parent_names = &parent_name; /* Mux Y1 to input */ | |
671 | init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name); | |
672 | data->clk[0].chip = data; | |
673 | data->clk[0].hw.init = &init; | |
674 | data->clk[0].index = 0; | |
675 | data->clk[0].pdiv = 1; | |
a85d1171 | 676 | err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); |
19fbbbbc | 677 | kfree(init.name); /* clock framework made a copy of the name */ |
a85d1171 | 678 | if (err) { |
19fbbbbc | 679 | dev_err(&client->dev, "clock registration Y1 failed\n"); |
19fbbbbc ML |
680 | goto error; |
681 | } | |
19fbbbbc ML |
682 | |
683 | /* Register output clocks Y2 .. Y5*/ | |
684 | init.ops = &cdce925_clk_ops; | |
685 | init.flags = CLK_SET_RATE_PARENT; | |
686 | init.num_parents = 1; | |
687 | for (i = 1; i < NUMBER_OF_OUTPUTS; ++i) { | |
688 | init.name = kasprintf(GFP_KERNEL, "%s.Y%d", | |
689 | client->dev.of_node->name, i+1); | |
690 | data->clk[i].chip = data; | |
691 | data->clk[i].hw.init = &init; | |
692 | data->clk[i].index = i; | |
693 | data->clk[i].pdiv = 1; | |
694 | switch (i) { | |
695 | case 1: | |
696 | case 2: | |
697 | /* Mux Y2/3 to PLL1 */ | |
698 | init.parent_names = &pll_clk_name[0]; | |
699 | break; | |
700 | case 3: | |
701 | case 4: | |
702 | /* Mux Y4/5 to PLL2 */ | |
703 | init.parent_names = &pll_clk_name[1]; | |
704 | break; | |
705 | } | |
a85d1171 | 706 | err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); |
19fbbbbc | 707 | kfree(init.name); /* clock framework made a copy of the name */ |
a85d1171 | 708 | if (err) { |
19fbbbbc | 709 | dev_err(&client->dev, "clock registration failed\n"); |
19fbbbbc ML |
710 | goto error; |
711 | } | |
19fbbbbc ML |
712 | } |
713 | ||
714 | /* Register the output clocks */ | |
a85d1171 SB |
715 | err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, |
716 | data); | |
19fbbbbc ML |
717 | if (err) |
718 | dev_err(&client->dev, "unable to add OF clock provider\n"); | |
719 | ||
720 | err = 0; | |
721 | ||
722 | error: | |
723 | for (i = 0; i < NUMBER_OF_PLLS; ++i) | |
724 | /* clock framework made a copy of the name */ | |
725 | kfree(pll_clk_name[i]); | |
726 | ||
727 | return err; | |
728 | } | |
729 | ||
730 | static const struct i2c_device_id cdce925_id[] = { | |
731 | { "cdce925", 0 }, | |
732 | { } | |
733 | }; | |
734 | MODULE_DEVICE_TABLE(i2c, cdce925_id); | |
735 | ||
736 | static const struct of_device_id clk_cdce925_of_match[] = { | |
737 | { .compatible = "ti,cdce925" }, | |
738 | { }, | |
739 | }; | |
740 | MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); | |
741 | ||
742 | static struct i2c_driver cdce925_driver = { | |
743 | .driver = { | |
744 | .name = "cdce925", | |
745 | .of_match_table = of_match_ptr(clk_cdce925_of_match), | |
746 | }, | |
747 | .probe = cdce925_probe, | |
748 | .id_table = cdce925_id, | |
749 | }; | |
750 | module_i2c_driver(cdce925_driver); | |
751 | ||
752 | MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); | |
753 | MODULE_DESCRIPTION("cdce925 driver"); | |
754 | MODULE_LICENSE("GPL"); |