Commit | Line | Data |
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9d9f78ed MT |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> | |
4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Adjustable divider clock implementation | |
11 | */ | |
12 | ||
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/string.h> | |
1a3cd184 | 19 | #include <linux/log2.h> |
9d9f78ed MT |
20 | |
21 | /* | |
22 | * DOC: basic adjustable divider clock that cannot gate | |
23 | * | |
24 | * Traits of this clock: | |
25 | * prepare - clk_prepare only ensures that parents are prepared | |
26 | * enable - clk_enable only ensures that parents are enabled | |
b11d282d | 27 | * rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor) |
9d9f78ed MT |
28 | * parent - fixed parent. No clk_set_parent support |
29 | */ | |
30 | ||
31 | #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) | |
32 | ||
1a3cd184 | 33 | #define div_mask(d) ((1 << ((d)->width)) - 1) |
6d9252bd | 34 | |
357c3f0a RN |
35 | static unsigned int _get_table_maxdiv(const struct clk_div_table *table) |
36 | { | |
37 | unsigned int maxdiv = 0; | |
38 | const struct clk_div_table *clkt; | |
39 | ||
40 | for (clkt = table; clkt->div; clkt++) | |
41 | if (clkt->div > maxdiv) | |
42 | maxdiv = clkt->div; | |
43 | return maxdiv; | |
44 | } | |
45 | ||
774b5143 MC |
46 | static unsigned int _get_table_mindiv(const struct clk_div_table *table) |
47 | { | |
48 | unsigned int mindiv = UINT_MAX; | |
49 | const struct clk_div_table *clkt; | |
50 | ||
51 | for (clkt = table; clkt->div; clkt++) | |
52 | if (clkt->div < mindiv) | |
53 | mindiv = clkt->div; | |
54 | return mindiv; | |
55 | } | |
56 | ||
6d9252bd RN |
57 | static unsigned int _get_maxdiv(struct clk_divider *divider) |
58 | { | |
59 | if (divider->flags & CLK_DIVIDER_ONE_BASED) | |
60 | return div_mask(divider); | |
61 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
62 | return 1 << div_mask(divider); | |
357c3f0a RN |
63 | if (divider->table) |
64 | return _get_table_maxdiv(divider->table); | |
6d9252bd RN |
65 | return div_mask(divider) + 1; |
66 | } | |
67 | ||
357c3f0a RN |
68 | static unsigned int _get_table_div(const struct clk_div_table *table, |
69 | unsigned int val) | |
70 | { | |
71 | const struct clk_div_table *clkt; | |
72 | ||
73 | for (clkt = table; clkt->div; clkt++) | |
74 | if (clkt->val == val) | |
75 | return clkt->div; | |
76 | return 0; | |
77 | } | |
78 | ||
6d9252bd RN |
79 | static unsigned int _get_div(struct clk_divider *divider, unsigned int val) |
80 | { | |
81 | if (divider->flags & CLK_DIVIDER_ONE_BASED) | |
82 | return val; | |
83 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
84 | return 1 << val; | |
357c3f0a RN |
85 | if (divider->table) |
86 | return _get_table_div(divider->table, val); | |
6d9252bd RN |
87 | return val + 1; |
88 | } | |
89 | ||
357c3f0a RN |
90 | static unsigned int _get_table_val(const struct clk_div_table *table, |
91 | unsigned int div) | |
92 | { | |
93 | const struct clk_div_table *clkt; | |
94 | ||
95 | for (clkt = table; clkt->div; clkt++) | |
96 | if (clkt->div == div) | |
97 | return clkt->val; | |
98 | return 0; | |
99 | } | |
100 | ||
778037e1 | 101 | static unsigned int _get_val(struct clk_divider *divider, unsigned int div) |
6d9252bd RN |
102 | { |
103 | if (divider->flags & CLK_DIVIDER_ONE_BASED) | |
104 | return div; | |
105 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
106 | return __ffs(div); | |
357c3f0a RN |
107 | if (divider->table) |
108 | return _get_table_val(divider->table, div); | |
6d9252bd RN |
109 | return div - 1; |
110 | } | |
9d9f78ed MT |
111 | |
112 | static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, | |
113 | unsigned long parent_rate) | |
114 | { | |
115 | struct clk_divider *divider = to_clk_divider(hw); | |
6d9252bd | 116 | unsigned int div, val; |
9d9f78ed | 117 | |
aa514ce3 | 118 | val = clk_readl(divider->reg) >> divider->shift; |
6d9252bd | 119 | val &= div_mask(divider); |
9d9f78ed | 120 | |
6d9252bd RN |
121 | div = _get_div(divider, val); |
122 | if (!div) { | |
056b2053 SB |
123 | WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), |
124 | "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", | |
125 | __clk_get_name(hw->clk)); | |
6d9252bd RN |
126 | return parent_rate; |
127 | } | |
9d9f78ed | 128 | |
b11d282d | 129 | return DIV_ROUND_UP(parent_rate, div); |
9d9f78ed | 130 | } |
9d9f78ed MT |
131 | |
132 | /* | |
133 | * The reverse of DIV_ROUND_UP: The maximum number which | |
134 | * divided by m is r | |
135 | */ | |
136 | #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1) | |
137 | ||
357c3f0a RN |
138 | static bool _is_valid_table_div(const struct clk_div_table *table, |
139 | unsigned int div) | |
140 | { | |
141 | const struct clk_div_table *clkt; | |
142 | ||
143 | for (clkt = table; clkt->div; clkt++) | |
144 | if (clkt->div == div) | |
145 | return true; | |
146 | return false; | |
147 | } | |
148 | ||
149 | static bool _is_valid_div(struct clk_divider *divider, unsigned int div) | |
150 | { | |
151 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
1a3cd184 | 152 | return is_power_of_2(div); |
357c3f0a RN |
153 | if (divider->table) |
154 | return _is_valid_table_div(divider->table, div); | |
155 | return true; | |
156 | } | |
157 | ||
dd23c2cd MC |
158 | static int _round_up_table(const struct clk_div_table *table, int div) |
159 | { | |
160 | const struct clk_div_table *clkt; | |
fe52e750 | 161 | int up = INT_MAX; |
dd23c2cd MC |
162 | |
163 | for (clkt = table; clkt->div; clkt++) { | |
164 | if (clkt->div == div) | |
165 | return clkt->div; | |
166 | else if (clkt->div < div) | |
167 | continue; | |
168 | ||
169 | if ((clkt->div - div) < (up - div)) | |
170 | up = clkt->div; | |
171 | } | |
172 | ||
173 | return up; | |
174 | } | |
175 | ||
774b5143 MC |
176 | static int _round_down_table(const struct clk_div_table *table, int div) |
177 | { | |
178 | const struct clk_div_table *clkt; | |
179 | int down = _get_table_mindiv(table); | |
180 | ||
181 | for (clkt = table; clkt->div; clkt++) { | |
182 | if (clkt->div == div) | |
183 | return clkt->div; | |
184 | else if (clkt->div > div) | |
185 | continue; | |
186 | ||
187 | if ((div - clkt->div) < (div - down)) | |
188 | down = clkt->div; | |
189 | } | |
190 | ||
191 | return down; | |
192 | } | |
193 | ||
dd23c2cd MC |
194 | static int _div_round_up(struct clk_divider *divider, |
195 | unsigned long parent_rate, unsigned long rate) | |
196 | { | |
197 | int div = DIV_ROUND_UP(parent_rate, rate); | |
198 | ||
199 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
200 | div = __roundup_pow_of_two(div); | |
201 | if (divider->table) | |
202 | div = _round_up_table(divider->table, div); | |
203 | ||
204 | return div; | |
205 | } | |
206 | ||
774b5143 MC |
207 | static int _div_round_closest(struct clk_divider *divider, |
208 | unsigned long parent_rate, unsigned long rate) | |
209 | { | |
210 | int up, down, div; | |
211 | ||
212 | up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate); | |
213 | ||
214 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) { | |
215 | up = __roundup_pow_of_two(div); | |
216 | down = __rounddown_pow_of_two(div); | |
217 | } else if (divider->table) { | |
218 | up = _round_up_table(divider->table, div); | |
219 | down = _round_down_table(divider->table, div); | |
220 | } | |
221 | ||
222 | return (up - div) <= (div - down) ? up : down; | |
223 | } | |
224 | ||
225 | static int _div_round(struct clk_divider *divider, unsigned long parent_rate, | |
226 | unsigned long rate) | |
227 | { | |
228 | if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST) | |
229 | return _div_round_closest(divider, parent_rate, rate); | |
230 | ||
231 | return _div_round_up(divider, parent_rate, rate); | |
232 | } | |
233 | ||
234 | static bool _is_best_div(struct clk_divider *divider, | |
3c17296f | 235 | unsigned long rate, unsigned long now, unsigned long best) |
774b5143 MC |
236 | { |
237 | if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST) | |
238 | return abs(rate - now) < abs(rate - best); | |
239 | ||
240 | return now <= rate && now > best; | |
241 | } | |
242 | ||
0e2de78e MC |
243 | static int _next_div(struct clk_divider *divider, int div) |
244 | { | |
245 | div++; | |
246 | ||
247 | if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) | |
248 | return __roundup_pow_of_two(div); | |
249 | if (divider->table) | |
250 | return _round_up_table(divider->table, div); | |
251 | ||
252 | return div; | |
253 | } | |
254 | ||
9d9f78ed MT |
255 | static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, |
256 | unsigned long *best_parent_rate) | |
257 | { | |
258 | struct clk_divider *divider = to_clk_divider(hw); | |
259 | int i, bestdiv = 0; | |
260 | unsigned long parent_rate, best = 0, now, maxdiv; | |
081c9025 | 261 | unsigned long parent_rate_saved = *best_parent_rate; |
9d9f78ed MT |
262 | |
263 | if (!rate) | |
264 | rate = 1; | |
265 | ||
6d9252bd | 266 | maxdiv = _get_maxdiv(divider); |
9d9f78ed | 267 | |
81536e07 SG |
268 | if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { |
269 | parent_rate = *best_parent_rate; | |
774b5143 | 270 | bestdiv = _div_round(divider, parent_rate, rate); |
9d9f78ed MT |
271 | bestdiv = bestdiv == 0 ? 1 : bestdiv; |
272 | bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; | |
273 | return bestdiv; | |
274 | } | |
275 | ||
276 | /* | |
277 | * The maximum divider we can use without overflowing | |
278 | * unsigned long in rate * i below | |
279 | */ | |
280 | maxdiv = min(ULONG_MAX / rate, maxdiv); | |
281 | ||
0e2de78e | 282 | for (i = 1; i <= maxdiv; i = _next_div(divider, i)) { |
357c3f0a | 283 | if (!_is_valid_div(divider, i)) |
6d9252bd | 284 | continue; |
081c9025 SG |
285 | if (rate * i == parent_rate_saved) { |
286 | /* | |
287 | * It's the most ideal case if the requested rate can be | |
288 | * divided from parent clock without needing to change | |
289 | * parent rate, so return the divider immediately. | |
290 | */ | |
291 | *best_parent_rate = parent_rate_saved; | |
292 | return i; | |
293 | } | |
9d9f78ed MT |
294 | parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), |
295 | MULT_ROUND_UP(rate, i)); | |
b11d282d | 296 | now = DIV_ROUND_UP(parent_rate, i); |
774b5143 | 297 | if (_is_best_div(divider, rate, now, best)) { |
9d9f78ed MT |
298 | bestdiv = i; |
299 | best = now; | |
300 | *best_parent_rate = parent_rate; | |
301 | } | |
302 | } | |
303 | ||
304 | if (!bestdiv) { | |
6d9252bd | 305 | bestdiv = _get_maxdiv(divider); |
9d9f78ed MT |
306 | *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1); |
307 | } | |
308 | ||
309 | return bestdiv; | |
310 | } | |
311 | ||
312 | static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, | |
313 | unsigned long *prate) | |
314 | { | |
315 | int div; | |
316 | div = clk_divider_bestdiv(hw, rate, prate); | |
317 | ||
b11d282d | 318 | return DIV_ROUND_UP(*prate, div); |
9d9f78ed | 319 | } |
9d9f78ed | 320 | |
1c0035d7 SG |
321 | static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, |
322 | unsigned long parent_rate) | |
9d9f78ed MT |
323 | { |
324 | struct clk_divider *divider = to_clk_divider(hw); | |
6d9252bd | 325 | unsigned int div, value; |
9d9f78ed MT |
326 | unsigned long flags = 0; |
327 | u32 val; | |
328 | ||
b11d282d | 329 | div = DIV_ROUND_UP(parent_rate, rate); |
dd23c2cd MC |
330 | |
331 | if (!_is_valid_div(divider, div)) | |
332 | return -EINVAL; | |
333 | ||
6d9252bd | 334 | value = _get_val(divider, div); |
9d9f78ed | 335 | |
6d9252bd RN |
336 | if (value > div_mask(divider)) |
337 | value = div_mask(divider); | |
9d9f78ed MT |
338 | |
339 | if (divider->lock) | |
340 | spin_lock_irqsave(divider->lock, flags); | |
341 | ||
d57dfe75 HZ |
342 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { |
343 | val = div_mask(divider) << (divider->shift + 16); | |
344 | } else { | |
aa514ce3 | 345 | val = clk_readl(divider->reg); |
d57dfe75 HZ |
346 | val &= ~(div_mask(divider) << divider->shift); |
347 | } | |
6d9252bd | 348 | val |= value << divider->shift; |
aa514ce3 | 349 | clk_writel(val, divider->reg); |
9d9f78ed MT |
350 | |
351 | if (divider->lock) | |
352 | spin_unlock_irqrestore(divider->lock, flags); | |
353 | ||
354 | return 0; | |
355 | } | |
9d9f78ed | 356 | |
822c250e | 357 | const struct clk_ops clk_divider_ops = { |
9d9f78ed MT |
358 | .recalc_rate = clk_divider_recalc_rate, |
359 | .round_rate = clk_divider_round_rate, | |
360 | .set_rate = clk_divider_set_rate, | |
361 | }; | |
362 | EXPORT_SYMBOL_GPL(clk_divider_ops); | |
363 | ||
79c6ab50 HS |
364 | const struct clk_ops clk_divider_ro_ops = { |
365 | .recalc_rate = clk_divider_recalc_rate, | |
366 | }; | |
367 | EXPORT_SYMBOL_GPL(clk_divider_ro_ops); | |
368 | ||
357c3f0a | 369 | static struct clk *_register_divider(struct device *dev, const char *name, |
9d9f78ed MT |
370 | const char *parent_name, unsigned long flags, |
371 | void __iomem *reg, u8 shift, u8 width, | |
357c3f0a RN |
372 | u8 clk_divider_flags, const struct clk_div_table *table, |
373 | spinlock_t *lock) | |
9d9f78ed MT |
374 | { |
375 | struct clk_divider *div; | |
376 | struct clk *clk; | |
0197b3ea | 377 | struct clk_init_data init; |
9d9f78ed | 378 | |
d57dfe75 HZ |
379 | if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { |
380 | if (width + shift > 16) { | |
381 | pr_warn("divider value exceeds LOWORD field\n"); | |
382 | return ERR_PTR(-EINVAL); | |
383 | } | |
384 | } | |
385 | ||
27d54591 | 386 | /* allocate the divider */ |
9d9f78ed | 387 | div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); |
9d9f78ed MT |
388 | if (!div) { |
389 | pr_err("%s: could not allocate divider clk\n", __func__); | |
27d54591 | 390 | return ERR_PTR(-ENOMEM); |
9d9f78ed MT |
391 | } |
392 | ||
0197b3ea | 393 | init.name = name; |
79c6ab50 HS |
394 | if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) |
395 | init.ops = &clk_divider_ro_ops; | |
396 | else | |
397 | init.ops = &clk_divider_ops; | |
f7d8caad | 398 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
399 | init.parent_names = (parent_name ? &parent_name: NULL); |
400 | init.num_parents = (parent_name ? 1 : 0); | |
401 | ||
9d9f78ed MT |
402 | /* struct clk_divider assignments */ |
403 | div->reg = reg; | |
404 | div->shift = shift; | |
405 | div->width = width; | |
406 | div->flags = clk_divider_flags; | |
407 | div->lock = lock; | |
0197b3ea | 408 | div->hw.init = &init; |
357c3f0a | 409 | div->table = table; |
9d9f78ed | 410 | |
27d54591 | 411 | /* register the clock */ |
0197b3ea | 412 | clk = clk_register(dev, &div->hw); |
9d9f78ed | 413 | |
27d54591 MT |
414 | if (IS_ERR(clk)) |
415 | kfree(div); | |
9d9f78ed | 416 | |
27d54591 | 417 | return clk; |
9d9f78ed | 418 | } |
357c3f0a RN |
419 | |
420 | /** | |
421 | * clk_register_divider - register a divider clock with the clock framework | |
422 | * @dev: device registering this clock | |
423 | * @name: name of this clock | |
424 | * @parent_name: name of clock's parent | |
425 | * @flags: framework-specific flags | |
426 | * @reg: register address to adjust divider | |
427 | * @shift: number of bits to shift the bitfield | |
428 | * @width: width of the bitfield | |
429 | * @clk_divider_flags: divider-specific flags for this clock | |
430 | * @lock: shared register lock for this clock | |
431 | */ | |
432 | struct clk *clk_register_divider(struct device *dev, const char *name, | |
433 | const char *parent_name, unsigned long flags, | |
434 | void __iomem *reg, u8 shift, u8 width, | |
435 | u8 clk_divider_flags, spinlock_t *lock) | |
436 | { | |
437 | return _register_divider(dev, name, parent_name, flags, reg, shift, | |
438 | width, clk_divider_flags, NULL, lock); | |
439 | } | |
4c5eeea9 | 440 | EXPORT_SYMBOL_GPL(clk_register_divider); |
357c3f0a RN |
441 | |
442 | /** | |
443 | * clk_register_divider_table - register a table based divider clock with | |
444 | * the clock framework | |
445 | * @dev: device registering this clock | |
446 | * @name: name of this clock | |
447 | * @parent_name: name of clock's parent | |
448 | * @flags: framework-specific flags | |
449 | * @reg: register address to adjust divider | |
450 | * @shift: number of bits to shift the bitfield | |
451 | * @width: width of the bitfield | |
452 | * @clk_divider_flags: divider-specific flags for this clock | |
453 | * @table: array of divider/value pairs ending with a div set to 0 | |
454 | * @lock: shared register lock for this clock | |
455 | */ | |
456 | struct clk *clk_register_divider_table(struct device *dev, const char *name, | |
457 | const char *parent_name, unsigned long flags, | |
458 | void __iomem *reg, u8 shift, u8 width, | |
459 | u8 clk_divider_flags, const struct clk_div_table *table, | |
460 | spinlock_t *lock) | |
461 | { | |
462 | return _register_divider(dev, name, parent_name, flags, reg, shift, | |
463 | width, clk_divider_flags, table, lock); | |
464 | } | |
4c5eeea9 | 465 | EXPORT_SYMBOL_GPL(clk_register_divider_table); |