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9d9f78ed MT |
1 | /* |
2 | * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> | |
3 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Fixed rate clock implementation | |
10 | */ | |
11 | ||
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/err.h> | |
015ba402 | 17 | #include <linux/of.h> |
9d9f78ed MT |
18 | |
19 | /* | |
20 | * DOC: basic fixed-rate clock that cannot gate | |
21 | * | |
22 | * Traits of this clock: | |
23 | * prepare - clk_(un)prepare only ensures parents are prepared | |
24 | * enable - clk_enable only ensures parents are enabled | |
25 | * rate - rate is always a fixed value. No clk_set_rate support | |
26 | * parent - fixed parent. No clk_set_parent support | |
27 | */ | |
28 | ||
29 | #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) | |
30 | ||
31 | static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw, | |
32 | unsigned long parent_rate) | |
33 | { | |
34 | return to_clk_fixed_rate(hw)->fixed_rate; | |
35 | } | |
9d9f78ed | 36 | |
822c250e | 37 | const struct clk_ops clk_fixed_rate_ops = { |
9d9f78ed MT |
38 | .recalc_rate = clk_fixed_rate_recalc_rate, |
39 | }; | |
40 | EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); | |
41 | ||
27d54591 MT |
42 | /** |
43 | * clk_register_fixed_rate - register fixed-rate clock with the clock framework | |
44 | * @dev: device that is registering this clock | |
45 | * @name: name of this clock | |
46 | * @parent_name: name of clock's parent | |
47 | * @flags: framework-specific flags | |
48 | * @fixed_rate: non-adjustable clock rate | |
49 | */ | |
9d9f78ed MT |
50 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
51 | const char *parent_name, unsigned long flags, | |
52 | unsigned long fixed_rate) | |
53 | { | |
54 | struct clk_fixed_rate *fixed; | |
27d54591 | 55 | struct clk *clk; |
0197b3ea | 56 | struct clk_init_data init; |
9d9f78ed | 57 | |
27d54591 | 58 | /* allocate fixed-rate clock */ |
9d9f78ed | 59 | fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); |
9d9f78ed MT |
60 | if (!fixed) { |
61 | pr_err("%s: could not allocate fixed clk\n", __func__); | |
62 | return ERR_PTR(-ENOMEM); | |
63 | } | |
64 | ||
0197b3ea SK |
65 | init.name = name; |
66 | init.ops = &clk_fixed_rate_ops; | |
f7d8caad | 67 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
68 | init.parent_names = (parent_name ? &parent_name: NULL); |
69 | init.num_parents = (parent_name ? 1 : 0); | |
70 | ||
9d9f78ed MT |
71 | /* struct clk_fixed_rate assignments */ |
72 | fixed->fixed_rate = fixed_rate; | |
0197b3ea | 73 | fixed->hw.init = &init; |
9d9f78ed | 74 | |
27d54591 | 75 | /* register the clock */ |
0197b3ea | 76 | clk = clk_register(dev, &fixed->hw); |
27d54591 MT |
77 | |
78 | if (IS_ERR(clk)) | |
79 | kfree(fixed); | |
80 | ||
81 | return clk; | |
9d9f78ed | 82 | } |
015ba402 GL |
83 | |
84 | #ifdef CONFIG_OF | |
85 | /** | |
86 | * of_fixed_clk_setup() - Setup function for simple fixed rate clock | |
87 | */ | |
88 | void __init of_fixed_clk_setup(struct device_node *node) | |
89 | { | |
90 | struct clk *clk; | |
91 | const char *clk_name = node->name; | |
92 | u32 rate; | |
93 | ||
94 | if (of_property_read_u32(node, "clock-frequency", &rate)) | |
95 | return; | |
96 | ||
97 | of_property_read_string(node, "clock-output-names", &clk_name); | |
98 | ||
99 | clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate); | |
100 | if (clk) | |
101 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
102 | } | |
103 | EXPORT_SYMBOL_GPL(of_fixed_clk_setup); | |
104 | #endif |