[deliverable/linux.git] / drivers / clk / clk-fractional-divider.c

/*
 * Copyright (C) 2014 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Adjustable fractional divider clock implementation.
 * Output rate = (m / n) * parent_rate.
 * Uses rational best approximation algorithm.
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/rational.h>

#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)

static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
					unsigned long parent_rate)
{
	struct clk_fractional_divider *fd = to_clk_fd(hw);
	unsigned long flags = 0;
	unsigned long m, n;
	u32 val;
	u64 ret;

	if (fd->lock)
		spin_lock_irqsave(fd->lock, flags);
	else
		__acquire(fd->lock);

	val = clk_readl(fd->reg);

	if (fd->lock)
		spin_unlock_irqrestore(fd->lock, flags);
	else
		__release(fd->lock);

	m = (val & fd->mmask) >> fd->mshift;
	n = (val & fd->nmask) >> fd->nshift;

	if (!n || !m)
		return parent_rate;

	ret = (u64)parent_rate * m;
	do_div(ret, n);

	return ret;
}

static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long *parent_rate)
{
	struct clk_fractional_divider *fd = to_clk_fd(hw);
	unsigned long scale;
	unsigned long m, n;
	u64 ret;

	if (!rate || rate >= *parent_rate)
		return *parent_rate;

	/*
	 * Get rate closer to *parent_rate to guarantee there is no overflow
	 * for m and n. In the result it will be the nearest rate left shifted
	 * by (scale - fd->nwidth) bits.
	 */
	scale = fls_long(*parent_rate / rate - 1);
	if (scale > fd->nwidth)
		rate <<= scale - fd->nwidth;

	rational_best_approximation(rate, *parent_rate,
			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
			&m, &n);

	ret = (u64)*parent_rate * m;
	do_div(ret, n);

	return ret;
}

static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
			   unsigned long parent_rate)
{
	struct clk_fractional_divider *fd = to_clk_fd(hw);
	unsigned long flags = 0;
	unsigned long m, n;
	u32 val;

	rational_best_approximation(rate, parent_rate,
			GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
			&m, &n);

	if (fd->lock)
		spin_lock_irqsave(fd->lock, flags);
	else
		__acquire(fd->lock);

	val = clk_readl(fd->reg);
	val &= ~(fd->mmask | fd->nmask);
	val |= (m << fd->mshift) | (n << fd->nshift);
	clk_writel(val, fd->reg);

	if (fd->lock)
		spin_unlock_irqrestore(fd->lock, flags);
	else
		__release(fd->lock);

	return 0;
}

const struct clk_ops clk_fractional_divider_ops = {
	.recalc_rate = clk_fd_recalc_rate,
	.round_rate = clk_fd_round_rate,
	.set_rate = clk_fd_set_rate,
};
EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);

struct clk *clk_register_fractional_divider(struct device *dev,
		const char *name, const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
		u8 clk_divider_flags, spinlock_t *lock)
{
	struct clk_fractional_divider *fd;
	struct clk_init_data init;
	struct clk *clk;

	fd = kzalloc(sizeof(*fd), GFP_KERNEL);
	if (!fd)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &clk_fractional_divider_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = parent_name ? &parent_name : NULL;
	init.num_parents = parent_name ? 1 : 0;

	fd->reg = reg;
	fd->mshift = mshift;
	fd->mwidth = mwidth;
	fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
	fd->nshift = nshift;
	fd->nwidth = nwidth;
	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
	fd->flags = clk_divider_flags;
	fd->lock = lock;
	fd->hw.init = &init;

	clk = clk_register(dev, &fd->hw);
	if (IS_ERR(clk))
		kfree(fd);

	return clk;
}
EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
Commit	Line	Data
e2d0e90f HK	1	/*
	2	* Copyright (C) 2014 Intel Corporation
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Adjustable fractional divider clock implementation.
	9	* Output rate = (m / n) * parent_rate.
0777591e	10	* Uses rational best approximation algorithm.
e2d0e90f HK	11	*/
	12
	13	#include <linux/clk-provider.h>
	14	#include <linux/module.h>
	15	#include <linux/device.h>
	16	#include <linux/slab.h>
0777591e	17	#include <linux/rational.h>
e2d0e90f HK	18
	19	#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
	20
	21	static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
	22	unsigned long parent_rate)
	23	{
	24	struct clk_fractional_divider *fd = to_clk_fd(hw);
	25	unsigned long flags = 0;
0777591e AS	26	unsigned long m, n;
0777591e AS	27	u32 val;
e2d0e90f HK	28	u64 ret;
	29
	30	if (fd->lock)
	31	spin_lock_irqsave(fd->lock, flags);
661e2180 SB	32	else
661e2180 SB	33	__acquire(fd->lock);
e2d0e90f HK	34
	35	val = clk_readl(fd->reg);
	36
	37	if (fd->lock)
	38	spin_unlock_irqrestore(fd->lock, flags);
661e2180 SB	39	else
661e2180 SB	40	__release(fd->lock);
e2d0e90f HK	41
	42	m = (val & fd->mmask) >> fd->mshift;
	43	n = (val & fd->nmask) >> fd->nshift;
	44
6b547836 HK	45	if (!n \|\| !m)
	46	return parent_rate;
	47
feaefa0e	48	ret = (u64)parent_rate * m;
e2d0e90f HK	49	do_div(ret, n);
	50
	51	return ret;
	52	}
	53
	54	static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
f7f087c2	55	unsigned long *parent_rate)
e2d0e90f HK	56	{
e2d0e90f HK	57	struct clk_fractional_divider *fd = to_clk_fd(hw);
0777591e AS	58	unsigned long scale;
	59	unsigned long m, n;
	60	u64 ret;
e2d0e90f	61
f7f087c2 AS	62	if (!rate \|\| rate >= *parent_rate)
f7f087c2 AS	63	return *parent_rate;
e2d0e90f	64
0777591e AS	65	/*
	66	* Get rate closer to *parent_rate to guarantee there is no overflow
	67	* for m and n. In the result it will be the nearest rate left shifted
	68	* by (scale - fd->nwidth) bits.
	69	*/
	70	scale = fls_long(*parent_rate / rate - 1);
	71	if (scale > fd->nwidth)
	72	rate <<= scale - fd->nwidth;
e2d0e90f	73
0777591e AS	74	rational_best_approximation(rate, *parent_rate,
	75	GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
	76	&m, &n);
e2d0e90f	77
0777591e AS	78	ret = (u64)parent_rate m;
	79	do_div(ret, n);
	80
	81	return ret;
e2d0e90f HK	82	}
	83
	84	static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
	85	unsigned long parent_rate)
	86	{
	87	struct clk_fractional_divider *fd = to_clk_fd(hw);
	88	unsigned long flags = 0;
0777591e	89	unsigned long m, n;
e2d0e90f HK	90	u32 val;
e2d0e90f HK	91
0777591e AS	92	rational_best_approximation(rate, parent_rate,
	93	GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0),
	94	&m, &n);
e2d0e90f HK	95
	96	if (fd->lock)
	97	spin_lock_irqsave(fd->lock, flags);
661e2180 SB	98	else
661e2180 SB	99	__acquire(fd->lock);
e2d0e90f HK	100
	101	val = clk_readl(fd->reg);
	102	val &= ~(fd->mmask \| fd->nmask);
	103	val \|= (m << fd->mshift) \| (n << fd->nshift);
	104	clk_writel(val, fd->reg);
	105
	106	if (fd->lock)
	107	spin_unlock_irqrestore(fd->lock, flags);
661e2180 SB	108	else
661e2180 SB	109	__release(fd->lock);
e2d0e90f HK	110
	111	return 0;
	112	}
	113
	114	const struct clk_ops clk_fractional_divider_ops = {
	115	.recalc_rate = clk_fd_recalc_rate,
	116	.round_rate = clk_fd_round_rate,
	117	.set_rate = clk_fd_set_rate,
	118	};
	119	EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
	120
	121	struct clk clk_register_fractional_divider(struct device dev,
	122	const char name, const char parent_name, unsigned long flags,
	123	void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
	124	u8 clk_divider_flags, spinlock_t *lock)
	125	{
	126	struct clk_fractional_divider *fd;
	127	struct clk_init_data init;
	128	struct clk *clk;
	129
	130	fd = kzalloc(sizeof(*fd), GFP_KERNEL);
d122db7e	131	if (!fd)
e2d0e90f	132	return ERR_PTR(-ENOMEM);
e2d0e90f HK	133
	134	init.name = name;
	135	init.ops = &clk_fractional_divider_ops;
	136	init.flags = flags \| CLK_IS_BASIC;
	137	init.parent_names = parent_name ? &parent_name : NULL;
	138	init.num_parents = parent_name ? 1 : 0;
	139
	140	fd->reg = reg;
	141	fd->mshift = mshift;
934e2536 AS	142	fd->mwidth = mwidth;
934e2536 AS	143	fd->mmask = GENMASK(mwidth - 1, 0) << mshift;
e2d0e90f	144	fd->nshift = nshift;
934e2536 AS	145	fd->nwidth = nwidth;
934e2536 AS	146	fd->nmask = GENMASK(nwidth - 1, 0) << nshift;
e2d0e90f HK	147	fd->flags = clk_divider_flags;
	148	fd->lock = lock;
	149	fd->hw.init = &init;
	150
	151	clk = clk_register(dev, &fd->hw);
	152	if (IS_ERR(clk))
	153	kfree(fd);
	154
	155	return clk;
	156	}
	157	EXPORT_SYMBOL_GPL(clk_register_fractional_divider);