[deliverable/linux.git] / drivers / clk / clk-ls1x.c

/*
 * Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>

#include <loongson1.h>

#define OSC		(33 * 1000000)
#define DIV_APB		2

static DEFINE_SPINLOCK(_lock);

static int ls1x_pll_clk_enable(struct clk_hw *hw)
{
	return 0;
}

static void ls1x_pll_clk_disable(struct clk_hw *hw)
{
}

static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
					  unsigned long parent_rate)
{
	u32 pll, rate;

	pll = __raw_readl(LS1X_CLK_PLL_FREQ);
	rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10);
	rate *= OSC;
	rate >>= 1;

	return rate;
}

static const struct clk_ops ls1x_pll_clk_ops = {
	.enable = ls1x_pll_clk_enable,
	.disable = ls1x_pll_clk_disable,
	.recalc_rate = ls1x_pll_recalc_rate,
};

static struct clk_hw *__init clk_hw_register_pll(struct device *dev,
						 const char *name,
						 const char *parent_name,
						 unsigned long flags)
{
	int ret;
	struct clk_hw *hw;
	struct clk_init_data init;

	/* allocate the divider */
	hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
	if (!hw) {
		pr_err("%s: could not allocate clk_hw\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	init.ops = &ls1x_pll_clk_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = (parent_name ? &parent_name : NULL);
	init.num_parents = (parent_name ? 1 : 0);
	hw->init = &init;

	/* register the clock */
	ret = clk_hw_register(dev, hw);
	if (ret) {
		kfree(hw);
		hw = ERR_PTR(ret);
	}

	return hw;
}

static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };
static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", };

void __init ls1x_clk_init(void)
{
	struct clk_hw *hw;

	hw = clk_hw_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC);
	clk_hw_register_clkdev(hw, "osc_33m_clk", NULL);

	/* clock derived from 33 MHz OSC clk */
	hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
	clk_hw_register_clkdev(hw, "pll_clk", NULL);

	/* clock derived from PLL clk */
	/*                                 _____
	 *         _______________________|     |
	 * OSC ___/                       | MUX |___ CPU CLK
	 *        \___ PLL ___ CPU DIV ___|     |
	 *                                |_____|
	 */
	hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
				   CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
				   DIV_CPU_SHIFT, DIV_CPU_WIDTH,
				   CLK_DIVIDER_ONE_BASED |
				   CLK_DIVIDER_ROUND_CLOSEST, &_lock);
	clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
	hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents,
			       ARRAY_SIZE(cpu_parents),
			       CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
			       BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
	clk_hw_register_clkdev(hw, "cpu_clk", NULL);

	/*                                 _____
	 *         _______________________|     |
	 * OSC ___/                       | MUX |___ DC  CLK
	 *        \___ PLL ___ DC  DIV ___|     |
	 *                                |_____|
	 */
	hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
				   0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
				   DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
	clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
	hw = clk_hw_register_mux(NULL, "dc_clk", dc_parents,
			       ARRAY_SIZE(dc_parents),
			       CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
			       BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
	clk_hw_register_clkdev(hw, "dc_clk", NULL);

	/*                                 _____
	 *         _______________________|     |
	 * OSC ___/                       | MUX |___ DDR CLK
	 *        \___ PLL ___ DDR DIV ___|     |
	 *                                |_____|
	 */
	hw = clk_hw_register_divider(NULL, "ahb_clk_div", "pll_clk",
				   0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
				   DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
				   &_lock);
	clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
	hw = clk_hw_register_mux(NULL, "ahb_clk", ahb_parents,
			       ARRAY_SIZE(ahb_parents),
			       CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
			       BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
	clk_hw_register_clkdev(hw, "ahb_clk", NULL);
	clk_hw_register_clkdev(hw, "stmmaceth", NULL);

	/* clock derived from AHB clk */
	/* APB clk is always half of the AHB clk */
	hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
					DIV_APB);
	clk_hw_register_clkdev(hw, "apb_clk", NULL);
	clk_hw_register_clkdev(hw, "ls1x_i2c", NULL);
	clk_hw_register_clkdev(hw, "ls1x_pwmtimer", NULL);
	clk_hw_register_clkdev(hw, "ls1x_spi", NULL);
	clk_hw_register_clkdev(hw, "ls1x_wdt", NULL);
	clk_hw_register_clkdev(hw, "serial8250", NULL);
}
Commit	Line	Data
5175cb58 KC	1	/*
	2	* Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation; either version 2 of the License, or (at your
	7	* option) any later version.
	8	*/
	9
	10	#include <linux/clkdev.h>
	11	#include <linux/clk-provider.h>
	12	#include <linux/io.h>
	13	#include <linux/slab.h>
	14	#include <linux/err.h>
	15
	16	#include <loongson1.h>
	17
3526f74f KC	18	#define OSC (33 * 1000000)
3526f74f KC	19	#define DIV_APB 2
5175cb58 KC	20
	21	static DEFINE_SPINLOCK(_lock);
	22
	23	static int ls1x_pll_clk_enable(struct clk_hw *hw)
	24	{
	25	return 0;
	26	}
	27
	28	static void ls1x_pll_clk_disable(struct clk_hw *hw)
	29	{
	30	}
	31
	32	static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
3526f74f	33	unsigned long parent_rate)
5175cb58 KC	34	{
	35	u32 pll, rate;
	36
	37	pll = __raw_readl(LS1X_CLK_PLL_FREQ);
3526f74f	38	rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10);
5175cb58 KC	39	rate *= OSC;
	40	rate >>= 1;
	41
	42	return rate;
	43	}
	44
	45	static const struct clk_ops ls1x_pll_clk_ops = {
	46	.enable = ls1x_pll_clk_enable,
	47	.disable = ls1x_pll_clk_disable,
	48	.recalc_rate = ls1x_pll_recalc_rate,
	49	};
	50
944b9a41 SB	51	static struct clk_hw __init clk_hw_register_pll(struct device dev,
	52	const char *name,
	53	const char *parent_name,
	54	unsigned long flags)
5175cb58	55	{
944b9a41	56	int ret;
5175cb58	57	struct clk_hw *hw;
5175cb58 KC	58	struct clk_init_data init;
	59
	60	/* allocate the divider */
	61	hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
	62	if (!hw) {
	63	pr_err("%s: could not allocate clk_hw\n", __func__);
	64	return ERR_PTR(-ENOMEM);
	65	}
	66
	67	init.name = name;
	68	init.ops = &ls1x_pll_clk_ops;
	69	init.flags = flags \| CLK_IS_BASIC;
	70	init.parent_names = (parent_name ? &parent_name : NULL);
	71	init.num_parents = (parent_name ? 1 : 0);
	72	hw->init = &init;
	73
	74	/* register the clock */
944b9a41 SB	75	ret = clk_hw_register(dev, hw);
944b9a41 SB	76	if (ret) {
5175cb58	77	kfree(hw);
944b9a41 SB	78	hw = ERR_PTR(ret);
944b9a41 SB	79	}
5175cb58	80
944b9a41	81	return hw;
5175cb58 KC	82	}
5175cb58 KC	83
2ad8b3fc KK	84	static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
	85	static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };
	86	static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
3526f74f	87
5175cb58 KC	88	void __init ls1x_clk_init(void)
5175cb58 KC	89	{
944b9a41	90	struct clk_hw *hw;
5175cb58	91
944b9a41 SB	92	hw = clk_hw_register_fixed_rate(NULL, "osc_33m_clk", NULL, 0, OSC);
944b9a41 SB	93	clk_hw_register_clkdev(hw, "osc_33m_clk", NULL);
3526f74f KC	94
3526f74f KC	95	/* clock derived from 33 MHz OSC clk */
944b9a41 SB	96	hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
944b9a41 SB	97	clk_hw_register_clkdev(hw, "pll_clk", NULL);
3526f74f KC	98
	99	/* clock derived from PLL clk */
	100	/* _____
	101	* _______________________\| \|
	102	* OSC ___/ \| MUX \|___ CPU CLK
	103	* \___ PLL ___ CPU DIV ___\| \|
	104	* \|_____\|
	105	*/
944b9a41	106	hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
3526f74f KC	107	CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
	108	DIV_CPU_SHIFT, DIV_CPU_WIDTH,
	109	CLK_DIVIDER_ONE_BASED \|
	110	CLK_DIVIDER_ROUND_CLOSEST, &_lock);
944b9a41 SB	111	clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
944b9a41 SB	112	hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents,
3526f74f KC	113	ARRAY_SIZE(cpu_parents),
	114	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
	115	BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
944b9a41	116	clk_hw_register_clkdev(hw, "cpu_clk", NULL);
3526f74f KC	117
	118	/* _____
	119	* _______________________\| \|
	120	* OSC ___/ \| MUX \|___ DC CLK
	121	* \___ PLL ___ DC DIV ___\| \|
	122	* \|_____\|
	123	*/
944b9a41	124	hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
3526f74f KC	125	0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
3526f74f KC	126	DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
944b9a41 SB	127	clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
944b9a41 SB	128	hw = clk_hw_register_mux(NULL, "dc_clk", dc_parents,
3526f74f KC	129	ARRAY_SIZE(dc_parents),
	130	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
	131	BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
944b9a41	132	clk_hw_register_clkdev(hw, "dc_clk", NULL);
3526f74f KC	133
	134	/* _____
	135	* _______________________\| \|
	136	* OSC ___/ \| MUX \|___ DDR CLK
	137	* \___ PLL ___ DDR DIV ___\| \|
	138	* \|_____\|
	139	*/
944b9a41	140	hw = clk_hw_register_divider(NULL, "ahb_clk_div", "pll_clk",
3526f74f KC	141	0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
	142	DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
	143	&_lock);
944b9a41 SB	144	clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
944b9a41 SB	145	hw = clk_hw_register_mux(NULL, "ahb_clk", ahb_parents,
3526f74f KC	146	ARRAY_SIZE(ahb_parents),
	147	CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
	148	BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
944b9a41 SB	149	clk_hw_register_clkdev(hw, "ahb_clk", NULL);
944b9a41 SB	150	clk_hw_register_clkdev(hw, "stmmaceth", NULL);
5175cb58	151
3526f74f KC	152	/* clock derived from AHB clk */
3526f74f KC	153	/* APB clk is always half of the AHB clk */
944b9a41	154	hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
3526f74f	155	DIV_APB);
944b9a41 SB	156	clk_hw_register_clkdev(hw, "apb_clk", NULL);
	157	clk_hw_register_clkdev(hw, "ls1x_i2c", NULL);
	158	clk_hw_register_clkdev(hw, "ls1x_pwmtimer", NULL);
	159	clk_hw_register_clkdev(hw, "ls1x_spi", NULL);
	160	clk_hw_register_clkdev(hw, "ls1x_wdt", NULL);
	161	clk_hw_register_clkdev(hw, "serial8250", NULL);
5175cb58	162	}