[deliverable/linux.git] / drivers / clk / clk-scpi.c

/*
 * System Control and Power Interface (SCPI) Protocol based clock driver
 *
 * Copyright (C) 2015 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/scpi_protocol.h>

struct scpi_clk {
	u32 id;
	struct clk_hw hw;
	struct scpi_dvfs_info *info;
	struct scpi_ops *scpi_ops;
};

#define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)

static struct platform_device *cpufreq_dev;

static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
					  unsigned long parent_rate)
{
	struct scpi_clk *clk = to_scpi_clk(hw);

	return clk->scpi_ops->clk_get_val(clk->id);
}

static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *parent_rate)
{
	/*
	 * We can't figure out what rate it will be, so just return the
	 * rate back to the caller. scpi_clk_recalc_rate() will be called
	 * after the rate is set and we'll know what rate the clock is
	 * running at then.
	 */
	return rate;
}

static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
			     unsigned long parent_rate)
{
	struct scpi_clk *clk = to_scpi_clk(hw);

	return clk->scpi_ops->clk_set_val(clk->id, rate);
}

static const struct clk_ops scpi_clk_ops = {
	.recalc_rate = scpi_clk_recalc_rate,
	.round_rate = scpi_clk_round_rate,
	.set_rate = scpi_clk_set_rate,
};

/* find closest match to given frequency in OPP table */
static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
{
	int idx;
	u32 fmin = 0, fmax = ~0, ftmp;
	const struct scpi_opp *opp = clk->info->opps;

	for (idx = 0; idx < clk->info->count; idx++, opp++) {
		ftmp = opp->freq;
		if (ftmp >= (u32)rate) {
			if (ftmp <= fmax)
				fmax = ftmp;
			break;
		} else if (ftmp >= fmin) {
			fmin = ftmp;
		}
	}
	return fmax != ~0 ? fmax : fmin;
}

static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{
	struct scpi_clk *clk = to_scpi_clk(hw);
	int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
	const struct scpi_opp *opp;

	if (idx < 0)
		return 0;

	opp = clk->info->opps + idx;
	return opp->freq;
}

static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *parent_rate)
{
	struct scpi_clk *clk = to_scpi_clk(hw);

	return __scpi_dvfs_round_rate(clk, rate);
}

static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
{
	int idx, max_opp = clk->info->count;
	const struct scpi_opp *opp = clk->info->opps;

	for (idx = 0; idx < max_opp; idx++, opp++)
		if (opp->freq == rate)
			return idx;
	return -EINVAL;
}

static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long parent_rate)
{
	struct scpi_clk *clk = to_scpi_clk(hw);
	int ret = __scpi_find_dvfs_index(clk, rate);

	if (ret < 0)
		return ret;
	return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
}

static const struct clk_ops scpi_dvfs_ops = {
	.recalc_rate = scpi_dvfs_recalc_rate,
	.round_rate = scpi_dvfs_round_rate,
	.set_rate = scpi_dvfs_set_rate,
};

static const struct of_device_id scpi_clk_match[] = {
	{ .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
	{ .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
	{}
};

static int
scpi_clk_ops_init(struct device *dev, const struct of_device_id *match,
		  struct scpi_clk *sclk, const char *name)
{
	struct clk_init_data init;
	unsigned long min = 0, max = 0;
	int ret;

	init.name = name;
	init.flags = 0;
	init.num_parents = 0;
	init.ops = match->data;
	sclk->hw.init = &init;
	sclk->scpi_ops = get_scpi_ops();

	if (init.ops == &scpi_dvfs_ops) {
		sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
		if (IS_ERR(sclk->info))
			return PTR_ERR(sclk->info);
	} else if (init.ops == &scpi_clk_ops) {
		if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max)
			return -EINVAL;
	} else {
		return -EINVAL;
	}

	ret = devm_clk_hw_register(dev, &sclk->hw);
	if (!ret && max)
		clk_hw_set_rate_range(&sclk->hw, min, max);
	return ret;
}

struct scpi_clk_data {
	struct scpi_clk **clk;
	unsigned int clk_num;
};

static struct clk_hw *
scpi_of_clk_src_get(struct of_phandle_args *clkspec, void *data)
{
	struct scpi_clk *sclk;
	struct scpi_clk_data *clk_data = data;
	unsigned int idx = clkspec->args[0], count;

	for (count = 0; count < clk_data->clk_num; count++) {
		sclk = clk_data->clk[count];
		if (idx == sclk->id)
			return &sclk->hw;
	}

	return ERR_PTR(-EINVAL);
}

static int scpi_clk_add(struct device *dev, struct device_node *np,
			const struct of_device_id *match)
{
	int idx, count, err;
	struct scpi_clk_data *clk_data;

	count = of_property_count_strings(np, "clock-output-names");
	if (count < 0) {
		dev_err(dev, "%s: invalid clock output count\n", np->name);
		return -EINVAL;
	}

	clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
	if (!clk_data)
		return -ENOMEM;

	clk_data->clk_num = count;
	clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
				     GFP_KERNEL);
	if (!clk_data->clk)
		return -ENOMEM;

	for (idx = 0; idx < count; idx++) {
		struct scpi_clk *sclk;
		const char *name;
		u32 val;

		sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
		if (!sclk)
			return -ENOMEM;

		if (of_property_read_string_index(np, "clock-output-names",
						  idx, &name)) {
			dev_err(dev, "invalid clock name @ %s\n", np->name);
			return -EINVAL;
		}

		if (of_property_read_u32_index(np, "clock-indices",
					       idx, &val)) {
			dev_err(dev, "invalid clock index @ %s\n", np->name);
			return -EINVAL;
		}

		sclk->id = val;

		err = scpi_clk_ops_init(dev, match, sclk, name);
		if (err)
			dev_err(dev, "failed to register clock '%s'\n", name);
		else
			dev_dbg(dev, "Registered clock '%s'\n", name);
		clk_data->clk[idx] = sclk;
	}

	return of_clk_add_hw_provider(np, scpi_of_clk_src_get, clk_data);
}

static int scpi_clocks_remove(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *child, *np = dev->of_node;

	if (cpufreq_dev) {
		platform_device_unregister(cpufreq_dev);
		cpufreq_dev = NULL;
	}

	for_each_available_child_of_node(np, child)
		of_clk_del_provider(np);
	return 0;
}

static int scpi_clocks_probe(struct platform_device *pdev)
{
	int ret;
	struct device *dev = &pdev->dev;
	struct device_node *child, *np = dev->of_node;
	const struct of_device_id *match;

	if (!get_scpi_ops())
		return -ENXIO;

	for_each_available_child_of_node(np, child) {
		match = of_match_node(scpi_clk_match, child);
		if (!match)
			continue;
		ret = scpi_clk_add(dev, child, match);
		if (ret) {
			scpi_clocks_remove(pdev);
			of_node_put(child);
			return ret;
		}
	}
	/* Add the virtual cpufreq device */
	cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
						      -1, NULL, 0);
	if (IS_ERR(cpufreq_dev))
		pr_warn("unable to register cpufreq device");

	return 0;
}

static const struct of_device_id scpi_clocks_ids[] = {
	{ .compatible = "arm,scpi-clocks", },
	{}
};
MODULE_DEVICE_TABLE(of, scpi_clocks_ids);

static struct platform_driver scpi_clocks_driver = {
	.driver	= {
		.name = "scpi_clocks",
		.of_match_table = scpi_clocks_ids,
	},
	.probe = scpi_clocks_probe,
	.remove = scpi_clocks_remove,
};
module_platform_driver(scpi_clocks_driver);

MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
MODULE_DESCRIPTION("ARM SCPI clock driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
cd52c2a4 SH	1	/*
	2	* System Control and Power Interface (SCPI) Protocol based clock driver
	3	*
	4	* Copyright (C) 2015 ARM Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include <linux/clk-provider.h>
	20	#include <linux/device.h>
	21	#include <linux/err.h>
	22	#include <linux/of.h>
	23	#include <linux/module.h>
	24	#include <linux/of_platform.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/scpi_protocol.h>
	27
	28	struct scpi_clk {
	29	u32 id;
	30	struct clk_hw hw;
	31	struct scpi_dvfs_info *info;
	32	struct scpi_ops *scpi_ops;
	33	};
	34
	35	#define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
	36
9490f01e SH	37	static struct platform_device *cpufreq_dev;
9490f01e SH	38
cd52c2a4 SH	39	static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
	40	unsigned long parent_rate)
	41	{
	42	struct scpi_clk *clk = to_scpi_clk(hw);
	43
	44	return clk->scpi_ops->clk_get_val(clk->id);
	45	}
	46
	47	static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
	48	unsigned long *parent_rate)
	49	{
	50	/*
	51	* We can't figure out what rate it will be, so just return the
	52	* rate back to the caller. scpi_clk_recalc_rate() will be called
	53	* after the rate is set and we'll know what rate the clock is
	54	* running at then.
	55	*/
	56	return rate;
	57	}
	58
	59	static int scpi_clk_set_rate(struct clk_hw *hw, unsigned long rate,
	60	unsigned long parent_rate)
	61	{
	62	struct scpi_clk *clk = to_scpi_clk(hw);
	63
	64	return clk->scpi_ops->clk_set_val(clk->id, rate);
	65	}
	66
	67	static const struct clk_ops scpi_clk_ops = {
	68	.recalc_rate = scpi_clk_recalc_rate,
	69	.round_rate = scpi_clk_round_rate,
	70	.set_rate = scpi_clk_set_rate,
	71	};
	72
	73	/* find closest match to given frequency in OPP table */
	74	static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate)
	75	{
	76	int idx;
	77	u32 fmin = 0, fmax = ~0, ftmp;
	78	const struct scpi_opp *opp = clk->info->opps;
	79
	80	for (idx = 0; idx < clk->info->count; idx++, opp++) {
	81	ftmp = opp->freq;
	82	if (ftmp >= (u32)rate) {
	83	if (ftmp <= fmax)
	84	fmax = ftmp;
	85	break;
	86	} else if (ftmp >= fmin) {
	87	fmin = ftmp;
	88	}
	89	}
	90	return fmax != ~0 ? fmax : fmin;
	91	}
	92
	93	static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
	94	unsigned long parent_rate)
	95	{
	96	struct scpi_clk *clk = to_scpi_clk(hw);
	97	int idx = clk->scpi_ops->dvfs_get_idx(clk->id);
	98	const struct scpi_opp *opp;
	99
	100	if (idx < 0)
	101	return 0;
	102
103	opp = clk->info->opps + idx;
104	return opp->freq;
105	}
106
107	static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
108	unsigned long *parent_rate)
109	{
110	struct scpi_clk *clk = to_scpi_clk(hw);
111
112	return __scpi_dvfs_round_rate(clk, rate);
113	}
114
115	static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate)
116	{
117	int idx, max_opp = clk->info->count;
118	const struct scpi_opp *opp = clk->info->opps;
119
120	for (idx = 0; idx < max_opp; idx++, opp++)
121	if (opp->freq == rate)
122	return idx;
123	return -EINVAL;
124	}
125
126	static int scpi_dvfs_set_rate(struct clk_hw *hw, unsigned long rate,
127	unsigned long parent_rate)
128	{
129	struct scpi_clk *clk = to_scpi_clk(hw);
130	int ret = __scpi_find_dvfs_index(clk, rate);
131
132	if (ret < 0)
133	return ret;
134	return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret);
135	}
136
137	static const struct clk_ops scpi_dvfs_ops = {
138	.recalc_rate = scpi_dvfs_recalc_rate,
139	.round_rate = scpi_dvfs_round_rate,
140	.set_rate = scpi_dvfs_set_rate,
141	};
142
143	static const struct of_device_id scpi_clk_match[] = {
144	{ .compatible = "arm,scpi-dvfs-clocks", .data = &scpi_dvfs_ops, },
145	{ .compatible = "arm,scpi-variable-clocks", .data = &scpi_clk_ops, },
146	{}
147	};
148
93ae00be	149	static int
cd52c2a4 SH	150	scpi_clk_ops_init(struct device dev, const struct of_device_id match,
	151	struct scpi_clk sclk, const char name)
	152	{
	153	struct clk_init_data init;
cd52c2a4	154	unsigned long min = 0, max = 0;
93ae00be	155	int ret;
cd52c2a4 SH	156
cd52c2a4 SH	157	init.name = name;
90593682	158	init.flags = 0;
cd52c2a4 SH	159	init.num_parents = 0;
	160	init.ops = match->data;
	161	sclk->hw.init = &init;
	162	sclk->scpi_ops = get_scpi_ops();
	163
	164	if (init.ops == &scpi_dvfs_ops) {
	165	sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
	166	if (IS_ERR(sclk->info))
93ae00be	167	return PTR_ERR(sclk->info);
cd52c2a4 SH	168	} else if (init.ops == &scpi_clk_ops) {
cd52c2a4 SH	169	if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) \|\| !max)
93ae00be	170	return -EINVAL;
cd52c2a4	171	} else {
93ae00be	172	return -EINVAL;
cd52c2a4 SH	173	}
cd52c2a4 SH	174
93ae00be SB	175	ret = devm_clk_hw_register(dev, &sclk->hw);
93ae00be SB	176	if (!ret && max)
cd52c2a4	177	clk_hw_set_rate_range(&sclk->hw, min, max);
93ae00be	178	return ret;
cd52c2a4 SH	179	}
	180
	181	struct scpi_clk_data {
	182	struct scpi_clk **clk;
	183	unsigned int clk_num;
	184	};
	185
93ae00be	186	static struct clk_hw *
cd52c2a4 SH	187	scpi_of_clk_src_get(struct of_phandle_args clkspec, void data)
	188	{
	189	struct scpi_clk *sclk;
	190	struct scpi_clk_data *clk_data = data;
	191	unsigned int idx = clkspec->args[0], count;
	192
	193	for (count = 0; count < clk_data->clk_num; count++) {
	194	sclk = clk_data->clk[count];
	195	if (idx == sclk->id)
93ae00be	196	return &sclk->hw;
cd52c2a4 SH	197	}
	198
	199	return ERR_PTR(-EINVAL);
	200	}
	201
	202	static int scpi_clk_add(struct device dev, struct device_node np,
	203	const struct of_device_id *match)
	204	{
93ae00be	205	int idx, count, err;
cd52c2a4 SH	206	struct scpi_clk_data *clk_data;
	207
	208	count = of_property_count_strings(np, "clock-output-names");
	209	if (count < 0) {
	210	dev_err(dev, "%s: invalid clock output count\n", np->name);
	211	return -EINVAL;
	212	}
	213
	214	clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
	215	if (!clk_data)
	216	return -ENOMEM;
	217
	218	clk_data->clk_num = count;
	219	clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
	220	GFP_KERNEL);
	221	if (!clk_data->clk)
	222	return -ENOMEM;
	223
cd52c2a4 SH	224	for (idx = 0; idx < count; idx++) {
	225	struct scpi_clk *sclk;
	226	const char *name;
	227	u32 val;
	228
	229	sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
	230	if (!sclk)
	231	return -ENOMEM;
	232
	233	if (of_property_read_string_index(np, "clock-output-names",
	234	idx, &name)) {
	235	dev_err(dev, "invalid clock name @ %s\n", np->name);
	236	return -EINVAL;
	237	}
	238
	239	if (of_property_read_u32_index(np, "clock-indices",
	240	idx, &val)) {
	241	dev_err(dev, "invalid clock index @ %s\n", np->name);
	242	return -EINVAL;
	243	}
	244
	245	sclk->id = val;
	246
93ae00be SB	247	err = scpi_clk_ops_init(dev, match, sclk, name);
93ae00be SB	248	if (err)
cd52c2a4 SH	249	dev_err(dev, "failed to register clock '%s'\n", name);
	250	else
	251	dev_dbg(dev, "Registered clock '%s'\n", name);
	252	clk_data->clk[idx] = sclk;
	253	}
	254
93ae00be	255	return of_clk_add_hw_provider(np, scpi_of_clk_src_get, clk_data);
cd52c2a4 SH	256	}
	257
	258	static int scpi_clocks_remove(struct platform_device *pdev)
	259	{
	260	struct device *dev = &pdev->dev;
	261	struct device_node child, np = dev->of_node;
	262
9490f01e SH	263	if (cpufreq_dev) {
	264	platform_device_unregister(cpufreq_dev);
	265	cpufreq_dev = NULL;
	266	}
	267
cd52c2a4 SH	268	for_each_available_child_of_node(np, child)
	269	of_clk_del_provider(np);
	270	return 0;
	271	}
	272
	273	static int scpi_clocks_probe(struct platform_device *pdev)
	274	{
	275	int ret;
	276	struct device *dev = &pdev->dev;
	277	struct device_node child, np = dev->of_node;
	278	const struct of_device_id *match;
	279
	280	if (!get_scpi_ops())
	281	return -ENXIO;
	282
	283	for_each_available_child_of_node(np, child) {
	284	match = of_match_node(scpi_clk_match, child);
	285	if (!match)
	286	continue;
	287	ret = scpi_clk_add(dev, child, match);
	288	if (ret) {
	289	scpi_clocks_remove(pdev);
e80cf2e5	290	of_node_put(child);
cd52c2a4 SH	291	return ret;
	292	}
	293	}
9490f01e SH	294	/* Add the virtual cpufreq device */
	295	cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
	296	-1, NULL, 0);
d22eb66b	297	if (IS_ERR(cpufreq_dev))
9490f01e SH	298	pr_warn("unable to register cpufreq device");
9490f01e SH	299
cd52c2a4 SH	300	return 0;
	301	}
	302
	303	static const struct of_device_id scpi_clocks_ids[] = {
	304	{ .compatible = "arm,scpi-clocks", },
	305	{}
	306	};
	307	MODULE_DEVICE_TABLE(of, scpi_clocks_ids);
	308
	309	static struct platform_driver scpi_clocks_driver = {
	310	.driver = {
	311	.name = "scpi_clocks",
	312	.of_match_table = scpi_clocks_ids,
	313	},
	314	.probe = scpi_clocks_probe,
	315	.remove = scpi_clocks_remove,
	316	};
	317	module_platform_driver(scpi_clocks_driver);
	318
	319	MODULE_AUTHOR("Sudeep Holla <sudeep.holla@arm.com>");
	320	MODULE_DESCRIPTION("ARM SCPI clock driver");
	321	MODULE_LICENSE("GPL v2");