[deliverable/linux.git] / drivers / clk / clk-vt8500.c

/*
 * Clock implementation for VIA/Wondermedia SoC's
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>

#define LEGACY_PMC_BASE		0xD8130000

/* All clocks share the same lock as none can be changed concurrently */
static DEFINE_SPINLOCK(_lock);

struct clk_device {
	struct clk_hw	hw;
	void __iomem	*div_reg;
	unsigned int	div_mask;
	void __iomem	*en_reg;
	int		en_bit;
	spinlock_t	*lock;
};

/*
 * Add new PLL_TYPE_x definitions here as required. Use the first known model
 * to support the new type as the name.
 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
 */

#define PLL_TYPE_VT8500		0
#define PLL_TYPE_WM8650		1
#define PLL_TYPE_WM8750		2
#define PLL_TYPE_WM8850		3

struct clk_pll {
	struct clk_hw	hw;
	void __iomem	*reg;
	spinlock_t	*lock;
	int		type;
};

static void __iomem *pmc_base;

static __init void vtwm_set_pmc_base(void)
{
	struct device_node *np =
		of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");

	if (np)
		pmc_base = of_iomap(np, 0);
	else
		pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
	of_node_put(np);

	if (!pmc_base)
		pr_err("%s:of_iomap(pmc) failed\n", __func__);
}

#define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)

#define VT8500_PMC_BUSY_MASK		0x18

static void vt8500_pmc_wait_busy(void)
{
	while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
		cpu_relax();
}

static int vt8500_dclk_enable(struct clk_hw *hw)
{
	struct clk_device *cdev = to_clk_device(hw);
	u32 en_val;
	unsigned long flags = 0;

	spin_lock_irqsave(cdev->lock, flags);

	en_val = readl(cdev->en_reg);
	en_val |= BIT(cdev->en_bit);
	writel(en_val, cdev->en_reg);

	spin_unlock_irqrestore(cdev->lock, flags);
	return 0;
}

static void vt8500_dclk_disable(struct clk_hw *hw)
{
	struct clk_device *cdev = to_clk_device(hw);
	u32 en_val;
	unsigned long flags = 0;

	spin_lock_irqsave(cdev->lock, flags);

	en_val = readl(cdev->en_reg);
	en_val &= ~BIT(cdev->en_bit);
	writel(en_val, cdev->en_reg);

	spin_unlock_irqrestore(cdev->lock, flags);
}

static int vt8500_dclk_is_enabled(struct clk_hw *hw)
{
	struct clk_device *cdev = to_clk_device(hw);
	u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));

	return en_val ? 1 : 0;
}

static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
				unsigned long parent_rate)
{
	struct clk_device *cdev = to_clk_device(hw);
	u32 div = readl(cdev->div_reg) & cdev->div_mask;

	/* Special case for SDMMC devices */
	if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
		div = 64 * (div & 0x1f);

	/* div == 0 is actually the highest divisor */
	if (div == 0)
		div = (cdev->div_mask + 1);

	return parent_rate / div;
}

static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{
	struct clk_device *cdev = to_clk_device(hw);
	u32 divisor;

	if (rate == 0)
		return 0;

	divisor = *prate / rate;

	/* If prate / rate would be decimal, incr the divisor */
	if (rate * divisor < *prate)
		divisor++;

	/*
	 * If this is a request for SDMMC we have to adjust the divisor
	 * when >31 to use the fixed predivisor
	 */
	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
		divisor = 64 * ((divisor / 64) + 1);
	}

	return *prate / divisor;
}

static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	struct clk_device *cdev = to_clk_device(hw);
	u32 divisor;
	unsigned long flags = 0;

	if (rate == 0)
		return 0;

	divisor =  parent_rate / rate;

	if (divisor == cdev->div_mask + 1)
		divisor = 0;

	/* SDMMC mask may need to be corrected before testing if its valid */
	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
		/*
		 * Bit 5 is a fixed /64 predivisor. If the requested divisor
		 * is >31 then correct for the fixed divisor being required.
		 */
		divisor = 0x20 + (divisor / 64);
	}

	if (divisor > cdev->div_mask) {
		pr_err("%s: invalid divisor for clock\n", __func__);
		return -EINVAL;
	}

	spin_lock_irqsave(cdev->lock, flags);

	vt8500_pmc_wait_busy();
	writel(divisor, cdev->div_reg);
	vt8500_pmc_wait_busy();

	spin_unlock_irqrestore(cdev->lock, flags);

	return 0;
}


static const struct clk_ops vt8500_gated_clk_ops = {
	.enable = vt8500_dclk_enable,
	.disable = vt8500_dclk_disable,
	.is_enabled = vt8500_dclk_is_enabled,
};

static const struct clk_ops vt8500_divisor_clk_ops = {
	.round_rate = vt8500_dclk_round_rate,
	.set_rate = vt8500_dclk_set_rate,
	.recalc_rate = vt8500_dclk_recalc_rate,
};

static const struct clk_ops vt8500_gated_divisor_clk_ops = {
	.enable = vt8500_dclk_enable,
	.disable = vt8500_dclk_disable,
	.is_enabled = vt8500_dclk_is_enabled,
	.round_rate = vt8500_dclk_round_rate,
	.set_rate = vt8500_dclk_set_rate,
	.recalc_rate = vt8500_dclk_recalc_rate,
};

#define CLK_INIT_GATED			BIT(0)
#define CLK_INIT_DIVISOR		BIT(1)
#define CLK_INIT_GATED_DIVISOR		(CLK_INIT_DIVISOR | CLK_INIT_GATED)

static __init void vtwm_device_clk_init(struct device_node *node)
{
	u32 en_reg, div_reg;
	struct clk *clk;
	struct clk_device *dev_clk;
	const char *clk_name = node->name;
	const char *parent_name;
	struct clk_init_data init;
	int rc;
	int clk_init_flags = 0;

	if (!pmc_base)
		vtwm_set_pmc_base();

	dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
	if (WARN_ON(!dev_clk))
		return;

	dev_clk->lock = &_lock;

	rc = of_property_read_u32(node, "enable-reg", &en_reg);
	if (!rc) {
		dev_clk->en_reg = pmc_base + en_reg;
		rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
		if (rc) {
			pr_err("%s: enable-bit property required for gated clock\n",
								__func__);
			return;
		}
		clk_init_flags |= CLK_INIT_GATED;
	}

	rc = of_property_read_u32(node, "divisor-reg", &div_reg);
	if (!rc) {
		dev_clk->div_reg = pmc_base + div_reg;
		/*
		 * use 0x1f as the default mask since it covers
		 * almost all the clocks and reduces dts properties
		 */
		dev_clk->div_mask = 0x1f;

		of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
		clk_init_flags |= CLK_INIT_DIVISOR;
	}

	of_property_read_string(node, "clock-output-names", &clk_name);

	switch (clk_init_flags) {
	case CLK_INIT_GATED:
		init.ops = &vt8500_gated_clk_ops;
		break;
	case CLK_INIT_DIVISOR:
		init.ops = &vt8500_divisor_clk_ops;
		break;
	case CLK_INIT_GATED_DIVISOR:
		init.ops = &vt8500_gated_divisor_clk_ops;
		break;
	default:
		pr_err("%s: Invalid clock description in device tree\n",
								__func__);
		kfree(dev_clk);
		return;
	}

	init.name = clk_name;
	init.flags = 0;
	parent_name = of_clk_get_parent_name(node, 0);
	init.parent_names = &parent_name;
	init.num_parents = 1;

	dev_clk->hw.init = &init;

	clk = clk_register(NULL, &dev_clk->hw);
	if (WARN_ON(IS_ERR(clk))) {
		kfree(dev_clk);
		return;
	}
	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	clk_register_clkdev(clk, clk_name, NULL);
}
CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);

/* PLL clock related functions */

#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)

/* Helper macros for PLL_VT8500 */
#define VT8500_PLL_MUL(x)	((x & 0x1F) << 1)
#define VT8500_PLL_DIV(x)	((x & 0x100) ? 1 : 2)

#define VT8500_BITS_TO_FREQ(r, m, d)					\
				((r / d) * m)

#define VT8500_BITS_TO_VAL(m, d)					\
				((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))

/* Helper macros for PLL_WM8650 */
#define WM8650_PLL_MUL(x)	(x & 0x3FF)
#define WM8650_PLL_DIV(x)	(((x >> 10) & 7) * (1 << ((x >> 13) & 3)))

#define WM8650_BITS_TO_FREQ(r, m, d1, d2)				\
				(r * m / (d1 * (1 << d2)))

#define WM8650_BITS_TO_VAL(m, d1, d2)					\
				((d2 << 13) | (d1 << 10) | (m & 0x3FF))

/* Helper macros for PLL_WM8750 */
#define WM8750_PLL_MUL(x)	(((x >> 16) & 0xFF) + 1)
#define WM8750_PLL_DIV(x)	((((x >> 8) & 1) + 1) * (1 << (x & 7)))

#define WM8750_BITS_TO_FREQ(r, m, d1, d2)				\
				(r * (m+1) / ((d1+1) * (1 << d2)))

#define WM8750_BITS_TO_VAL(f, m, d1, d2)				\
		((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)

/* Helper macros for PLL_WM8850 */
#define WM8850_PLL_MUL(x)	((((x >> 16) & 0x7F) + 1) * 2)
#define WM8850_PLL_DIV(x)	((((x >> 8) & 1) + 1) * (1 << (x & 3)))

#define WM8850_BITS_TO_FREQ(r, m, d1, d2)				\
				(r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))

#define WM8850_BITS_TO_VAL(m, d1, d2)					\
		((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)

static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
				u32 *multiplier, u32 *prediv)
{
	unsigned long tclk;

	/* sanity check */
	if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
		pr_err("%s: requested rate out of range\n", __func__);
		*multiplier = 0;
		*prediv = 1;
		return;
	}
	if (rate <= parent_rate * 31)
		/* use the prediv to double the resolution */
		*prediv = 2;
	else
		*prediv = 1;

	*multiplier = rate / (parent_rate / *prediv);
	tclk = (parent_rate / *prediv) * *multiplier;

	if (tclk != rate)
		pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
								rate, tclk);
}

static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
				u32 *multiplier, u32 *divisor1, u32 *divisor2)
{
	u32 mul, div1;
	int div2;
	u32 best_mul, best_div1, best_div2;
	unsigned long tclk, rate_err, best_err;

	best_err = (unsigned long)-1;

	/* Find the closest match (lower or equal to requested) */
	for (div1 = 5; div1 >= 3; div1--)
		for (div2 = 3; div2 >= 0; div2--)
			for (mul = 3; mul <= 1023; mul++) {
				tclk = parent_rate * mul / (div1 * (1 << div2));
				if (tclk > rate)
					continue;
				/* error will always be +ve */
				rate_err = rate - tclk;
				if (rate_err == 0) {
					*multiplier = mul;
					*divisor1 = div1;
					*divisor2 = div2;
					return;
				}

				if (rate_err < best_err) {
					best_err = rate_err;
					best_mul = mul;
					best_div1 = div1;
					best_div2 = div2;
				}
			}

	/* if we got here, it wasn't an exact match */
	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
							rate - best_err);
	*multiplier = best_mul;
	*divisor1 = best_div1;
	*divisor2 = best_div2;
}

static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
{
	/* calculate frequency (MHz) after pre-divisor */
	u32 freq = (parent_rate / 1000000) / (divisor1 + 1);

	if ((freq < 10) || (freq > 200))
		pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
				__func__, freq);

	if (freq >= 166)
		return 7;
	else if (freq >= 104)
		return 6;
	else if (freq >= 65)
		return 5;
	else if (freq >= 42)
		return 4;
	else if (freq >= 26)
		return 3;
	else if (freq >= 16)
		return 2;
	else if (freq >= 10)
		return 1;

	return 0;
}

static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
				u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
{
	u32 mul;
	int div1, div2;
	u32 best_mul, best_div1, best_div2;
	unsigned long tclk, rate_err, best_err;

	best_err = (unsigned long)-1;

	/* Find the closest match (lower or equal to requested) */
	for (div1 = 1; div1 >= 0; div1--)
		for (div2 = 7; div2 >= 0; div2--)
			for (mul = 0; mul <= 255; mul++) {
				tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
				if (tclk > rate)
					continue;
				/* error will always be +ve */
				rate_err = rate - tclk;
				if (rate_err == 0) {
					*filter = wm8750_get_filter(parent_rate, div1);
					*multiplier = mul;
					*divisor1 = div1;
					*divisor2 = div2;
					return;
				}

				if (rate_err < best_err) {
					best_err = rate_err;
					best_mul = mul;
					best_div1 = div1;
					best_div2 = div2;
				}
			}

	/* if we got here, it wasn't an exact match */
	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
							rate - best_err);

	*filter = wm8750_get_filter(parent_rate, best_div1);
	*multiplier = best_mul;
	*divisor1 = best_div1;
	*divisor2 = best_div2;
}

static void wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
				u32 *multiplier, u32 *divisor1, u32 *divisor2)
{
	u32 mul;
	int div1, div2;
	u32 best_mul, best_div1, best_div2;
	unsigned long tclk, rate_err, best_err;

	best_err = (unsigned long)-1;

	/* Find the closest match (lower or equal to requested) */
	for (div1 = 1; div1 >= 0; div1--)
		for (div2 = 3; div2 >= 0; div2--)
			for (mul = 0; mul <= 127; mul++) {
				tclk = parent_rate * ((mul + 1) * 2) /
						((div1 + 1) * (1 << div2));
				if (tclk > rate)
					continue;
				/* error will always be +ve */
				rate_err = rate - tclk;
				if (rate_err == 0) {
					*multiplier = mul;
					*divisor1 = div1;
					*divisor2 = div2;
					return;
				}

				if (rate_err < best_err) {
					best_err = rate_err;
					best_mul = mul;
					best_div1 = div1;
					best_div2 = div2;
				}
			}

	/* if we got here, it wasn't an exact match */
	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
							rate - best_err);

	*multiplier = best_mul;
	*divisor1 = best_div1;
	*divisor2 = best_div2;
}

static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	struct clk_pll *pll = to_clk_pll(hw);
	u32 filter, mul, div1, div2;
	u32 pll_val;
	unsigned long flags = 0;

	/* sanity check */

	switch (pll->type) {
	case PLL_TYPE_VT8500:
		vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
		pll_val = VT8500_BITS_TO_VAL(mul, div1);
		break;
	case PLL_TYPE_WM8650:
		wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
		pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
		break;
	case PLL_TYPE_WM8750:
		wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
		pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
		break;
	case PLL_TYPE_WM8850:
		wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
		pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
		break;
	default:
		pr_err("%s: invalid pll type\n", __func__);
		return 0;
	}

	spin_lock_irqsave(pll->lock, flags);

	vt8500_pmc_wait_busy();
	writel(pll_val, pll->reg);
	vt8500_pmc_wait_busy();

	spin_unlock_irqrestore(pll->lock, flags);

	return 0;
}

static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{
	struct clk_pll *pll = to_clk_pll(hw);
	u32 filter, mul, div1, div2;
	long round_rate;

	switch (pll->type) {
	case PLL_TYPE_VT8500:
		vt8500_find_pll_bits(rate, *prate, &mul, &div1);
		round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
		break;
	case PLL_TYPE_WM8650:
		wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
		round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
		break;
	case PLL_TYPE_WM8750:
		wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
		round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
		break;
	case PLL_TYPE_WM8850:
		wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
		round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
		break;
	default:
		round_rate = 0;
	}

	return round_rate;
}

static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
				unsigned long parent_rate)
{
	struct clk_pll *pll = to_clk_pll(hw);
	u32 pll_val = readl(pll->reg);
	unsigned long pll_freq;

	switch (pll->type) {
	case PLL_TYPE_VT8500:
		pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
		pll_freq /= VT8500_PLL_DIV(pll_val);
		break;
	case PLL_TYPE_WM8650:
		pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
		pll_freq /= WM8650_PLL_DIV(pll_val);
		break;
	case PLL_TYPE_WM8750:
		pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
		pll_freq /= WM8750_PLL_DIV(pll_val);
		break;
	case PLL_TYPE_WM8850:
		pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
		pll_freq /= WM8850_PLL_DIV(pll_val);
		break;
	default:
		pll_freq = 0;
	}

	return pll_freq;
}

static const struct clk_ops vtwm_pll_ops = {
	.round_rate = vtwm_pll_round_rate,
	.set_rate = vtwm_pll_set_rate,
	.recalc_rate = vtwm_pll_recalc_rate,
};

static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
{
	u32 reg;
	struct clk *clk;
	struct clk_pll *pll_clk;
	const char *clk_name = node->name;
	const char *parent_name;
	struct clk_init_data init;
	int rc;

	if (!pmc_base)
		vtwm_set_pmc_base();

	rc = of_property_read_u32(node, "reg", &reg);
	if (WARN_ON(rc))
		return;

	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
	if (WARN_ON(!pll_clk))
		return;

	pll_clk->reg = pmc_base + reg;
	pll_clk->lock = &_lock;
	pll_clk->type = pll_type;

	of_property_read_string(node, "clock-output-names", &clk_name);

	init.name = clk_name;
	init.ops = &vtwm_pll_ops;
	init.flags = 0;
	parent_name = of_clk_get_parent_name(node, 0);
	init.parent_names = &parent_name;
	init.num_parents = 1;

	pll_clk->hw.init = &init;

	clk = clk_register(NULL, &pll_clk->hw);
	if (WARN_ON(IS_ERR(clk))) {
		kfree(pll_clk);
		return;
	}
	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	clk_register_clkdev(clk, clk_name, NULL);
}


/* Wrappers for initialization functions */

static void __init vt8500_pll_init(struct device_node *node)
{
	vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
}
CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);

static void __init wm8650_pll_init(struct device_node *node)
{
	vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
}
CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);

static void __init wm8750_pll_init(struct device_node *node)
{
	vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
}
CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);

static void __init wm8850_pll_init(struct device_node *node)
{
	vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
}
CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
Commit	Line	Data
85814d69 TP	1	/*
	2	* Clock implementation for VIA/Wondermedia SoC's
	3	* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	*/
	15
	16	#include <linux/io.h>
	17	#include <linux/of.h>
f9e4a18d	18	#include <linux/of_address.h>
85814d69 TP	19	#include <linux/slab.h>
	20	#include <linux/bitops.h>
	21	#include <linux/clkdev.h>
	22	#include <linux/clk-provider.h>
	23
f9e4a18d SH	24	#define LEGACY_PMC_BASE 0xD8130000
f9e4a18d SH	25
85814d69 TP	26	/* All clocks share the same lock as none can be changed concurrently */
	27	static DEFINE_SPINLOCK(_lock);
	28
	29	struct clk_device {
	30	struct clk_hw hw;
	31	void __iomem *div_reg;
	32	unsigned int div_mask;
	33	void __iomem *en_reg;
	34	int en_bit;
	35	spinlock_t *lock;
	36	};
	37
	38	/*
	39	* Add new PLL_TYPE_x definitions here as required. Use the first known model
	40	* to support the new type as the name.
	41	* Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
	42	* vtwm_pll_set_rate() to handle the new PLL_TYPE_x
	43	*/
	44
	45	#define PLL_TYPE_VT8500 0
	46	#define PLL_TYPE_WM8650 1
abb165a8	47	#define PLL_TYPE_WM8750 2
518d4709	48	#define PLL_TYPE_WM8850 3
85814d69 TP	49
	50	struct clk_pll {
	51	struct clk_hw hw;
	52	void __iomem *reg;
	53	spinlock_t *lock;
	54	int type;
	55	};
	56
	57	static void __iomem *pmc_base;
	58
f9e4a18d SH	59	static __init void vtwm_set_pmc_base(void)
	60	{
	61	struct device_node *np =
	62	of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
	63
	64	if (np)
	65	pmc_base = of_iomap(np, 0);
	66	else
	67	pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
	68	of_node_put(np);
	69
	70	if (!pmc_base)
	71	pr_err("%s:of_iomap(pmc) failed\n", __func__);
	72	}
	73
85814d69 TP	74	#define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
	75
	76	#define VT8500_PMC_BUSY_MASK 0x18
	77
	78	static void vt8500_pmc_wait_busy(void)
	79	{
	80	while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
	81	cpu_relax();
	82	}
	83
	84	static int vt8500_dclk_enable(struct clk_hw *hw)
	85	{
	86	struct clk_device *cdev = to_clk_device(hw);
	87	u32 en_val;
	88	unsigned long flags = 0;
	89
	90	spin_lock_irqsave(cdev->lock, flags);
	91
	92	en_val = readl(cdev->en_reg);
	93	en_val \|= BIT(cdev->en_bit);
	94	writel(en_val, cdev->en_reg);
	95
	96	spin_unlock_irqrestore(cdev->lock, flags);
	97	return 0;
	98	}
	99
	100	static void vt8500_dclk_disable(struct clk_hw *hw)
	101	{
	102	struct clk_device *cdev = to_clk_device(hw);
	103	u32 en_val;
	104	unsigned long flags = 0;
	105
	106	spin_lock_irqsave(cdev->lock, flags);
	107
	108	en_val = readl(cdev->en_reg);
	109	en_val &= ~BIT(cdev->en_bit);
	110	writel(en_val, cdev->en_reg);
	111
	112	spin_unlock_irqrestore(cdev->lock, flags);
	113	}
	114
	115	static int vt8500_dclk_is_enabled(struct clk_hw *hw)
	116	{
	117	struct clk_device *cdev = to_clk_device(hw);
	118	u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
	119
	120	return en_val ? 1 : 0;
	121	}
	122
	123	static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
	124	unsigned long parent_rate)
	125	{
	126	struct clk_device *cdev = to_clk_device(hw);
	127	u32 div = readl(cdev->div_reg) & cdev->div_mask;
	128
	129	/* Special case for SDMMC devices */
	130	if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
	131	div = 64 * (div & 0x1f);
	132
	133	/* div == 0 is actually the highest divisor */
	134	if (div == 0)
	135	div = (cdev->div_mask + 1);
	136
	137	return parent_rate / div;
138	}
139
140	static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
141	unsigned long *prate)
142	{
973e1d1d	143	struct clk_device *cdev = to_clk_device(hw);
58eb5a67 TP	144	u32 divisor;
	145
	146	if (rate == 0)
	147	return 0;
	148
	149	divisor = *prate / rate;
85814d69	150
72480014 TP	151	/* If prate / rate would be decimal, incr the divisor */
	152	if (rate * divisor < *prate)
	153	divisor++;
	154
973e1d1d TP	155	/*
	156	* If this is a request for SDMMC we have to adjust the divisor
	157	* when >31 to use the fixed predivisor
	158	*/
	159	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
	160	divisor = 64 * ((divisor / 64) + 1);
	161	}
	162
85814d69 TP	163	return *prate / divisor;
	164	}
	165
	166	static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
	167	unsigned long parent_rate)
	168	{
	169	struct clk_device *cdev = to_clk_device(hw);
58eb5a67	170	u32 divisor;
85814d69 TP	171	unsigned long flags = 0;
85814d69 TP	172
58eb5a67 TP	173	if (rate == 0)
	174	return 0;
	175
	176	divisor = parent_rate / rate;
	177
85814d69 TP	178	if (divisor == cdev->div_mask + 1)
	179	divisor = 0;
	180
973e1d1d TP	181	/* SDMMC mask may need to be corrected before testing if its valid */
	182	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
	183	/*
	184	* Bit 5 is a fixed /64 predivisor. If the requested divisor
	185	* is >31 then correct for the fixed divisor being required.
	186	*/
	187	divisor = 0x20 + (divisor / 64);
	188	}
	189
85814d69 TP	190	if (divisor > cdev->div_mask) {
	191	pr_err("%s: invalid divisor for clock\n", __func__);
	192	return -EINVAL;
	193	}
	194
	195	spin_lock_irqsave(cdev->lock, flags);
	196
	197	vt8500_pmc_wait_busy();
	198	writel(divisor, cdev->div_reg);
	199	vt8500_pmc_wait_busy();
	200
419e321d	201	spin_unlock_irqrestore(cdev->lock, flags);
85814d69 TP	202
	203	return 0;
	204	}
	205
	206
	207	static const struct clk_ops vt8500_gated_clk_ops = {
	208	.enable = vt8500_dclk_enable,
	209	.disable = vt8500_dclk_disable,
	210	.is_enabled = vt8500_dclk_is_enabled,
	211	};
	212
	213	static const struct clk_ops vt8500_divisor_clk_ops = {
	214	.round_rate = vt8500_dclk_round_rate,
	215	.set_rate = vt8500_dclk_set_rate,
	216	.recalc_rate = vt8500_dclk_recalc_rate,
	217	};
	218
	219	static const struct clk_ops vt8500_gated_divisor_clk_ops = {
	220	.enable = vt8500_dclk_enable,
	221	.disable = vt8500_dclk_disable,
	222	.is_enabled = vt8500_dclk_is_enabled,
	223	.round_rate = vt8500_dclk_round_rate,
	224	.set_rate = vt8500_dclk_set_rate,
	225	.recalc_rate = vt8500_dclk_recalc_rate,
	226	};
	227
	228	#define CLK_INIT_GATED BIT(0)
	229	#define CLK_INIT_DIVISOR BIT(1)
	230	#define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR \| CLK_INIT_GATED)
	231
	232	static __init void vtwm_device_clk_init(struct device_node *node)
	233	{
	234	u32 en_reg, div_reg;
	235	struct clk *clk;
	236	struct clk_device *dev_clk;
	237	const char *clk_name = node->name;
	238	const char *parent_name;
	239	struct clk_init_data init;
	240	int rc;
	241	int clk_init_flags = 0;
	242
f9e4a18d SH	243	if (!pmc_base)
	244	vtwm_set_pmc_base();
	245
85814d69 TP	246	dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
	247	if (WARN_ON(!dev_clk))
	248	return;
	249
	250	dev_clk->lock = &_lock;
	251
	252	rc = of_property_read_u32(node, "enable-reg", &en_reg);
	253	if (!rc) {
	254	dev_clk->en_reg = pmc_base + en_reg;
	255	rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
	256	if (rc) {
	257	pr_err("%s: enable-bit property required for gated clock\n",
	258	__func__);
	259	return;
	260	}
	261	clk_init_flags \|= CLK_INIT_GATED;
	262	}
	263
	264	rc = of_property_read_u32(node, "divisor-reg", &div_reg);
	265	if (!rc) {
	266	dev_clk->div_reg = pmc_base + div_reg;
	267	/*
	268	* use 0x1f as the default mask since it covers
	269	* almost all the clocks and reduces dts properties
	270	*/
	271	dev_clk->div_mask = 0x1f;
	272
	273	of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
	274	clk_init_flags \|= CLK_INIT_DIVISOR;
	275	}
	276
	277	of_property_read_string(node, "clock-output-names", &clk_name);
	278
	279	switch (clk_init_flags) {
	280	case CLK_INIT_GATED:
	281	init.ops = &vt8500_gated_clk_ops;
	282	break;
	283	case CLK_INIT_DIVISOR:
	284	init.ops = &vt8500_divisor_clk_ops;
	285	break;
	286	case CLK_INIT_GATED_DIVISOR:
	287	init.ops = &vt8500_gated_divisor_clk_ops;
	288	break;
	289	default:
	290	pr_err("%s: Invalid clock description in device tree\n",
	291	__func__);
	292	kfree(dev_clk);
	293	return;
	294	}
	295
	296	init.name = clk_name;
	297	init.flags = 0;
	298	parent_name = of_clk_get_parent_name(node, 0);
	299	init.parent_names = &parent_name;
	300	init.num_parents = 1;
	301
	302	dev_clk->hw.init = &init;
	303
	304	clk = clk_register(NULL, &dev_clk->hw);
	305	if (WARN_ON(IS_ERR(clk))) {
	306	kfree(dev_clk);
	307	return;
	308	}
	309	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
310	clk_register_clkdev(clk, clk_name, NULL);
311	}
5b6e0adb	312	CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
85814d69 TP	313
	314	/* PLL clock related functions */
	315
	316	#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
	317
	318	/* Helper macros for PLL_VT8500 */
	319	#define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
	320	#define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
	321
	322	#define VT8500_BITS_TO_FREQ(r, m, d) \
	323	((r / d) * m)
	324
	325	#define VT8500_BITS_TO_VAL(m, d) \
	326	((d == 2 ? 0 : 0x100) \| ((m >> 1) & 0x1F))
	327
	328	/* Helper macros for PLL_WM8650 */
	329	#define WM8650_PLL_MUL(x) (x & 0x3FF)
	330	#define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
	331
	332	#define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
	333	(r * m / (d1 * (1 << d2)))
	334
	335	#define WM8650_BITS_TO_VAL(m, d1, d2) \
	336	((d2 << 13) \| (d1 << 10) \| (m & 0x3FF))
	337
abb165a8 TP	338	/* Helper macros for PLL_WM8750 */
	339	#define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
	340	#define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
	341
	342	#define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
	343	(r * (m+1) / ((d1+1) * (1 << d2)))
	344
	345	#define WM8750_BITS_TO_VAL(f, m, d1, d2) \
	346	((f << 24) \| ((m - 1) << 16) \| ((d1 - 1) << 8) \| d2)
	347
518d4709 TP	348	/* Helper macros for PLL_WM8850 */
	349	#define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2)
	350	#define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
	351
	352	#define WM8850_BITS_TO_FREQ(r, m, d1, d2) \
	353	(r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
	354
	355	#define WM8850_BITS_TO_VAL(m, d1, d2) \
	356	((((m / 2) - 1) << 16) \| ((d1 - 1) << 8) \| d2)
85814d69 TP	357
	358	static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
	359	u32 multiplier, u32 prediv)
	360	{
	361	unsigned long tclk;
	362
	363	/* sanity check */
	364	if ((rate < parent_rate * 4) \|\| (rate > parent_rate * 62)) {
	365	pr_err("%s: requested rate out of range\n", __func__);
	366	*multiplier = 0;
	367	*prediv = 1;
	368	return;
	369	}
	370	if (rate <= parent_rate * 31)
	371	/* use the prediv to double the resolution */
	372	*prediv = 2;
	373	else
	374	*prediv = 1;
	375
	376	multiplier = rate / (parent_rate / prediv);
	377	tclk = (parent_rate / prediv) *multiplier;
	378
	379	if (tclk != rate)
	380	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
	381	rate, tclk);
	382	}
	383
	384	static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
	385	u32 multiplier, u32 divisor1, u32 *divisor2)
	386	{
090341b0 AH	387	u32 mul, div1;
090341b0 AH	388	int div2;
85814d69 TP	389	u32 best_mul, best_div1, best_div2;
	390	unsigned long tclk, rate_err, best_err;
	391
	392	best_err = (unsigned long)-1;
	393
	394	/* Find the closest match (lower or equal to requested) */
	395	for (div1 = 5; div1 >= 3; div1--)
	396	for (div2 = 3; div2 >= 0; div2--)
	397	for (mul = 3; mul <= 1023; mul++) {
	398	tclk = parent_rate * mul / (div1 * (1 << div2));
	399	if (tclk > rate)
	400	continue;
	401	/* error will always be +ve */
	402	rate_err = rate - tclk;
	403	if (rate_err == 0) {
	404	*multiplier = mul;
	405	*divisor1 = div1;
	406	*divisor2 = div2;
	407	return;
	408	}
	409
	410	if (rate_err < best_err) {
	411	best_err = rate_err;
	412	best_mul = mul;
	413	best_div1 = div1;
	414	best_div2 = div2;
	415	}
	416	}
	417
	418	/* if we got here, it wasn't an exact match */
	419	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
	420	rate - best_err);
35a5db55 TP	421	*multiplier = best_mul;
	422	*divisor1 = best_div1;
	423	*divisor2 = best_div2;
85814d69 TP	424	}
85814d69 TP	425
abb165a8 TP	426	static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
	427	{
	428	/* calculate frequency (MHz) after pre-divisor */
	429	u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
	430
	431	if ((freq < 10) \|\| (freq > 200))
	432	pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
	433	__func__, freq);
	434
	435	if (freq >= 166)
	436	return 7;
	437	else if (freq >= 104)
	438	return 6;
	439	else if (freq >= 65)
	440	return 5;
	441	else if (freq >= 42)
	442	return 4;
	443	else if (freq >= 26)
	444	return 3;
	445	else if (freq >= 16)
	446	return 2;
	447	else if (freq >= 10)
	448	return 1;
	449
	450	return 0;
	451	}
	452
	453	static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
	454	u32 filter, u32 multiplier, u32 divisor1, u32 divisor2)
	455	{
090341b0 AH	456	u32 mul;
090341b0 AH	457	int div1, div2;
abb165a8 TP	458	u32 best_mul, best_div1, best_div2;
	459	unsigned long tclk, rate_err, best_err;
	460
	461	best_err = (unsigned long)-1;
	462
	463	/* Find the closest match (lower or equal to requested) */
	464	for (div1 = 1; div1 >= 0; div1--)
	465	for (div2 = 7; div2 >= 0; div2--)
	466	for (mul = 0; mul <= 255; mul++) {
	467	tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
	468	if (tclk > rate)
	469	continue;
	470	/* error will always be +ve */
	471	rate_err = rate - tclk;
	472	if (rate_err == 0) {
	473	*filter = wm8750_get_filter(parent_rate, div1);
	474	*multiplier = mul;
	475	*divisor1 = div1;
	476	*divisor2 = div2;
	477	return;
	478	}
	479
	480	if (rate_err < best_err) {
	481	best_err = rate_err;
	482	best_mul = mul;
	483	best_div1 = div1;
	484	best_div2 = div2;
	485	}
	486	}
	487
	488	/* if we got here, it wasn't an exact match */
	489	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
	490	rate - best_err);
	491
	492	*filter = wm8750_get_filter(parent_rate, best_div1);
	493	*multiplier = best_mul;
	494	*divisor1 = best_div1;
	495	*divisor2 = best_div2;
	496	}
	497
518d4709 TP	498	static void wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
	499	u32 multiplier, u32 divisor1, u32 *divisor2)
	500	{
090341b0 AH	501	u32 mul;
090341b0 AH	502	int div1, div2;
518d4709 TP	503	u32 best_mul, best_div1, best_div2;
	504	unsigned long tclk, rate_err, best_err;
	505
	506	best_err = (unsigned long)-1;
	507
	508	/* Find the closest match (lower or equal to requested) */
	509	for (div1 = 1; div1 >= 0; div1--)
	510	for (div2 = 3; div2 >= 0; div2--)
	511	for (mul = 0; mul <= 127; mul++) {
	512	tclk = parent_rate * ((mul + 1) * 2) /
	513	((div1 + 1) * (1 << div2));
	514	if (tclk > rate)
	515	continue;
	516	/* error will always be +ve */
	517	rate_err = rate - tclk;
	518	if (rate_err == 0) {
	519	*multiplier = mul;
	520	*divisor1 = div1;
	521	*divisor2 = div2;
	522	return;
	523	}
	524
	525	if (rate_err < best_err) {
	526	best_err = rate_err;
	527	best_mul = mul;
	528	best_div1 = div1;
	529	best_div2 = div2;
	530	}
	531	}
	532
	533	/* if we got here, it wasn't an exact match */
	534	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
	535	rate - best_err);
	536
	537	*multiplier = best_mul;
	538	*divisor1 = best_div1;
	539	*divisor2 = best_div2;
	540	}
	541
85814d69 TP	542	static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
	543	unsigned long parent_rate)
	544	{
	545	struct clk_pll *pll = to_clk_pll(hw);
abb165a8	546	u32 filter, mul, div1, div2;
85814d69 TP	547	u32 pll_val;
	548	unsigned long flags = 0;
	549
	550	/* sanity check */
	551
	552	switch (pll->type) {
	553	case PLL_TYPE_VT8500:
	554	vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
	555	pll_val = VT8500_BITS_TO_VAL(mul, div1);
	556	break;
	557	case PLL_TYPE_WM8650:
	558	wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
	559	pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
	560	break;
abb165a8 TP	561	case PLL_TYPE_WM8750:
	562	wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
	563	pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
bdca21ec	564	break;
518d4709 TP	565	case PLL_TYPE_WM8850:
	566	wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
	567	pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
	568	break;
85814d69 TP	569	default:
	570	pr_err("%s: invalid pll type\n", __func__);
	571	return 0;
	572	}
	573
	574	spin_lock_irqsave(pll->lock, flags);
	575
	576	vt8500_pmc_wait_busy();
	577	writel(pll_val, pll->reg);
	578	vt8500_pmc_wait_busy();
	579
	580	spin_unlock_irqrestore(pll->lock, flags);
	581
	582	return 0;
	583	}
	584
	585	static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
	586	unsigned long *prate)
	587	{
	588	struct clk_pll *pll = to_clk_pll(hw);
abb165a8	589	u32 filter, mul, div1, div2;
85814d69 TP	590	long round_rate;
	591
	592	switch (pll->type) {
	593	case PLL_TYPE_VT8500:
	594	vt8500_find_pll_bits(rate, *prate, &mul, &div1);
	595	round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
	596	break;
	597	case PLL_TYPE_WM8650:
	598	wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
	599	round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
	600	break;
abb165a8 TP	601	case PLL_TYPE_WM8750:
	602	wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
	603	round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
bdca21ec	604	break;
518d4709 TP	605	case PLL_TYPE_WM8850:
	606	wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
	607	round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
	608	break;
85814d69 TP	609	default:
	610	round_rate = 0;
	611	}
	612
	613	return round_rate;
	614	}
	615
	616	static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
	617	unsigned long parent_rate)
	618	{
	619	struct clk_pll *pll = to_clk_pll(hw);
	620	u32 pll_val = readl(pll->reg);
	621	unsigned long pll_freq;
	622
	623	switch (pll->type) {
	624	case PLL_TYPE_VT8500:
	625	pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
	626	pll_freq /= VT8500_PLL_DIV(pll_val);
	627	break;
	628	case PLL_TYPE_WM8650:
	629	pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
	630	pll_freq /= WM8650_PLL_DIV(pll_val);
	631	break;
abb165a8 TP	632	case PLL_TYPE_WM8750:
	633	pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
	634	pll_freq /= WM8750_PLL_DIV(pll_val);
	635	break;
518d4709 TP	636	case PLL_TYPE_WM8850:
	637	pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
	638	pll_freq /= WM8850_PLL_DIV(pll_val);
	639	break;
85814d69 TP	640	default:
	641	pll_freq = 0;
	642	}
	643
	644	return pll_freq;
	645	}
	646
7acc3bca	647	static const struct clk_ops vtwm_pll_ops = {
85814d69 TP	648	.round_rate = vtwm_pll_round_rate,
	649	.set_rate = vtwm_pll_set_rate,
	650	.recalc_rate = vtwm_pll_recalc_rate,
	651	};
	652
	653	static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
	654	{
	655	u32 reg;
	656	struct clk *clk;
	657	struct clk_pll *pll_clk;
	658	const char *clk_name = node->name;
	659	const char *parent_name;
	660	struct clk_init_data init;
	661	int rc;
	662
f9e4a18d SH	663	if (!pmc_base)
	664	vtwm_set_pmc_base();
	665
85814d69 TP	666	rc = of_property_read_u32(node, "reg", &reg);
	667	if (WARN_ON(rc))
	668	return;
	669
	670	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
	671	if (WARN_ON(!pll_clk))
	672	return;
	673
	674	pll_clk->reg = pmc_base + reg;
	675	pll_clk->lock = &_lock;
	676	pll_clk->type = pll_type;
	677
	678	of_property_read_string(node, "clock-output-names", &clk_name);
	679
	680	init.name = clk_name;
	681	init.ops = &vtwm_pll_ops;
	682	init.flags = 0;
	683	parent_name = of_clk_get_parent_name(node, 0);
	684	init.parent_names = &parent_name;
	685	init.num_parents = 1;
	686
	687	pll_clk->hw.init = &init;
	688
	689	clk = clk_register(NULL, &pll_clk->hw);
	690	if (WARN_ON(IS_ERR(clk))) {
	691	kfree(pll_clk);
	692	return;
	693	}
	694	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	695	clk_register_clkdev(clk, clk_name, NULL);
	696	}
	697
	698
	699	/* Wrappers for initialization functions */
	700
	701	static void __init vt8500_pll_init(struct device_node *node)
	702	{
	703	vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
	704	}
5b6e0adb	705	CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
85814d69 TP	706
	707	static void __init wm8650_pll_init(struct device_node *node)
	708	{
	709	vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
	710	}
5b6e0adb	711	CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
85814d69	712
abb165a8 TP	713	static void __init wm8750_pll_init(struct device_node *node)
	714	{
	715	vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
	716	}
5b6e0adb	717	CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
85814d69	718
518d4709 TP	719	static void __init wm8850_pll_init(struct device_node *node)
	720	{
	721	vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
	722	}
	723	CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);