[deliverable/linux.git] / drivers / clk / clk-xgene.c

/*
 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
 *
 * Copyright (c) 2013, Applied Micro Circuits Corporation
 * Author: Loc Ho <lho@apm.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>

/* Register SCU_PCPPLL bit fields */
#define N_DIV_RD(src)			(((src) & 0x000001ff))

/* Register SCU_SOCPLL bit fields */
#define CLKR_RD(src)			(((src) & 0x07000000)>>24)
#define CLKOD_RD(src)			(((src) & 0x00300000)>>20)
#define REGSPEC_RESET_F1_MASK		0x00010000
#define CLKF_RD(src)			(((src) & 0x000001ff))

#define XGENE_CLK_DRIVER_VER		"0.1"

static DEFINE_SPINLOCK(clk_lock);

static inline u32 xgene_clk_read(void __iomem *csr)
{
	return readl_relaxed(csr);
}

static inline void xgene_clk_write(u32 data, void __iomem *csr)
{
	return writel_relaxed(data, csr);
}

/* PLL Clock */
enum xgene_pll_type {
	PLL_TYPE_PCP = 0,
	PLL_TYPE_SOC = 1,
};

struct xgene_clk_pll {
	struct clk_hw	hw;
	void __iomem	*reg;
	spinlock_t	*lock;
	u32		pll_offset;
	enum xgene_pll_type	type;
};

#define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)

static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
{
	struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
	u32 data;

	data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
	pr_debug("%s pll %s\n", clk_hw_get_name(hw),
		data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");

	return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
}

static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
				unsigned long parent_rate)
{
	struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
	unsigned long fref;
	unsigned long fvco;
	u32 pll;
	u32 nref;
	u32 nout;
	u32 nfb;

	pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);

	if (pllclk->type == PLL_TYPE_PCP) {
		/*
		 * PLL VCO = Reference clock * NF
		 * PCP PLL = PLL_VCO / 2
		 */
		nout = 2;
		fvco = parent_rate * (N_DIV_RD(pll) + 4);
	} else {
		/*
		 * Fref = Reference Clock / NREF;
		 * Fvco = Fref * NFB;
		 * Fout = Fvco / NOUT;
		 */
		nref = CLKR_RD(pll) + 1;
		nout = CLKOD_RD(pll) + 1;
		nfb = CLKF_RD(pll);
		fref = parent_rate / nref;
		fvco = fref * nfb;
	}
	pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
		fvco / nout, parent_rate);

	return fvco / nout;
}

static const struct clk_ops xgene_clk_pll_ops = {
	.is_enabled = xgene_clk_pll_is_enabled,
	.recalc_rate = xgene_clk_pll_recalc_rate,
};

static struct clk *xgene_register_clk_pll(struct device *dev,
	const char *name, const char *parent_name,
	unsigned long flags, void __iomem *reg, u32 pll_offset,
	u32 type, spinlock_t *lock)
{
	struct xgene_clk_pll *apmclk;
	struct clk *clk;
	struct clk_init_data init;

	/* allocate the APM clock structure */
	apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
	if (!apmclk) {
		pr_err("%s: could not allocate APM clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	init.ops = &xgene_clk_pll_ops;
	init.flags = flags;
	init.parent_names = parent_name ? &parent_name : NULL;
	init.num_parents = parent_name ? 1 : 0;

	apmclk->reg = reg;
	apmclk->lock = lock;
	apmclk->pll_offset = pll_offset;
	apmclk->type = type;
	apmclk->hw.init = &init;

	/* Register the clock */
	clk = clk_register(dev, &apmclk->hw);
	if (IS_ERR(clk)) {
		pr_err("%s: could not register clk %s\n", __func__, name);
		kfree(apmclk);
		return NULL;
	}
	return clk;
}

static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
{
        const char *clk_name = np->full_name;
        struct clk *clk;
        void __iomem *reg;

        reg = of_iomap(np, 0);
        if (reg == NULL) {
                pr_err("Unable to map CSR register for %s\n", np->full_name);
                return;
        }
        of_property_read_string(np, "clock-output-names", &clk_name);
        clk = xgene_register_clk_pll(NULL,
                        clk_name, of_clk_get_parent_name(np, 0),
                        CLK_IS_ROOT, reg, 0, pll_type, &clk_lock);
        if (!IS_ERR(clk)) {
                of_clk_add_provider(np, of_clk_src_simple_get, clk);
                clk_register_clkdev(clk, clk_name, NULL);
                pr_debug("Add %s clock PLL\n", clk_name);
        }
}

static void xgene_socpllclk_init(struct device_node *np)
{
	xgene_pllclk_init(np, PLL_TYPE_SOC);
}

static void xgene_pcppllclk_init(struct device_node *np)
{
	xgene_pllclk_init(np, PLL_TYPE_PCP);
}

/* IP Clock */
struct xgene_dev_parameters {
	void __iomem *csr_reg;		/* CSR for IP clock */
	u32 reg_clk_offset;		/* Offset to clock enable CSR */
	u32 reg_clk_mask;		/* Mask bit for clock enable */
	u32 reg_csr_offset;		/* Offset to CSR reset */
	u32 reg_csr_mask;		/* Mask bit for disable CSR reset */
	void __iomem *divider_reg;	/* CSR for divider */
	u32 reg_divider_offset;		/* Offset to divider register */
	u32 reg_divider_shift;		/* Bit shift to divider field */
	u32 reg_divider_width;		/* Width of the bit to divider field */
};

struct xgene_clk {
	struct clk_hw	hw;
	spinlock_t	*lock;
	struct xgene_dev_parameters	param;
};

#define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw)

static int xgene_clk_enable(struct clk_hw *hw)
{
	struct xgene_clk *pclk = to_xgene_clk(hw);
	unsigned long flags = 0;
	u32 data;
	phys_addr_t reg;

	if (pclk->lock)
		spin_lock_irqsave(pclk->lock, flags);

	if (pclk->param.csr_reg != NULL) {
		pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
		reg = __pa(pclk->param.csr_reg);
		/* First enable the clock */
		data = xgene_clk_read(pclk->param.csr_reg +
					pclk->param.reg_clk_offset);
		data |= pclk->param.reg_clk_mask;
		xgene_clk_write(data, pclk->param.csr_reg +
					pclk->param.reg_clk_offset);
		pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
			clk_hw_get_name(hw), &reg,
			pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
			data);

		/* Second enable the CSR */
		data = xgene_clk_read(pclk->param.csr_reg +
					pclk->param.reg_csr_offset);
		data &= ~pclk->param.reg_csr_mask;
		xgene_clk_write(data, pclk->param.csr_reg +
					pclk->param.reg_csr_offset);
		pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
			clk_hw_get_name(hw), &reg,
			pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
			data);
	}

	if (pclk->lock)
		spin_unlock_irqrestore(pclk->lock, flags);

	return 0;
}

static void xgene_clk_disable(struct clk_hw *hw)
{
	struct xgene_clk *pclk = to_xgene_clk(hw);
	unsigned long flags = 0;
	u32 data;

	if (pclk->lock)
		spin_lock_irqsave(pclk->lock, flags);

	if (pclk->param.csr_reg != NULL) {
		pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
		/* First put the CSR in reset */
		data = xgene_clk_read(pclk->param.csr_reg +
					pclk->param.reg_csr_offset);
		data |= pclk->param.reg_csr_mask;
		xgene_clk_write(data, pclk->param.csr_reg +
					pclk->param.reg_csr_offset);

		/* Second disable the clock */
		data = xgene_clk_read(pclk->param.csr_reg +
					pclk->param.reg_clk_offset);
		data &= ~pclk->param.reg_clk_mask;
		xgene_clk_write(data, pclk->param.csr_reg +
					pclk->param.reg_clk_offset);
	}

	if (pclk->lock)
		spin_unlock_irqrestore(pclk->lock, flags);
}

static int xgene_clk_is_enabled(struct clk_hw *hw)
{
	struct xgene_clk *pclk = to_xgene_clk(hw);
	u32 data = 0;

	if (pclk->param.csr_reg != NULL) {
		pr_debug("%s clock checking\n", clk_hw_get_name(hw));
		data = xgene_clk_read(pclk->param.csr_reg +
					pclk->param.reg_clk_offset);
		pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
			data & pclk->param.reg_clk_mask ? "enabled" :
							"disabled");
	}

	if (pclk->param.csr_reg == NULL)
		return 1;
	return data & pclk->param.reg_clk_mask ? 1 : 0;
}

static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
				unsigned long parent_rate)
{
	struct xgene_clk *pclk = to_xgene_clk(hw);
	u32 data;

	if (pclk->param.divider_reg) {
		data = xgene_clk_read(pclk->param.divider_reg +
					pclk->param.reg_divider_offset);
		data >>= pclk->param.reg_divider_shift;
		data &= (1 << pclk->param.reg_divider_width) - 1;

		pr_debug("%s clock recalc rate %ld parent %ld\n",
			clk_hw_get_name(hw),
			parent_rate / data, parent_rate);

		return parent_rate / data;
	} else {
		pr_debug("%s clock recalc rate %ld parent %ld\n",
			clk_hw_get_name(hw), parent_rate, parent_rate);
		return parent_rate;
	}
}

static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	struct xgene_clk *pclk = to_xgene_clk(hw);
	unsigned long flags = 0;
	u32 data;
	u32 divider;
	u32 divider_save;

	if (pclk->lock)
		spin_lock_irqsave(pclk->lock, flags);

	if (pclk->param.divider_reg) {
		/* Let's compute the divider */
		if (rate > parent_rate)
			rate = parent_rate;
		divider_save = divider = parent_rate / rate; /* Rounded down */
		divider &= (1 << pclk->param.reg_divider_width) - 1;
		divider <<= pclk->param.reg_divider_shift;

		/* Set new divider */
		data = xgene_clk_read(pclk->param.divider_reg +
				pclk->param.reg_divider_offset);
		data &= ~((1 << pclk->param.reg_divider_width) - 1)
				<< pclk->param.reg_divider_shift;
		data |= divider;
		xgene_clk_write(data, pclk->param.divider_reg +
					pclk->param.reg_divider_offset);
		pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
			parent_rate / divider_save);
	} else {
		divider_save = 1;
	}

	if (pclk->lock)
		spin_unlock_irqrestore(pclk->lock, flags);

	return parent_rate / divider_save;
}

static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{
	struct xgene_clk *pclk = to_xgene_clk(hw);
	unsigned long parent_rate = *prate;
	u32 divider;

	if (pclk->param.divider_reg) {
		/* Let's compute the divider */
		if (rate > parent_rate)
			rate = parent_rate;
		divider = parent_rate / rate;   /* Rounded down */
	} else {
		divider = 1;
	}

	return parent_rate / divider;
}

static const struct clk_ops xgene_clk_ops = {
	.enable = xgene_clk_enable,
	.disable = xgene_clk_disable,
	.is_enabled = xgene_clk_is_enabled,
	.recalc_rate = xgene_clk_recalc_rate,
	.set_rate = xgene_clk_set_rate,
	.round_rate = xgene_clk_round_rate,
};

static struct clk *xgene_register_clk(struct device *dev,
		const char *name, const char *parent_name,
		struct xgene_dev_parameters *parameters, spinlock_t *lock)
{
	struct xgene_clk *apmclk;
	struct clk *clk;
	struct clk_init_data init;
	int rc;

	/* allocate the APM clock structure */
	apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
	if (!apmclk) {
		pr_err("%s: could not allocate APM clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	init.ops = &xgene_clk_ops;
	init.flags = 0;
	init.parent_names = parent_name ? &parent_name : NULL;
	init.num_parents = parent_name ? 1 : 0;

	apmclk->lock = lock;
	apmclk->hw.init = &init;
	apmclk->param = *parameters;

	/* Register the clock */
	clk = clk_register(dev, &apmclk->hw);
	if (IS_ERR(clk)) {
		pr_err("%s: could not register clk %s\n", __func__, name);
		kfree(apmclk);
		return clk;
	}

	/* Register the clock for lookup */
	rc = clk_register_clkdev(clk, name, NULL);
	if (rc != 0) {
		pr_err("%s: could not register lookup clk %s\n",
			__func__, name);
	}
	return clk;
}

static void __init xgene_devclk_init(struct device_node *np)
{
	const char *clk_name = np->full_name;
	struct clk *clk;
	struct resource res;
	int rc;
	struct xgene_dev_parameters parameters;
	int i;

	/* Check if the entry is disabled */
        if (!of_device_is_available(np))
                return;

	/* Parse the DTS register for resource */
	parameters.csr_reg = NULL;
	parameters.divider_reg = NULL;
	for (i = 0; i < 2; i++) {
		void __iomem *map_res;
		rc = of_address_to_resource(np, i, &res);
		if (rc != 0) {
			if (i == 0) {
				pr_err("no DTS register for %s\n", 
					np->full_name);
				return;
			}
			break;
		}
		map_res = of_iomap(np, i);
		if (map_res == NULL) {
			pr_err("Unable to map resource %d for %s\n",
				i, np->full_name);
			goto err;
		}
		if (strcmp(res.name, "div-reg") == 0)
			parameters.divider_reg = map_res;
		else /* if (strcmp(res->name, "csr-reg") == 0) */
			parameters.csr_reg = map_res;
	}
	if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))
		parameters.reg_csr_offset = 0;
	if (of_property_read_u32(np, "csr-mask", &parameters.reg_csr_mask))
		parameters.reg_csr_mask = 0xF;
	if (of_property_read_u32(np, "enable-offset",
				&parameters.reg_clk_offset))
		parameters.reg_clk_offset = 0x8;
	if (of_property_read_u32(np, "enable-mask", &parameters.reg_clk_mask))
		parameters.reg_clk_mask = 0xF;
	if (of_property_read_u32(np, "divider-offset",
				&parameters.reg_divider_offset))
		parameters.reg_divider_offset = 0;
	if (of_property_read_u32(np, "divider-width",
				&parameters.reg_divider_width))
		parameters.reg_divider_width = 0;
	if (of_property_read_u32(np, "divider-shift",
				&parameters.reg_divider_shift))
		parameters.reg_divider_shift = 0;
	of_property_read_string(np, "clock-output-names", &clk_name);

	clk = xgene_register_clk(NULL, clk_name,
		of_clk_get_parent_name(np, 0), &parameters, &clk_lock);
	if (IS_ERR(clk))
		goto err;
	pr_debug("Add %s clock\n", clk_name);
	rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
	if (rc != 0)
		pr_err("%s: could register provider clk %s\n", __func__,
			np->full_name);

	return;

err:
	if (parameters.csr_reg)
		iounmap(parameters.csr_reg);
	if (parameters.divider_reg)
		iounmap(parameters.divider_reg);
}

CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
Commit	Line	Data
308964ca LH	1	/*
	2	* clk-xgene.c - AppliedMicro X-Gene Clock Interface
	3	*
	4	* Copyright (c) 2013, Applied Micro Circuits Corporation
	5	* Author: Loc Ho <lho@apm.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*
	22	*/
	23	#include <linux/module.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/io.h>
	26	#include <linux/of.h>
	27	#include <linux/clkdev.h>
	28	#include <linux/clk-provider.h>
	29	#include <linux/of_address.h>
308964ca LH	30
	31	/* Register SCU_PCPPLL bit fields */
	32	#define N_DIV_RD(src) (((src) & 0x000001ff))
	33
	34	/* Register SCU_SOCPLL bit fields */
	35	#define CLKR_RD(src) (((src) & 0x07000000)>>24)
	36	#define CLKOD_RD(src) (((src) & 0x00300000)>>20)
	37	#define REGSPEC_RESET_F1_MASK 0x00010000
	38	#define CLKF_RD(src) (((src) & 0x000001ff))
	39
	40	#define XGENE_CLK_DRIVER_VER "0.1"
	41
	42	static DEFINE_SPINLOCK(clk_lock);
	43
6ae5fd38	44	static inline u32 xgene_clk_read(void __iomem *csr)
308964ca LH	45	{
	46	return readl_relaxed(csr);
	47	}
	48
6ae5fd38	49	static inline void xgene_clk_write(u32 data, void __iomem *csr)
308964ca LH	50	{
	51	return writel_relaxed(data, csr);
	52	}
	53
	54	/* PLL Clock */
	55	enum xgene_pll_type {
	56	PLL_TYPE_PCP = 0,
	57	PLL_TYPE_SOC = 1,
	58	};
	59
	60	struct xgene_clk_pll {
	61	struct clk_hw hw;
308964ca LH	62	void __iomem *reg;
	63	spinlock_t *lock;
	64	u32 pll_offset;
	65	enum xgene_pll_type type;
	66	};
	67
	68	#define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
	69
	70	static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
	71	{
	72	struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
	73	u32 data;
	74
	75	data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
836ee0f7	76	pr_debug("%s pll %s\n", clk_hw_get_name(hw),
308964ca LH	77	data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");
	78
	79	return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
	80	}
	81
	82	static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
	83	unsigned long parent_rate)
	84	{
	85	struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
	86	unsigned long fref;
	87	unsigned long fvco;
	88	u32 pll;
	89	u32 nref;
	90	u32 nout;
	91	u32 nfb;
	92
	93	pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
	94
	95	if (pllclk->type == PLL_TYPE_PCP) {
	96	/*
	97	* PLL VCO = Reference clock * NF
	98	* PCP PLL = PLL_VCO / 2
	99	*/
	100	nout = 2;
	101	fvco = parent_rate * (N_DIV_RD(pll) + 4);
	102	} else {
	103	/*
	104	* Fref = Reference Clock / NREF;
	105	* Fvco = Fref * NFB;
	106	* Fout = Fvco / NOUT;
	107	*/
	108	nref = CLKR_RD(pll) + 1;
	109	nout = CLKOD_RD(pll) + 1;
	110	nfb = CLKF_RD(pll);
	111	fref = parent_rate / nref;
	112	fvco = fref * nfb;
	113	}
836ee0f7	114	pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
308964ca LH	115	fvco / nout, parent_rate);
	116
	117	return fvco / nout;
	118	}
	119
6ae5fd38	120	static const struct clk_ops xgene_clk_pll_ops = {
308964ca LH	121	.is_enabled = xgene_clk_pll_is_enabled,
	122	.recalc_rate = xgene_clk_pll_recalc_rate,
	123	};
	124
	125	static struct clk xgene_register_clk_pll(struct device dev,
	126	const char name, const char parent_name,
	127	unsigned long flags, void __iomem *reg, u32 pll_offset,
	128	u32 type, spinlock_t *lock)
	129	{
	130	struct xgene_clk_pll *apmclk;
	131	struct clk *clk;
	132	struct clk_init_data init;
	133
	134	/* allocate the APM clock structure */
	135	apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
	136	if (!apmclk) {
	137	pr_err("%s: could not allocate APM clk\n", __func__);
	138	return ERR_PTR(-ENOMEM);
	139	}
	140
	141	init.name = name;
	142	init.ops = &xgene_clk_pll_ops;
	143	init.flags = flags;
	144	init.parent_names = parent_name ? &parent_name : NULL;
	145	init.num_parents = parent_name ? 1 : 0;
	146
308964ca LH	147	apmclk->reg = reg;
	148	apmclk->lock = lock;
	149	apmclk->pll_offset = pll_offset;
	150	apmclk->type = type;
	151	apmclk->hw.init = &init;
	152
	153	/* Register the clock */
	154	clk = clk_register(dev, &apmclk->hw);
	155	if (IS_ERR(clk)) {
	156	pr_err("%s: could not register clk %s\n", __func__, name);
	157	kfree(apmclk);
	158	return NULL;
	159	}
	160	return clk;
	161	}
	162
	163	static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
	164	{
	165	const char *clk_name = np->full_name;
	166	struct clk *clk;
6ae5fd38	167	void __iomem *reg;
308964ca LH	168
	169	reg = of_iomap(np, 0);
	170	if (reg == NULL) {
	171	pr_err("Unable to map CSR register for %s\n", np->full_name);
	172	return;
	173	}
	174	of_property_read_string(np, "clock-output-names", &clk_name);
	175	clk = xgene_register_clk_pll(NULL,
	176	clk_name, of_clk_get_parent_name(np, 0),
	177	CLK_IS_ROOT, reg, 0, pll_type, &clk_lock);
	178	if (!IS_ERR(clk)) {
	179	of_clk_add_provider(np, of_clk_src_simple_get, clk);
	180	clk_register_clkdev(clk, clk_name, NULL);
	181	pr_debug("Add %s clock PLL\n", clk_name);
	182	}
	183	}
	184
	185	static void xgene_socpllclk_init(struct device_node *np)
	186	{
	187	xgene_pllclk_init(np, PLL_TYPE_SOC);
	188	}
	189
	190	static void xgene_pcppllclk_init(struct device_node *np)
	191	{
	192	xgene_pllclk_init(np, PLL_TYPE_PCP);
	193	}
	194
	195	/* IP Clock */
	196	struct xgene_dev_parameters {
	197	void __iomem csr_reg; / CSR for IP clock */
	198	u32 reg_clk_offset; /* Offset to clock enable CSR */
	199	u32 reg_clk_mask; /* Mask bit for clock enable */
	200	u32 reg_csr_offset; /* Offset to CSR reset */
	201	u32 reg_csr_mask; /* Mask bit for disable CSR reset */
	202	void __iomem divider_reg; / CSR for divider */
	203	u32 reg_divider_offset; /* Offset to divider register */
	204	u32 reg_divider_shift; /* Bit shift to divider field */
	205	u32 reg_divider_width; /* Width of the bit to divider field */
	206	};
	207
	208	struct xgene_clk {
	209	struct clk_hw hw;
308964ca LH	210	spinlock_t *lock;
	211	struct xgene_dev_parameters param;
	212	};
	213
	214	#define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw)
	215
	216	static int xgene_clk_enable(struct clk_hw *hw)
	217	{
	218	struct xgene_clk *pclk = to_xgene_clk(hw);
	219	unsigned long flags = 0;
	220	u32 data;
6ae5fd38	221	phys_addr_t reg;
308964ca LH	222
	223	if (pclk->lock)
	224	spin_lock_irqsave(pclk->lock, flags);
	225
	226	if (pclk->param.csr_reg != NULL) {
836ee0f7	227	pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
6ae5fd38	228	reg = __pa(pclk->param.csr_reg);
308964ca LH	229	/* First enable the clock */
	230	data = xgene_clk_read(pclk->param.csr_reg +
	231	pclk->param.reg_clk_offset);
	232	data \|= pclk->param.reg_clk_mask;
	233	xgene_clk_write(data, pclk->param.csr_reg +
	234	pclk->param.reg_clk_offset);
6ae5fd38	235	pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
836ee0f7	236	clk_hw_get_name(hw), &reg,
308964ca LH	237	pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
	238	data);
	239
	240	/* Second enable the CSR */
	241	data = xgene_clk_read(pclk->param.csr_reg +
	242	pclk->param.reg_csr_offset);
	243	data &= ~pclk->param.reg_csr_mask;
	244	xgene_clk_write(data, pclk->param.csr_reg +
	245	pclk->param.reg_csr_offset);
6ae5fd38	246	pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
836ee0f7	247	clk_hw_get_name(hw), &reg,
308964ca LH	248	pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
	249	data);
	250	}
	251
	252	if (pclk->lock)
	253	spin_unlock_irqrestore(pclk->lock, flags);
	254
	255	return 0;
	256	}
	257
	258	static void xgene_clk_disable(struct clk_hw *hw)
	259	{
	260	struct xgene_clk *pclk = to_xgene_clk(hw);
	261	unsigned long flags = 0;
	262	u32 data;
	263
	264	if (pclk->lock)
	265	spin_lock_irqsave(pclk->lock, flags);
	266
	267	if (pclk->param.csr_reg != NULL) {
836ee0f7	268	pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
308964ca LH	269	/* First put the CSR in reset */
	270	data = xgene_clk_read(pclk->param.csr_reg +
	271	pclk->param.reg_csr_offset);
	272	data \|= pclk->param.reg_csr_mask;
	273	xgene_clk_write(data, pclk->param.csr_reg +
	274	pclk->param.reg_csr_offset);
	275
	276	/* Second disable the clock */
	277	data = xgene_clk_read(pclk->param.csr_reg +
	278	pclk->param.reg_clk_offset);
	279	data &= ~pclk->param.reg_clk_mask;
	280	xgene_clk_write(data, pclk->param.csr_reg +
	281	pclk->param.reg_clk_offset);
	282	}
	283
	284	if (pclk->lock)
	285	spin_unlock_irqrestore(pclk->lock, flags);
	286	}
	287
	288	static int xgene_clk_is_enabled(struct clk_hw *hw)
	289	{
	290	struct xgene_clk *pclk = to_xgene_clk(hw);
	291	u32 data = 0;
	292
	293	if (pclk->param.csr_reg != NULL) {
836ee0f7	294	pr_debug("%s clock checking\n", clk_hw_get_name(hw));
308964ca LH	295	data = xgene_clk_read(pclk->param.csr_reg +
308964ca LH	296	pclk->param.reg_clk_offset);
836ee0f7	297	pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
308964ca LH	298	data & pclk->param.reg_clk_mask ? "enabled" :
	299	"disabled");
	300	}
	301
	302	if (pclk->param.csr_reg == NULL)
	303	return 1;
	304	return data & pclk->param.reg_clk_mask ? 1 : 0;
	305	}
	306
	307	static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
	308	unsigned long parent_rate)
	309	{
	310	struct xgene_clk *pclk = to_xgene_clk(hw);
	311	u32 data;
	312
	313	if (pclk->param.divider_reg) {
	314	data = xgene_clk_read(pclk->param.divider_reg +
	315	pclk->param.reg_divider_offset);
	316	data >>= pclk->param.reg_divider_shift;
	317	data &= (1 << pclk->param.reg_divider_width) - 1;
	318
	319	pr_debug("%s clock recalc rate %ld parent %ld\n",
836ee0f7	320	clk_hw_get_name(hw),
78e50c6d MB	321	parent_rate / data, parent_rate);
78e50c6d MB	322
308964ca LH	323	return parent_rate / data;
	324	} else {
	325	pr_debug("%s clock recalc rate %ld parent %ld\n",
836ee0f7	326	clk_hw_get_name(hw), parent_rate, parent_rate);
308964ca LH	327	return parent_rate;
	328	}
	329	}
	330
	331	static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
	332	unsigned long parent_rate)
	333	{
	334	struct xgene_clk *pclk = to_xgene_clk(hw);
	335	unsigned long flags = 0;
	336	u32 data;
	337	u32 divider;
	338	u32 divider_save;
	339
	340	if (pclk->lock)
	341	spin_lock_irqsave(pclk->lock, flags);
	342
	343	if (pclk->param.divider_reg) {
	344	/* Let's compute the divider */
	345	if (rate > parent_rate)
	346	rate = parent_rate;
	347	divider_save = divider = parent_rate / rate; /* Rounded down */
	348	divider &= (1 << pclk->param.reg_divider_width) - 1;
	349	divider <<= pclk->param.reg_divider_shift;
	350
	351	/* Set new divider */
	352	data = xgene_clk_read(pclk->param.divider_reg +
	353	pclk->param.reg_divider_offset);
1382ea63 LH	354	data &= ~((1 << pclk->param.reg_divider_width) - 1)
1382ea63 LH	355	<< pclk->param.reg_divider_shift;
308964ca LH	356	data \|= divider;
	357	xgene_clk_write(data, pclk->param.divider_reg +
	358	pclk->param.reg_divider_offset);
836ee0f7	359	pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
308964ca LH	360	parent_rate / divider_save);
	361	} else {
	362	divider_save = 1;
	363	}
	364
	365	if (pclk->lock)
	366	spin_unlock_irqrestore(pclk->lock, flags);
	367
	368	return parent_rate / divider_save;
	369	}
	370
	371	static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
	372	unsigned long *prate)
	373	{
	374	struct xgene_clk *pclk = to_xgene_clk(hw);
	375	unsigned long parent_rate = *prate;
	376	u32 divider;
	377
	378	if (pclk->param.divider_reg) {
	379	/* Let's compute the divider */
	380	if (rate > parent_rate)
	381	rate = parent_rate;
	382	divider = parent_rate / rate; /* Rounded down */
	383	} else {
	384	divider = 1;
	385	}
	386
	387	return parent_rate / divider;
	388	}
	389
6ae5fd38	390	static const struct clk_ops xgene_clk_ops = {
308964ca LH	391	.enable = xgene_clk_enable,
	392	.disable = xgene_clk_disable,
	393	.is_enabled = xgene_clk_is_enabled,
	394	.recalc_rate = xgene_clk_recalc_rate,
	395	.set_rate = xgene_clk_set_rate,
	396	.round_rate = xgene_clk_round_rate,
	397	};
	398
	399	static struct clk xgene_register_clk(struct device dev,
	400	const char name, const char parent_name,
	401	struct xgene_dev_parameters parameters, spinlock_t lock)
	402	{
	403	struct xgene_clk *apmclk;
	404	struct clk *clk;
	405	struct clk_init_data init;
	406	int rc;
	407
	408	/* allocate the APM clock structure */
	409	apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
	410	if (!apmclk) {
	411	pr_err("%s: could not allocate APM clk\n", __func__);
	412	return ERR_PTR(-ENOMEM);
	413	}
	414
	415	init.name = name;
	416	init.ops = &xgene_clk_ops;
	417	init.flags = 0;
	418	init.parent_names = parent_name ? &parent_name : NULL;
	419	init.num_parents = parent_name ? 1 : 0;
	420
308964ca LH	421	apmclk->lock = lock;
	422	apmclk->hw.init = &init;
	423	apmclk->param = *parameters;
	424
	425	/* Register the clock */
	426	clk = clk_register(dev, &apmclk->hw);
	427	if (IS_ERR(clk)) {
	428	pr_err("%s: could not register clk %s\n", __func__, name);
	429	kfree(apmclk);
	430	return clk;
	431	}
	432
	433	/* Register the clock for lookup */
	434	rc = clk_register_clkdev(clk, name, NULL);
	435	if (rc != 0) {
	436	pr_err("%s: could not register lookup clk %s\n",
	437	__func__, name);
	438	}
	439	return clk;
	440	}
	441
	442	static void __init xgene_devclk_init(struct device_node *np)
	443	{
	444	const char *clk_name = np->full_name;
	445	struct clk *clk;
	446	struct resource res;
	447	int rc;
	448	struct xgene_dev_parameters parameters;
	449	int i;
	450
	451	/* Check if the entry is disabled */
	452	if (!of_device_is_available(np))
	453	return;
	454
	455	/* Parse the DTS register for resource */
	456	parameters.csr_reg = NULL;
	457	parameters.divider_reg = NULL;
	458	for (i = 0; i < 2; i++) {
6ae5fd38	459	void __iomem *map_res;
308964ca LH	460	rc = of_address_to_resource(np, i, &res);
	461	if (rc != 0) {
	462	if (i == 0) {
	463	pr_err("no DTS register for %s\n",
	464	np->full_name);
	465	return;
	466	}
	467	break;
	468	}
	469	map_res = of_iomap(np, i);
	470	if (map_res == NULL) {
	471	pr_err("Unable to map resource %d for %s\n",
	472	i, np->full_name);
	473	goto err;
	474	}
	475	if (strcmp(res.name, "div-reg") == 0)
	476	parameters.divider_reg = map_res;
	477	else /* if (strcmp(res->name, "csr-reg") == 0) */
	478	parameters.csr_reg = map_res;
	479	}
	480	if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))
	481	parameters.reg_csr_offset = 0;
	482	if (of_property_read_u32(np, "csr-mask", &parameters.reg_csr_mask))
	483	parameters.reg_csr_mask = 0xF;
	484	if (of_property_read_u32(np, "enable-offset",
	485	&parameters.reg_clk_offset))
	486	parameters.reg_clk_offset = 0x8;
	487	if (of_property_read_u32(np, "enable-mask", &parameters.reg_clk_mask))
	488	parameters.reg_clk_mask = 0xF;
	489	if (of_property_read_u32(np, "divider-offset",
	490	&parameters.reg_divider_offset))
	491	parameters.reg_divider_offset = 0;
	492	if (of_property_read_u32(np, "divider-width",
	493	&parameters.reg_divider_width))
	494	parameters.reg_divider_width = 0;
	495	if (of_property_read_u32(np, "divider-shift",
	496	&parameters.reg_divider_shift))
	497	parameters.reg_divider_shift = 0;
	498	of_property_read_string(np, "clock-output-names", &clk_name);
	499
	500	clk = xgene_register_clk(NULL, clk_name,
	501	of_clk_get_parent_name(np, 0), &parameters, &clk_lock);
	502	if (IS_ERR(clk))
	503	goto err;
	504	pr_debug("Add %s clock\n", clk_name);
	505	rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
	506	if (rc != 0)
	507	pr_err("%s: could register provider clk %s\n", __func__,
	508	np->full_name);
	509
	510	return;
	511
	512	err:
	513	if (parameters.csr_reg)
	514	iounmap(parameters.csr_reg);
	515	if (parameters.divider_reg)
	516	iounmap(parameters.divider_reg);
	517	}
	518
	519	CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
	520	CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
	521	CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);