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308964ca LH |
1 | /* |
2 | * clk-xgene.c - AppliedMicro X-Gene Clock Interface | |
3 | * | |
4 | * Copyright (c) 2013, Applied Micro Circuits Corporation | |
5 | * Author: Loc Ho <lho@apm.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | #include <linux/module.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/clkdev.h> | |
28 | #include <linux/clk-provider.h> | |
29 | #include <linux/of_address.h> | |
30 | #include <asm/setup.h> | |
31 | ||
32 | /* Register SCU_PCPPLL bit fields */ | |
33 | #define N_DIV_RD(src) (((src) & 0x000001ff)) | |
34 | ||
35 | /* Register SCU_SOCPLL bit fields */ | |
36 | #define CLKR_RD(src) (((src) & 0x07000000)>>24) | |
37 | #define CLKOD_RD(src) (((src) & 0x00300000)>>20) | |
38 | #define REGSPEC_RESET_F1_MASK 0x00010000 | |
39 | #define CLKF_RD(src) (((src) & 0x000001ff)) | |
40 | ||
41 | #define XGENE_CLK_DRIVER_VER "0.1" | |
42 | ||
43 | static DEFINE_SPINLOCK(clk_lock); | |
44 | ||
6ae5fd38 | 45 | static inline u32 xgene_clk_read(void __iomem *csr) |
308964ca LH |
46 | { |
47 | return readl_relaxed(csr); | |
48 | } | |
49 | ||
6ae5fd38 | 50 | static inline void xgene_clk_write(u32 data, void __iomem *csr) |
308964ca LH |
51 | { |
52 | return writel_relaxed(data, csr); | |
53 | } | |
54 | ||
55 | /* PLL Clock */ | |
56 | enum xgene_pll_type { | |
57 | PLL_TYPE_PCP = 0, | |
58 | PLL_TYPE_SOC = 1, | |
59 | }; | |
60 | ||
61 | struct xgene_clk_pll { | |
62 | struct clk_hw hw; | |
308964ca LH |
63 | void __iomem *reg; |
64 | spinlock_t *lock; | |
65 | u32 pll_offset; | |
66 | enum xgene_pll_type type; | |
67 | }; | |
68 | ||
69 | #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw) | |
70 | ||
71 | static int xgene_clk_pll_is_enabled(struct clk_hw *hw) | |
72 | { | |
73 | struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); | |
74 | u32 data; | |
75 | ||
76 | data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); | |
78e50c6d | 77 | pr_debug("%s pll %s\n", __clk_get_name(hw->clk), |
308964ca LH |
78 | data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled"); |
79 | ||
80 | return data & REGSPEC_RESET_F1_MASK ? 0 : 1; | |
81 | } | |
82 | ||
83 | static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw, | |
84 | unsigned long parent_rate) | |
85 | { | |
86 | struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); | |
87 | unsigned long fref; | |
88 | unsigned long fvco; | |
89 | u32 pll; | |
90 | u32 nref; | |
91 | u32 nout; | |
92 | u32 nfb; | |
93 | ||
94 | pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); | |
95 | ||
96 | if (pllclk->type == PLL_TYPE_PCP) { | |
97 | /* | |
98 | * PLL VCO = Reference clock * NF | |
99 | * PCP PLL = PLL_VCO / 2 | |
100 | */ | |
101 | nout = 2; | |
102 | fvco = parent_rate * (N_DIV_RD(pll) + 4); | |
103 | } else { | |
104 | /* | |
105 | * Fref = Reference Clock / NREF; | |
106 | * Fvco = Fref * NFB; | |
107 | * Fout = Fvco / NOUT; | |
108 | */ | |
109 | nref = CLKR_RD(pll) + 1; | |
110 | nout = CLKOD_RD(pll) + 1; | |
111 | nfb = CLKF_RD(pll); | |
112 | fref = parent_rate / nref; | |
113 | fvco = fref * nfb; | |
114 | } | |
78e50c6d | 115 | pr_debug("%s pll recalc rate %ld parent %ld\n", __clk_get_name(hw->clk), |
308964ca LH |
116 | fvco / nout, parent_rate); |
117 | ||
118 | return fvco / nout; | |
119 | } | |
120 | ||
6ae5fd38 | 121 | static const struct clk_ops xgene_clk_pll_ops = { |
308964ca LH |
122 | .is_enabled = xgene_clk_pll_is_enabled, |
123 | .recalc_rate = xgene_clk_pll_recalc_rate, | |
124 | }; | |
125 | ||
126 | static struct clk *xgene_register_clk_pll(struct device *dev, | |
127 | const char *name, const char *parent_name, | |
128 | unsigned long flags, void __iomem *reg, u32 pll_offset, | |
129 | u32 type, spinlock_t *lock) | |
130 | { | |
131 | struct xgene_clk_pll *apmclk; | |
132 | struct clk *clk; | |
133 | struct clk_init_data init; | |
134 | ||
135 | /* allocate the APM clock structure */ | |
136 | apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL); | |
137 | if (!apmclk) { | |
138 | pr_err("%s: could not allocate APM clk\n", __func__); | |
139 | return ERR_PTR(-ENOMEM); | |
140 | } | |
141 | ||
142 | init.name = name; | |
143 | init.ops = &xgene_clk_pll_ops; | |
144 | init.flags = flags; | |
145 | init.parent_names = parent_name ? &parent_name : NULL; | |
146 | init.num_parents = parent_name ? 1 : 0; | |
147 | ||
308964ca LH |
148 | apmclk->reg = reg; |
149 | apmclk->lock = lock; | |
150 | apmclk->pll_offset = pll_offset; | |
151 | apmclk->type = type; | |
152 | apmclk->hw.init = &init; | |
153 | ||
154 | /* Register the clock */ | |
155 | clk = clk_register(dev, &apmclk->hw); | |
156 | if (IS_ERR(clk)) { | |
157 | pr_err("%s: could not register clk %s\n", __func__, name); | |
158 | kfree(apmclk); | |
159 | return NULL; | |
160 | } | |
161 | return clk; | |
162 | } | |
163 | ||
164 | static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) | |
165 | { | |
166 | const char *clk_name = np->full_name; | |
167 | struct clk *clk; | |
6ae5fd38 | 168 | void __iomem *reg; |
308964ca LH |
169 | |
170 | reg = of_iomap(np, 0); | |
171 | if (reg == NULL) { | |
172 | pr_err("Unable to map CSR register for %s\n", np->full_name); | |
173 | return; | |
174 | } | |
175 | of_property_read_string(np, "clock-output-names", &clk_name); | |
176 | clk = xgene_register_clk_pll(NULL, | |
177 | clk_name, of_clk_get_parent_name(np, 0), | |
178 | CLK_IS_ROOT, reg, 0, pll_type, &clk_lock); | |
179 | if (!IS_ERR(clk)) { | |
180 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
181 | clk_register_clkdev(clk, clk_name, NULL); | |
182 | pr_debug("Add %s clock PLL\n", clk_name); | |
183 | } | |
184 | } | |
185 | ||
186 | static void xgene_socpllclk_init(struct device_node *np) | |
187 | { | |
188 | xgene_pllclk_init(np, PLL_TYPE_SOC); | |
189 | } | |
190 | ||
191 | static void xgene_pcppllclk_init(struct device_node *np) | |
192 | { | |
193 | xgene_pllclk_init(np, PLL_TYPE_PCP); | |
194 | } | |
195 | ||
196 | /* IP Clock */ | |
197 | struct xgene_dev_parameters { | |
198 | void __iomem *csr_reg; /* CSR for IP clock */ | |
199 | u32 reg_clk_offset; /* Offset to clock enable CSR */ | |
200 | u32 reg_clk_mask; /* Mask bit for clock enable */ | |
201 | u32 reg_csr_offset; /* Offset to CSR reset */ | |
202 | u32 reg_csr_mask; /* Mask bit for disable CSR reset */ | |
203 | void __iomem *divider_reg; /* CSR for divider */ | |
204 | u32 reg_divider_offset; /* Offset to divider register */ | |
205 | u32 reg_divider_shift; /* Bit shift to divider field */ | |
206 | u32 reg_divider_width; /* Width of the bit to divider field */ | |
207 | }; | |
208 | ||
209 | struct xgene_clk { | |
210 | struct clk_hw hw; | |
308964ca LH |
211 | spinlock_t *lock; |
212 | struct xgene_dev_parameters param; | |
213 | }; | |
214 | ||
215 | #define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw) | |
216 | ||
217 | static int xgene_clk_enable(struct clk_hw *hw) | |
218 | { | |
219 | struct xgene_clk *pclk = to_xgene_clk(hw); | |
220 | unsigned long flags = 0; | |
221 | u32 data; | |
6ae5fd38 | 222 | phys_addr_t reg; |
308964ca LH |
223 | |
224 | if (pclk->lock) | |
225 | spin_lock_irqsave(pclk->lock, flags); | |
226 | ||
227 | if (pclk->param.csr_reg != NULL) { | |
78e50c6d | 228 | pr_debug("%s clock enabled\n", __clk_get_name(hw->clk)); |
6ae5fd38 | 229 | reg = __pa(pclk->param.csr_reg); |
308964ca LH |
230 | /* First enable the clock */ |
231 | data = xgene_clk_read(pclk->param.csr_reg + | |
232 | pclk->param.reg_clk_offset); | |
233 | data |= pclk->param.reg_clk_mask; | |
234 | xgene_clk_write(data, pclk->param.csr_reg + | |
235 | pclk->param.reg_clk_offset); | |
6ae5fd38 | 236 | pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n", |
78e50c6d | 237 | __clk_get_name(hw->clk), ®, |
308964ca LH |
238 | pclk->param.reg_clk_offset, pclk->param.reg_clk_mask, |
239 | data); | |
240 | ||
241 | /* Second enable the CSR */ | |
242 | data = xgene_clk_read(pclk->param.csr_reg + | |
243 | pclk->param.reg_csr_offset); | |
244 | data &= ~pclk->param.reg_csr_mask; | |
245 | xgene_clk_write(data, pclk->param.csr_reg + | |
246 | pclk->param.reg_csr_offset); | |
6ae5fd38 | 247 | pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n", |
78e50c6d | 248 | __clk_get_name(hw->clk), ®, |
308964ca LH |
249 | pclk->param.reg_csr_offset, pclk->param.reg_csr_mask, |
250 | data); | |
251 | } | |
252 | ||
253 | if (pclk->lock) | |
254 | spin_unlock_irqrestore(pclk->lock, flags); | |
255 | ||
256 | return 0; | |
257 | } | |
258 | ||
259 | static void xgene_clk_disable(struct clk_hw *hw) | |
260 | { | |
261 | struct xgene_clk *pclk = to_xgene_clk(hw); | |
262 | unsigned long flags = 0; | |
263 | u32 data; | |
264 | ||
265 | if (pclk->lock) | |
266 | spin_lock_irqsave(pclk->lock, flags); | |
267 | ||
268 | if (pclk->param.csr_reg != NULL) { | |
78e50c6d | 269 | pr_debug("%s clock disabled\n", __clk_get_name(hw->clk)); |
308964ca LH |
270 | /* First put the CSR in reset */ |
271 | data = xgene_clk_read(pclk->param.csr_reg + | |
272 | pclk->param.reg_csr_offset); | |
273 | data |= pclk->param.reg_csr_mask; | |
274 | xgene_clk_write(data, pclk->param.csr_reg + | |
275 | pclk->param.reg_csr_offset); | |
276 | ||
277 | /* Second disable the clock */ | |
278 | data = xgene_clk_read(pclk->param.csr_reg + | |
279 | pclk->param.reg_clk_offset); | |
280 | data &= ~pclk->param.reg_clk_mask; | |
281 | xgene_clk_write(data, pclk->param.csr_reg + | |
282 | pclk->param.reg_clk_offset); | |
283 | } | |
284 | ||
285 | if (pclk->lock) | |
286 | spin_unlock_irqrestore(pclk->lock, flags); | |
287 | } | |
288 | ||
289 | static int xgene_clk_is_enabled(struct clk_hw *hw) | |
290 | { | |
291 | struct xgene_clk *pclk = to_xgene_clk(hw); | |
292 | u32 data = 0; | |
293 | ||
294 | if (pclk->param.csr_reg != NULL) { | |
78e50c6d | 295 | pr_debug("%s clock checking\n", __clk_get_name(hw->clk)); |
308964ca LH |
296 | data = xgene_clk_read(pclk->param.csr_reg + |
297 | pclk->param.reg_clk_offset); | |
78e50c6d | 298 | pr_debug("%s clock is %s\n", __clk_get_name(hw->clk), |
308964ca LH |
299 | data & pclk->param.reg_clk_mask ? "enabled" : |
300 | "disabled"); | |
301 | } | |
302 | ||
303 | if (pclk->param.csr_reg == NULL) | |
304 | return 1; | |
305 | return data & pclk->param.reg_clk_mask ? 1 : 0; | |
306 | } | |
307 | ||
308 | static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw, | |
309 | unsigned long parent_rate) | |
310 | { | |
311 | struct xgene_clk *pclk = to_xgene_clk(hw); | |
312 | u32 data; | |
313 | ||
314 | if (pclk->param.divider_reg) { | |
315 | data = xgene_clk_read(pclk->param.divider_reg + | |
316 | pclk->param.reg_divider_offset); | |
317 | data >>= pclk->param.reg_divider_shift; | |
318 | data &= (1 << pclk->param.reg_divider_width) - 1; | |
319 | ||
320 | pr_debug("%s clock recalc rate %ld parent %ld\n", | |
78e50c6d MB |
321 | __clk_get_name(hw->clk), |
322 | parent_rate / data, parent_rate); | |
323 | ||
308964ca LH |
324 | return parent_rate / data; |
325 | } else { | |
326 | pr_debug("%s clock recalc rate %ld parent %ld\n", | |
78e50c6d | 327 | __clk_get_name(hw->clk), parent_rate, parent_rate); |
308964ca LH |
328 | return parent_rate; |
329 | } | |
330 | } | |
331 | ||
332 | static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate, | |
333 | unsigned long parent_rate) | |
334 | { | |
335 | struct xgene_clk *pclk = to_xgene_clk(hw); | |
336 | unsigned long flags = 0; | |
337 | u32 data; | |
338 | u32 divider; | |
339 | u32 divider_save; | |
340 | ||
341 | if (pclk->lock) | |
342 | spin_lock_irqsave(pclk->lock, flags); | |
343 | ||
344 | if (pclk->param.divider_reg) { | |
345 | /* Let's compute the divider */ | |
346 | if (rate > parent_rate) | |
347 | rate = parent_rate; | |
348 | divider_save = divider = parent_rate / rate; /* Rounded down */ | |
349 | divider &= (1 << pclk->param.reg_divider_width) - 1; | |
350 | divider <<= pclk->param.reg_divider_shift; | |
351 | ||
352 | /* Set new divider */ | |
353 | data = xgene_clk_read(pclk->param.divider_reg + | |
354 | pclk->param.reg_divider_offset); | |
355 | data &= ~((1 << pclk->param.reg_divider_width) - 1); | |
356 | data |= divider; | |
357 | xgene_clk_write(data, pclk->param.divider_reg + | |
358 | pclk->param.reg_divider_offset); | |
78e50c6d | 359 | pr_debug("%s clock set rate %ld\n", __clk_get_name(hw->clk), |
308964ca LH |
360 | parent_rate / divider_save); |
361 | } else { | |
362 | divider_save = 1; | |
363 | } | |
364 | ||
365 | if (pclk->lock) | |
366 | spin_unlock_irqrestore(pclk->lock, flags); | |
367 | ||
368 | return parent_rate / divider_save; | |
369 | } | |
370 | ||
371 | static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
372 | unsigned long *prate) | |
373 | { | |
374 | struct xgene_clk *pclk = to_xgene_clk(hw); | |
375 | unsigned long parent_rate = *prate; | |
376 | u32 divider; | |
377 | ||
378 | if (pclk->param.divider_reg) { | |
379 | /* Let's compute the divider */ | |
380 | if (rate > parent_rate) | |
381 | rate = parent_rate; | |
382 | divider = parent_rate / rate; /* Rounded down */ | |
383 | } else { | |
384 | divider = 1; | |
385 | } | |
386 | ||
387 | return parent_rate / divider; | |
388 | } | |
389 | ||
6ae5fd38 | 390 | static const struct clk_ops xgene_clk_ops = { |
308964ca LH |
391 | .enable = xgene_clk_enable, |
392 | .disable = xgene_clk_disable, | |
393 | .is_enabled = xgene_clk_is_enabled, | |
394 | .recalc_rate = xgene_clk_recalc_rate, | |
395 | .set_rate = xgene_clk_set_rate, | |
396 | .round_rate = xgene_clk_round_rate, | |
397 | }; | |
398 | ||
399 | static struct clk *xgene_register_clk(struct device *dev, | |
400 | const char *name, const char *parent_name, | |
401 | struct xgene_dev_parameters *parameters, spinlock_t *lock) | |
402 | { | |
403 | struct xgene_clk *apmclk; | |
404 | struct clk *clk; | |
405 | struct clk_init_data init; | |
406 | int rc; | |
407 | ||
408 | /* allocate the APM clock structure */ | |
409 | apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL); | |
410 | if (!apmclk) { | |
411 | pr_err("%s: could not allocate APM clk\n", __func__); | |
412 | return ERR_PTR(-ENOMEM); | |
413 | } | |
414 | ||
415 | init.name = name; | |
416 | init.ops = &xgene_clk_ops; | |
417 | init.flags = 0; | |
418 | init.parent_names = parent_name ? &parent_name : NULL; | |
419 | init.num_parents = parent_name ? 1 : 0; | |
420 | ||
308964ca LH |
421 | apmclk->lock = lock; |
422 | apmclk->hw.init = &init; | |
423 | apmclk->param = *parameters; | |
424 | ||
425 | /* Register the clock */ | |
426 | clk = clk_register(dev, &apmclk->hw); | |
427 | if (IS_ERR(clk)) { | |
428 | pr_err("%s: could not register clk %s\n", __func__, name); | |
429 | kfree(apmclk); | |
430 | return clk; | |
431 | } | |
432 | ||
433 | /* Register the clock for lookup */ | |
434 | rc = clk_register_clkdev(clk, name, NULL); | |
435 | if (rc != 0) { | |
436 | pr_err("%s: could not register lookup clk %s\n", | |
437 | __func__, name); | |
438 | } | |
439 | return clk; | |
440 | } | |
441 | ||
442 | static void __init xgene_devclk_init(struct device_node *np) | |
443 | { | |
444 | const char *clk_name = np->full_name; | |
445 | struct clk *clk; | |
446 | struct resource res; | |
447 | int rc; | |
448 | struct xgene_dev_parameters parameters; | |
449 | int i; | |
450 | ||
451 | /* Check if the entry is disabled */ | |
452 | if (!of_device_is_available(np)) | |
453 | return; | |
454 | ||
455 | /* Parse the DTS register for resource */ | |
456 | parameters.csr_reg = NULL; | |
457 | parameters.divider_reg = NULL; | |
458 | for (i = 0; i < 2; i++) { | |
6ae5fd38 | 459 | void __iomem *map_res; |
308964ca LH |
460 | rc = of_address_to_resource(np, i, &res); |
461 | if (rc != 0) { | |
462 | if (i == 0) { | |
463 | pr_err("no DTS register for %s\n", | |
464 | np->full_name); | |
465 | return; | |
466 | } | |
467 | break; | |
468 | } | |
469 | map_res = of_iomap(np, i); | |
470 | if (map_res == NULL) { | |
471 | pr_err("Unable to map resource %d for %s\n", | |
472 | i, np->full_name); | |
473 | goto err; | |
474 | } | |
475 | if (strcmp(res.name, "div-reg") == 0) | |
476 | parameters.divider_reg = map_res; | |
477 | else /* if (strcmp(res->name, "csr-reg") == 0) */ | |
478 | parameters.csr_reg = map_res; | |
479 | } | |
480 | if (of_property_read_u32(np, "csr-offset", ¶meters.reg_csr_offset)) | |
481 | parameters.reg_csr_offset = 0; | |
482 | if (of_property_read_u32(np, "csr-mask", ¶meters.reg_csr_mask)) | |
483 | parameters.reg_csr_mask = 0xF; | |
484 | if (of_property_read_u32(np, "enable-offset", | |
485 | ¶meters.reg_clk_offset)) | |
486 | parameters.reg_clk_offset = 0x8; | |
487 | if (of_property_read_u32(np, "enable-mask", ¶meters.reg_clk_mask)) | |
488 | parameters.reg_clk_mask = 0xF; | |
489 | if (of_property_read_u32(np, "divider-offset", | |
490 | ¶meters.reg_divider_offset)) | |
491 | parameters.reg_divider_offset = 0; | |
492 | if (of_property_read_u32(np, "divider-width", | |
493 | ¶meters.reg_divider_width)) | |
494 | parameters.reg_divider_width = 0; | |
495 | if (of_property_read_u32(np, "divider-shift", | |
496 | ¶meters.reg_divider_shift)) | |
497 | parameters.reg_divider_shift = 0; | |
498 | of_property_read_string(np, "clock-output-names", &clk_name); | |
499 | ||
500 | clk = xgene_register_clk(NULL, clk_name, | |
501 | of_clk_get_parent_name(np, 0), ¶meters, &clk_lock); | |
502 | if (IS_ERR(clk)) | |
503 | goto err; | |
504 | pr_debug("Add %s clock\n", clk_name); | |
505 | rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
506 | if (rc != 0) | |
507 | pr_err("%s: could register provider clk %s\n", __func__, | |
508 | np->full_name); | |
509 | ||
510 | return; | |
511 | ||
512 | err: | |
513 | if (parameters.csr_reg) | |
514 | iounmap(parameters.csr_reg); | |
515 | if (parameters.divider_reg) | |
516 | iounmap(parameters.divider_reg); | |
517 | } | |
518 | ||
519 | CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init); | |
520 | CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init); | |
521 | CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init); |