Merge remote-tracking branch 'clk/clk-next'
[deliverable/linux.git] / drivers / clk / clk.c
CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
3c373117 12#include <linux/clk.h>
b09d6d99 13#include <linux/clk-provider.h>
86be408b 14#include <linux/clk/clk-conf.h>
b2476490
MT
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/spinlock.h>
18#include <linux/err.h>
19#include <linux/list.h>
20#include <linux/slab.h>
766e6a4e 21#include <linux/of.h>
46c8773a 22#include <linux/device.h>
f2f6c255 23#include <linux/init.h>
533ddeb1 24#include <linux/sched.h>
562ef0b0 25#include <linux/clkdev.h>
b2476490 26
d6782c26
SN
27#include "clk.h"
28
b2476490
MT
29static DEFINE_SPINLOCK(enable_lock);
30static DEFINE_MUTEX(prepare_lock);
31
533ddeb1
MT
32static struct task_struct *prepare_owner;
33static struct task_struct *enable_owner;
34
35static int prepare_refcnt;
36static int enable_refcnt;
37
b2476490
MT
38static HLIST_HEAD(clk_root_list);
39static HLIST_HEAD(clk_orphan_list);
40static LIST_HEAD(clk_notifier_list);
41
b09d6d99
MT
42/*** private data structures ***/
43
44struct clk_core {
45 const char *name;
46 const struct clk_ops *ops;
47 struct clk_hw *hw;
48 struct module *owner;
49 struct clk_core *parent;
50 const char **parent_names;
51 struct clk_core **parents;
52 u8 num_parents;
53 u8 new_parent_index;
54 unsigned long rate;
1c8e6004 55 unsigned long req_rate;
b09d6d99
MT
56 unsigned long new_rate;
57 struct clk_core *new_parent;
58 struct clk_core *new_child;
59 unsigned long flags;
e6500344 60 bool orphan;
b09d6d99
MT
61 unsigned int enable_count;
62 unsigned int prepare_count;
9783c0d9
SB
63 unsigned long min_rate;
64 unsigned long max_rate;
b09d6d99
MT
65 unsigned long accuracy;
66 int phase;
67 struct hlist_head children;
68 struct hlist_node child_node;
1c8e6004 69 struct hlist_head clks;
b09d6d99
MT
70 unsigned int notifier_count;
71#ifdef CONFIG_DEBUG_FS
72 struct dentry *dentry;
8c9a8a8f 73 struct hlist_node debug_node;
b09d6d99
MT
74#endif
75 struct kref ref;
76};
77
dfc202ea
SB
78#define CREATE_TRACE_POINTS
79#include <trace/events/clk.h>
80
b09d6d99
MT
81struct clk {
82 struct clk_core *core;
83 const char *dev_id;
84 const char *con_id;
1c8e6004
TV
85 unsigned long min_rate;
86 unsigned long max_rate;
50595f8b 87 struct hlist_node clks_node;
b09d6d99
MT
88};
89
eab89f69
MT
90/*** locking ***/
91static void clk_prepare_lock(void)
92{
533ddeb1
MT
93 if (!mutex_trylock(&prepare_lock)) {
94 if (prepare_owner == current) {
95 prepare_refcnt++;
96 return;
97 }
98 mutex_lock(&prepare_lock);
99 }
100 WARN_ON_ONCE(prepare_owner != NULL);
101 WARN_ON_ONCE(prepare_refcnt != 0);
102 prepare_owner = current;
103 prepare_refcnt = 1;
eab89f69
MT
104}
105
106static void clk_prepare_unlock(void)
107{
533ddeb1
MT
108 WARN_ON_ONCE(prepare_owner != current);
109 WARN_ON_ONCE(prepare_refcnt == 0);
110
111 if (--prepare_refcnt)
112 return;
113 prepare_owner = NULL;
eab89f69
MT
114 mutex_unlock(&prepare_lock);
115}
116
117static unsigned long clk_enable_lock(void)
a57aa185 118 __acquires(enable_lock)
eab89f69
MT
119{
120 unsigned long flags;
533ddeb1
MT
121
122 if (!spin_trylock_irqsave(&enable_lock, flags)) {
123 if (enable_owner == current) {
124 enable_refcnt++;
a57aa185 125 __acquire(enable_lock);
533ddeb1
MT
126 return flags;
127 }
128 spin_lock_irqsave(&enable_lock, flags);
129 }
130 WARN_ON_ONCE(enable_owner != NULL);
131 WARN_ON_ONCE(enable_refcnt != 0);
132 enable_owner = current;
133 enable_refcnt = 1;
eab89f69
MT
134 return flags;
135}
136
137static void clk_enable_unlock(unsigned long flags)
a57aa185 138 __releases(enable_lock)
eab89f69 139{
533ddeb1
MT
140 WARN_ON_ONCE(enable_owner != current);
141 WARN_ON_ONCE(enable_refcnt == 0);
142
a57aa185
SB
143 if (--enable_refcnt) {
144 __release(enable_lock);
533ddeb1 145 return;
a57aa185 146 }
533ddeb1 147 enable_owner = NULL;
eab89f69
MT
148 spin_unlock_irqrestore(&enable_lock, flags);
149}
150
4dff95dc
SB
151static bool clk_core_is_prepared(struct clk_core *core)
152{
153 /*
154 * .is_prepared is optional for clocks that can prepare
155 * fall back to software usage counter if it is missing
156 */
157 if (!core->ops->is_prepared)
158 return core->prepare_count;
b2476490 159
4dff95dc
SB
160 return core->ops->is_prepared(core->hw);
161}
b2476490 162
4dff95dc
SB
163static bool clk_core_is_enabled(struct clk_core *core)
164{
165 /*
166 * .is_enabled is only mandatory for clocks that gate
167 * fall back to software usage counter if .is_enabled is missing
168 */
169 if (!core->ops->is_enabled)
170 return core->enable_count;
6b44c854 171
4dff95dc
SB
172 return core->ops->is_enabled(core->hw);
173}
6b44c854 174
4dff95dc 175/*** helper functions ***/
1af599df 176
b76281cb 177const char *__clk_get_name(const struct clk *clk)
1af599df 178{
4dff95dc 179 return !clk ? NULL : clk->core->name;
1af599df 180}
4dff95dc 181EXPORT_SYMBOL_GPL(__clk_get_name);
1af599df 182
e7df6f6e 183const char *clk_hw_get_name(const struct clk_hw *hw)
1a9c069c
SB
184{
185 return hw->core->name;
186}
187EXPORT_SYMBOL_GPL(clk_hw_get_name);
188
4dff95dc
SB
189struct clk_hw *__clk_get_hw(struct clk *clk)
190{
191 return !clk ? NULL : clk->core->hw;
192}
193EXPORT_SYMBOL_GPL(__clk_get_hw);
1af599df 194
e7df6f6e 195unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
1a9c069c
SB
196{
197 return hw->core->num_parents;
198}
199EXPORT_SYMBOL_GPL(clk_hw_get_num_parents);
200
e7df6f6e 201struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
1a9c069c
SB
202{
203 return hw->core->parent ? hw->core->parent->hw : NULL;
204}
205EXPORT_SYMBOL_GPL(clk_hw_get_parent);
206
4dff95dc
SB
207static struct clk_core *__clk_lookup_subtree(const char *name,
208 struct clk_core *core)
bddca894 209{
035a61c3 210 struct clk_core *child;
4dff95dc 211 struct clk_core *ret;
bddca894 212
4dff95dc
SB
213 if (!strcmp(core->name, name))
214 return core;
bddca894 215
4dff95dc
SB
216 hlist_for_each_entry(child, &core->children, child_node) {
217 ret = __clk_lookup_subtree(name, child);
218 if (ret)
219 return ret;
bddca894
PG
220 }
221
4dff95dc 222 return NULL;
bddca894
PG
223}
224
4dff95dc 225static struct clk_core *clk_core_lookup(const char *name)
bddca894 226{
4dff95dc
SB
227 struct clk_core *root_clk;
228 struct clk_core *ret;
bddca894 229
4dff95dc
SB
230 if (!name)
231 return NULL;
bddca894 232
4dff95dc
SB
233 /* search the 'proper' clk tree first */
234 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
235 ret = __clk_lookup_subtree(name, root_clk);
236 if (ret)
237 return ret;
bddca894
PG
238 }
239
4dff95dc
SB
240 /* if not found, then search the orphan tree */
241 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
242 ret = __clk_lookup_subtree(name, root_clk);
243 if (ret)
244 return ret;
245 }
bddca894 246
4dff95dc 247 return NULL;
bddca894
PG
248}
249
4dff95dc
SB
250static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
251 u8 index)
bddca894 252{
4dff95dc
SB
253 if (!core || index >= core->num_parents)
254 return NULL;
88cfbef2
MY
255
256 if (!core->parents[index])
257 core->parents[index] =
258 clk_core_lookup(core->parent_names[index]);
259
260 return core->parents[index];
bddca894
PG
261}
262
e7df6f6e
SB
263struct clk_hw *
264clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
1a9c069c
SB
265{
266 struct clk_core *parent;
267
268 parent = clk_core_get_parent_by_index(hw->core, index);
269
270 return !parent ? NULL : parent->hw;
271}
272EXPORT_SYMBOL_GPL(clk_hw_get_parent_by_index);
273
4dff95dc
SB
274unsigned int __clk_get_enable_count(struct clk *clk)
275{
276 return !clk ? 0 : clk->core->enable_count;
277}
b2476490 278
4dff95dc
SB
279static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
280{
281 unsigned long ret;
b2476490 282
4dff95dc
SB
283 if (!core) {
284 ret = 0;
285 goto out;
286 }
b2476490 287
4dff95dc 288 ret = core->rate;
b2476490 289
47b0eeb3 290 if (!core->num_parents)
4dff95dc 291 goto out;
c646cbf1 292
4dff95dc
SB
293 if (!core->parent)
294 ret = 0;
b2476490 295
b2476490
MT
296out:
297 return ret;
298}
299
e7df6f6e 300unsigned long clk_hw_get_rate(const struct clk_hw *hw)
1a9c069c
SB
301{
302 return clk_core_get_rate_nolock(hw->core);
303}
304EXPORT_SYMBOL_GPL(clk_hw_get_rate);
305
4dff95dc
SB
306static unsigned long __clk_get_accuracy(struct clk_core *core)
307{
308 if (!core)
309 return 0;
b2476490 310
4dff95dc 311 return core->accuracy;
b2476490
MT
312}
313
4dff95dc 314unsigned long __clk_get_flags(struct clk *clk)
fcb0ee6a 315{
4dff95dc 316 return !clk ? 0 : clk->core->flags;
fcb0ee6a 317}
4dff95dc 318EXPORT_SYMBOL_GPL(__clk_get_flags);
fcb0ee6a 319
e7df6f6e 320unsigned long clk_hw_get_flags(const struct clk_hw *hw)
1a9c069c
SB
321{
322 return hw->core->flags;
323}
324EXPORT_SYMBOL_GPL(clk_hw_get_flags);
325
e7df6f6e 326bool clk_hw_is_prepared(const struct clk_hw *hw)
1a9c069c
SB
327{
328 return clk_core_is_prepared(hw->core);
329}
330
be68bf88
JE
331bool clk_hw_is_enabled(const struct clk_hw *hw)
332{
333 return clk_core_is_enabled(hw->core);
334}
335
4dff95dc 336bool __clk_is_enabled(struct clk *clk)
b2476490 337{
4dff95dc
SB
338 if (!clk)
339 return false;
b2476490 340
4dff95dc
SB
341 return clk_core_is_enabled(clk->core);
342}
343EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 344
4dff95dc
SB
345static bool mux_is_better_rate(unsigned long rate, unsigned long now,
346 unsigned long best, unsigned long flags)
347{
348 if (flags & CLK_MUX_ROUND_CLOSEST)
349 return abs(now - rate) < abs(best - rate);
1af599df 350
4dff95dc
SB
351 return now <= rate && now > best;
352}
bddca894 353
0817b62c
BB
354static int
355clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
4dff95dc
SB
356 unsigned long flags)
357{
358 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
0817b62c
BB
359 int i, num_parents, ret;
360 unsigned long best = 0;
361 struct clk_rate_request parent_req = *req;
b2476490 362
4dff95dc
SB
363 /* if NO_REPARENT flag set, pass through to current parent */
364 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
365 parent = core->parent;
0817b62c
BB
366 if (core->flags & CLK_SET_RATE_PARENT) {
367 ret = __clk_determine_rate(parent ? parent->hw : NULL,
368 &parent_req);
369 if (ret)
370 return ret;
371
372 best = parent_req.rate;
373 } else if (parent) {
4dff95dc 374 best = clk_core_get_rate_nolock(parent);
0817b62c 375 } else {
4dff95dc 376 best = clk_core_get_rate_nolock(core);
0817b62c
BB
377 }
378
4dff95dc
SB
379 goto out;
380 }
b2476490 381
4dff95dc
SB
382 /* find the parent that can provide the fastest rate <= rate */
383 num_parents = core->num_parents;
384 for (i = 0; i < num_parents; i++) {
385 parent = clk_core_get_parent_by_index(core, i);
386 if (!parent)
387 continue;
0817b62c
BB
388
389 if (core->flags & CLK_SET_RATE_PARENT) {
390 parent_req = *req;
391 ret = __clk_determine_rate(parent->hw, &parent_req);
392 if (ret)
393 continue;
394 } else {
395 parent_req.rate = clk_core_get_rate_nolock(parent);
396 }
397
398 if (mux_is_better_rate(req->rate, parent_req.rate,
399 best, flags)) {
4dff95dc 400 best_parent = parent;
0817b62c 401 best = parent_req.rate;
4dff95dc
SB
402 }
403 }
b2476490 404
57d866e6
BB
405 if (!best_parent)
406 return -EINVAL;
407
4dff95dc
SB
408out:
409 if (best_parent)
0817b62c
BB
410 req->best_parent_hw = best_parent->hw;
411 req->best_parent_rate = best;
412 req->rate = best;
b2476490 413
0817b62c 414 return 0;
b33d212f 415}
4dff95dc
SB
416
417struct clk *__clk_lookup(const char *name)
fcb0ee6a 418{
4dff95dc
SB
419 struct clk_core *core = clk_core_lookup(name);
420
421 return !core ? NULL : core->hw->clk;
fcb0ee6a 422}
b2476490 423
4dff95dc
SB
424static void clk_core_get_boundaries(struct clk_core *core,
425 unsigned long *min_rate,
426 unsigned long *max_rate)
1c155b3d 427{
4dff95dc 428 struct clk *clk_user;
1c155b3d 429
9783c0d9
SB
430 *min_rate = core->min_rate;
431 *max_rate = core->max_rate;
496eadf8 432
4dff95dc
SB
433 hlist_for_each_entry(clk_user, &core->clks, clks_node)
434 *min_rate = max(*min_rate, clk_user->min_rate);
1c155b3d 435
4dff95dc
SB
436 hlist_for_each_entry(clk_user, &core->clks, clks_node)
437 *max_rate = min(*max_rate, clk_user->max_rate);
438}
1c155b3d 439
9783c0d9
SB
440void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
441 unsigned long max_rate)
442{
443 hw->core->min_rate = min_rate;
444 hw->core->max_rate = max_rate;
445}
446EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
447
4dff95dc
SB
448/*
449 * Helper for finding best parent to provide a given frequency. This can be used
450 * directly as a determine_rate callback (e.g. for a mux), or from a more
451 * complex clock that may combine a mux with other operations.
452 */
0817b62c
BB
453int __clk_mux_determine_rate(struct clk_hw *hw,
454 struct clk_rate_request *req)
4dff95dc 455{
0817b62c 456 return clk_mux_determine_rate_flags(hw, req, 0);
1c155b3d 457}
4dff95dc 458EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
1c155b3d 459
0817b62c
BB
460int __clk_mux_determine_rate_closest(struct clk_hw *hw,
461 struct clk_rate_request *req)
b2476490 462{
0817b62c 463 return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
4dff95dc
SB
464}
465EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
b2476490 466
4dff95dc 467/*** clk api ***/
496eadf8 468
4dff95dc
SB
469static void clk_core_unprepare(struct clk_core *core)
470{
a6334725
SB
471 lockdep_assert_held(&prepare_lock);
472
4dff95dc
SB
473 if (!core)
474 return;
b2476490 475
4dff95dc
SB
476 if (WARN_ON(core->prepare_count == 0))
477 return;
b2476490 478
2e20fbf5
LJ
479 if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL))
480 return;
481
4dff95dc
SB
482 if (--core->prepare_count > 0)
483 return;
b2476490 484
4dff95dc 485 WARN_ON(core->enable_count > 0);
b2476490 486
4dff95dc 487 trace_clk_unprepare(core);
b2476490 488
4dff95dc
SB
489 if (core->ops->unprepare)
490 core->ops->unprepare(core->hw);
491
492 trace_clk_unprepare_complete(core);
493 clk_core_unprepare(core->parent);
b2476490
MT
494}
495
a6adc30b
DA
496static void clk_core_unprepare_lock(struct clk_core *core)
497{
498 clk_prepare_lock();
499 clk_core_unprepare(core);
500 clk_prepare_unlock();
501}
502
4dff95dc
SB
503/**
504 * clk_unprepare - undo preparation of a clock source
505 * @clk: the clk being unprepared
506 *
507 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
508 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
509 * if the operation may sleep. One example is a clk which is accessed over
510 * I2c. In the complex case a clk gate operation may require a fast and a slow
511 * part. It is this reason that clk_unprepare and clk_disable are not mutually
512 * exclusive. In fact clk_disable must be called before clk_unprepare.
513 */
514void clk_unprepare(struct clk *clk)
1e435256 515{
4dff95dc
SB
516 if (IS_ERR_OR_NULL(clk))
517 return;
518
a6adc30b 519 clk_core_unprepare_lock(clk->core);
1e435256 520}
4dff95dc 521EXPORT_SYMBOL_GPL(clk_unprepare);
1e435256 522
4dff95dc 523static int clk_core_prepare(struct clk_core *core)
b2476490 524{
4dff95dc 525 int ret = 0;
b2476490 526
a6334725
SB
527 lockdep_assert_held(&prepare_lock);
528
4dff95dc 529 if (!core)
1e435256 530 return 0;
1e435256 531
4dff95dc
SB
532 if (core->prepare_count == 0) {
533 ret = clk_core_prepare(core->parent);
534 if (ret)
535 return ret;
b2476490 536
4dff95dc 537 trace_clk_prepare(core);
b2476490 538
4dff95dc
SB
539 if (core->ops->prepare)
540 ret = core->ops->prepare(core->hw);
b2476490 541
4dff95dc 542 trace_clk_prepare_complete(core);
1c155b3d 543
4dff95dc
SB
544 if (ret) {
545 clk_core_unprepare(core->parent);
546 return ret;
547 }
548 }
1c155b3d 549
4dff95dc 550 core->prepare_count++;
b2476490
MT
551
552 return 0;
553}
b2476490 554
a6adc30b
DA
555static int clk_core_prepare_lock(struct clk_core *core)
556{
557 int ret;
558
559 clk_prepare_lock();
560 ret = clk_core_prepare(core);
561 clk_prepare_unlock();
562
563 return ret;
564}
565
4dff95dc
SB
566/**
567 * clk_prepare - prepare a clock source
568 * @clk: the clk being prepared
569 *
570 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
571 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
572 * operation may sleep. One example is a clk which is accessed over I2c. In
573 * the complex case a clk ungate operation may require a fast and a slow part.
574 * It is this reason that clk_prepare and clk_enable are not mutually
575 * exclusive. In fact clk_prepare must be called before clk_enable.
576 * Returns 0 on success, -EERROR otherwise.
577 */
578int clk_prepare(struct clk *clk)
b2476490 579{
4dff95dc
SB
580 if (!clk)
581 return 0;
b2476490 582
a6adc30b 583 return clk_core_prepare_lock(clk->core);
b2476490 584}
4dff95dc 585EXPORT_SYMBOL_GPL(clk_prepare);
b2476490 586
4dff95dc 587static void clk_core_disable(struct clk_core *core)
b2476490 588{
a6334725
SB
589 lockdep_assert_held(&enable_lock);
590
4dff95dc
SB
591 if (!core)
592 return;
035a61c3 593
4dff95dc
SB
594 if (WARN_ON(core->enable_count == 0))
595 return;
b2476490 596
2e20fbf5
LJ
597 if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL))
598 return;
599
4dff95dc
SB
600 if (--core->enable_count > 0)
601 return;
035a61c3 602
2f87a6ea 603 trace_clk_disable_rcuidle(core);
035a61c3 604
4dff95dc
SB
605 if (core->ops->disable)
606 core->ops->disable(core->hw);
035a61c3 607
2f87a6ea 608 trace_clk_disable_complete_rcuidle(core);
035a61c3 609
4dff95dc 610 clk_core_disable(core->parent);
035a61c3 611}
7ef3dcc8 612
a6adc30b
DA
613static void clk_core_disable_lock(struct clk_core *core)
614{
615 unsigned long flags;
616
617 flags = clk_enable_lock();
618 clk_core_disable(core);
619 clk_enable_unlock(flags);
620}
621
4dff95dc
SB
622/**
623 * clk_disable - gate a clock
624 * @clk: the clk being gated
625 *
626 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
627 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
628 * clk if the operation is fast and will never sleep. One example is a
629 * SoC-internal clk which is controlled via simple register writes. In the
630 * complex case a clk gate operation may require a fast and a slow part. It is
631 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
632 * In fact clk_disable must be called before clk_unprepare.
633 */
634void clk_disable(struct clk *clk)
b2476490 635{
4dff95dc
SB
636 if (IS_ERR_OR_NULL(clk))
637 return;
638
a6adc30b 639 clk_core_disable_lock(clk->core);
b2476490 640}
4dff95dc 641EXPORT_SYMBOL_GPL(clk_disable);
b2476490 642
4dff95dc 643static int clk_core_enable(struct clk_core *core)
b2476490 644{
4dff95dc 645 int ret = 0;
b2476490 646
a6334725
SB
647 lockdep_assert_held(&enable_lock);
648
4dff95dc
SB
649 if (!core)
650 return 0;
b2476490 651
4dff95dc
SB
652 if (WARN_ON(core->prepare_count == 0))
653 return -ESHUTDOWN;
b2476490 654
4dff95dc
SB
655 if (core->enable_count == 0) {
656 ret = clk_core_enable(core->parent);
b2476490 657
4dff95dc
SB
658 if (ret)
659 return ret;
b2476490 660
f17a0dd1 661 trace_clk_enable_rcuidle(core);
035a61c3 662
4dff95dc
SB
663 if (core->ops->enable)
664 ret = core->ops->enable(core->hw);
035a61c3 665
f17a0dd1 666 trace_clk_enable_complete_rcuidle(core);
4dff95dc
SB
667
668 if (ret) {
669 clk_core_disable(core->parent);
670 return ret;
671 }
672 }
673
674 core->enable_count++;
675 return 0;
035a61c3 676}
b2476490 677
a6adc30b
DA
678static int clk_core_enable_lock(struct clk_core *core)
679{
680 unsigned long flags;
681 int ret;
682
683 flags = clk_enable_lock();
684 ret = clk_core_enable(core);
685 clk_enable_unlock(flags);
686
687 return ret;
688}
689
4dff95dc
SB
690/**
691 * clk_enable - ungate a clock
692 * @clk: the clk being ungated
693 *
694 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
695 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
696 * if the operation will never sleep. One example is a SoC-internal clk which
697 * is controlled via simple register writes. In the complex case a clk ungate
698 * operation may require a fast and a slow part. It is this reason that
699 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
700 * must be called before clk_enable. Returns 0 on success, -EERROR
701 * otherwise.
702 */
703int clk_enable(struct clk *clk)
5279fc40 704{
4dff95dc 705 if (!clk)
5279fc40
BB
706 return 0;
707
a6adc30b
DA
708 return clk_core_enable_lock(clk->core);
709}
710EXPORT_SYMBOL_GPL(clk_enable);
711
712static int clk_core_prepare_enable(struct clk_core *core)
713{
714 int ret;
715
716 ret = clk_core_prepare_lock(core);
717 if (ret)
718 return ret;
719
720 ret = clk_core_enable_lock(core);
721 if (ret)
722 clk_core_unprepare_lock(core);
5279fc40 723
4dff95dc 724 return ret;
b2476490 725}
a6adc30b
DA
726
727static void clk_core_disable_unprepare(struct clk_core *core)
728{
729 clk_core_disable_lock(core);
730 clk_core_unprepare_lock(core);
731}
b2476490 732
7ec986ef
DA
733static void clk_unprepare_unused_subtree(struct clk_core *core)
734{
735 struct clk_core *child;
736
737 lockdep_assert_held(&prepare_lock);
738
739 hlist_for_each_entry(child, &core->children, child_node)
740 clk_unprepare_unused_subtree(child);
741
742 if (core->prepare_count)
743 return;
744
745 if (core->flags & CLK_IGNORE_UNUSED)
746 return;
747
748 if (clk_core_is_prepared(core)) {
749 trace_clk_unprepare(core);
750 if (core->ops->unprepare_unused)
751 core->ops->unprepare_unused(core->hw);
752 else if (core->ops->unprepare)
753 core->ops->unprepare(core->hw);
754 trace_clk_unprepare_complete(core);
755 }
756}
757
758static void clk_disable_unused_subtree(struct clk_core *core)
759{
760 struct clk_core *child;
761 unsigned long flags;
762
763 lockdep_assert_held(&prepare_lock);
764
765 hlist_for_each_entry(child, &core->children, child_node)
766 clk_disable_unused_subtree(child);
767
a4b3518d
DA
768 if (core->flags & CLK_OPS_PARENT_ENABLE)
769 clk_core_prepare_enable(core->parent);
770
7ec986ef
DA
771 flags = clk_enable_lock();
772
773 if (core->enable_count)
774 goto unlock_out;
775
776 if (core->flags & CLK_IGNORE_UNUSED)
777 goto unlock_out;
778
779 /*
780 * some gate clocks have special needs during the disable-unused
781 * sequence. call .disable_unused if available, otherwise fall
782 * back to .disable
783 */
784 if (clk_core_is_enabled(core)) {
785 trace_clk_disable(core);
786 if (core->ops->disable_unused)
787 core->ops->disable_unused(core->hw);
788 else if (core->ops->disable)
789 core->ops->disable(core->hw);
790 trace_clk_disable_complete(core);
791 }
792
793unlock_out:
794 clk_enable_unlock(flags);
a4b3518d
DA
795 if (core->flags & CLK_OPS_PARENT_ENABLE)
796 clk_core_disable_unprepare(core->parent);
7ec986ef
DA
797}
798
799static bool clk_ignore_unused;
800static int __init clk_ignore_unused_setup(char *__unused)
801{
802 clk_ignore_unused = true;
803 return 1;
804}
805__setup("clk_ignore_unused", clk_ignore_unused_setup);
806
807static int clk_disable_unused(void)
808{
809 struct clk_core *core;
810
811 if (clk_ignore_unused) {
812 pr_warn("clk: Not disabling unused clocks\n");
813 return 0;
814 }
815
816 clk_prepare_lock();
817
818 hlist_for_each_entry(core, &clk_root_list, child_node)
819 clk_disable_unused_subtree(core);
820
821 hlist_for_each_entry(core, &clk_orphan_list, child_node)
822 clk_disable_unused_subtree(core);
823
824 hlist_for_each_entry(core, &clk_root_list, child_node)
825 clk_unprepare_unused_subtree(core);
826
827 hlist_for_each_entry(core, &clk_orphan_list, child_node)
828 clk_unprepare_unused_subtree(core);
829
830 clk_prepare_unlock();
831
832 return 0;
833}
834late_initcall_sync(clk_disable_unused);
835
0817b62c
BB
836static int clk_core_round_rate_nolock(struct clk_core *core,
837 struct clk_rate_request *req)
3d6ee287 838{
4dff95dc 839 struct clk_core *parent;
0817b62c 840 long rate;
4dff95dc
SB
841
842 lockdep_assert_held(&prepare_lock);
3d6ee287 843
d6968fca 844 if (!core)
4dff95dc 845 return 0;
3d6ee287 846
4dff95dc 847 parent = core->parent;
0817b62c
BB
848 if (parent) {
849 req->best_parent_hw = parent->hw;
850 req->best_parent_rate = parent->rate;
851 } else {
852 req->best_parent_hw = NULL;
853 req->best_parent_rate = 0;
854 }
3d6ee287 855
4dff95dc 856 if (core->ops->determine_rate) {
0817b62c
BB
857 return core->ops->determine_rate(core->hw, req);
858 } else if (core->ops->round_rate) {
859 rate = core->ops->round_rate(core->hw, req->rate,
860 &req->best_parent_rate);
861 if (rate < 0)
862 return rate;
863
864 req->rate = rate;
865 } else if (core->flags & CLK_SET_RATE_PARENT) {
866 return clk_core_round_rate_nolock(parent, req);
867 } else {
868 req->rate = core->rate;
869 }
870
871 return 0;
3d6ee287
UH
872}
873
4dff95dc
SB
874/**
875 * __clk_determine_rate - get the closest rate actually supported by a clock
876 * @hw: determine the rate of this clock
2d5b520c 877 * @req: target rate request
4dff95dc 878 *
6e5ab41b 879 * Useful for clk_ops such as .set_rate and .determine_rate.
4dff95dc 880 */
0817b62c 881int __clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
035a61c3 882{
0817b62c
BB
883 if (!hw) {
884 req->rate = 0;
4dff95dc 885 return 0;
0817b62c 886 }
035a61c3 887
0817b62c 888 return clk_core_round_rate_nolock(hw->core, req);
035a61c3 889}
4dff95dc 890EXPORT_SYMBOL_GPL(__clk_determine_rate);
035a61c3 891
1a9c069c
SB
892unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
893{
894 int ret;
895 struct clk_rate_request req;
896
897 clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);
898 req.rate = rate;
899
900 ret = clk_core_round_rate_nolock(hw->core, &req);
901 if (ret)
902 return 0;
903
904 return req.rate;
905}
906EXPORT_SYMBOL_GPL(clk_hw_round_rate);
907
4dff95dc
SB
908/**
909 * clk_round_rate - round the given rate for a clk
910 * @clk: the clk for which we are rounding a rate
911 * @rate: the rate which is to be rounded
912 *
913 * Takes in a rate as input and rounds it to a rate that the clk can actually
914 * use which is then returned. If clk doesn't support round_rate operation
915 * then the parent rate is returned.
916 */
917long clk_round_rate(struct clk *clk, unsigned long rate)
035a61c3 918{
fc4a05d4
SB
919 struct clk_rate_request req;
920 int ret;
4dff95dc 921
035a61c3 922 if (!clk)
4dff95dc 923 return 0;
035a61c3 924
4dff95dc 925 clk_prepare_lock();
fc4a05d4
SB
926
927 clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
928 req.rate = rate;
929
930 ret = clk_core_round_rate_nolock(clk->core, &req);
4dff95dc
SB
931 clk_prepare_unlock();
932
fc4a05d4
SB
933 if (ret)
934 return ret;
935
936 return req.rate;
035a61c3 937}
4dff95dc 938EXPORT_SYMBOL_GPL(clk_round_rate);
b2476490 939
4dff95dc
SB
940/**
941 * __clk_notify - call clk notifier chain
942 * @core: clk that is changing rate
943 * @msg: clk notifier type (see include/linux/clk.h)
944 * @old_rate: old clk rate
945 * @new_rate: new clk rate
946 *
947 * Triggers a notifier call chain on the clk rate-change notification
948 * for 'clk'. Passes a pointer to the struct clk and the previous
949 * and current rates to the notifier callback. Intended to be called by
950 * internal clock code only. Returns NOTIFY_DONE from the last driver
951 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
952 * a driver returns that.
953 */
954static int __clk_notify(struct clk_core *core, unsigned long msg,
955 unsigned long old_rate, unsigned long new_rate)
b2476490 956{
4dff95dc
SB
957 struct clk_notifier *cn;
958 struct clk_notifier_data cnd;
959 int ret = NOTIFY_DONE;
b2476490 960
4dff95dc
SB
961 cnd.old_rate = old_rate;
962 cnd.new_rate = new_rate;
b2476490 963
4dff95dc
SB
964 list_for_each_entry(cn, &clk_notifier_list, node) {
965 if (cn->clk->core == core) {
966 cnd.clk = cn->clk;
967 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
968 &cnd);
969 }
b2476490
MT
970 }
971
4dff95dc 972 return ret;
b2476490
MT
973}
974
4dff95dc
SB
975/**
976 * __clk_recalc_accuracies
977 * @core: first clk in the subtree
978 *
979 * Walks the subtree of clks starting with clk and recalculates accuracies as
980 * it goes. Note that if a clk does not implement the .recalc_accuracy
6e5ab41b 981 * callback then it is assumed that the clock will take on the accuracy of its
4dff95dc 982 * parent.
4dff95dc
SB
983 */
984static void __clk_recalc_accuracies(struct clk_core *core)
b2476490 985{
4dff95dc
SB
986 unsigned long parent_accuracy = 0;
987 struct clk_core *child;
b2476490 988
4dff95dc 989 lockdep_assert_held(&prepare_lock);
b2476490 990
4dff95dc
SB
991 if (core->parent)
992 parent_accuracy = core->parent->accuracy;
b2476490 993
4dff95dc
SB
994 if (core->ops->recalc_accuracy)
995 core->accuracy = core->ops->recalc_accuracy(core->hw,
996 parent_accuracy);
997 else
998 core->accuracy = parent_accuracy;
b2476490 999
4dff95dc
SB
1000 hlist_for_each_entry(child, &core->children, child_node)
1001 __clk_recalc_accuracies(child);
b2476490
MT
1002}
1003
4dff95dc 1004static long clk_core_get_accuracy(struct clk_core *core)
e366fdd7 1005{
4dff95dc 1006 unsigned long accuracy;
15a02c1f 1007
4dff95dc
SB
1008 clk_prepare_lock();
1009 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
1010 __clk_recalc_accuracies(core);
15a02c1f 1011
4dff95dc
SB
1012 accuracy = __clk_get_accuracy(core);
1013 clk_prepare_unlock();
e366fdd7 1014
4dff95dc 1015 return accuracy;
e366fdd7 1016}
15a02c1f 1017
4dff95dc
SB
1018/**
1019 * clk_get_accuracy - return the accuracy of clk
1020 * @clk: the clk whose accuracy is being returned
1021 *
1022 * Simply returns the cached accuracy of the clk, unless
1023 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
1024 * issued.
1025 * If clk is NULL then returns 0.
1026 */
1027long clk_get_accuracy(struct clk *clk)
035a61c3 1028{
4dff95dc
SB
1029 if (!clk)
1030 return 0;
035a61c3 1031
4dff95dc 1032 return clk_core_get_accuracy(clk->core);
035a61c3 1033}
4dff95dc 1034EXPORT_SYMBOL_GPL(clk_get_accuracy);
035a61c3 1035
4dff95dc
SB
1036static unsigned long clk_recalc(struct clk_core *core,
1037 unsigned long parent_rate)
1c8e6004 1038{
4dff95dc
SB
1039 if (core->ops->recalc_rate)
1040 return core->ops->recalc_rate(core->hw, parent_rate);
1041 return parent_rate;
1c8e6004
TV
1042}
1043
4dff95dc
SB
1044/**
1045 * __clk_recalc_rates
1046 * @core: first clk in the subtree
1047 * @msg: notification type (see include/linux/clk.h)
1048 *
1049 * Walks the subtree of clks starting with clk and recalculates rates as it
1050 * goes. Note that if a clk does not implement the .recalc_rate callback then
1051 * it is assumed that the clock will take on the rate of its parent.
1052 *
1053 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1054 * if necessary.
15a02c1f 1055 */
4dff95dc 1056static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
15a02c1f 1057{
4dff95dc
SB
1058 unsigned long old_rate;
1059 unsigned long parent_rate = 0;
1060 struct clk_core *child;
e366fdd7 1061
4dff95dc 1062 lockdep_assert_held(&prepare_lock);
15a02c1f 1063
4dff95dc 1064 old_rate = core->rate;
b2476490 1065
4dff95dc
SB
1066 if (core->parent)
1067 parent_rate = core->parent->rate;
b2476490 1068
4dff95dc 1069 core->rate = clk_recalc(core, parent_rate);
b2476490 1070
4dff95dc
SB
1071 /*
1072 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1073 * & ABORT_RATE_CHANGE notifiers
1074 */
1075 if (core->notifier_count && msg)
1076 __clk_notify(core, msg, old_rate, core->rate);
b2476490 1077
4dff95dc
SB
1078 hlist_for_each_entry(child, &core->children, child_node)
1079 __clk_recalc_rates(child, msg);
1080}
b2476490 1081
4dff95dc
SB
1082static unsigned long clk_core_get_rate(struct clk_core *core)
1083{
1084 unsigned long rate;
dfc202ea 1085
4dff95dc 1086 clk_prepare_lock();
b2476490 1087
4dff95dc
SB
1088 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1089 __clk_recalc_rates(core, 0);
1090
1091 rate = clk_core_get_rate_nolock(core);
1092 clk_prepare_unlock();
1093
1094 return rate;
b2476490
MT
1095}
1096
1097/**
4dff95dc
SB
1098 * clk_get_rate - return the rate of clk
1099 * @clk: the clk whose rate is being returned
b2476490 1100 *
4dff95dc
SB
1101 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1102 * is set, which means a recalc_rate will be issued.
1103 * If clk is NULL then returns 0.
b2476490 1104 */
4dff95dc 1105unsigned long clk_get_rate(struct clk *clk)
b2476490 1106{
4dff95dc
SB
1107 if (!clk)
1108 return 0;
63589e92 1109
4dff95dc 1110 return clk_core_get_rate(clk->core);
b2476490 1111}
4dff95dc 1112EXPORT_SYMBOL_GPL(clk_get_rate);
b2476490 1113
4dff95dc
SB
1114static int clk_fetch_parent_index(struct clk_core *core,
1115 struct clk_core *parent)
b2476490 1116{
4dff95dc 1117 int i;
b2476490 1118
508f884a
MY
1119 if (!parent)
1120 return -EINVAL;
1121
470b5e2f
MY
1122 for (i = 0; i < core->num_parents; i++)
1123 if (clk_core_get_parent_by_index(core, i) == parent)
4dff95dc 1124 return i;
b2476490 1125
4dff95dc 1126 return -EINVAL;
b2476490
MT
1127}
1128
e6500344
HS
1129/*
1130 * Update the orphan status of @core and all its children.
1131 */
1132static void clk_core_update_orphan_status(struct clk_core *core, bool is_orphan)
1133{
1134 struct clk_core *child;
1135
1136 core->orphan = is_orphan;
1137
1138 hlist_for_each_entry(child, &core->children, child_node)
1139 clk_core_update_orphan_status(child, is_orphan);
1140}
1141
4dff95dc 1142static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
b2476490 1143{
e6500344
HS
1144 bool was_orphan = core->orphan;
1145
4dff95dc 1146 hlist_del(&core->child_node);
035a61c3 1147
4dff95dc 1148 if (new_parent) {
e6500344
HS
1149 bool becomes_orphan = new_parent->orphan;
1150
4dff95dc
SB
1151 /* avoid duplicate POST_RATE_CHANGE notifications */
1152 if (new_parent->new_child == core)
1153 new_parent->new_child = NULL;
b2476490 1154
4dff95dc 1155 hlist_add_head(&core->child_node, &new_parent->children);
e6500344
HS
1156
1157 if (was_orphan != becomes_orphan)
1158 clk_core_update_orphan_status(core, becomes_orphan);
4dff95dc
SB
1159 } else {
1160 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
1161 if (!was_orphan)
1162 clk_core_update_orphan_status(core, true);
4dff95dc 1163 }
dfc202ea 1164
4dff95dc 1165 core->parent = new_parent;
035a61c3
TV
1166}
1167
4dff95dc
SB
1168static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1169 struct clk_core *parent)
b2476490
MT
1170{
1171 unsigned long flags;
4dff95dc 1172 struct clk_core *old_parent = core->parent;
b2476490 1173
4dff95dc 1174 /*
fc8726a2
DA
1175 * 1. enable parents for CLK_OPS_PARENT_ENABLE clock
1176 *
1177 * 2. Migrate prepare state between parents and prevent race with
4dff95dc
SB
1178 * clk_enable().
1179 *
1180 * If the clock is not prepared, then a race with
1181 * clk_enable/disable() is impossible since we already have the
1182 * prepare lock (future calls to clk_enable() need to be preceded by
1183 * a clk_prepare()).
1184 *
1185 * If the clock is prepared, migrate the prepared state to the new
1186 * parent and also protect against a race with clk_enable() by
1187 * forcing the clock and the new parent on. This ensures that all
1188 * future calls to clk_enable() are practically NOPs with respect to
1189 * hardware and software states.
1190 *
1191 * See also: Comment for clk_set_parent() below.
1192 */
fc8726a2
DA
1193
1194 /* enable old_parent & parent if CLK_OPS_PARENT_ENABLE is set */
1195 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1196 clk_core_prepare_enable(old_parent);
1197 clk_core_prepare_enable(parent);
1198 }
1199
1200 /* migrate prepare count if > 0 */
4dff95dc 1201 if (core->prepare_count) {
fc8726a2
DA
1202 clk_core_prepare_enable(parent);
1203 clk_core_enable_lock(core);
4dff95dc 1204 }
63589e92 1205
4dff95dc 1206 /* update the clk tree topology */
eab89f69 1207 flags = clk_enable_lock();
4dff95dc 1208 clk_reparent(core, parent);
eab89f69 1209 clk_enable_unlock(flags);
4dff95dc
SB
1210
1211 return old_parent;
b2476490 1212}
b2476490 1213
4dff95dc
SB
1214static void __clk_set_parent_after(struct clk_core *core,
1215 struct clk_core *parent,
1216 struct clk_core *old_parent)
b2476490 1217{
4dff95dc
SB
1218 /*
1219 * Finish the migration of prepare state and undo the changes done
1220 * for preventing a race with clk_enable().
1221 */
1222 if (core->prepare_count) {
fc8726a2
DA
1223 clk_core_disable_lock(core);
1224 clk_core_disable_unprepare(old_parent);
1225 }
1226
1227 /* re-balance ref counting if CLK_OPS_PARENT_ENABLE is set */
1228 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1229 clk_core_disable_unprepare(parent);
1230 clk_core_disable_unprepare(old_parent);
4dff95dc
SB
1231 }
1232}
b2476490 1233
4dff95dc
SB
1234static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
1235 u8 p_index)
1236{
1237 unsigned long flags;
1238 int ret = 0;
1239 struct clk_core *old_parent;
b2476490 1240
4dff95dc 1241 old_parent = __clk_set_parent_before(core, parent);
b2476490 1242
4dff95dc 1243 trace_clk_set_parent(core, parent);
b2476490 1244
4dff95dc
SB
1245 /* change clock input source */
1246 if (parent && core->ops->set_parent)
1247 ret = core->ops->set_parent(core->hw, p_index);
dfc202ea 1248
4dff95dc 1249 trace_clk_set_parent_complete(core, parent);
dfc202ea 1250
4dff95dc
SB
1251 if (ret) {
1252 flags = clk_enable_lock();
1253 clk_reparent(core, old_parent);
1254 clk_enable_unlock(flags);
c660b2eb 1255 __clk_set_parent_after(core, old_parent, parent);
dfc202ea 1256
4dff95dc 1257 return ret;
b2476490
MT
1258 }
1259
4dff95dc
SB
1260 __clk_set_parent_after(core, parent, old_parent);
1261
b2476490
MT
1262 return 0;
1263}
1264
1265/**
4dff95dc
SB
1266 * __clk_speculate_rates
1267 * @core: first clk in the subtree
1268 * @parent_rate: the "future" rate of clk's parent
b2476490 1269 *
4dff95dc
SB
1270 * Walks the subtree of clks starting with clk, speculating rates as it
1271 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1272 *
1273 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1274 * pre-rate change notifications and returns early if no clks in the
1275 * subtree have subscribed to the notifications. Note that if a clk does not
1276 * implement the .recalc_rate callback then it is assumed that the clock will
1277 * take on the rate of its parent.
b2476490 1278 */
4dff95dc
SB
1279static int __clk_speculate_rates(struct clk_core *core,
1280 unsigned long parent_rate)
b2476490 1281{
4dff95dc
SB
1282 struct clk_core *child;
1283 unsigned long new_rate;
1284 int ret = NOTIFY_DONE;
b2476490 1285
4dff95dc 1286 lockdep_assert_held(&prepare_lock);
864e160a 1287
4dff95dc
SB
1288 new_rate = clk_recalc(core, parent_rate);
1289
1290 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1291 if (core->notifier_count)
1292 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
1293
1294 if (ret & NOTIFY_STOP_MASK) {
1295 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1296 __func__, core->name, ret);
1297 goto out;
1298 }
1299
1300 hlist_for_each_entry(child, &core->children, child_node) {
1301 ret = __clk_speculate_rates(child, new_rate);
1302 if (ret & NOTIFY_STOP_MASK)
1303 break;
1304 }
b2476490 1305
4dff95dc 1306out:
b2476490
MT
1307 return ret;
1308}
b2476490 1309
4dff95dc
SB
1310static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
1311 struct clk_core *new_parent, u8 p_index)
b2476490 1312{
4dff95dc 1313 struct clk_core *child;
b2476490 1314
4dff95dc
SB
1315 core->new_rate = new_rate;
1316 core->new_parent = new_parent;
1317 core->new_parent_index = p_index;
1318 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1319 core->new_child = NULL;
1320 if (new_parent && new_parent != core->parent)
1321 new_parent->new_child = core;
496eadf8 1322
4dff95dc
SB
1323 hlist_for_each_entry(child, &core->children, child_node) {
1324 child->new_rate = clk_recalc(child, new_rate);
1325 clk_calc_subtree(child, child->new_rate, NULL, 0);
1326 }
1327}
b2476490 1328
4dff95dc
SB
1329/*
1330 * calculate the new rates returning the topmost clock that has to be
1331 * changed.
1332 */
1333static struct clk_core *clk_calc_new_rates(struct clk_core *core,
1334 unsigned long rate)
1335{
1336 struct clk_core *top = core;
1337 struct clk_core *old_parent, *parent;
4dff95dc
SB
1338 unsigned long best_parent_rate = 0;
1339 unsigned long new_rate;
1340 unsigned long min_rate;
1341 unsigned long max_rate;
1342 int p_index = 0;
1343 long ret;
1344
1345 /* sanity */
1346 if (IS_ERR_OR_NULL(core))
1347 return NULL;
1348
1349 /* save parent rate, if it exists */
1350 parent = old_parent = core->parent;
71472c0c 1351 if (parent)
4dff95dc 1352 best_parent_rate = parent->rate;
71472c0c 1353
4dff95dc
SB
1354 clk_core_get_boundaries(core, &min_rate, &max_rate);
1355
1356 /* find the closest rate and parent clk/rate */
d6968fca 1357 if (core->ops->determine_rate) {
0817b62c
BB
1358 struct clk_rate_request req;
1359
1360 req.rate = rate;
1361 req.min_rate = min_rate;
1362 req.max_rate = max_rate;
1363 if (parent) {
1364 req.best_parent_hw = parent->hw;
1365 req.best_parent_rate = parent->rate;
1366 } else {
1367 req.best_parent_hw = NULL;
1368 req.best_parent_rate = 0;
1369 }
1370
1371 ret = core->ops->determine_rate(core->hw, &req);
4dff95dc
SB
1372 if (ret < 0)
1373 return NULL;
1c8e6004 1374
0817b62c
BB
1375 best_parent_rate = req.best_parent_rate;
1376 new_rate = req.rate;
1377 parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
4dff95dc
SB
1378 } else if (core->ops->round_rate) {
1379 ret = core->ops->round_rate(core->hw, rate,
0817b62c 1380 &best_parent_rate);
4dff95dc
SB
1381 if (ret < 0)
1382 return NULL;
035a61c3 1383
4dff95dc
SB
1384 new_rate = ret;
1385 if (new_rate < min_rate || new_rate > max_rate)
1386 return NULL;
1387 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
1388 /* pass-through clock without adjustable parent */
1389 core->new_rate = core->rate;
1390 return NULL;
1391 } else {
1392 /* pass-through clock with adjustable parent */
1393 top = clk_calc_new_rates(parent, rate);
1394 new_rate = parent->new_rate;
1395 goto out;
1396 }
1c8e6004 1397
4dff95dc
SB
1398 /* some clocks must be gated to change parent */
1399 if (parent != old_parent &&
1400 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1401 pr_debug("%s: %s not gated but wants to reparent\n",
1402 __func__, core->name);
1403 return NULL;
1404 }
b2476490 1405
4dff95dc
SB
1406 /* try finding the new parent index */
1407 if (parent && core->num_parents > 1) {
1408 p_index = clk_fetch_parent_index(core, parent);
1409 if (p_index < 0) {
1410 pr_debug("%s: clk %s can not be parent of clk %s\n",
1411 __func__, parent->name, core->name);
1412 return NULL;
1413 }
1414 }
b2476490 1415
4dff95dc
SB
1416 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
1417 best_parent_rate != parent->rate)
1418 top = clk_calc_new_rates(parent, best_parent_rate);
035a61c3 1419
4dff95dc
SB
1420out:
1421 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490 1422
4dff95dc 1423 return top;
b2476490 1424}
b2476490 1425
4dff95dc
SB
1426/*
1427 * Notify about rate changes in a subtree. Always walk down the whole tree
1428 * so that in case of an error we can walk down the whole tree again and
1429 * abort the change.
b2476490 1430 */
4dff95dc
SB
1431static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
1432 unsigned long event)
b2476490 1433{
4dff95dc 1434 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1435 int ret = NOTIFY_DONE;
1436
4dff95dc
SB
1437 if (core->rate == core->new_rate)
1438 return NULL;
b2476490 1439
4dff95dc
SB
1440 if (core->notifier_count) {
1441 ret = __clk_notify(core, event, core->rate, core->new_rate);
1442 if (ret & NOTIFY_STOP_MASK)
1443 fail_clk = core;
b2476490
MT
1444 }
1445
4dff95dc
SB
1446 hlist_for_each_entry(child, &core->children, child_node) {
1447 /* Skip children who will be reparented to another clock */
1448 if (child->new_parent && child->new_parent != core)
1449 continue;
1450 tmp_clk = clk_propagate_rate_change(child, event);
1451 if (tmp_clk)
1452 fail_clk = tmp_clk;
1453 }
5279fc40 1454
4dff95dc
SB
1455 /* handle the new child who might not be in core->children yet */
1456 if (core->new_child) {
1457 tmp_clk = clk_propagate_rate_change(core->new_child, event);
1458 if (tmp_clk)
1459 fail_clk = tmp_clk;
1460 }
5279fc40 1461
4dff95dc 1462 return fail_clk;
5279fc40
BB
1463}
1464
4dff95dc
SB
1465/*
1466 * walk down a subtree and set the new rates notifying the rate
1467 * change on the way
1468 */
1469static void clk_change_rate(struct clk_core *core)
035a61c3 1470{
4dff95dc
SB
1471 struct clk_core *child;
1472 struct hlist_node *tmp;
1473 unsigned long old_rate;
1474 unsigned long best_parent_rate = 0;
1475 bool skip_set_rate = false;
1476 struct clk_core *old_parent;
fc8726a2 1477 struct clk_core *parent = NULL;
035a61c3 1478
4dff95dc 1479 old_rate = core->rate;
035a61c3 1480
fc8726a2
DA
1481 if (core->new_parent) {
1482 parent = core->new_parent;
4dff95dc 1483 best_parent_rate = core->new_parent->rate;
fc8726a2
DA
1484 } else if (core->parent) {
1485 parent = core->parent;
4dff95dc 1486 best_parent_rate = core->parent->rate;
fc8726a2 1487 }
035a61c3 1488
2eb8c710
HS
1489 if (core->flags & CLK_SET_RATE_UNGATE) {
1490 unsigned long flags;
1491
1492 clk_core_prepare(core);
1493 flags = clk_enable_lock();
1494 clk_core_enable(core);
1495 clk_enable_unlock(flags);
1496 }
1497
4dff95dc
SB
1498 if (core->new_parent && core->new_parent != core->parent) {
1499 old_parent = __clk_set_parent_before(core, core->new_parent);
1500 trace_clk_set_parent(core, core->new_parent);
5279fc40 1501
4dff95dc
SB
1502 if (core->ops->set_rate_and_parent) {
1503 skip_set_rate = true;
1504 core->ops->set_rate_and_parent(core->hw, core->new_rate,
1505 best_parent_rate,
1506 core->new_parent_index);
1507 } else if (core->ops->set_parent) {
1508 core->ops->set_parent(core->hw, core->new_parent_index);
1509 }
5279fc40 1510
4dff95dc
SB
1511 trace_clk_set_parent_complete(core, core->new_parent);
1512 __clk_set_parent_after(core, core->new_parent, old_parent);
1513 }
8f2c2db1 1514
fc8726a2
DA
1515 if (core->flags & CLK_OPS_PARENT_ENABLE)
1516 clk_core_prepare_enable(parent);
1517
4dff95dc 1518 trace_clk_set_rate(core, core->new_rate);
b2476490 1519
4dff95dc
SB
1520 if (!skip_set_rate && core->ops->set_rate)
1521 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
496eadf8 1522
4dff95dc 1523 trace_clk_set_rate_complete(core, core->new_rate);
b2476490 1524
4dff95dc 1525 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1526
2eb8c710
HS
1527 if (core->flags & CLK_SET_RATE_UNGATE) {
1528 unsigned long flags;
1529
1530 flags = clk_enable_lock();
1531 clk_core_disable(core);
1532 clk_enable_unlock(flags);
1533 clk_core_unprepare(core);
1534 }
1535
fc8726a2
DA
1536 if (core->flags & CLK_OPS_PARENT_ENABLE)
1537 clk_core_disable_unprepare(parent);
1538
4dff95dc
SB
1539 if (core->notifier_count && old_rate != core->rate)
1540 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1541
85e88fab
MT
1542 if (core->flags & CLK_RECALC_NEW_RATES)
1543 (void)clk_calc_new_rates(core, core->new_rate);
d8d91987 1544
b2476490 1545 /*
4dff95dc
SB
1546 * Use safe iteration, as change_rate can actually swap parents
1547 * for certain clock types.
b2476490 1548 */
4dff95dc
SB
1549 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
1550 /* Skip children who will be reparented to another clock */
1551 if (child->new_parent && child->new_parent != core)
1552 continue;
1553 clk_change_rate(child);
1554 }
b2476490 1555
4dff95dc
SB
1556 /* handle the new child who might not be in core->children yet */
1557 if (core->new_child)
1558 clk_change_rate(core->new_child);
b2476490
MT
1559}
1560
4dff95dc
SB
1561static int clk_core_set_rate_nolock(struct clk_core *core,
1562 unsigned long req_rate)
a093bde2 1563{
4dff95dc
SB
1564 struct clk_core *top, *fail_clk;
1565 unsigned long rate = req_rate;
a093bde2 1566
4dff95dc
SB
1567 if (!core)
1568 return 0;
a093bde2 1569
4dff95dc
SB
1570 /* bail early if nothing to do */
1571 if (rate == clk_core_get_rate_nolock(core))
1572 return 0;
a093bde2 1573
4dff95dc
SB
1574 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1575 return -EBUSY;
a093bde2 1576
4dff95dc
SB
1577 /* calculate new rates and get the topmost changed clock */
1578 top = clk_calc_new_rates(core, rate);
1579 if (!top)
1580 return -EINVAL;
1581
1582 /* notify that we are about to change rates */
1583 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1584 if (fail_clk) {
1585 pr_debug("%s: failed to set %s rate\n", __func__,
1586 fail_clk->name);
1587 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1588 return -EBUSY;
1589 }
1590
1591 /* change the rates */
1592 clk_change_rate(top);
1593
1594 core->req_rate = req_rate;
1595
06b37e4a 1596 return 0;
a093bde2 1597}
035a61c3
TV
1598
1599/**
4dff95dc
SB
1600 * clk_set_rate - specify a new rate for clk
1601 * @clk: the clk whose rate is being changed
1602 * @rate: the new rate for clk
035a61c3 1603 *
4dff95dc
SB
1604 * In the simplest case clk_set_rate will only adjust the rate of clk.
1605 *
1606 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1607 * propagate up to clk's parent; whether or not this happens depends on the
1608 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1609 * after calling .round_rate then upstream parent propagation is ignored. If
1610 * *parent_rate comes back with a new rate for clk's parent then we propagate
1611 * up to clk's parent and set its rate. Upward propagation will continue
1612 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1613 * .round_rate stops requesting changes to clk's parent_rate.
1614 *
1615 * Rate changes are accomplished via tree traversal that also recalculates the
1616 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
1617 *
1618 * Returns 0 on success, -EERROR otherwise.
035a61c3 1619 */
4dff95dc 1620int clk_set_rate(struct clk *clk, unsigned long rate)
035a61c3 1621{
4dff95dc
SB
1622 int ret;
1623
035a61c3
TV
1624 if (!clk)
1625 return 0;
1626
4dff95dc
SB
1627 /* prevent racing with updates to the clock topology */
1628 clk_prepare_lock();
da0f0b2c 1629
4dff95dc 1630 ret = clk_core_set_rate_nolock(clk->core, rate);
da0f0b2c 1631
4dff95dc 1632 clk_prepare_unlock();
4935b22c 1633
4dff95dc 1634 return ret;
4935b22c 1635}
4dff95dc 1636EXPORT_SYMBOL_GPL(clk_set_rate);
4935b22c 1637
4dff95dc
SB
1638/**
1639 * clk_set_rate_range - set a rate range for a clock source
1640 * @clk: clock source
1641 * @min: desired minimum clock rate in Hz, inclusive
1642 * @max: desired maximum clock rate in Hz, inclusive
1643 *
1644 * Returns success (0) or negative errno.
1645 */
1646int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
4935b22c 1647{
4dff95dc 1648 int ret = 0;
4935b22c 1649
4dff95dc
SB
1650 if (!clk)
1651 return 0;
903efc55 1652
4dff95dc
SB
1653 if (min > max) {
1654 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1655 __func__, clk->core->name, clk->dev_id, clk->con_id,
1656 min, max);
1657 return -EINVAL;
903efc55 1658 }
4935b22c 1659
4dff95dc 1660 clk_prepare_lock();
4935b22c 1661
4dff95dc
SB
1662 if (min != clk->min_rate || max != clk->max_rate) {
1663 clk->min_rate = min;
1664 clk->max_rate = max;
1665 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
4935b22c
JH
1666 }
1667
4dff95dc 1668 clk_prepare_unlock();
4935b22c 1669
4dff95dc 1670 return ret;
3fa2252b 1671}
4dff95dc 1672EXPORT_SYMBOL_GPL(clk_set_rate_range);
3fa2252b 1673
4dff95dc
SB
1674/**
1675 * clk_set_min_rate - set a minimum clock rate for a clock source
1676 * @clk: clock source
1677 * @rate: desired minimum clock rate in Hz, inclusive
1678 *
1679 * Returns success (0) or negative errno.
1680 */
1681int clk_set_min_rate(struct clk *clk, unsigned long rate)
3fa2252b 1682{
4dff95dc
SB
1683 if (!clk)
1684 return 0;
1685
1686 return clk_set_rate_range(clk, rate, clk->max_rate);
3fa2252b 1687}
4dff95dc 1688EXPORT_SYMBOL_GPL(clk_set_min_rate);
3fa2252b 1689
4dff95dc
SB
1690/**
1691 * clk_set_max_rate - set a maximum clock rate for a clock source
1692 * @clk: clock source
1693 * @rate: desired maximum clock rate in Hz, inclusive
1694 *
1695 * Returns success (0) or negative errno.
1696 */
1697int clk_set_max_rate(struct clk *clk, unsigned long rate)
3fa2252b 1698{
4dff95dc
SB
1699 if (!clk)
1700 return 0;
4935b22c 1701
4dff95dc 1702 return clk_set_rate_range(clk, clk->min_rate, rate);
4935b22c 1703}
4dff95dc 1704EXPORT_SYMBOL_GPL(clk_set_max_rate);
4935b22c 1705
b2476490 1706/**
4dff95dc
SB
1707 * clk_get_parent - return the parent of a clk
1708 * @clk: the clk whose parent gets returned
b2476490 1709 *
4dff95dc 1710 * Simply returns clk->parent. Returns NULL if clk is NULL.
b2476490 1711 */
4dff95dc 1712struct clk *clk_get_parent(struct clk *clk)
b2476490 1713{
4dff95dc 1714 struct clk *parent;
b2476490 1715
fc4a05d4
SB
1716 if (!clk)
1717 return NULL;
1718
4dff95dc 1719 clk_prepare_lock();
fc4a05d4
SB
1720 /* TODO: Create a per-user clk and change callers to call clk_put */
1721 parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
4dff95dc 1722 clk_prepare_unlock();
496eadf8 1723
4dff95dc
SB
1724 return parent;
1725}
1726EXPORT_SYMBOL_GPL(clk_get_parent);
b2476490 1727
4dff95dc
SB
1728static struct clk_core *__clk_init_parent(struct clk_core *core)
1729{
5146e0b0 1730 u8 index = 0;
4dff95dc 1731
2430a94d 1732 if (core->num_parents > 1 && core->ops->get_parent)
5146e0b0 1733 index = core->ops->get_parent(core->hw);
b2476490 1734
5146e0b0 1735 return clk_core_get_parent_by_index(core, index);
b2476490
MT
1736}
1737
4dff95dc
SB
1738static void clk_core_reparent(struct clk_core *core,
1739 struct clk_core *new_parent)
b2476490 1740{
4dff95dc
SB
1741 clk_reparent(core, new_parent);
1742 __clk_recalc_accuracies(core);
1743 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
1744}
1745
42c86547
TV
1746void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
1747{
1748 if (!hw)
1749 return;
1750
1751 clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
1752}
1753
4dff95dc
SB
1754/**
1755 * clk_has_parent - check if a clock is a possible parent for another
1756 * @clk: clock source
1757 * @parent: parent clock source
1758 *
1759 * This function can be used in drivers that need to check that a clock can be
1760 * the parent of another without actually changing the parent.
1761 *
1762 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 1763 */
4dff95dc 1764bool clk_has_parent(struct clk *clk, struct clk *parent)
b2476490 1765{
4dff95dc
SB
1766 struct clk_core *core, *parent_core;
1767 unsigned int i;
b2476490 1768
4dff95dc
SB
1769 /* NULL clocks should be nops, so return success if either is NULL. */
1770 if (!clk || !parent)
1771 return true;
7452b219 1772
4dff95dc
SB
1773 core = clk->core;
1774 parent_core = parent->core;
71472c0c 1775
4dff95dc
SB
1776 /* Optimize for the case where the parent is already the parent. */
1777 if (core->parent == parent_core)
1778 return true;
1c8e6004 1779
4dff95dc
SB
1780 for (i = 0; i < core->num_parents; i++)
1781 if (strcmp(core->parent_names[i], parent_core->name) == 0)
1782 return true;
03bc10ab 1783
4dff95dc
SB
1784 return false;
1785}
1786EXPORT_SYMBOL_GPL(clk_has_parent);
03bc10ab 1787
4dff95dc
SB
1788static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1789{
1790 int ret = 0;
1791 int p_index = 0;
1792 unsigned long p_rate = 0;
1793
1794 if (!core)
1795 return 0;
1796
1797 /* prevent racing with updates to the clock topology */
1798 clk_prepare_lock();
1799
1800 if (core->parent == parent)
1801 goto out;
1802
1803 /* verify ops for for multi-parent clks */
1804 if ((core->num_parents > 1) && (!core->ops->set_parent)) {
1805 ret = -ENOSYS;
63f5c3b2 1806 goto out;
7452b219
MT
1807 }
1808
4dff95dc
SB
1809 /* check that we are allowed to re-parent if the clock is in use */
1810 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1811 ret = -EBUSY;
1812 goto out;
b2476490
MT
1813 }
1814
71472c0c 1815 /* try finding the new parent index */
4dff95dc 1816 if (parent) {
d6968fca 1817 p_index = clk_fetch_parent_index(core, parent);
f1c8b2ed 1818 if (p_index < 0) {
71472c0c 1819 pr_debug("%s: clk %s can not be parent of clk %s\n",
4dff95dc
SB
1820 __func__, parent->name, core->name);
1821 ret = p_index;
1822 goto out;
71472c0c 1823 }
e8f0e68e 1824 p_rate = parent->rate;
b2476490
MT
1825 }
1826
4dff95dc
SB
1827 /* propagate PRE_RATE_CHANGE notifications */
1828 ret = __clk_speculate_rates(core, p_rate);
b2476490 1829
4dff95dc
SB
1830 /* abort if a driver objects */
1831 if (ret & NOTIFY_STOP_MASK)
1832 goto out;
b2476490 1833
4dff95dc
SB
1834 /* do the re-parent */
1835 ret = __clk_set_parent(core, parent, p_index);
b2476490 1836
4dff95dc
SB
1837 /* propagate rate an accuracy recalculation accordingly */
1838 if (ret) {
1839 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
1840 } else {
1841 __clk_recalc_rates(core, POST_RATE_CHANGE);
1842 __clk_recalc_accuracies(core);
b2476490
MT
1843 }
1844
4dff95dc
SB
1845out:
1846 clk_prepare_unlock();
71472c0c 1847
4dff95dc
SB
1848 return ret;
1849}
b2476490 1850
4dff95dc
SB
1851/**
1852 * clk_set_parent - switch the parent of a mux clk
1853 * @clk: the mux clk whose input we are switching
1854 * @parent: the new input to clk
1855 *
1856 * Re-parent clk to use parent as its new input source. If clk is in
1857 * prepared state, the clk will get enabled for the duration of this call. If
1858 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1859 * that, the reparenting is glitchy in hardware, etc), use the
1860 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1861 *
1862 * After successfully changing clk's parent clk_set_parent will update the
1863 * clk topology, sysfs topology and propagate rate recalculation via
1864 * __clk_recalc_rates.
1865 *
1866 * Returns 0 on success, -EERROR otherwise.
1867 */
1868int clk_set_parent(struct clk *clk, struct clk *parent)
1869{
1870 if (!clk)
1871 return 0;
1872
1873 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
b2476490 1874}
4dff95dc 1875EXPORT_SYMBOL_GPL(clk_set_parent);
b2476490 1876
4dff95dc
SB
1877/**
1878 * clk_set_phase - adjust the phase shift of a clock signal
1879 * @clk: clock signal source
1880 * @degrees: number of degrees the signal is shifted
1881 *
1882 * Shifts the phase of a clock signal by the specified
1883 * degrees. Returns 0 on success, -EERROR otherwise.
1884 *
1885 * This function makes no distinction about the input or reference
1886 * signal that we adjust the clock signal phase against. For example
1887 * phase locked-loop clock signal generators we may shift phase with
1888 * respect to feedback clock signal input, but for other cases the
1889 * clock phase may be shifted with respect to some other, unspecified
1890 * signal.
1891 *
1892 * Additionally the concept of phase shift does not propagate through
1893 * the clock tree hierarchy, which sets it apart from clock rates and
1894 * clock accuracy. A parent clock phase attribute does not have an
1895 * impact on the phase attribute of a child clock.
b2476490 1896 */
4dff95dc 1897int clk_set_phase(struct clk *clk, int degrees)
b2476490 1898{
4dff95dc 1899 int ret = -EINVAL;
b2476490 1900
4dff95dc
SB
1901 if (!clk)
1902 return 0;
b2476490 1903
4dff95dc
SB
1904 /* sanity check degrees */
1905 degrees %= 360;
1906 if (degrees < 0)
1907 degrees += 360;
bf47b4fd 1908
4dff95dc 1909 clk_prepare_lock();
3fa2252b 1910
4dff95dc 1911 trace_clk_set_phase(clk->core, degrees);
3fa2252b 1912
4dff95dc
SB
1913 if (clk->core->ops->set_phase)
1914 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
3fa2252b 1915
4dff95dc 1916 trace_clk_set_phase_complete(clk->core, degrees);
dfc202ea 1917
4dff95dc
SB
1918 if (!ret)
1919 clk->core->phase = degrees;
b2476490 1920
4dff95dc 1921 clk_prepare_unlock();
dfc202ea 1922
4dff95dc
SB
1923 return ret;
1924}
1925EXPORT_SYMBOL_GPL(clk_set_phase);
b2476490 1926
4dff95dc
SB
1927static int clk_core_get_phase(struct clk_core *core)
1928{
1929 int ret;
b2476490 1930
4dff95dc
SB
1931 clk_prepare_lock();
1932 ret = core->phase;
1933 clk_prepare_unlock();
71472c0c 1934
4dff95dc 1935 return ret;
b2476490
MT
1936}
1937
4dff95dc
SB
1938/**
1939 * clk_get_phase - return the phase shift of a clock signal
1940 * @clk: clock signal source
1941 *
1942 * Returns the phase shift of a clock node in degrees, otherwise returns
1943 * -EERROR.
1944 */
1945int clk_get_phase(struct clk *clk)
1c8e6004 1946{
4dff95dc 1947 if (!clk)
1c8e6004
TV
1948 return 0;
1949
4dff95dc
SB
1950 return clk_core_get_phase(clk->core);
1951}
1952EXPORT_SYMBOL_GPL(clk_get_phase);
1c8e6004 1953
4dff95dc
SB
1954/**
1955 * clk_is_match - check if two clk's point to the same hardware clock
1956 * @p: clk compared against q
1957 * @q: clk compared against p
1958 *
1959 * Returns true if the two struct clk pointers both point to the same hardware
1960 * clock node. Put differently, returns true if struct clk *p and struct clk *q
1961 * share the same struct clk_core object.
1962 *
1963 * Returns false otherwise. Note that two NULL clks are treated as matching.
1964 */
1965bool clk_is_match(const struct clk *p, const struct clk *q)
1966{
1967 /* trivial case: identical struct clk's or both NULL */
1968 if (p == q)
1969 return true;
1c8e6004 1970
3fe003f9 1971 /* true if clk->core pointers match. Avoid dereferencing garbage */
4dff95dc
SB
1972 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
1973 if (p->core == q->core)
1974 return true;
1c8e6004 1975
4dff95dc
SB
1976 return false;
1977}
1978EXPORT_SYMBOL_GPL(clk_is_match);
1c8e6004 1979
4dff95dc 1980/*** debugfs support ***/
1c8e6004 1981
4dff95dc
SB
1982#ifdef CONFIG_DEBUG_FS
1983#include <linux/debugfs.h>
1c8e6004 1984
4dff95dc
SB
1985static struct dentry *rootdir;
1986static int inited = 0;
1987static DEFINE_MUTEX(clk_debug_lock);
1988static HLIST_HEAD(clk_debug_list);
1c8e6004 1989
4dff95dc
SB
1990static struct hlist_head *all_lists[] = {
1991 &clk_root_list,
1992 &clk_orphan_list,
1993 NULL,
1994};
1995
1996static struct hlist_head *orphan_list[] = {
1997 &clk_orphan_list,
1998 NULL,
1999};
2000
2001static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
2002 int level)
b2476490 2003{
4dff95dc
SB
2004 if (!c)
2005 return;
b2476490 2006
4dff95dc
SB
2007 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
2008 level * 3 + 1, "",
2009 30 - level * 3, c->name,
2010 c->enable_count, c->prepare_count, clk_core_get_rate(c),
2011 clk_core_get_accuracy(c), clk_core_get_phase(c));
2012}
89ac8d7a 2013
4dff95dc
SB
2014static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2015 int level)
2016{
2017 struct clk_core *child;
b2476490 2018
4dff95dc
SB
2019 if (!c)
2020 return;
b2476490 2021
4dff95dc 2022 clk_summary_show_one(s, c, level);
0e1c0301 2023
4dff95dc
SB
2024 hlist_for_each_entry(child, &c->children, child_node)
2025 clk_summary_show_subtree(s, child, level + 1);
1c8e6004 2026}
b2476490 2027
4dff95dc 2028static int clk_summary_show(struct seq_file *s, void *data)
1c8e6004 2029{
4dff95dc
SB
2030 struct clk_core *c;
2031 struct hlist_head **lists = (struct hlist_head **)s->private;
1c8e6004 2032
4dff95dc
SB
2033 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
2034 seq_puts(s, "----------------------------------------------------------------------------------------\n");
b2476490 2035
1c8e6004
TV
2036 clk_prepare_lock();
2037
4dff95dc
SB
2038 for (; *lists; lists++)
2039 hlist_for_each_entry(c, *lists, child_node)
2040 clk_summary_show_subtree(s, c, 0);
b2476490 2041
eab89f69 2042 clk_prepare_unlock();
b2476490 2043
4dff95dc 2044 return 0;
b2476490 2045}
1c8e6004 2046
1c8e6004 2047
4dff95dc 2048static int clk_summary_open(struct inode *inode, struct file *file)
1c8e6004 2049{
4dff95dc 2050 return single_open(file, clk_summary_show, inode->i_private);
1c8e6004 2051}
b2476490 2052
4dff95dc
SB
2053static const struct file_operations clk_summary_fops = {
2054 .open = clk_summary_open,
2055 .read = seq_read,
2056 .llseek = seq_lseek,
2057 .release = single_release,
2058};
b2476490 2059
4dff95dc
SB
2060static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2061{
2062 if (!c)
2063 return;
b2476490 2064
7cb81136 2065 /* This should be JSON format, i.e. elements separated with a comma */
4dff95dc
SB
2066 seq_printf(s, "\"%s\": { ", c->name);
2067 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
2068 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
7cb81136
SW
2069 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2070 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
4dff95dc 2071 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
b2476490 2072}
b2476490 2073
4dff95dc 2074static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
b2476490 2075{
4dff95dc 2076 struct clk_core *child;
b2476490 2077
4dff95dc
SB
2078 if (!c)
2079 return;
b2476490 2080
4dff95dc 2081 clk_dump_one(s, c, level);
b2476490 2082
4dff95dc
SB
2083 hlist_for_each_entry(child, &c->children, child_node) {
2084 seq_printf(s, ",");
2085 clk_dump_subtree(s, child, level + 1);
b2476490
MT
2086 }
2087
4dff95dc 2088 seq_printf(s, "}");
b2476490
MT
2089}
2090
4dff95dc 2091static int clk_dump(struct seq_file *s, void *data)
4e88f3de 2092{
4dff95dc
SB
2093 struct clk_core *c;
2094 bool first_node = true;
2095 struct hlist_head **lists = (struct hlist_head **)s->private;
4e88f3de 2096
4dff95dc 2097 seq_printf(s, "{");
4e88f3de 2098
4dff95dc 2099 clk_prepare_lock();
035a61c3 2100
4dff95dc
SB
2101 for (; *lists; lists++) {
2102 hlist_for_each_entry(c, *lists, child_node) {
2103 if (!first_node)
2104 seq_puts(s, ",");
2105 first_node = false;
2106 clk_dump_subtree(s, c, 0);
2107 }
2108 }
4e88f3de 2109
4dff95dc 2110 clk_prepare_unlock();
4e88f3de 2111
70e9f4dd 2112 seq_puts(s, "}\n");
4dff95dc 2113 return 0;
4e88f3de 2114}
4e88f3de 2115
4dff95dc
SB
2116
2117static int clk_dump_open(struct inode *inode, struct file *file)
b2476490 2118{
4dff95dc
SB
2119 return single_open(file, clk_dump, inode->i_private);
2120}
b2476490 2121
4dff95dc
SB
2122static const struct file_operations clk_dump_fops = {
2123 .open = clk_dump_open,
2124 .read = seq_read,
2125 .llseek = seq_lseek,
2126 .release = single_release,
2127};
89ac8d7a 2128
4dff95dc
SB
2129static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2130{
2131 struct dentry *d;
2132 int ret = -ENOMEM;
b2476490 2133
4dff95dc
SB
2134 if (!core || !pdentry) {
2135 ret = -EINVAL;
b2476490 2136 goto out;
4dff95dc 2137 }
b2476490 2138
4dff95dc
SB
2139 d = debugfs_create_dir(core->name, pdentry);
2140 if (!d)
b61c43c0 2141 goto out;
b61c43c0 2142
4dff95dc
SB
2143 core->dentry = d;
2144
2145 d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
2146 (u32 *)&core->rate);
2147 if (!d)
2148 goto err_out;
2149
2150 d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
2151 (u32 *)&core->accuracy);
2152 if (!d)
2153 goto err_out;
2154
2155 d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
2156 (u32 *)&core->phase);
2157 if (!d)
2158 goto err_out;
031dcc9b 2159
4dff95dc
SB
2160 d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
2161 (u32 *)&core->flags);
2162 if (!d)
2163 goto err_out;
031dcc9b 2164
4dff95dc
SB
2165 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
2166 (u32 *)&core->prepare_count);
2167 if (!d)
2168 goto err_out;
b2476490 2169
4dff95dc
SB
2170 d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
2171 (u32 *)&core->enable_count);
2172 if (!d)
2173 goto err_out;
b2476490 2174
4dff95dc
SB
2175 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
2176 (u32 *)&core->notifier_count);
2177 if (!d)
2178 goto err_out;
b2476490 2179
4dff95dc
SB
2180 if (core->ops->debug_init) {
2181 ret = core->ops->debug_init(core->hw, core->dentry);
2182 if (ret)
2183 goto err_out;
5279fc40 2184 }
b2476490 2185
4dff95dc
SB
2186 ret = 0;
2187 goto out;
b2476490 2188
4dff95dc
SB
2189err_out:
2190 debugfs_remove_recursive(core->dentry);
2191 core->dentry = NULL;
2192out:
b2476490
MT
2193 return ret;
2194}
035a61c3
TV
2195
2196/**
6e5ab41b
SB
2197 * clk_debug_register - add a clk node to the debugfs clk directory
2198 * @core: the clk being added to the debugfs clk directory
035a61c3 2199 *
6e5ab41b
SB
2200 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2201 * initialized. Otherwise it bails out early since the debugfs clk directory
4dff95dc 2202 * will be created lazily by clk_debug_init as part of a late_initcall.
035a61c3 2203 */
4dff95dc 2204static int clk_debug_register(struct clk_core *core)
035a61c3 2205{
4dff95dc 2206 int ret = 0;
035a61c3 2207
4dff95dc
SB
2208 mutex_lock(&clk_debug_lock);
2209 hlist_add_head(&core->debug_node, &clk_debug_list);
2210
2211 if (!inited)
2212 goto unlock;
2213
2214 ret = clk_debug_create_one(core, rootdir);
2215unlock:
2216 mutex_unlock(&clk_debug_lock);
2217
2218 return ret;
035a61c3 2219}
b2476490 2220
4dff95dc 2221 /**
6e5ab41b
SB
2222 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2223 * @core: the clk being removed from the debugfs clk directory
e59c5371 2224 *
6e5ab41b
SB
2225 * Dynamically removes a clk and all its child nodes from the
2226 * debugfs clk directory if clk->dentry points to debugfs created by
706d5c73 2227 * clk_debug_register in __clk_core_init.
e59c5371 2228 */
4dff95dc 2229static void clk_debug_unregister(struct clk_core *core)
e59c5371 2230{
4dff95dc
SB
2231 mutex_lock(&clk_debug_lock);
2232 hlist_del_init(&core->debug_node);
2233 debugfs_remove_recursive(core->dentry);
2234 core->dentry = NULL;
2235 mutex_unlock(&clk_debug_lock);
2236}
e59c5371 2237
4dff95dc
SB
2238struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
2239 void *data, const struct file_operations *fops)
2240{
2241 struct dentry *d = NULL;
e59c5371 2242
4dff95dc
SB
2243 if (hw->core->dentry)
2244 d = debugfs_create_file(name, mode, hw->core->dentry, data,
2245 fops);
e59c5371 2246
4dff95dc
SB
2247 return d;
2248}
2249EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
e59c5371 2250
4dff95dc 2251/**
6e5ab41b 2252 * clk_debug_init - lazily populate the debugfs clk directory
4dff95dc 2253 *
6e5ab41b
SB
2254 * clks are often initialized very early during boot before memory can be
2255 * dynamically allocated and well before debugfs is setup. This function
2256 * populates the debugfs clk directory once at boot-time when we know that
2257 * debugfs is setup. It should only be called once at boot-time, all other clks
2258 * added dynamically will be done so with clk_debug_register.
4dff95dc
SB
2259 */
2260static int __init clk_debug_init(void)
2261{
2262 struct clk_core *core;
2263 struct dentry *d;
dfc202ea 2264
4dff95dc 2265 rootdir = debugfs_create_dir("clk", NULL);
e59c5371 2266
4dff95dc
SB
2267 if (!rootdir)
2268 return -ENOMEM;
dfc202ea 2269
4dff95dc
SB
2270 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
2271 &clk_summary_fops);
2272 if (!d)
2273 return -ENOMEM;
e59c5371 2274
4dff95dc
SB
2275 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
2276 &clk_dump_fops);
2277 if (!d)
2278 return -ENOMEM;
e59c5371 2279
4dff95dc
SB
2280 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
2281 &orphan_list, &clk_summary_fops);
2282 if (!d)
2283 return -ENOMEM;
e59c5371 2284
4dff95dc
SB
2285 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
2286 &orphan_list, &clk_dump_fops);
2287 if (!d)
2288 return -ENOMEM;
e59c5371 2289
4dff95dc
SB
2290 mutex_lock(&clk_debug_lock);
2291 hlist_for_each_entry(core, &clk_debug_list, debug_node)
2292 clk_debug_create_one(core, rootdir);
e59c5371 2293
4dff95dc
SB
2294 inited = 1;
2295 mutex_unlock(&clk_debug_lock);
e59c5371 2296
4dff95dc
SB
2297 return 0;
2298}
2299late_initcall(clk_debug_init);
2300#else
2301static inline int clk_debug_register(struct clk_core *core) { return 0; }
2302static inline void clk_debug_reparent(struct clk_core *core,
2303 struct clk_core *new_parent)
035a61c3 2304{
035a61c3 2305}
4dff95dc 2306static inline void clk_debug_unregister(struct clk_core *core)
3d3801ef 2307{
3d3801ef 2308}
4dff95dc 2309#endif
3d3801ef 2310
b2476490 2311/**
be45ebf2 2312 * __clk_core_init - initialize the data structures in a struct clk_core
d35c80c2 2313 * @core: clk_core being initialized
b2476490 2314 *
035a61c3 2315 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2316 * parent and rate and sets them both.
b2476490 2317 */
be45ebf2 2318static int __clk_core_init(struct clk_core *core)
b2476490 2319{
d1302a36 2320 int i, ret = 0;
035a61c3 2321 struct clk_core *orphan;
b67bfe0d 2322 struct hlist_node *tmp2;
1c8e6004 2323 unsigned long rate;
b2476490 2324
d35c80c2 2325 if (!core)
d1302a36 2326 return -EINVAL;
b2476490 2327
eab89f69 2328 clk_prepare_lock();
b2476490
MT
2329
2330 /* check to see if a clock with this name is already registered */
d6968fca 2331 if (clk_core_lookup(core->name)) {
d1302a36 2332 pr_debug("%s: clk %s already initialized\n",
d6968fca 2333 __func__, core->name);
d1302a36 2334 ret = -EEXIST;
b2476490 2335 goto out;
d1302a36 2336 }
b2476490 2337
d4d7e3dd 2338 /* check that clk_ops are sane. See Documentation/clk.txt */
d6968fca
SB
2339 if (core->ops->set_rate &&
2340 !((core->ops->round_rate || core->ops->determine_rate) &&
2341 core->ops->recalc_rate)) {
c44fccb5
MY
2342 pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
2343 __func__, core->name);
d1302a36 2344 ret = -EINVAL;
d4d7e3dd
MT
2345 goto out;
2346 }
2347
d6968fca 2348 if (core->ops->set_parent && !core->ops->get_parent) {
c44fccb5
MY
2349 pr_err("%s: %s must implement .get_parent & .set_parent\n",
2350 __func__, core->name);
d1302a36 2351 ret = -EINVAL;
d4d7e3dd
MT
2352 goto out;
2353 }
2354
3c8e77dd
MY
2355 if (core->num_parents > 1 && !core->ops->get_parent) {
2356 pr_err("%s: %s must implement .get_parent as it has multi parents\n",
2357 __func__, core->name);
2358 ret = -EINVAL;
2359 goto out;
2360 }
2361
d6968fca
SB
2362 if (core->ops->set_rate_and_parent &&
2363 !(core->ops->set_parent && core->ops->set_rate)) {
c44fccb5 2364 pr_err("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 2365 __func__, core->name);
3fa2252b
SB
2366 ret = -EINVAL;
2367 goto out;
2368 }
2369
b2476490 2370 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
2371 for (i = 0; i < core->num_parents; i++)
2372 WARN(!core->parent_names[i],
b2476490 2373 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 2374 __func__, core->name);
b2476490 2375
d6968fca 2376 core->parent = __clk_init_parent(core);
b2476490
MT
2377
2378 /*
706d5c73
SB
2379 * Populate core->parent if parent has already been clk_core_init'd. If
2380 * parent has not yet been clk_core_init'd then place clk in the orphan
47b0eeb3 2381 * list. If clk doesn't have any parents then place it in the root
b2476490
MT
2382 * clk list.
2383 *
2384 * Every time a new clk is clk_init'd then we walk the list of orphan
2385 * clocks and re-parent any that are children of the clock currently
2386 * being clk_init'd.
2387 */
e6500344 2388 if (core->parent) {
d6968fca
SB
2389 hlist_add_head(&core->child_node,
2390 &core->parent->children);
e6500344 2391 core->orphan = core->parent->orphan;
47b0eeb3 2392 } else if (!core->num_parents) {
d6968fca 2393 hlist_add_head(&core->child_node, &clk_root_list);
e6500344
HS
2394 core->orphan = false;
2395 } else {
d6968fca 2396 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
2397 core->orphan = true;
2398 }
b2476490 2399
5279fc40
BB
2400 /*
2401 * Set clk's accuracy. The preferred method is to use
2402 * .recalc_accuracy. For simple clocks and lazy developers the default
2403 * fallback is to use the parent's accuracy. If a clock doesn't have a
2404 * parent (or is orphaned) then accuracy is set to zero (perfect
2405 * clock).
2406 */
d6968fca
SB
2407 if (core->ops->recalc_accuracy)
2408 core->accuracy = core->ops->recalc_accuracy(core->hw,
2409 __clk_get_accuracy(core->parent));
2410 else if (core->parent)
2411 core->accuracy = core->parent->accuracy;
5279fc40 2412 else
d6968fca 2413 core->accuracy = 0;
5279fc40 2414
9824cf73
MR
2415 /*
2416 * Set clk's phase.
2417 * Since a phase is by definition relative to its parent, just
2418 * query the current clock phase, or just assume it's in phase.
2419 */
d6968fca
SB
2420 if (core->ops->get_phase)
2421 core->phase = core->ops->get_phase(core->hw);
9824cf73 2422 else
d6968fca 2423 core->phase = 0;
9824cf73 2424
b2476490
MT
2425 /*
2426 * Set clk's rate. The preferred method is to use .recalc_rate. For
2427 * simple clocks and lazy developers the default fallback is to use the
2428 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2429 * then rate is set to zero.
2430 */
d6968fca
SB
2431 if (core->ops->recalc_rate)
2432 rate = core->ops->recalc_rate(core->hw,
2433 clk_core_get_rate_nolock(core->parent));
2434 else if (core->parent)
2435 rate = core->parent->rate;
b2476490 2436 else
1c8e6004 2437 rate = 0;
d6968fca 2438 core->rate = core->req_rate = rate;
b2476490
MT
2439
2440 /*
0e8f6e49
MY
2441 * walk the list of orphan clocks and reparent any that newly finds a
2442 * parent.
b2476490 2443 */
b67bfe0d 2444 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
0e8f6e49 2445 struct clk_core *parent = __clk_init_parent(orphan);
1f61e5f1 2446
904e6ead
MT
2447 /*
2448 * we could call __clk_set_parent, but that would result in a
2449 * redundant call to the .set_rate op, if it exists
2450 */
2451 if (parent) {
2452 __clk_set_parent_before(orphan, parent);
2453 __clk_set_parent_after(orphan, parent, NULL);
2454 __clk_recalc_accuracies(orphan);
2455 __clk_recalc_rates(orphan, 0);
2456 }
0e8f6e49 2457 }
b2476490
MT
2458
2459 /*
2460 * optional platform-specific magic
2461 *
2462 * The .init callback is not used by any of the basic clock types, but
2463 * exists for weird hardware that must perform initialization magic.
2464 * Please consider other ways of solving initialization problems before
24ee1a08 2465 * using this callback, as its use is discouraged.
b2476490 2466 */
d6968fca
SB
2467 if (core->ops->init)
2468 core->ops->init(core->hw);
b2476490 2469
32b9b109 2470 if (core->flags & CLK_IS_CRITICAL) {
ef56b79b
MR
2471 unsigned long flags;
2472
32b9b109 2473 clk_core_prepare(core);
ef56b79b
MR
2474
2475 flags = clk_enable_lock();
32b9b109 2476 clk_core_enable(core);
ef56b79b 2477 clk_enable_unlock(flags);
32b9b109
LJ
2478 }
2479
d6968fca 2480 kref_init(&core->ref);
b2476490 2481out:
eab89f69 2482 clk_prepare_unlock();
b2476490 2483
89f7e9de 2484 if (!ret)
d6968fca 2485 clk_debug_register(core);
89f7e9de 2486
d1302a36 2487 return ret;
b2476490
MT
2488}
2489
035a61c3
TV
2490struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2491 const char *con_id)
0197b3ea 2492{
0197b3ea
SK
2493 struct clk *clk;
2494
035a61c3 2495 /* This is to allow this function to be chained to others */
c1de1357 2496 if (IS_ERR_OR_NULL(hw))
8a23133c 2497 return ERR_CAST(hw);
0197b3ea 2498
035a61c3
TV
2499 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2500 if (!clk)
2501 return ERR_PTR(-ENOMEM);
2502
2503 clk->core = hw->core;
2504 clk->dev_id = dev_id;
2505 clk->con_id = con_id;
1c8e6004
TV
2506 clk->max_rate = ULONG_MAX;
2507
2508 clk_prepare_lock();
50595f8b 2509 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2510 clk_prepare_unlock();
0197b3ea
SK
2511
2512 return clk;
2513}
035a61c3 2514
73e0e496 2515void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2516{
2517 clk_prepare_lock();
50595f8b 2518 hlist_del(&clk->clks_node);
1c8e6004
TV
2519 clk_prepare_unlock();
2520
2521 kfree(clk);
2522}
0197b3ea 2523
293ba3b4
SB
2524/**
2525 * clk_register - allocate a new clock, register it and return an opaque cookie
2526 * @dev: device that is registering this clock
2527 * @hw: link to hardware-specific clock data
2528 *
2529 * clk_register is the primary interface for populating the clock tree with new
2530 * clock nodes. It returns a pointer to the newly allocated struct clk which
a59a5163 2531 * cannot be dereferenced by driver code but may be used in conjunction with the
293ba3b4
SB
2532 * rest of the clock API. In the event of an error clk_register will return an
2533 * error code; drivers must test for an error code after calling clk_register.
2534 */
2535struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2536{
d1302a36 2537 int i, ret;
d6968fca 2538 struct clk_core *core;
293ba3b4 2539
d6968fca
SB
2540 core = kzalloc(sizeof(*core), GFP_KERNEL);
2541 if (!core) {
293ba3b4
SB
2542 ret = -ENOMEM;
2543 goto fail_out;
2544 }
b2476490 2545
d6968fca
SB
2546 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
2547 if (!core->name) {
0197b3ea
SK
2548 ret = -ENOMEM;
2549 goto fail_name;
2550 }
d6968fca 2551 core->ops = hw->init->ops;
ac2df527 2552 if (dev && dev->driver)
d6968fca
SB
2553 core->owner = dev->driver->owner;
2554 core->hw = hw;
2555 core->flags = hw->init->flags;
2556 core->num_parents = hw->init->num_parents;
9783c0d9
SB
2557 core->min_rate = 0;
2558 core->max_rate = ULONG_MAX;
d6968fca 2559 hw->core = core;
b2476490 2560
d1302a36 2561 /* allocate local copy in case parent_names is __initdata */
d6968fca 2562 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 2563 GFP_KERNEL);
d1302a36 2564
d6968fca 2565 if (!core->parent_names) {
d1302a36
MT
2566 ret = -ENOMEM;
2567 goto fail_parent_names;
2568 }
2569
2570
2571 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
2572 for (i = 0; i < core->num_parents; i++) {
2573 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2574 GFP_KERNEL);
d6968fca 2575 if (!core->parent_names[i]) {
d1302a36
MT
2576 ret = -ENOMEM;
2577 goto fail_parent_names_copy;
2578 }
2579 }
2580
176d1169
MY
2581 /* avoid unnecessary string look-ups of clk_core's possible parents. */
2582 core->parents = kcalloc(core->num_parents, sizeof(*core->parents),
2583 GFP_KERNEL);
2584 if (!core->parents) {
2585 ret = -ENOMEM;
2586 goto fail_parents;
2587 };
2588
d6968fca 2589 INIT_HLIST_HEAD(&core->clks);
1c8e6004 2590
035a61c3
TV
2591 hw->clk = __clk_create_clk(hw, NULL, NULL);
2592 if (IS_ERR(hw->clk)) {
035a61c3 2593 ret = PTR_ERR(hw->clk);
176d1169 2594 goto fail_parents;
035a61c3
TV
2595 }
2596
be45ebf2 2597 ret = __clk_core_init(core);
d1302a36 2598 if (!ret)
035a61c3 2599 return hw->clk;
b2476490 2600
1c8e6004 2601 __clk_free_clk(hw->clk);
035a61c3 2602 hw->clk = NULL;
b2476490 2603
176d1169
MY
2604fail_parents:
2605 kfree(core->parents);
d1302a36
MT
2606fail_parent_names_copy:
2607 while (--i >= 0)
d6968fca
SB
2608 kfree_const(core->parent_names[i]);
2609 kfree(core->parent_names);
d1302a36 2610fail_parent_names:
d6968fca 2611 kfree_const(core->name);
0197b3ea 2612fail_name:
d6968fca 2613 kfree(core);
d1302a36
MT
2614fail_out:
2615 return ERR_PTR(ret);
b2476490
MT
2616}
2617EXPORT_SYMBOL_GPL(clk_register);
2618
4143804c
SB
2619/**
2620 * clk_hw_register - register a clk_hw and return an error code
2621 * @dev: device that is registering this clock
2622 * @hw: link to hardware-specific clock data
2623 *
2624 * clk_hw_register is the primary interface for populating the clock tree with
2625 * new clock nodes. It returns an integer equal to zero indicating success or
2626 * less than zero indicating failure. Drivers must test for an error code after
2627 * calling clk_hw_register().
2628 */
2629int clk_hw_register(struct device *dev, struct clk_hw *hw)
2630{
2631 return PTR_ERR_OR_ZERO(clk_register(dev, hw));
2632}
2633EXPORT_SYMBOL_GPL(clk_hw_register);
2634
6e5ab41b 2635/* Free memory allocated for a clock. */
fcb0ee6a
SN
2636static void __clk_release(struct kref *ref)
2637{
d6968fca
SB
2638 struct clk_core *core = container_of(ref, struct clk_core, ref);
2639 int i = core->num_parents;
fcb0ee6a 2640
496eadf8
KK
2641 lockdep_assert_held(&prepare_lock);
2642
d6968fca 2643 kfree(core->parents);
fcb0ee6a 2644 while (--i >= 0)
d6968fca 2645 kfree_const(core->parent_names[i]);
fcb0ee6a 2646
d6968fca
SB
2647 kfree(core->parent_names);
2648 kfree_const(core->name);
2649 kfree(core);
fcb0ee6a
SN
2650}
2651
2652/*
2653 * Empty clk_ops for unregistered clocks. These are used temporarily
2654 * after clk_unregister() was called on a clock and until last clock
2655 * consumer calls clk_put() and the struct clk object is freed.
2656 */
2657static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2658{
2659 return -ENXIO;
2660}
2661
2662static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2663{
2664 WARN_ON_ONCE(1);
2665}
2666
2667static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2668 unsigned long parent_rate)
2669{
2670 return -ENXIO;
2671}
2672
2673static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2674{
2675 return -ENXIO;
2676}
2677
2678static const struct clk_ops clk_nodrv_ops = {
2679 .enable = clk_nodrv_prepare_enable,
2680 .disable = clk_nodrv_disable_unprepare,
2681 .prepare = clk_nodrv_prepare_enable,
2682 .unprepare = clk_nodrv_disable_unprepare,
2683 .set_rate = clk_nodrv_set_rate,
2684 .set_parent = clk_nodrv_set_parent,
2685};
2686
1df5c939
MB
2687/**
2688 * clk_unregister - unregister a currently registered clock
2689 * @clk: clock to unregister
1df5c939 2690 */
fcb0ee6a
SN
2691void clk_unregister(struct clk *clk)
2692{
2693 unsigned long flags;
2694
6314b679
SB
2695 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2696 return;
2697
035a61c3 2698 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2699
2700 clk_prepare_lock();
2701
035a61c3
TV
2702 if (clk->core->ops == &clk_nodrv_ops) {
2703 pr_err("%s: unregistered clock: %s\n", __func__,
2704 clk->core->name);
4106a3d9 2705 goto unlock;
fcb0ee6a
SN
2706 }
2707 /*
2708 * Assign empty clock ops for consumers that might still hold
2709 * a reference to this clock.
2710 */
2711 flags = clk_enable_lock();
035a61c3 2712 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2713 clk_enable_unlock(flags);
2714
035a61c3
TV
2715 if (!hlist_empty(&clk->core->children)) {
2716 struct clk_core *child;
874f224c 2717 struct hlist_node *t;
fcb0ee6a
SN
2718
2719 /* Reparent all children to the orphan list. */
035a61c3
TV
2720 hlist_for_each_entry_safe(child, t, &clk->core->children,
2721 child_node)
2722 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2723 }
2724
035a61c3 2725 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2726
035a61c3 2727 if (clk->core->prepare_count)
fcb0ee6a 2728 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2729 __func__, clk->core->name);
2730 kref_put(&clk->core->ref, __clk_release);
4106a3d9 2731unlock:
fcb0ee6a
SN
2732 clk_prepare_unlock();
2733}
1df5c939
MB
2734EXPORT_SYMBOL_GPL(clk_unregister);
2735
4143804c
SB
2736/**
2737 * clk_hw_unregister - unregister a currently registered clk_hw
2738 * @hw: hardware-specific clock data to unregister
2739 */
2740void clk_hw_unregister(struct clk_hw *hw)
2741{
2742 clk_unregister(hw->clk);
2743}
2744EXPORT_SYMBOL_GPL(clk_hw_unregister);
2745
46c8773a
SB
2746static void devm_clk_release(struct device *dev, void *res)
2747{
293ba3b4 2748 clk_unregister(*(struct clk **)res);
46c8773a
SB
2749}
2750
4143804c
SB
2751static void devm_clk_hw_release(struct device *dev, void *res)
2752{
2753 clk_hw_unregister(*(struct clk_hw **)res);
2754}
2755
46c8773a
SB
2756/**
2757 * devm_clk_register - resource managed clk_register()
2758 * @dev: device that is registering this clock
2759 * @hw: link to hardware-specific clock data
2760 *
2761 * Managed clk_register(). Clocks returned from this function are
2762 * automatically clk_unregister()ed on driver detach. See clk_register() for
2763 * more information.
2764 */
2765struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2766{
2767 struct clk *clk;
293ba3b4 2768 struct clk **clkp;
46c8773a 2769
293ba3b4
SB
2770 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2771 if (!clkp)
46c8773a
SB
2772 return ERR_PTR(-ENOMEM);
2773
293ba3b4
SB
2774 clk = clk_register(dev, hw);
2775 if (!IS_ERR(clk)) {
2776 *clkp = clk;
2777 devres_add(dev, clkp);
46c8773a 2778 } else {
293ba3b4 2779 devres_free(clkp);
46c8773a
SB
2780 }
2781
2782 return clk;
2783}
2784EXPORT_SYMBOL_GPL(devm_clk_register);
2785
4143804c
SB
2786/**
2787 * devm_clk_hw_register - resource managed clk_hw_register()
2788 * @dev: device that is registering this clock
2789 * @hw: link to hardware-specific clock data
2790 *
c47265ad 2791 * Managed clk_hw_register(). Clocks registered by this function are
4143804c
SB
2792 * automatically clk_hw_unregister()ed on driver detach. See clk_hw_register()
2793 * for more information.
2794 */
2795int devm_clk_hw_register(struct device *dev, struct clk_hw *hw)
2796{
2797 struct clk_hw **hwp;
2798 int ret;
2799
2800 hwp = devres_alloc(devm_clk_hw_release, sizeof(*hwp), GFP_KERNEL);
2801 if (!hwp)
2802 return -ENOMEM;
2803
2804 ret = clk_hw_register(dev, hw);
2805 if (!ret) {
2806 *hwp = hw;
2807 devres_add(dev, hwp);
2808 } else {
2809 devres_free(hwp);
2810 }
2811
2812 return ret;
2813}
2814EXPORT_SYMBOL_GPL(devm_clk_hw_register);
2815
46c8773a
SB
2816static int devm_clk_match(struct device *dev, void *res, void *data)
2817{
2818 struct clk *c = res;
2819 if (WARN_ON(!c))
2820 return 0;
2821 return c == data;
2822}
2823
4143804c
SB
2824static int devm_clk_hw_match(struct device *dev, void *res, void *data)
2825{
2826 struct clk_hw *hw = res;
2827
2828 if (WARN_ON(!hw))
2829 return 0;
2830 return hw == data;
2831}
2832
46c8773a
SB
2833/**
2834 * devm_clk_unregister - resource managed clk_unregister()
2835 * @clk: clock to unregister
2836 *
2837 * Deallocate a clock allocated with devm_clk_register(). Normally
2838 * this function will not need to be called and the resource management
2839 * code will ensure that the resource is freed.
2840 */
2841void devm_clk_unregister(struct device *dev, struct clk *clk)
2842{
2843 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2844}
2845EXPORT_SYMBOL_GPL(devm_clk_unregister);
2846
4143804c
SB
2847/**
2848 * devm_clk_hw_unregister - resource managed clk_hw_unregister()
2849 * @dev: device that is unregistering the hardware-specific clock data
2850 * @hw: link to hardware-specific clock data
2851 *
2852 * Unregister a clk_hw registered with devm_clk_hw_register(). Normally
2853 * this function will not need to be called and the resource management
2854 * code will ensure that the resource is freed.
2855 */
2856void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
2857{
2858 WARN_ON(devres_release(dev, devm_clk_hw_release, devm_clk_hw_match,
2859 hw));
2860}
2861EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
2862
ac2df527
SN
2863/*
2864 * clkdev helpers
2865 */
2866int __clk_get(struct clk *clk)
2867{
035a61c3
TV
2868 struct clk_core *core = !clk ? NULL : clk->core;
2869
2870 if (core) {
2871 if (!try_module_get(core->owner))
00efcb1c 2872 return 0;
ac2df527 2873
035a61c3 2874 kref_get(&core->ref);
00efcb1c 2875 }
ac2df527
SN
2876 return 1;
2877}
2878
2879void __clk_put(struct clk *clk)
2880{
10cdfe54
TV
2881 struct module *owner;
2882
00efcb1c 2883 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2884 return;
2885
fcb0ee6a 2886 clk_prepare_lock();
1c8e6004 2887
50595f8b 2888 hlist_del(&clk->clks_node);
ec02ace8
TV
2889 if (clk->min_rate > clk->core->req_rate ||
2890 clk->max_rate < clk->core->req_rate)
2891 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2892
1c8e6004
TV
2893 owner = clk->core->owner;
2894 kref_put(&clk->core->ref, __clk_release);
2895
fcb0ee6a
SN
2896 clk_prepare_unlock();
2897
10cdfe54 2898 module_put(owner);
035a61c3 2899
035a61c3 2900 kfree(clk);
ac2df527
SN
2901}
2902
b2476490
MT
2903/*** clk rate change notifiers ***/
2904
2905/**
2906 * clk_notifier_register - add a clk rate change notifier
2907 * @clk: struct clk * to watch
2908 * @nb: struct notifier_block * with callback info
2909 *
2910 * Request notification when clk's rate changes. This uses an SRCU
2911 * notifier because we want it to block and notifier unregistrations are
2912 * uncommon. The callbacks associated with the notifier must not
2913 * re-enter into the clk framework by calling any top-level clk APIs;
2914 * this will cause a nested prepare_lock mutex.
2915 *
198bb594
MY
2916 * In all notification cases (pre, post and abort rate change) the original
2917 * clock rate is passed to the callback via struct clk_notifier_data.old_rate
2918 * and the new frequency is passed via struct clk_notifier_data.new_rate.
b2476490 2919 *
b2476490
MT
2920 * clk_notifier_register() must be called from non-atomic context.
2921 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2922 * allocation failure; otherwise, passes along the return value of
2923 * srcu_notifier_chain_register().
2924 */
2925int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2926{
2927 struct clk_notifier *cn;
2928 int ret = -ENOMEM;
2929
2930 if (!clk || !nb)
2931 return -EINVAL;
2932
eab89f69 2933 clk_prepare_lock();
b2476490
MT
2934
2935 /* search the list of notifiers for this clk */
2936 list_for_each_entry(cn, &clk_notifier_list, node)
2937 if (cn->clk == clk)
2938 break;
2939
2940 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2941 if (cn->clk != clk) {
2942 cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2943 if (!cn)
2944 goto out;
2945
2946 cn->clk = clk;
2947 srcu_init_notifier_head(&cn->notifier_head);
2948
2949 list_add(&cn->node, &clk_notifier_list);
2950 }
2951
2952 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2953
035a61c3 2954 clk->core->notifier_count++;
b2476490
MT
2955
2956out:
eab89f69 2957 clk_prepare_unlock();
b2476490
MT
2958
2959 return ret;
2960}
2961EXPORT_SYMBOL_GPL(clk_notifier_register);
2962
2963/**
2964 * clk_notifier_unregister - remove a clk rate change notifier
2965 * @clk: struct clk *
2966 * @nb: struct notifier_block * with callback info
2967 *
2968 * Request no further notification for changes to 'clk' and frees memory
2969 * allocated in clk_notifier_register.
2970 *
2971 * Returns -EINVAL if called with null arguments; otherwise, passes
2972 * along the return value of srcu_notifier_chain_unregister().
2973 */
2974int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2975{
2976 struct clk_notifier *cn = NULL;
2977 int ret = -EINVAL;
2978
2979 if (!clk || !nb)
2980 return -EINVAL;
2981
eab89f69 2982 clk_prepare_lock();
b2476490
MT
2983
2984 list_for_each_entry(cn, &clk_notifier_list, node)
2985 if (cn->clk == clk)
2986 break;
2987
2988 if (cn->clk == clk) {
2989 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2990
035a61c3 2991 clk->core->notifier_count--;
b2476490
MT
2992
2993 /* XXX the notifier code should handle this better */
2994 if (!cn->notifier_head.head) {
2995 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 2996 list_del(&cn->node);
b2476490
MT
2997 kfree(cn);
2998 }
2999
3000 } else {
3001 ret = -ENOENT;
3002 }
3003
eab89f69 3004 clk_prepare_unlock();
b2476490
MT
3005
3006 return ret;
3007}
3008EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
3009
3010#ifdef CONFIG_OF
3011/**
3012 * struct of_clk_provider - Clock provider registration structure
3013 * @link: Entry in global list of clock providers
3014 * @node: Pointer to device tree node of clock provider
3015 * @get: Get clock callback. Returns NULL or a struct clk for the
3016 * given clock specifier
3017 * @data: context pointer to be passed into @get callback
3018 */
3019struct of_clk_provider {
3020 struct list_head link;
3021
3022 struct device_node *node;
3023 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
0861e5b8 3024 struct clk_hw *(*get_hw)(struct of_phandle_args *clkspec, void *data);
766e6a4e
GL
3025 void *data;
3026};
3027
f2f6c255
PG
3028static const struct of_device_id __clk_of_table_sentinel
3029 __used __section(__clk_of_table_end);
3030
766e6a4e 3031static LIST_HEAD(of_clk_providers);
d6782c26
SN
3032static DEFINE_MUTEX(of_clk_mutex);
3033
766e6a4e
GL
3034struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
3035 void *data)
3036{
3037 return data;
3038}
3039EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
3040
0861e5b8
SB
3041struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
3042{
3043 return data;
3044}
3045EXPORT_SYMBOL_GPL(of_clk_hw_simple_get);
3046
494bfec9
SG
3047struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
3048{
3049 struct clk_onecell_data *clk_data = data;
3050 unsigned int idx = clkspec->args[0];
3051
3052 if (idx >= clk_data->clk_num) {
7e96353c 3053 pr_err("%s: invalid clock index %u\n", __func__, idx);
494bfec9
SG
3054 return ERR_PTR(-EINVAL);
3055 }
3056
3057 return clk_data->clks[idx];
3058}
3059EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
3060
0861e5b8
SB
3061struct clk_hw *
3062of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
3063{
3064 struct clk_hw_onecell_data *hw_data = data;
3065 unsigned int idx = clkspec->args[0];
3066
3067 if (idx >= hw_data->num) {
3068 pr_err("%s: invalid index %u\n", __func__, idx);
3069 return ERR_PTR(-EINVAL);
3070 }
3071
3072 return hw_data->hws[idx];
3073}
3074EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get);
3075
766e6a4e
GL
3076/**
3077 * of_clk_add_provider() - Register a clock provider for a node
3078 * @np: Device node pointer associated with clock provider
3079 * @clk_src_get: callback for decoding clock
3080 * @data: context pointer for @clk_src_get callback.
3081 */
3082int of_clk_add_provider(struct device_node *np,
3083 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
3084 void *data),
3085 void *data)
3086{
3087 struct of_clk_provider *cp;
86be408b 3088 int ret;
766e6a4e
GL
3089
3090 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
3091 if (!cp)
3092 return -ENOMEM;
3093
3094 cp->node = of_node_get(np);
3095 cp->data = data;
3096 cp->get = clk_src_get;
3097
d6782c26 3098 mutex_lock(&of_clk_mutex);
766e6a4e 3099 list_add(&cp->link, &of_clk_providers);
d6782c26 3100 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3101 pr_debug("Added clock from %s\n", np->full_name);
3102
86be408b
SN
3103 ret = of_clk_set_defaults(np, true);
3104 if (ret < 0)
3105 of_clk_del_provider(np);
3106
3107 return ret;
766e6a4e
GL
3108}
3109EXPORT_SYMBOL_GPL(of_clk_add_provider);
3110
0861e5b8
SB
3111/**
3112 * of_clk_add_hw_provider() - Register a clock provider for a node
3113 * @np: Device node pointer associated with clock provider
3114 * @get: callback for decoding clk_hw
3115 * @data: context pointer for @get callback.
3116 */
3117int of_clk_add_hw_provider(struct device_node *np,
3118 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3119 void *data),
3120 void *data)
3121{
3122 struct of_clk_provider *cp;
3123 int ret;
3124
3125 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
3126 if (!cp)
3127 return -ENOMEM;
3128
3129 cp->node = of_node_get(np);
3130 cp->data = data;
3131 cp->get_hw = get;
3132
3133 mutex_lock(&of_clk_mutex);
3134 list_add(&cp->link, &of_clk_providers);
3135 mutex_unlock(&of_clk_mutex);
3136 pr_debug("Added clk_hw provider from %s\n", np->full_name);
3137
3138 ret = of_clk_set_defaults(np, true);
3139 if (ret < 0)
3140 of_clk_del_provider(np);
3141
3142 return ret;
3143}
3144EXPORT_SYMBOL_GPL(of_clk_add_hw_provider);
3145
766e6a4e
GL
3146/**
3147 * of_clk_del_provider() - Remove a previously registered clock provider
3148 * @np: Device node pointer associated with clock provider
3149 */
3150void of_clk_del_provider(struct device_node *np)
3151{
3152 struct of_clk_provider *cp;
3153
d6782c26 3154 mutex_lock(&of_clk_mutex);
766e6a4e
GL
3155 list_for_each_entry(cp, &of_clk_providers, link) {
3156 if (cp->node == np) {
3157 list_del(&cp->link);
3158 of_node_put(cp->node);
3159 kfree(cp);
3160 break;
3161 }
3162 }
d6782c26 3163 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3164}
3165EXPORT_SYMBOL_GPL(of_clk_del_provider);
3166
0861e5b8
SB
3167static struct clk_hw *
3168__of_clk_get_hw_from_provider(struct of_clk_provider *provider,
3169 struct of_phandle_args *clkspec)
3170{
3171 struct clk *clk;
0861e5b8 3172
74002fcd
SB
3173 if (provider->get_hw)
3174 return provider->get_hw(clkspec, provider->data);
0861e5b8 3175
74002fcd
SB
3176 clk = provider->get(clkspec, provider->data);
3177 if (IS_ERR(clk))
3178 return ERR_CAST(clk);
3179 return __clk_get_hw(clk);
0861e5b8
SB
3180}
3181
73e0e496
SB
3182struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
3183 const char *dev_id, const char *con_id)
766e6a4e
GL
3184{
3185 struct of_clk_provider *provider;
a34cd466 3186 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
f155d15b 3187 struct clk_hw *hw;
766e6a4e 3188
306c342f
SB
3189 if (!clkspec)
3190 return ERR_PTR(-EINVAL);
3191
766e6a4e 3192 /* Check if we have such a provider in our array */
306c342f 3193 mutex_lock(&of_clk_mutex);
766e6a4e 3194 list_for_each_entry(provider, &of_clk_providers, link) {
f155d15b 3195 if (provider->node == clkspec->np) {
0861e5b8 3196 hw = __of_clk_get_hw_from_provider(provider, clkspec);
0861e5b8 3197 clk = __clk_create_clk(hw, dev_id, con_id);
f155d15b 3198 }
73e0e496 3199
f155d15b
SB
3200 if (!IS_ERR(clk)) {
3201 if (!__clk_get(clk)) {
73e0e496
SB
3202 __clk_free_clk(clk);
3203 clk = ERR_PTR(-ENOENT);
3204 }
3205
766e6a4e 3206 break;
73e0e496 3207 }
766e6a4e 3208 }
306c342f 3209 mutex_unlock(&of_clk_mutex);
d6782c26
SN
3210
3211 return clk;
3212}
3213
306c342f
SB
3214/**
3215 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3216 * @clkspec: pointer to a clock specifier data structure
3217 *
3218 * This function looks up a struct clk from the registered list of clock
3219 * providers, an input is a clock specifier data structure as returned
3220 * from the of_parse_phandle_with_args() function call.
3221 */
d6782c26
SN
3222struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
3223{
306c342f 3224 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e 3225}
fb4dd222 3226EXPORT_SYMBOL_GPL(of_clk_get_from_provider);
766e6a4e 3227
929e7f3b
SB
3228/**
3229 * of_clk_get_parent_count() - Count the number of clocks a device node has
3230 * @np: device node to count
3231 *
3232 * Returns: The number of clocks that are possible parents of this node
3233 */
3234unsigned int of_clk_get_parent_count(struct device_node *np)
f6102742 3235{
929e7f3b
SB
3236 int count;
3237
3238 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
3239 if (count < 0)
3240 return 0;
3241
3242 return count;
f6102742
MT
3243}
3244EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
3245
766e6a4e
GL
3246const char *of_clk_get_parent_name(struct device_node *np, int index)
3247{
3248 struct of_phandle_args clkspec;
7a0fc1a3 3249 struct property *prop;
766e6a4e 3250 const char *clk_name;
7a0fc1a3
BD
3251 const __be32 *vp;
3252 u32 pv;
766e6a4e 3253 int rc;
7a0fc1a3 3254 int count;
0a4807c2 3255 struct clk *clk;
766e6a4e 3256
766e6a4e
GL
3257 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3258 &clkspec);
3259 if (rc)
3260 return NULL;
3261
7a0fc1a3
BD
3262 index = clkspec.args_count ? clkspec.args[0] : 0;
3263 count = 0;
3264
3265 /* if there is an indices property, use it to transfer the index
3266 * specified into an array offset for the clock-output-names property.
3267 */
3268 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3269 if (index == pv) {
3270 index = count;
3271 break;
3272 }
3273 count++;
3274 }
8da411cc
MY
3275 /* We went off the end of 'clock-indices' without finding it */
3276 if (prop && !vp)
3277 return NULL;
7a0fc1a3 3278
766e6a4e 3279 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3280 index,
0a4807c2
SB
3281 &clk_name) < 0) {
3282 /*
3283 * Best effort to get the name if the clock has been
3284 * registered with the framework. If the clock isn't
3285 * registered, we return the node name as the name of
3286 * the clock as long as #clock-cells = 0.
3287 */
3288 clk = of_clk_get_from_provider(&clkspec);
3289 if (IS_ERR(clk)) {
3290 if (clkspec.args_count == 0)
3291 clk_name = clkspec.np->name;
3292 else
3293 clk_name = NULL;
3294 } else {
3295 clk_name = __clk_get_name(clk);
3296 clk_put(clk);
3297 }
3298 }
3299
766e6a4e
GL
3300
3301 of_node_put(clkspec.np);
3302 return clk_name;
3303}
3304EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3305
2e61dfb3
DN
3306/**
3307 * of_clk_parent_fill() - Fill @parents with names of @np's parents and return
3308 * number of parents
3309 * @np: Device node pointer associated with clock provider
3310 * @parents: pointer to char array that hold the parents' names
3311 * @size: size of the @parents array
3312 *
3313 * Return: number of parents for the clock node.
3314 */
3315int of_clk_parent_fill(struct device_node *np, const char **parents,
3316 unsigned int size)
3317{
3318 unsigned int i = 0;
3319
3320 while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
3321 i++;
3322
3323 return i;
3324}
3325EXPORT_SYMBOL_GPL(of_clk_parent_fill);
3326
1771b10d
GC
3327struct clock_provider {
3328 of_clk_init_cb_t clk_init_cb;
3329 struct device_node *np;
3330 struct list_head node;
3331};
3332
1771b10d
GC
3333/*
3334 * This function looks for a parent clock. If there is one, then it
3335 * checks that the provider for this parent clock was initialized, in
3336 * this case the parent clock will be ready.
3337 */
3338static int parent_ready(struct device_node *np)
3339{
3340 int i = 0;
3341
3342 while (true) {
3343 struct clk *clk = of_clk_get(np, i);
3344
3345 /* this parent is ready we can check the next one */
3346 if (!IS_ERR(clk)) {
3347 clk_put(clk);
3348 i++;
3349 continue;
3350 }
3351
3352 /* at least one parent is not ready, we exit now */
3353 if (PTR_ERR(clk) == -EPROBE_DEFER)
3354 return 0;
3355
3356 /*
3357 * Here we make assumption that the device tree is
3358 * written correctly. So an error means that there is
3359 * no more parent. As we didn't exit yet, then the
3360 * previous parent are ready. If there is no clock
3361 * parent, no need to wait for them, then we can
3362 * consider their absence as being ready
3363 */
3364 return 1;
3365 }
3366}
3367
d56f8994
LJ
3368/**
3369 * of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree
3370 * @np: Device node pointer associated with clock provider
3371 * @index: clock index
3372 * @flags: pointer to clk_core->flags
3373 *
3374 * Detects if the clock-critical property exists and, if so, sets the
3375 * corresponding CLK_IS_CRITICAL flag.
3376 *
3377 * Do not use this function. It exists only for legacy Device Tree
3378 * bindings, such as the one-clock-per-node style that are outdated.
3379 * Those bindings typically put all clock data into .dts and the Linux
3380 * driver has no clock data, thus making it impossible to set this flag
3381 * correctly from the driver. Only those drivers may call
3382 * of_clk_detect_critical from their setup functions.
3383 *
3384 * Return: error code or zero on success
3385 */
3386int of_clk_detect_critical(struct device_node *np,
3387 int index, unsigned long *flags)
3388{
3389 struct property *prop;
3390 const __be32 *cur;
3391 uint32_t idx;
3392
3393 if (!np || !flags)
3394 return -EINVAL;
3395
3396 of_property_for_each_u32(np, "clock-critical", prop, cur, idx)
3397 if (index == idx)
3398 *flags |= CLK_IS_CRITICAL;
3399
3400 return 0;
3401}
3402
766e6a4e
GL
3403/**
3404 * of_clk_init() - Scan and init clock providers from the DT
3405 * @matches: array of compatible values and init functions for providers.
3406 *
1771b10d 3407 * This function scans the device tree for matching clock providers
e5ca8fb4 3408 * and calls their initialization functions. It also does it by trying
1771b10d 3409 * to follow the dependencies.
766e6a4e
GL
3410 */
3411void __init of_clk_init(const struct of_device_id *matches)
3412{
7f7ed584 3413 const struct of_device_id *match;
766e6a4e 3414 struct device_node *np;
1771b10d
GC
3415 struct clock_provider *clk_provider, *next;
3416 bool is_init_done;
3417 bool force = false;
2573a02a 3418 LIST_HEAD(clk_provider_list);
766e6a4e 3419
f2f6c255 3420 if (!matches)
819b4861 3421 matches = &__clk_of_table;
f2f6c255 3422
1771b10d 3423 /* First prepare the list of the clocks providers */
7f7ed584 3424 for_each_matching_node_and_match(np, matches, &match) {
2e3b19f1
SB
3425 struct clock_provider *parent;
3426
3e5dd6f6
GU
3427 if (!of_device_is_available(np))
3428 continue;
3429
2e3b19f1
SB
3430 parent = kzalloc(sizeof(*parent), GFP_KERNEL);
3431 if (!parent) {
3432 list_for_each_entry_safe(clk_provider, next,
3433 &clk_provider_list, node) {
3434 list_del(&clk_provider->node);
6bc9d9d6 3435 of_node_put(clk_provider->np);
2e3b19f1
SB
3436 kfree(clk_provider);
3437 }
6bc9d9d6 3438 of_node_put(np);
2e3b19f1
SB
3439 return;
3440 }
1771b10d
GC
3441
3442 parent->clk_init_cb = match->data;
6bc9d9d6 3443 parent->np = of_node_get(np);
3f6d439f 3444 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3445 }
3446
3447 while (!list_empty(&clk_provider_list)) {
3448 is_init_done = false;
3449 list_for_each_entry_safe(clk_provider, next,
3450 &clk_provider_list, node) {
3451 if (force || parent_ready(clk_provider->np)) {
86be408b 3452
989eafd0
RRD
3453 /* Don't populate platform devices */
3454 of_node_set_flag(clk_provider->np,
3455 OF_POPULATED);
3456
1771b10d 3457 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3458 of_clk_set_defaults(clk_provider->np, true);
3459
1771b10d 3460 list_del(&clk_provider->node);
6bc9d9d6 3461 of_node_put(clk_provider->np);
1771b10d
GC
3462 kfree(clk_provider);
3463 is_init_done = true;
3464 }
3465 }
3466
3467 /*
e5ca8fb4 3468 * We didn't manage to initialize any of the
1771b10d
GC
3469 * remaining providers during the last loop, so now we
3470 * initialize all the remaining ones unconditionally
3471 * in case the clock parent was not mandatory
3472 */
3473 if (!is_init_done)
3474 force = true;
766e6a4e
GL
3475 }
3476}
3477#endif
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