clk: s/clk/core/ for struct clk_core
[deliverable/linux.git] / drivers / clk / clk.c
CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
b09d6d99 12#include <linux/clk-provider.h>
86be408b 13#include <linux/clk/clk-conf.h>
b2476490
MT
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/spinlock.h>
17#include <linux/err.h>
18#include <linux/list.h>
19#include <linux/slab.h>
766e6a4e 20#include <linux/of.h>
46c8773a 21#include <linux/device.h>
f2f6c255 22#include <linux/init.h>
533ddeb1 23#include <linux/sched.h>
b2476490 24
d6782c26
SN
25#include "clk.h"
26
b2476490
MT
27static DEFINE_SPINLOCK(enable_lock);
28static DEFINE_MUTEX(prepare_lock);
29
533ddeb1
MT
30static struct task_struct *prepare_owner;
31static struct task_struct *enable_owner;
32
33static int prepare_refcnt;
34static int enable_refcnt;
35
b2476490
MT
36static HLIST_HEAD(clk_root_list);
37static HLIST_HEAD(clk_orphan_list);
38static LIST_HEAD(clk_notifier_list);
39
d6968fca
SB
40static long clk_core_get_accuracy(struct clk_core *core);
41static unsigned long clk_core_get_rate(struct clk_core *core);
42static int clk_core_get_phase(struct clk_core *core);
43static bool clk_core_is_prepared(struct clk_core *core);
44static bool clk_core_is_enabled(struct clk_core *core);
035a61c3
TV
45static struct clk_core *clk_core_lookup(const char *name);
46
b09d6d99
MT
47/*** private data structures ***/
48
49struct clk_core {
50 const char *name;
51 const struct clk_ops *ops;
52 struct clk_hw *hw;
53 struct module *owner;
54 struct clk_core *parent;
55 const char **parent_names;
56 struct clk_core **parents;
57 u8 num_parents;
58 u8 new_parent_index;
59 unsigned long rate;
1c8e6004 60 unsigned long req_rate;
b09d6d99
MT
61 unsigned long new_rate;
62 struct clk_core *new_parent;
63 struct clk_core *new_child;
64 unsigned long flags;
65 unsigned int enable_count;
66 unsigned int prepare_count;
67 unsigned long accuracy;
68 int phase;
69 struct hlist_head children;
70 struct hlist_node child_node;
71 struct hlist_node debug_node;
1c8e6004 72 struct hlist_head clks;
b09d6d99
MT
73 unsigned int notifier_count;
74#ifdef CONFIG_DEBUG_FS
75 struct dentry *dentry;
76#endif
77 struct kref ref;
78};
79
dfc202ea
SB
80#define CREATE_TRACE_POINTS
81#include <trace/events/clk.h>
82
b09d6d99
MT
83struct clk {
84 struct clk_core *core;
85 const char *dev_id;
86 const char *con_id;
1c8e6004
TV
87 unsigned long min_rate;
88 unsigned long max_rate;
50595f8b 89 struct hlist_node clks_node;
b09d6d99
MT
90};
91
eab89f69
MT
92/*** locking ***/
93static void clk_prepare_lock(void)
94{
533ddeb1
MT
95 if (!mutex_trylock(&prepare_lock)) {
96 if (prepare_owner == current) {
97 prepare_refcnt++;
98 return;
99 }
100 mutex_lock(&prepare_lock);
101 }
102 WARN_ON_ONCE(prepare_owner != NULL);
103 WARN_ON_ONCE(prepare_refcnt != 0);
104 prepare_owner = current;
105 prepare_refcnt = 1;
eab89f69
MT
106}
107
108static void clk_prepare_unlock(void)
109{
533ddeb1
MT
110 WARN_ON_ONCE(prepare_owner != current);
111 WARN_ON_ONCE(prepare_refcnt == 0);
112
113 if (--prepare_refcnt)
114 return;
115 prepare_owner = NULL;
eab89f69
MT
116 mutex_unlock(&prepare_lock);
117}
118
119static unsigned long clk_enable_lock(void)
120{
121 unsigned long flags;
533ddeb1
MT
122
123 if (!spin_trylock_irqsave(&enable_lock, flags)) {
124 if (enable_owner == current) {
125 enable_refcnt++;
126 return flags;
127 }
128 spin_lock_irqsave(&enable_lock, flags);
129 }
130 WARN_ON_ONCE(enable_owner != NULL);
131 WARN_ON_ONCE(enable_refcnt != 0);
132 enable_owner = current;
133 enable_refcnt = 1;
eab89f69
MT
134 return flags;
135}
136
137static void clk_enable_unlock(unsigned long flags)
138{
533ddeb1
MT
139 WARN_ON_ONCE(enable_owner != current);
140 WARN_ON_ONCE(enable_refcnt == 0);
141
142 if (--enable_refcnt)
143 return;
144 enable_owner = NULL;
eab89f69
MT
145 spin_unlock_irqrestore(&enable_lock, flags);
146}
147
b2476490
MT
148/*** debugfs support ***/
149
ea72dc2c 150#ifdef CONFIG_DEBUG_FS
b2476490
MT
151#include <linux/debugfs.h>
152
153static struct dentry *rootdir;
b2476490 154static int inited = 0;
6314b679
SB
155static DEFINE_MUTEX(clk_debug_lock);
156static HLIST_HEAD(clk_debug_list);
b2476490 157
6b44c854
SK
158static struct hlist_head *all_lists[] = {
159 &clk_root_list,
160 &clk_orphan_list,
161 NULL,
162};
163
164static struct hlist_head *orphan_list[] = {
165 &clk_orphan_list,
166 NULL,
167};
168
035a61c3
TV
169static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
170 int level)
1af599df
PG
171{
172 if (!c)
173 return;
174
e59c5371 175 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
1af599df
PG
176 level * 3 + 1, "",
177 30 - level * 3, c->name,
035a61c3
TV
178 c->enable_count, c->prepare_count, clk_core_get_rate(c),
179 clk_core_get_accuracy(c), clk_core_get_phase(c));
1af599df
PG
180}
181
035a61c3 182static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
1af599df
PG
183 int level)
184{
035a61c3 185 struct clk_core *child;
1af599df
PG
186
187 if (!c)
188 return;
189
190 clk_summary_show_one(s, c, level);
191
b67bfe0d 192 hlist_for_each_entry(child, &c->children, child_node)
1af599df
PG
193 clk_summary_show_subtree(s, child, level + 1);
194}
195
196static int clk_summary_show(struct seq_file *s, void *data)
197{
035a61c3 198 struct clk_core *c;
27b8d5f7 199 struct hlist_head **lists = (struct hlist_head **)s->private;
1af599df 200
e59c5371
MT
201 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
202 seq_puts(s, "----------------------------------------------------------------------------------------\n");
1af599df 203
eab89f69 204 clk_prepare_lock();
1af599df 205
27b8d5f7
PDS
206 for (; *lists; lists++)
207 hlist_for_each_entry(c, *lists, child_node)
208 clk_summary_show_subtree(s, c, 0);
1af599df 209
eab89f69 210 clk_prepare_unlock();
1af599df
PG
211
212 return 0;
213}
214
215
216static int clk_summary_open(struct inode *inode, struct file *file)
217{
218 return single_open(file, clk_summary_show, inode->i_private);
219}
220
221static const struct file_operations clk_summary_fops = {
222 .open = clk_summary_open,
223 .read = seq_read,
224 .llseek = seq_lseek,
225 .release = single_release,
226};
227
035a61c3 228static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
bddca894
PG
229{
230 if (!c)
231 return;
232
233 seq_printf(s, "\"%s\": { ", c->name);
234 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
235 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
035a61c3
TV
236 seq_printf(s, "\"rate\": %lu", clk_core_get_rate(c));
237 seq_printf(s, "\"accuracy\": %lu", clk_core_get_accuracy(c));
238 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
bddca894
PG
239}
240
035a61c3 241static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
bddca894 242{
035a61c3 243 struct clk_core *child;
bddca894
PG
244
245 if (!c)
246 return;
247
248 clk_dump_one(s, c, level);
249
b67bfe0d 250 hlist_for_each_entry(child, &c->children, child_node) {
bddca894
PG
251 seq_printf(s, ",");
252 clk_dump_subtree(s, child, level + 1);
253 }
254
255 seq_printf(s, "}");
256}
257
258static int clk_dump(struct seq_file *s, void *data)
259{
035a61c3 260 struct clk_core *c;
bddca894 261 bool first_node = true;
27b8d5f7 262 struct hlist_head **lists = (struct hlist_head **)s->private;
bddca894
PG
263
264 seq_printf(s, "{");
265
eab89f69 266 clk_prepare_lock();
bddca894 267
27b8d5f7
PDS
268 for (; *lists; lists++) {
269 hlist_for_each_entry(c, *lists, child_node) {
270 if (!first_node)
271 seq_puts(s, ",");
272 first_node = false;
273 clk_dump_subtree(s, c, 0);
274 }
bddca894
PG
275 }
276
eab89f69 277 clk_prepare_unlock();
bddca894
PG
278
279 seq_printf(s, "}");
280 return 0;
281}
282
283
284static int clk_dump_open(struct inode *inode, struct file *file)
285{
286 return single_open(file, clk_dump, inode->i_private);
287}
288
289static const struct file_operations clk_dump_fops = {
290 .open = clk_dump_open,
291 .read = seq_read,
292 .llseek = seq_lseek,
293 .release = single_release,
294};
295
d6968fca 296static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
b2476490
MT
297{
298 struct dentry *d;
299 int ret = -ENOMEM;
300
d6968fca 301 if (!core || !pdentry) {
b2476490
MT
302 ret = -EINVAL;
303 goto out;
304 }
305
d6968fca 306 d = debugfs_create_dir(core->name, pdentry);
b2476490
MT
307 if (!d)
308 goto out;
309
d6968fca 310 core->dentry = d;
b2476490 311
d6968fca
SB
312 d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
313 (u32 *)&core->rate);
b2476490
MT
314 if (!d)
315 goto err_out;
316
d6968fca
SB
317 d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
318 (u32 *)&core->accuracy);
5279fc40
BB
319 if (!d)
320 goto err_out;
321
d6968fca
SB
322 d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
323 (u32 *)&core->phase);
e59c5371
MT
324 if (!d)
325 goto err_out;
326
d6968fca
SB
327 d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
328 (u32 *)&core->flags);
b2476490
MT
329 if (!d)
330 goto err_out;
331
d6968fca
SB
332 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
333 (u32 *)&core->prepare_count);
b2476490
MT
334 if (!d)
335 goto err_out;
336
d6968fca
SB
337 d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
338 (u32 *)&core->enable_count);
b2476490
MT
339 if (!d)
340 goto err_out;
341
d6968fca
SB
342 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
343 (u32 *)&core->notifier_count);
b2476490
MT
344 if (!d)
345 goto err_out;
346
d6968fca
SB
347 if (core->ops->debug_init) {
348 ret = core->ops->debug_init(core->hw, core->dentry);
abeab450 349 if (ret)
c646cbf1 350 goto err_out;
abeab450 351 }
c646cbf1 352
b2476490
MT
353 ret = 0;
354 goto out;
355
356err_out:
d6968fca
SB
357 debugfs_remove_recursive(core->dentry);
358 core->dentry = NULL;
b2476490
MT
359out:
360 return ret;
361}
362
b2476490
MT
363/**
364 * clk_debug_register - add a clk node to the debugfs clk tree
d6968fca 365 * @core: the clk being added to the debugfs clk tree
b2476490
MT
366 *
367 * Dynamically adds a clk to the debugfs clk tree if debugfs has been
368 * initialized. Otherwise it bails out early since the debugfs clk tree
369 * will be created lazily by clk_debug_init as part of a late_initcall.
b2476490 370 */
d6968fca 371static int clk_debug_register(struct clk_core *core)
b2476490 372{
b2476490
MT
373 int ret = 0;
374
6314b679 375 mutex_lock(&clk_debug_lock);
d6968fca 376 hlist_add_head(&core->debug_node, &clk_debug_list);
6314b679 377
b2476490 378 if (!inited)
6314b679 379 goto unlock;
b2476490 380
d6968fca 381 ret = clk_debug_create_one(core, rootdir);
6314b679
SB
382unlock:
383 mutex_unlock(&clk_debug_lock);
b2476490 384
b2476490
MT
385 return ret;
386}
387
fcb0ee6a
SN
388 /**
389 * clk_debug_unregister - remove a clk node from the debugfs clk tree
d6968fca 390 * @core: the clk being removed from the debugfs clk tree
fcb0ee6a
SN
391 *
392 * Dynamically removes a clk and all it's children clk nodes from the
393 * debugfs clk tree if clk->dentry points to debugfs created by
394 * clk_debug_register in __clk_init.
fcb0ee6a 395 */
d6968fca 396static void clk_debug_unregister(struct clk_core *core)
fcb0ee6a 397{
6314b679 398 mutex_lock(&clk_debug_lock);
d6968fca
SB
399 hlist_del_init(&core->debug_node);
400 debugfs_remove_recursive(core->dentry);
401 core->dentry = NULL;
6314b679 402 mutex_unlock(&clk_debug_lock);
fcb0ee6a
SN
403}
404
61c7cddf 405struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
fb2b3c9f
PDS
406 void *data, const struct file_operations *fops)
407{
408 struct dentry *d = NULL;
409
035a61c3
TV
410 if (hw->core->dentry)
411 d = debugfs_create_file(name, mode, hw->core->dentry, data,
412 fops);
fb2b3c9f
PDS
413
414 return d;
415}
416EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
417
b2476490
MT
418/**
419 * clk_debug_init - lazily create the debugfs clk tree visualization
420 *
421 * clks are often initialized very early during boot before memory can
422 * be dynamically allocated and well before debugfs is setup.
423 * clk_debug_init walks the clk tree hierarchy while holding
424 * prepare_lock and creates the topology as part of a late_initcall,
425 * thus insuring that clks initialized very early will still be
426 * represented in the debugfs clk tree. This function should only be
427 * called once at boot-time, and all other clks added dynamically will
428 * be done so with clk_debug_register.
429 */
430static int __init clk_debug_init(void)
431{
d6968fca 432 struct clk_core *core;
1af599df 433 struct dentry *d;
b2476490
MT
434
435 rootdir = debugfs_create_dir("clk", NULL);
436
437 if (!rootdir)
438 return -ENOMEM;
439
27b8d5f7 440 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
1af599df
PG
441 &clk_summary_fops);
442 if (!d)
443 return -ENOMEM;
444
27b8d5f7 445 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
bddca894
PG
446 &clk_dump_fops);
447 if (!d)
448 return -ENOMEM;
449
27b8d5f7
PDS
450 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
451 &orphan_list, &clk_summary_fops);
452 if (!d)
453 return -ENOMEM;
b2476490 454
27b8d5f7
PDS
455 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
456 &orphan_list, &clk_dump_fops);
457 if (!d)
b2476490
MT
458 return -ENOMEM;
459
6314b679 460 mutex_lock(&clk_debug_lock);
d6968fca
SB
461 hlist_for_each_entry(core, &clk_debug_list, debug_node)
462 clk_debug_create_one(core, rootdir);
b2476490
MT
463
464 inited = 1;
6314b679 465 mutex_unlock(&clk_debug_lock);
b2476490
MT
466
467 return 0;
468}
469late_initcall(clk_debug_init);
470#else
d6968fca
SB
471static inline int clk_debug_register(struct clk_core *core) { return 0; }
472static inline void clk_debug_reparent(struct clk_core *core,
035a61c3 473 struct clk_core *new_parent)
b33d212f
UH
474{
475}
d6968fca 476static inline void clk_debug_unregister(struct clk_core *core)
fcb0ee6a
SN
477{
478}
70d347e6 479#endif
b2476490 480
1c155b3d 481/* caller must hold prepare_lock */
d6968fca 482static void clk_unprepare_unused_subtree(struct clk_core *core)
1c155b3d 483{
035a61c3 484 struct clk_core *child;
1c155b3d 485
496eadf8
KK
486 lockdep_assert_held(&prepare_lock);
487
d6968fca 488 hlist_for_each_entry(child, &core->children, child_node)
1c155b3d
UH
489 clk_unprepare_unused_subtree(child);
490
d6968fca 491 if (core->prepare_count)
1c155b3d
UH
492 return;
493
d6968fca 494 if (core->flags & CLK_IGNORE_UNUSED)
1c155b3d
UH
495 return;
496
d6968fca
SB
497 if (clk_core_is_prepared(core)) {
498 trace_clk_unprepare(core);
499 if (core->ops->unprepare_unused)
500 core->ops->unprepare_unused(core->hw);
501 else if (core->ops->unprepare)
502 core->ops->unprepare(core->hw);
503 trace_clk_unprepare_complete(core);
3cc8247f 504 }
1c155b3d
UH
505}
506
b2476490 507/* caller must hold prepare_lock */
d6968fca 508static void clk_disable_unused_subtree(struct clk_core *core)
b2476490 509{
035a61c3 510 struct clk_core *child;
b2476490
MT
511 unsigned long flags;
512
496eadf8
KK
513 lockdep_assert_held(&prepare_lock);
514
d6968fca 515 hlist_for_each_entry(child, &core->children, child_node)
b2476490
MT
516 clk_disable_unused_subtree(child);
517
eab89f69 518 flags = clk_enable_lock();
b2476490 519
d6968fca 520 if (core->enable_count)
b2476490
MT
521 goto unlock_out;
522
d6968fca 523 if (core->flags & CLK_IGNORE_UNUSED)
b2476490
MT
524 goto unlock_out;
525
7c045a55
MT
526 /*
527 * some gate clocks have special needs during the disable-unused
528 * sequence. call .disable_unused if available, otherwise fall
529 * back to .disable
530 */
d6968fca
SB
531 if (clk_core_is_enabled(core)) {
532 trace_clk_disable(core);
533 if (core->ops->disable_unused)
534 core->ops->disable_unused(core->hw);
535 else if (core->ops->disable)
536 core->ops->disable(core->hw);
537 trace_clk_disable_complete(core);
7c045a55 538 }
b2476490
MT
539
540unlock_out:
eab89f69 541 clk_enable_unlock(flags);
b2476490
MT
542}
543
1e435256
OJ
544static bool clk_ignore_unused;
545static int __init clk_ignore_unused_setup(char *__unused)
546{
547 clk_ignore_unused = true;
548 return 1;
549}
550__setup("clk_ignore_unused", clk_ignore_unused_setup);
551
b2476490
MT
552static int clk_disable_unused(void)
553{
d6968fca 554 struct clk_core *core;
b2476490 555
1e435256
OJ
556 if (clk_ignore_unused) {
557 pr_warn("clk: Not disabling unused clocks\n");
558 return 0;
559 }
560
eab89f69 561 clk_prepare_lock();
b2476490 562
d6968fca
SB
563 hlist_for_each_entry(core, &clk_root_list, child_node)
564 clk_disable_unused_subtree(core);
b2476490 565
d6968fca
SB
566 hlist_for_each_entry(core, &clk_orphan_list, child_node)
567 clk_disable_unused_subtree(core);
b2476490 568
d6968fca
SB
569 hlist_for_each_entry(core, &clk_root_list, child_node)
570 clk_unprepare_unused_subtree(core);
1c155b3d 571
d6968fca
SB
572 hlist_for_each_entry(core, &clk_orphan_list, child_node)
573 clk_unprepare_unused_subtree(core);
1c155b3d 574
eab89f69 575 clk_prepare_unlock();
b2476490
MT
576
577 return 0;
578}
d41d5805 579late_initcall_sync(clk_disable_unused);
b2476490
MT
580
581/*** helper functions ***/
582
65800b2c 583const char *__clk_get_name(struct clk *clk)
b2476490 584{
035a61c3 585 return !clk ? NULL : clk->core->name;
b2476490 586}
4895084c 587EXPORT_SYMBOL_GPL(__clk_get_name);
b2476490 588
65800b2c 589struct clk_hw *__clk_get_hw(struct clk *clk)
b2476490 590{
035a61c3 591 return !clk ? NULL : clk->core->hw;
b2476490 592}
0b7f04b8 593EXPORT_SYMBOL_GPL(__clk_get_hw);
b2476490 594
65800b2c 595u8 __clk_get_num_parents(struct clk *clk)
b2476490 596{
035a61c3 597 return !clk ? 0 : clk->core->num_parents;
b2476490 598}
0b7f04b8 599EXPORT_SYMBOL_GPL(__clk_get_num_parents);
b2476490 600
65800b2c 601struct clk *__clk_get_parent(struct clk *clk)
b2476490 602{
035a61c3
TV
603 if (!clk)
604 return NULL;
605
606 /* TODO: Create a per-user clk and change callers to call clk_put */
607 return !clk->core->parent ? NULL : clk->core->parent->hw->clk;
b2476490 608}
0b7f04b8 609EXPORT_SYMBOL_GPL(__clk_get_parent);
b2476490 610
d6968fca 611static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
035a61c3 612 u8 index)
7ef3dcc8 613{
d6968fca 614 if (!core || index >= core->num_parents)
7ef3dcc8 615 return NULL;
d6968fca
SB
616 else if (!core->parents)
617 return clk_core_lookup(core->parent_names[index]);
618 else if (!core->parents[index])
619 return core->parents[index] =
620 clk_core_lookup(core->parent_names[index]);
7ef3dcc8 621 else
d6968fca 622 return core->parents[index];
7ef3dcc8 623}
035a61c3
TV
624
625struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
626{
627 struct clk_core *parent;
628
629 if (!clk)
630 return NULL;
631
632 parent = clk_core_get_parent_by_index(clk->core, index);
633
634 return !parent ? NULL : parent->hw->clk;
635}
0b7f04b8 636EXPORT_SYMBOL_GPL(clk_get_parent_by_index);
7ef3dcc8 637
65800b2c 638unsigned int __clk_get_enable_count(struct clk *clk)
b2476490 639{
035a61c3 640 return !clk ? 0 : clk->core->enable_count;
b2476490
MT
641}
642
d6968fca 643static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
b2476490
MT
644{
645 unsigned long ret;
646
d6968fca 647 if (!core) {
34e44fe8 648 ret = 0;
b2476490
MT
649 goto out;
650 }
651
d6968fca 652 ret = core->rate;
b2476490 653
d6968fca 654 if (core->flags & CLK_IS_ROOT)
b2476490
MT
655 goto out;
656
d6968fca 657 if (!core->parent)
34e44fe8 658 ret = 0;
b2476490
MT
659
660out:
661 return ret;
662}
035a61c3
TV
663
664unsigned long __clk_get_rate(struct clk *clk)
665{
666 if (!clk)
667 return 0;
668
669 return clk_core_get_rate_nolock(clk->core);
670}
0b7f04b8 671EXPORT_SYMBOL_GPL(__clk_get_rate);
b2476490 672
d6968fca 673static unsigned long __clk_get_accuracy(struct clk_core *core)
5279fc40 674{
d6968fca 675 if (!core)
5279fc40
BB
676 return 0;
677
d6968fca 678 return core->accuracy;
5279fc40
BB
679}
680
65800b2c 681unsigned long __clk_get_flags(struct clk *clk)
b2476490 682{
035a61c3 683 return !clk ? 0 : clk->core->flags;
b2476490 684}
b05c6836 685EXPORT_SYMBOL_GPL(__clk_get_flags);
b2476490 686
d6968fca 687static bool clk_core_is_prepared(struct clk_core *core)
3d6ee287
UH
688{
689 int ret;
690
d6968fca 691 if (!core)
3d6ee287
UH
692 return false;
693
694 /*
695 * .is_prepared is optional for clocks that can prepare
696 * fall back to software usage counter if it is missing
697 */
d6968fca
SB
698 if (!core->ops->is_prepared) {
699 ret = core->prepare_count ? 1 : 0;
3d6ee287
UH
700 goto out;
701 }
702
d6968fca 703 ret = core->ops->is_prepared(core->hw);
3d6ee287
UH
704out:
705 return !!ret;
706}
707
035a61c3
TV
708bool __clk_is_prepared(struct clk *clk)
709{
710 if (!clk)
711 return false;
712
713 return clk_core_is_prepared(clk->core);
714}
715
d6968fca 716static bool clk_core_is_enabled(struct clk_core *core)
b2476490
MT
717{
718 int ret;
719
d6968fca 720 if (!core)
2ac6b1f5 721 return false;
b2476490
MT
722
723 /*
724 * .is_enabled is only mandatory for clocks that gate
725 * fall back to software usage counter if .is_enabled is missing
726 */
d6968fca
SB
727 if (!core->ops->is_enabled) {
728 ret = core->enable_count ? 1 : 0;
b2476490
MT
729 goto out;
730 }
731
d6968fca 732 ret = core->ops->is_enabled(core->hw);
b2476490 733out:
2ac6b1f5 734 return !!ret;
b2476490 735}
035a61c3
TV
736
737bool __clk_is_enabled(struct clk *clk)
738{
739 if (!clk)
740 return false;
741
742 return clk_core_is_enabled(clk->core);
743}
0b7f04b8 744EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 745
035a61c3 746static struct clk_core *__clk_lookup_subtree(const char *name,
d6968fca 747 struct clk_core *core)
b2476490 748{
035a61c3
TV
749 struct clk_core *child;
750 struct clk_core *ret;
b2476490 751
d6968fca
SB
752 if (!strcmp(core->name, name))
753 return core;
b2476490 754
d6968fca 755 hlist_for_each_entry(child, &core->children, child_node) {
b2476490
MT
756 ret = __clk_lookup_subtree(name, child);
757 if (ret)
758 return ret;
759 }
760
761 return NULL;
762}
763
035a61c3 764static struct clk_core *clk_core_lookup(const char *name)
b2476490 765{
035a61c3
TV
766 struct clk_core *root_clk;
767 struct clk_core *ret;
b2476490
MT
768
769 if (!name)
770 return NULL;
771
772 /* search the 'proper' clk tree first */
b67bfe0d 773 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
b2476490
MT
774 ret = __clk_lookup_subtree(name, root_clk);
775 if (ret)
776 return ret;
777 }
778
779 /* if not found, then search the orphan tree */
b67bfe0d 780 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
b2476490
MT
781 ret = __clk_lookup_subtree(name, root_clk);
782 if (ret)
783 return ret;
784 }
785
786 return NULL;
787}
788
15a02c1f
SB
789static bool mux_is_better_rate(unsigned long rate, unsigned long now,
790 unsigned long best, unsigned long flags)
e366fdd7 791{
15a02c1f
SB
792 if (flags & CLK_MUX_ROUND_CLOSEST)
793 return abs(now - rate) < abs(best - rate);
794
795 return now <= rate && now > best;
796}
797
798static long
799clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
800 unsigned long min_rate,
801 unsigned long max_rate,
15a02c1f
SB
802 unsigned long *best_parent_rate,
803 struct clk_hw **best_parent_p,
804 unsigned long flags)
e366fdd7 805{
035a61c3 806 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
e366fdd7
JH
807 int i, num_parents;
808 unsigned long parent_rate, best = 0;
809
810 /* if NO_REPARENT flag set, pass through to current parent */
035a61c3
TV
811 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
812 parent = core->parent;
813 if (core->flags & CLK_SET_RATE_PARENT)
9e0ad7d2
JMC
814 best = __clk_determine_rate(parent ? parent->hw : NULL,
815 rate, min_rate, max_rate);
e366fdd7 816 else if (parent)
035a61c3 817 best = clk_core_get_rate_nolock(parent);
e366fdd7 818 else
035a61c3 819 best = clk_core_get_rate_nolock(core);
e366fdd7
JH
820 goto out;
821 }
822
823 /* find the parent that can provide the fastest rate <= rate */
035a61c3 824 num_parents = core->num_parents;
e366fdd7 825 for (i = 0; i < num_parents; i++) {
035a61c3 826 parent = clk_core_get_parent_by_index(core, i);
e366fdd7
JH
827 if (!parent)
828 continue;
035a61c3 829 if (core->flags & CLK_SET_RATE_PARENT)
1c8e6004
TV
830 parent_rate = __clk_determine_rate(parent->hw, rate,
831 min_rate,
832 max_rate);
e366fdd7 833 else
035a61c3 834 parent_rate = clk_core_get_rate_nolock(parent);
15a02c1f 835 if (mux_is_better_rate(rate, parent_rate, best, flags)) {
e366fdd7
JH
836 best_parent = parent;
837 best = parent_rate;
838 }
839 }
840
841out:
842 if (best_parent)
646cafc6 843 *best_parent_p = best_parent->hw;
e366fdd7
JH
844 *best_parent_rate = best;
845
846 return best;
847}
15a02c1f 848
035a61c3
TV
849struct clk *__clk_lookup(const char *name)
850{
851 struct clk_core *core = clk_core_lookup(name);
852
853 return !core ? NULL : core->hw->clk;
854}
855
d6968fca 856static void clk_core_get_boundaries(struct clk_core *core,
1c8e6004
TV
857 unsigned long *min_rate,
858 unsigned long *max_rate)
859{
860 struct clk *clk_user;
861
862 *min_rate = 0;
863 *max_rate = ULONG_MAX;
864
d6968fca 865 hlist_for_each_entry(clk_user, &core->clks, clks_node)
1c8e6004
TV
866 *min_rate = max(*min_rate, clk_user->min_rate);
867
d6968fca 868 hlist_for_each_entry(clk_user, &core->clks, clks_node)
1c8e6004
TV
869 *max_rate = min(*max_rate, clk_user->max_rate);
870}
871
15a02c1f
SB
872/*
873 * Helper for finding best parent to provide a given frequency. This can be used
874 * directly as a determine_rate callback (e.g. for a mux), or from a more
875 * complex clock that may combine a mux with other operations.
876 */
877long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
878 unsigned long min_rate,
879 unsigned long max_rate,
15a02c1f
SB
880 unsigned long *best_parent_rate,
881 struct clk_hw **best_parent_p)
882{
1c8e6004
TV
883 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
884 best_parent_rate,
15a02c1f
SB
885 best_parent_p, 0);
886}
0b7f04b8 887EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
e366fdd7 888
15a02c1f 889long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
890 unsigned long min_rate,
891 unsigned long max_rate,
15a02c1f
SB
892 unsigned long *best_parent_rate,
893 struct clk_hw **best_parent_p)
894{
1c8e6004
TV
895 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
896 best_parent_rate,
15a02c1f
SB
897 best_parent_p,
898 CLK_MUX_ROUND_CLOSEST);
899}
900EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
901
b2476490
MT
902/*** clk api ***/
903
d6968fca 904static void clk_core_unprepare(struct clk_core *core)
b2476490 905{
d6968fca 906 if (!core)
b2476490
MT
907 return;
908
d6968fca 909 if (WARN_ON(core->prepare_count == 0))
b2476490
MT
910 return;
911
d6968fca 912 if (--core->prepare_count > 0)
b2476490
MT
913 return;
914
d6968fca 915 WARN_ON(core->enable_count > 0);
b2476490 916
d6968fca 917 trace_clk_unprepare(core);
dfc202ea 918
d6968fca
SB
919 if (core->ops->unprepare)
920 core->ops->unprepare(core->hw);
b2476490 921
d6968fca
SB
922 trace_clk_unprepare_complete(core);
923 clk_core_unprepare(core->parent);
b2476490
MT
924}
925
926/**
927 * clk_unprepare - undo preparation of a clock source
24ee1a08 928 * @clk: the clk being unprepared
b2476490
MT
929 *
930 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
931 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
932 * if the operation may sleep. One example is a clk which is accessed over
933 * I2c. In the complex case a clk gate operation may require a fast and a slow
934 * part. It is this reason that clk_unprepare and clk_disable are not mutually
935 * exclusive. In fact clk_disable must be called before clk_unprepare.
936 */
937void clk_unprepare(struct clk *clk)
938{
63589e92
SB
939 if (IS_ERR_OR_NULL(clk))
940 return;
941
eab89f69 942 clk_prepare_lock();
035a61c3 943 clk_core_unprepare(clk->core);
eab89f69 944 clk_prepare_unlock();
b2476490
MT
945}
946EXPORT_SYMBOL_GPL(clk_unprepare);
947
d6968fca 948static int clk_core_prepare(struct clk_core *core)
b2476490
MT
949{
950 int ret = 0;
951
d6968fca 952 if (!core)
b2476490
MT
953 return 0;
954
d6968fca
SB
955 if (core->prepare_count == 0) {
956 ret = clk_core_prepare(core->parent);
b2476490
MT
957 if (ret)
958 return ret;
959
d6968fca 960 trace_clk_prepare(core);
dfc202ea 961
d6968fca
SB
962 if (core->ops->prepare)
963 ret = core->ops->prepare(core->hw);
dfc202ea 964
d6968fca 965 trace_clk_prepare_complete(core);
dfc202ea
SB
966
967 if (ret) {
d6968fca 968 clk_core_unprepare(core->parent);
dfc202ea 969 return ret;
b2476490
MT
970 }
971 }
972
d6968fca 973 core->prepare_count++;
b2476490
MT
974
975 return 0;
976}
977
978/**
979 * clk_prepare - prepare a clock source
980 * @clk: the clk being prepared
981 *
982 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
983 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
984 * operation may sleep. One example is a clk which is accessed over I2c. In
985 * the complex case a clk ungate operation may require a fast and a slow part.
986 * It is this reason that clk_prepare and clk_enable are not mutually
987 * exclusive. In fact clk_prepare must be called before clk_enable.
988 * Returns 0 on success, -EERROR otherwise.
989 */
990int clk_prepare(struct clk *clk)
991{
992 int ret;
993
035a61c3
TV
994 if (!clk)
995 return 0;
996
eab89f69 997 clk_prepare_lock();
035a61c3 998 ret = clk_core_prepare(clk->core);
eab89f69 999 clk_prepare_unlock();
b2476490
MT
1000
1001 return ret;
1002}
1003EXPORT_SYMBOL_GPL(clk_prepare);
1004
d6968fca 1005static void clk_core_disable(struct clk_core *core)
b2476490 1006{
d6968fca 1007 if (!core)
b2476490
MT
1008 return;
1009
d6968fca 1010 if (WARN_ON(core->enable_count == 0))
b2476490
MT
1011 return;
1012
d6968fca 1013 if (--core->enable_count > 0)
b2476490
MT
1014 return;
1015
d6968fca 1016 trace_clk_disable(core);
dfc202ea 1017
d6968fca
SB
1018 if (core->ops->disable)
1019 core->ops->disable(core->hw);
b2476490 1020
d6968fca 1021 trace_clk_disable_complete(core);
dfc202ea 1022
d6968fca 1023 clk_core_disable(core->parent);
035a61c3
TV
1024}
1025
1026static void __clk_disable(struct clk *clk)
1027{
1028 if (!clk)
1029 return;
1030
1031 clk_core_disable(clk->core);
b2476490
MT
1032}
1033
1034/**
1035 * clk_disable - gate a clock
1036 * @clk: the clk being gated
1037 *
1038 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
1039 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
1040 * clk if the operation is fast and will never sleep. One example is a
1041 * SoC-internal clk which is controlled via simple register writes. In the
1042 * complex case a clk gate operation may require a fast and a slow part. It is
1043 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
1044 * In fact clk_disable must be called before clk_unprepare.
1045 */
1046void clk_disable(struct clk *clk)
1047{
1048 unsigned long flags;
1049
63589e92
SB
1050 if (IS_ERR_OR_NULL(clk))
1051 return;
1052
eab89f69 1053 flags = clk_enable_lock();
b2476490 1054 __clk_disable(clk);
eab89f69 1055 clk_enable_unlock(flags);
b2476490
MT
1056}
1057EXPORT_SYMBOL_GPL(clk_disable);
1058
d6968fca 1059static int clk_core_enable(struct clk_core *core)
b2476490
MT
1060{
1061 int ret = 0;
1062
d6968fca 1063 if (!core)
b2476490
MT
1064 return 0;
1065
d6968fca 1066 if (WARN_ON(core->prepare_count == 0))
b2476490
MT
1067 return -ESHUTDOWN;
1068
d6968fca
SB
1069 if (core->enable_count == 0) {
1070 ret = clk_core_enable(core->parent);
b2476490
MT
1071
1072 if (ret)
1073 return ret;
1074
d6968fca 1075 trace_clk_enable(core);
dfc202ea 1076
d6968fca
SB
1077 if (core->ops->enable)
1078 ret = core->ops->enable(core->hw);
dfc202ea 1079
d6968fca 1080 trace_clk_enable_complete(core);
dfc202ea
SB
1081
1082 if (ret) {
d6968fca 1083 clk_core_disable(core->parent);
dfc202ea 1084 return ret;
b2476490
MT
1085 }
1086 }
1087
d6968fca 1088 core->enable_count++;
b2476490
MT
1089 return 0;
1090}
1091
035a61c3
TV
1092static int __clk_enable(struct clk *clk)
1093{
1094 if (!clk)
1095 return 0;
1096
1097 return clk_core_enable(clk->core);
1098}
1099
b2476490
MT
1100/**
1101 * clk_enable - ungate a clock
1102 * @clk: the clk being ungated
1103 *
1104 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
1105 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
1106 * if the operation will never sleep. One example is a SoC-internal clk which
1107 * is controlled via simple register writes. In the complex case a clk ungate
1108 * operation may require a fast and a slow part. It is this reason that
1109 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
1110 * must be called before clk_enable. Returns 0 on success, -EERROR
1111 * otherwise.
1112 */
1113int clk_enable(struct clk *clk)
1114{
1115 unsigned long flags;
1116 int ret;
1117
eab89f69 1118 flags = clk_enable_lock();
b2476490 1119 ret = __clk_enable(clk);
eab89f69 1120 clk_enable_unlock(flags);
b2476490
MT
1121
1122 return ret;
1123}
1124EXPORT_SYMBOL_GPL(clk_enable);
1125
d6968fca 1126static unsigned long clk_core_round_rate_nolock(struct clk_core *core,
1c8e6004
TV
1127 unsigned long rate,
1128 unsigned long min_rate,
1129 unsigned long max_rate)
b2476490 1130{
81536e07 1131 unsigned long parent_rate = 0;
035a61c3 1132 struct clk_core *parent;
646cafc6 1133 struct clk_hw *parent_hw;
b2476490 1134
496eadf8
KK
1135 lockdep_assert_held(&prepare_lock);
1136
d6968fca 1137 if (!core)
2ac6b1f5 1138 return 0;
b2476490 1139
d6968fca 1140 parent = core->parent;
71472c0c
JH
1141 if (parent)
1142 parent_rate = parent->rate;
1143
d6968fca 1144 if (core->ops->determine_rate) {
646cafc6 1145 parent_hw = parent ? parent->hw : NULL;
d6968fca 1146 return core->ops->determine_rate(core->hw, rate,
1c8e6004
TV
1147 min_rate, max_rate,
1148 &parent_rate, &parent_hw);
d6968fca
SB
1149 } else if (core->ops->round_rate)
1150 return core->ops->round_rate(core->hw, rate, &parent_rate);
1151 else if (core->flags & CLK_SET_RATE_PARENT)
1152 return clk_core_round_rate_nolock(core->parent, rate, min_rate,
1c8e6004 1153 max_rate);
71472c0c 1154 else
d6968fca 1155 return core->rate;
b2476490 1156}
035a61c3 1157
1c8e6004
TV
1158/**
1159 * __clk_determine_rate - get the closest rate actually supported by a clock
1160 * @hw: determine the rate of this clock
1161 * @rate: target rate
1162 * @min_rate: returned rate must be greater than this rate
1163 * @max_rate: returned rate must be less than this rate
1164 *
1165 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate and
1166 * .determine_rate.
1167 */
1168unsigned long __clk_determine_rate(struct clk_hw *hw,
1169 unsigned long rate,
1170 unsigned long min_rate,
1171 unsigned long max_rate)
1172{
1173 if (!hw)
1174 return 0;
1175
1176 return clk_core_round_rate_nolock(hw->core, rate, min_rate, max_rate);
1177}
1178EXPORT_SYMBOL_GPL(__clk_determine_rate);
1179
035a61c3
TV
1180/**
1181 * __clk_round_rate - round the given rate for a clk
1182 * @clk: round the rate of this clock
1183 * @rate: the rate which is to be rounded
1184 *
1185 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate
1186 */
1187unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
1188{
1c8e6004
TV
1189 unsigned long min_rate;
1190 unsigned long max_rate;
1191
035a61c3
TV
1192 if (!clk)
1193 return 0;
1194
1c8e6004
TV
1195 clk_core_get_boundaries(clk->core, &min_rate, &max_rate);
1196
1197 return clk_core_round_rate_nolock(clk->core, rate, min_rate, max_rate);
035a61c3 1198}
1cdf8ee2 1199EXPORT_SYMBOL_GPL(__clk_round_rate);
b2476490
MT
1200
1201/**
1202 * clk_round_rate - round the given rate for a clk
1203 * @clk: the clk for which we are rounding a rate
1204 * @rate: the rate which is to be rounded
1205 *
1206 * Takes in a rate as input and rounds it to a rate that the clk can actually
1207 * use which is then returned. If clk doesn't support round_rate operation
1208 * then the parent rate is returned.
1209 */
1210long clk_round_rate(struct clk *clk, unsigned long rate)
1211{
1212 unsigned long ret;
1213
035a61c3
TV
1214 if (!clk)
1215 return 0;
1216
eab89f69 1217 clk_prepare_lock();
b2476490 1218 ret = __clk_round_rate(clk, rate);
eab89f69 1219 clk_prepare_unlock();
b2476490
MT
1220
1221 return ret;
1222}
1223EXPORT_SYMBOL_GPL(clk_round_rate);
1224
1225/**
1226 * __clk_notify - call clk notifier chain
d6968fca 1227 * @core: clk that is changing rate
b2476490
MT
1228 * @msg: clk notifier type (see include/linux/clk.h)
1229 * @old_rate: old clk rate
1230 * @new_rate: new clk rate
1231 *
1232 * Triggers a notifier call chain on the clk rate-change notification
1233 * for 'clk'. Passes a pointer to the struct clk and the previous
1234 * and current rates to the notifier callback. Intended to be called by
1235 * internal clock code only. Returns NOTIFY_DONE from the last driver
1236 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
1237 * a driver returns that.
1238 */
d6968fca 1239static int __clk_notify(struct clk_core *core, unsigned long msg,
b2476490
MT
1240 unsigned long old_rate, unsigned long new_rate)
1241{
1242 struct clk_notifier *cn;
1243 struct clk_notifier_data cnd;
1244 int ret = NOTIFY_DONE;
1245
b2476490
MT
1246 cnd.old_rate = old_rate;
1247 cnd.new_rate = new_rate;
1248
1249 list_for_each_entry(cn, &clk_notifier_list, node) {
d6968fca 1250 if (cn->clk->core == core) {
035a61c3 1251 cnd.clk = cn->clk;
b2476490
MT
1252 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
1253 &cnd);
b2476490
MT
1254 }
1255 }
1256
1257 return ret;
1258}
1259
5279fc40
BB
1260/**
1261 * __clk_recalc_accuracies
d6968fca 1262 * @core: first clk in the subtree
5279fc40
BB
1263 *
1264 * Walks the subtree of clks starting with clk and recalculates accuracies as
1265 * it goes. Note that if a clk does not implement the .recalc_accuracy
1266 * callback then it is assumed that the clock will take on the accuracy of it's
1267 * parent.
1268 *
1269 * Caller must hold prepare_lock.
1270 */
d6968fca 1271static void __clk_recalc_accuracies(struct clk_core *core)
5279fc40
BB
1272{
1273 unsigned long parent_accuracy = 0;
035a61c3 1274 struct clk_core *child;
5279fc40 1275
496eadf8
KK
1276 lockdep_assert_held(&prepare_lock);
1277
d6968fca
SB
1278 if (core->parent)
1279 parent_accuracy = core->parent->accuracy;
5279fc40 1280
d6968fca
SB
1281 if (core->ops->recalc_accuracy)
1282 core->accuracy = core->ops->recalc_accuracy(core->hw,
5279fc40
BB
1283 parent_accuracy);
1284 else
d6968fca 1285 core->accuracy = parent_accuracy;
5279fc40 1286
d6968fca 1287 hlist_for_each_entry(child, &core->children, child_node)
5279fc40
BB
1288 __clk_recalc_accuracies(child);
1289}
1290
d6968fca 1291static long clk_core_get_accuracy(struct clk_core *core)
035a61c3
TV
1292{
1293 unsigned long accuracy;
1294
1295 clk_prepare_lock();
d6968fca
SB
1296 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
1297 __clk_recalc_accuracies(core);
035a61c3 1298
d6968fca 1299 accuracy = __clk_get_accuracy(core);
035a61c3
TV
1300 clk_prepare_unlock();
1301
1302 return accuracy;
1303}
1304
5279fc40
BB
1305/**
1306 * clk_get_accuracy - return the accuracy of clk
1307 * @clk: the clk whose accuracy is being returned
1308 *
1309 * Simply returns the cached accuracy of the clk, unless
1310 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
1311 * issued.
1312 * If clk is NULL then returns 0.
1313 */
1314long clk_get_accuracy(struct clk *clk)
1315{
035a61c3
TV
1316 if (!clk)
1317 return 0;
5279fc40 1318
035a61c3 1319 return clk_core_get_accuracy(clk->core);
5279fc40
BB
1320}
1321EXPORT_SYMBOL_GPL(clk_get_accuracy);
1322
d6968fca 1323static unsigned long clk_recalc(struct clk_core *core,
035a61c3 1324 unsigned long parent_rate)
8f2c2db1 1325{
d6968fca
SB
1326 if (core->ops->recalc_rate)
1327 return core->ops->recalc_rate(core->hw, parent_rate);
8f2c2db1
SB
1328 return parent_rate;
1329}
1330
b2476490
MT
1331/**
1332 * __clk_recalc_rates
d6968fca 1333 * @core: first clk in the subtree
b2476490
MT
1334 * @msg: notification type (see include/linux/clk.h)
1335 *
1336 * Walks the subtree of clks starting with clk and recalculates rates as it
1337 * goes. Note that if a clk does not implement the .recalc_rate callback then
24ee1a08 1338 * it is assumed that the clock will take on the rate of its parent.
b2476490
MT
1339 *
1340 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1341 * if necessary.
1342 *
1343 * Caller must hold prepare_lock.
1344 */
d6968fca 1345static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
b2476490
MT
1346{
1347 unsigned long old_rate;
1348 unsigned long parent_rate = 0;
035a61c3 1349 struct clk_core *child;
b2476490 1350
496eadf8
KK
1351 lockdep_assert_held(&prepare_lock);
1352
d6968fca 1353 old_rate = core->rate;
b2476490 1354
d6968fca
SB
1355 if (core->parent)
1356 parent_rate = core->parent->rate;
b2476490 1357
d6968fca 1358 core->rate = clk_recalc(core, parent_rate);
b2476490
MT
1359
1360 /*
1361 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1362 * & ABORT_RATE_CHANGE notifiers
1363 */
d6968fca
SB
1364 if (core->notifier_count && msg)
1365 __clk_notify(core, msg, old_rate, core->rate);
b2476490 1366
d6968fca 1367 hlist_for_each_entry(child, &core->children, child_node)
b2476490
MT
1368 __clk_recalc_rates(child, msg);
1369}
1370
d6968fca 1371static unsigned long clk_core_get_rate(struct clk_core *core)
a093bde2
UH
1372{
1373 unsigned long rate;
1374
eab89f69 1375 clk_prepare_lock();
a093bde2 1376
d6968fca
SB
1377 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1378 __clk_recalc_rates(core, 0);
a093bde2 1379
d6968fca 1380 rate = clk_core_get_rate_nolock(core);
eab89f69 1381 clk_prepare_unlock();
a093bde2
UH
1382
1383 return rate;
1384}
035a61c3
TV
1385
1386/**
1387 * clk_get_rate - return the rate of clk
1388 * @clk: the clk whose rate is being returned
1389 *
1390 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1391 * is set, which means a recalc_rate will be issued.
1392 * If clk is NULL then returns 0.
1393 */
1394unsigned long clk_get_rate(struct clk *clk)
1395{
1396 if (!clk)
1397 return 0;
1398
1399 return clk_core_get_rate(clk->core);
1400}
a093bde2
UH
1401EXPORT_SYMBOL_GPL(clk_get_rate);
1402
d6968fca 1403static int clk_fetch_parent_index(struct clk_core *core,
035a61c3 1404 struct clk_core *parent)
4935b22c 1405{
f1c8b2ed 1406 int i;
4935b22c 1407
d6968fca
SB
1408 if (!core->parents) {
1409 core->parents = kcalloc(core->num_parents,
96a7ed90 1410 sizeof(struct clk *), GFP_KERNEL);
d6968fca 1411 if (!core->parents)
f1c8b2ed
TF
1412 return -ENOMEM;
1413 }
4935b22c
JH
1414
1415 /*
1416 * find index of new parent clock using cached parent ptrs,
1417 * or if not yet cached, use string name comparison and cache
035a61c3 1418 * them now to avoid future calls to clk_core_lookup.
4935b22c 1419 */
d6968fca
SB
1420 for (i = 0; i < core->num_parents; i++) {
1421 if (core->parents[i] == parent)
f1c8b2ed 1422 return i;
da0f0b2c 1423
d6968fca 1424 if (core->parents[i])
da0f0b2c
TF
1425 continue;
1426
d6968fca
SB
1427 if (!strcmp(core->parent_names[i], parent->name)) {
1428 core->parents[i] = clk_core_lookup(parent->name);
f1c8b2ed 1429 return i;
4935b22c
JH
1430 }
1431 }
1432
f1c8b2ed 1433 return -EINVAL;
4935b22c
JH
1434}
1435
d6968fca 1436static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
4935b22c 1437{
d6968fca 1438 hlist_del(&core->child_node);
4935b22c 1439
903efc55
JH
1440 if (new_parent) {
1441 /* avoid duplicate POST_RATE_CHANGE notifications */
d6968fca 1442 if (new_parent->new_child == core)
903efc55
JH
1443 new_parent->new_child = NULL;
1444
d6968fca 1445 hlist_add_head(&core->child_node, &new_parent->children);
903efc55 1446 } else {
d6968fca 1447 hlist_add_head(&core->child_node, &clk_orphan_list);
903efc55 1448 }
4935b22c 1449
d6968fca 1450 core->parent = new_parent;
4935b22c
JH
1451}
1452
d6968fca 1453static struct clk_core *__clk_set_parent_before(struct clk_core *core,
035a61c3 1454 struct clk_core *parent)
4935b22c
JH
1455{
1456 unsigned long flags;
d6968fca 1457 struct clk_core *old_parent = core->parent;
4935b22c
JH
1458
1459 /*
1460 * Migrate prepare state between parents and prevent race with
1461 * clk_enable().
1462 *
1463 * If the clock is not prepared, then a race with
1464 * clk_enable/disable() is impossible since we already have the
1465 * prepare lock (future calls to clk_enable() need to be preceded by
1466 * a clk_prepare()).
1467 *
1468 * If the clock is prepared, migrate the prepared state to the new
1469 * parent and also protect against a race with clk_enable() by
1470 * forcing the clock and the new parent on. This ensures that all
1471 * future calls to clk_enable() are practically NOPs with respect to
1472 * hardware and software states.
1473 *
1474 * See also: Comment for clk_set_parent() below.
1475 */
d6968fca 1476 if (core->prepare_count) {
035a61c3
TV
1477 clk_core_prepare(parent);
1478 clk_core_enable(parent);
d6968fca 1479 clk_core_enable(core);
4935b22c
JH
1480 }
1481
1482 /* update the clk tree topology */
1483 flags = clk_enable_lock();
d6968fca 1484 clk_reparent(core, parent);
4935b22c
JH
1485 clk_enable_unlock(flags);
1486
3fa2252b
SB
1487 return old_parent;
1488}
1489
035a61c3
TV
1490static void __clk_set_parent_after(struct clk_core *core,
1491 struct clk_core *parent,
1492 struct clk_core *old_parent)
3fa2252b
SB
1493{
1494 /*
1495 * Finish the migration of prepare state and undo the changes done
1496 * for preventing a race with clk_enable().
1497 */
035a61c3
TV
1498 if (core->prepare_count) {
1499 clk_core_disable(core);
1500 clk_core_disable(old_parent);
1501 clk_core_unprepare(old_parent);
3fa2252b 1502 }
3fa2252b
SB
1503}
1504
d6968fca 1505static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
035a61c3 1506 u8 p_index)
3fa2252b
SB
1507{
1508 unsigned long flags;
1509 int ret = 0;
035a61c3 1510 struct clk_core *old_parent;
3fa2252b 1511
d6968fca 1512 old_parent = __clk_set_parent_before(core, parent);
3fa2252b 1513
d6968fca 1514 trace_clk_set_parent(core, parent);
dfc202ea 1515
4935b22c 1516 /* change clock input source */
d6968fca
SB
1517 if (parent && core->ops->set_parent)
1518 ret = core->ops->set_parent(core->hw, p_index);
4935b22c 1519
d6968fca 1520 trace_clk_set_parent_complete(core, parent);
dfc202ea 1521
4935b22c
JH
1522 if (ret) {
1523 flags = clk_enable_lock();
d6968fca 1524 clk_reparent(core, old_parent);
4935b22c
JH
1525 clk_enable_unlock(flags);
1526
d6968fca
SB
1527 if (core->prepare_count) {
1528 clk_core_disable(core);
035a61c3
TV
1529 clk_core_disable(parent);
1530 clk_core_unprepare(parent);
4935b22c
JH
1531 }
1532 return ret;
1533 }
1534
d6968fca 1535 __clk_set_parent_after(core, parent, old_parent);
4935b22c 1536
4935b22c
JH
1537 return 0;
1538}
1539
b2476490
MT
1540/**
1541 * __clk_speculate_rates
d6968fca 1542 * @core: first clk in the subtree
b2476490
MT
1543 * @parent_rate: the "future" rate of clk's parent
1544 *
1545 * Walks the subtree of clks starting with clk, speculating rates as it
1546 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1547 *
1548 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1549 * pre-rate change notifications and returns early if no clks in the
1550 * subtree have subscribed to the notifications. Note that if a clk does not
1551 * implement the .recalc_rate callback then it is assumed that the clock will
24ee1a08 1552 * take on the rate of its parent.
b2476490
MT
1553 *
1554 * Caller must hold prepare_lock.
1555 */
d6968fca 1556static int __clk_speculate_rates(struct clk_core *core,
035a61c3 1557 unsigned long parent_rate)
b2476490 1558{
035a61c3 1559 struct clk_core *child;
b2476490
MT
1560 unsigned long new_rate;
1561 int ret = NOTIFY_DONE;
1562
496eadf8
KK
1563 lockdep_assert_held(&prepare_lock);
1564
d6968fca 1565 new_rate = clk_recalc(core, parent_rate);
b2476490 1566
fb72a059 1567 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
d6968fca
SB
1568 if (core->notifier_count)
1569 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
b2476490 1570
86bcfa2e
MT
1571 if (ret & NOTIFY_STOP_MASK) {
1572 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
d6968fca 1573 __func__, core->name, ret);
b2476490 1574 goto out;
86bcfa2e 1575 }
b2476490 1576
d6968fca 1577 hlist_for_each_entry(child, &core->children, child_node) {
b2476490 1578 ret = __clk_speculate_rates(child, new_rate);
fb72a059 1579 if (ret & NOTIFY_STOP_MASK)
b2476490
MT
1580 break;
1581 }
1582
1583out:
1584 return ret;
1585}
1586
d6968fca 1587static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
035a61c3 1588 struct clk_core *new_parent, u8 p_index)
b2476490 1589{
035a61c3 1590 struct clk_core *child;
b2476490 1591
d6968fca
SB
1592 core->new_rate = new_rate;
1593 core->new_parent = new_parent;
1594 core->new_parent_index = p_index;
71472c0c 1595 /* include clk in new parent's PRE_RATE_CHANGE notifications */
d6968fca
SB
1596 core->new_child = NULL;
1597 if (new_parent && new_parent != core->parent)
1598 new_parent->new_child = core;
b2476490 1599
d6968fca 1600 hlist_for_each_entry(child, &core->children, child_node) {
8f2c2db1 1601 child->new_rate = clk_recalc(child, new_rate);
71472c0c 1602 clk_calc_subtree(child, child->new_rate, NULL, 0);
b2476490
MT
1603 }
1604}
1605
1606/*
1607 * calculate the new rates returning the topmost clock that has to be
1608 * changed.
1609 */
d6968fca 1610static struct clk_core *clk_calc_new_rates(struct clk_core *core,
035a61c3 1611 unsigned long rate)
b2476490 1612{
d6968fca 1613 struct clk_core *top = core;
035a61c3 1614 struct clk_core *old_parent, *parent;
646cafc6 1615 struct clk_hw *parent_hw;
81536e07 1616 unsigned long best_parent_rate = 0;
b2476490 1617 unsigned long new_rate;
1c8e6004
TV
1618 unsigned long min_rate;
1619 unsigned long max_rate;
f1c8b2ed 1620 int p_index = 0;
03bc10ab 1621 long ret;
b2476490 1622
7452b219 1623 /* sanity */
d6968fca 1624 if (IS_ERR_OR_NULL(core))
7452b219
MT
1625 return NULL;
1626
63f5c3b2 1627 /* save parent rate, if it exists */
d6968fca 1628 parent = old_parent = core->parent;
71472c0c
JH
1629 if (parent)
1630 best_parent_rate = parent->rate;
1631
d6968fca 1632 clk_core_get_boundaries(core, &min_rate, &max_rate);
1c8e6004 1633
71472c0c 1634 /* find the closest rate and parent clk/rate */
d6968fca 1635 if (core->ops->determine_rate) {
646cafc6 1636 parent_hw = parent ? parent->hw : NULL;
d6968fca 1637 ret = core->ops->determine_rate(core->hw, rate,
03bc10ab
BB
1638 min_rate,
1639 max_rate,
1640 &best_parent_rate,
1641 &parent_hw);
1642 if (ret < 0)
1643 return NULL;
1644
1645 new_rate = ret;
035a61c3 1646 parent = parent_hw ? parent_hw->core : NULL;
d6968fca
SB
1647 } else if (core->ops->round_rate) {
1648 ret = core->ops->round_rate(core->hw, rate,
03bc10ab
BB
1649 &best_parent_rate);
1650 if (ret < 0)
1651 return NULL;
1652
1653 new_rate = ret;
1c8e6004
TV
1654 if (new_rate < min_rate || new_rate > max_rate)
1655 return NULL;
d6968fca 1656 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
71472c0c 1657 /* pass-through clock without adjustable parent */
d6968fca 1658 core->new_rate = core->rate;
71472c0c
JH
1659 return NULL;
1660 } else {
1661 /* pass-through clock with adjustable parent */
1662 top = clk_calc_new_rates(parent, rate);
1663 new_rate = parent->new_rate;
63f5c3b2 1664 goto out;
7452b219
MT
1665 }
1666
71472c0c
JH
1667 /* some clocks must be gated to change parent */
1668 if (parent != old_parent &&
d6968fca 1669 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
71472c0c 1670 pr_debug("%s: %s not gated but wants to reparent\n",
d6968fca 1671 __func__, core->name);
b2476490
MT
1672 return NULL;
1673 }
1674
71472c0c 1675 /* try finding the new parent index */
d6968fca
SB
1676 if (parent && core->num_parents > 1) {
1677 p_index = clk_fetch_parent_index(core, parent);
f1c8b2ed 1678 if (p_index < 0) {
71472c0c 1679 pr_debug("%s: clk %s can not be parent of clk %s\n",
d6968fca 1680 __func__, parent->name, core->name);
71472c0c
JH
1681 return NULL;
1682 }
b2476490
MT
1683 }
1684
d6968fca 1685 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
71472c0c
JH
1686 best_parent_rate != parent->rate)
1687 top = clk_calc_new_rates(parent, best_parent_rate);
b2476490
MT
1688
1689out:
d6968fca 1690 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490
MT
1691
1692 return top;
1693}
1694
1695/*
1696 * Notify about rate changes in a subtree. Always walk down the whole tree
1697 * so that in case of an error we can walk down the whole tree again and
1698 * abort the change.
1699 */
d6968fca 1700static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
035a61c3 1701 unsigned long event)
b2476490 1702{
035a61c3 1703 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1704 int ret = NOTIFY_DONE;
1705
d6968fca 1706 if (core->rate == core->new_rate)
5fda6858 1707 return NULL;
b2476490 1708
d6968fca
SB
1709 if (core->notifier_count) {
1710 ret = __clk_notify(core, event, core->rate, core->new_rate);
fb72a059 1711 if (ret & NOTIFY_STOP_MASK)
d6968fca 1712 fail_clk = core;
b2476490
MT
1713 }
1714
d6968fca 1715 hlist_for_each_entry(child, &core->children, child_node) {
71472c0c 1716 /* Skip children who will be reparented to another clock */
d6968fca 1717 if (child->new_parent && child->new_parent != core)
71472c0c
JH
1718 continue;
1719 tmp_clk = clk_propagate_rate_change(child, event);
1720 if (tmp_clk)
1721 fail_clk = tmp_clk;
1722 }
1723
d6968fca
SB
1724 /* handle the new child who might not be in core->children yet */
1725 if (core->new_child) {
1726 tmp_clk = clk_propagate_rate_change(core->new_child, event);
71472c0c
JH
1727 if (tmp_clk)
1728 fail_clk = tmp_clk;
b2476490
MT
1729 }
1730
1731 return fail_clk;
1732}
1733
1734/*
1735 * walk down a subtree and set the new rates notifying the rate
1736 * change on the way
1737 */
d6968fca 1738static void clk_change_rate(struct clk_core *core)
b2476490 1739{
035a61c3 1740 struct clk_core *child;
067bb174 1741 struct hlist_node *tmp;
b2476490 1742 unsigned long old_rate;
bf47b4fd 1743 unsigned long best_parent_rate = 0;
3fa2252b 1744 bool skip_set_rate = false;
035a61c3 1745 struct clk_core *old_parent;
b2476490 1746
d6968fca 1747 old_rate = core->rate;
b2476490 1748
d6968fca
SB
1749 if (core->new_parent)
1750 best_parent_rate = core->new_parent->rate;
1751 else if (core->parent)
1752 best_parent_rate = core->parent->rate;
bf47b4fd 1753
d6968fca
SB
1754 if (core->new_parent && core->new_parent != core->parent) {
1755 old_parent = __clk_set_parent_before(core, core->new_parent);
1756 trace_clk_set_parent(core, core->new_parent);
3fa2252b 1757
d6968fca 1758 if (core->ops->set_rate_and_parent) {
3fa2252b 1759 skip_set_rate = true;
d6968fca 1760 core->ops->set_rate_and_parent(core->hw, core->new_rate,
3fa2252b 1761 best_parent_rate,
d6968fca
SB
1762 core->new_parent_index);
1763 } else if (core->ops->set_parent) {
1764 core->ops->set_parent(core->hw, core->new_parent_index);
3fa2252b
SB
1765 }
1766
d6968fca
SB
1767 trace_clk_set_parent_complete(core, core->new_parent);
1768 __clk_set_parent_after(core, core->new_parent, old_parent);
3fa2252b
SB
1769 }
1770
d6968fca 1771 trace_clk_set_rate(core, core->new_rate);
dfc202ea 1772
d6968fca
SB
1773 if (!skip_set_rate && core->ops->set_rate)
1774 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
b2476490 1775
d6968fca 1776 trace_clk_set_rate_complete(core, core->new_rate);
dfc202ea 1777
d6968fca 1778 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1779
d6968fca
SB
1780 if (core->notifier_count && old_rate != core->rate)
1781 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1782
067bb174
TK
1783 /*
1784 * Use safe iteration, as change_rate can actually swap parents
1785 * for certain clock types.
1786 */
d6968fca 1787 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
71472c0c 1788 /* Skip children who will be reparented to another clock */
d6968fca 1789 if (child->new_parent && child->new_parent != core)
71472c0c 1790 continue;
b2476490 1791 clk_change_rate(child);
71472c0c
JH
1792 }
1793
d6968fca
SB
1794 /* handle the new child who might not be in core->children yet */
1795 if (core->new_child)
1796 clk_change_rate(core->new_child);
b2476490
MT
1797}
1798
d6968fca 1799static int clk_core_set_rate_nolock(struct clk_core *core,
1c8e6004
TV
1800 unsigned long req_rate)
1801{
1802 struct clk_core *top, *fail_clk;
1803 unsigned long rate = req_rate;
1804 int ret = 0;
1805
d6968fca 1806 if (!core)
1c8e6004
TV
1807 return 0;
1808
1809 /* bail early if nothing to do */
d6968fca 1810 if (rate == clk_core_get_rate_nolock(core))
1c8e6004
TV
1811 return 0;
1812
d6968fca 1813 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1c8e6004
TV
1814 return -EBUSY;
1815
1816 /* calculate new rates and get the topmost changed clock */
d6968fca 1817 top = clk_calc_new_rates(core, rate);
1c8e6004
TV
1818 if (!top)
1819 return -EINVAL;
1820
1821 /* notify that we are about to change rates */
1822 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1823 if (fail_clk) {
1824 pr_debug("%s: failed to set %s rate\n", __func__,
1825 fail_clk->name);
1826 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1827 return -EBUSY;
1828 }
1829
1830 /* change the rates */
1831 clk_change_rate(top);
1832
d6968fca 1833 core->req_rate = req_rate;
1c8e6004
TV
1834
1835 return ret;
1836}
1837
b2476490
MT
1838/**
1839 * clk_set_rate - specify a new rate for clk
1840 * @clk: the clk whose rate is being changed
1841 * @rate: the new rate for clk
1842 *
5654dc94 1843 * In the simplest case clk_set_rate will only adjust the rate of clk.
b2476490 1844 *
5654dc94
MT
1845 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1846 * propagate up to clk's parent; whether or not this happens depends on the
1847 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1848 * after calling .round_rate then upstream parent propagation is ignored. If
1849 * *parent_rate comes back with a new rate for clk's parent then we propagate
24ee1a08 1850 * up to clk's parent and set its rate. Upward propagation will continue
5654dc94
MT
1851 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1852 * .round_rate stops requesting changes to clk's parent_rate.
b2476490 1853 *
5654dc94
MT
1854 * Rate changes are accomplished via tree traversal that also recalculates the
1855 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
b2476490
MT
1856 *
1857 * Returns 0 on success, -EERROR otherwise.
1858 */
1859int clk_set_rate(struct clk *clk, unsigned long rate)
1860{
1c8e6004 1861 int ret;
b2476490 1862
89ac8d7a
MT
1863 if (!clk)
1864 return 0;
1865
b2476490 1866 /* prevent racing with updates to the clock topology */
eab89f69 1867 clk_prepare_lock();
b2476490 1868
1c8e6004 1869 ret = clk_core_set_rate_nolock(clk->core, rate);
b2476490 1870
1c8e6004 1871 clk_prepare_unlock();
0e1c0301 1872
1c8e6004
TV
1873 return ret;
1874}
1875EXPORT_SYMBOL_GPL(clk_set_rate);
b2476490 1876
1c8e6004
TV
1877/**
1878 * clk_set_rate_range - set a rate range for a clock source
1879 * @clk: clock source
1880 * @min: desired minimum clock rate in Hz, inclusive
1881 * @max: desired maximum clock rate in Hz, inclusive
1882 *
1883 * Returns success (0) or negative errno.
1884 */
1885int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
1886{
1887 int ret = 0;
1888
1889 if (!clk)
1890 return 0;
1891
1892 if (min > max) {
1893 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1894 __func__, clk->core->name, clk->dev_id, clk->con_id,
1895 min, max);
1896 return -EINVAL;
b2476490
MT
1897 }
1898
1c8e6004
TV
1899 clk_prepare_lock();
1900
1901 if (min != clk->min_rate || max != clk->max_rate) {
1902 clk->min_rate = min;
1903 clk->max_rate = max;
1904 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
1905 }
b2476490 1906
eab89f69 1907 clk_prepare_unlock();
b2476490
MT
1908
1909 return ret;
1910}
1c8e6004
TV
1911EXPORT_SYMBOL_GPL(clk_set_rate_range);
1912
1913/**
1914 * clk_set_min_rate - set a minimum clock rate for a clock source
1915 * @clk: clock source
1916 * @rate: desired minimum clock rate in Hz, inclusive
1917 *
1918 * Returns success (0) or negative errno.
1919 */
1920int clk_set_min_rate(struct clk *clk, unsigned long rate)
1921{
1922 if (!clk)
1923 return 0;
1924
1925 return clk_set_rate_range(clk, rate, clk->max_rate);
1926}
1927EXPORT_SYMBOL_GPL(clk_set_min_rate);
1928
1929/**
1930 * clk_set_max_rate - set a maximum clock rate for a clock source
1931 * @clk: clock source
1932 * @rate: desired maximum clock rate in Hz, inclusive
1933 *
1934 * Returns success (0) or negative errno.
1935 */
1936int clk_set_max_rate(struct clk *clk, unsigned long rate)
1937{
1938 if (!clk)
1939 return 0;
1940
1941 return clk_set_rate_range(clk, clk->min_rate, rate);
1942}
1943EXPORT_SYMBOL_GPL(clk_set_max_rate);
b2476490
MT
1944
1945/**
1946 * clk_get_parent - return the parent of a clk
1947 * @clk: the clk whose parent gets returned
1948 *
1949 * Simply returns clk->parent. Returns NULL if clk is NULL.
1950 */
1951struct clk *clk_get_parent(struct clk *clk)
1952{
1953 struct clk *parent;
1954
eab89f69 1955 clk_prepare_lock();
b2476490 1956 parent = __clk_get_parent(clk);
eab89f69 1957 clk_prepare_unlock();
b2476490
MT
1958
1959 return parent;
1960}
1961EXPORT_SYMBOL_GPL(clk_get_parent);
1962
1963/*
1964 * .get_parent is mandatory for clocks with multiple possible parents. It is
1965 * optional for single-parent clocks. Always call .get_parent if it is
1966 * available and WARN if it is missing for multi-parent clocks.
1967 *
1968 * For single-parent clocks without .get_parent, first check to see if the
1969 * .parents array exists, and if so use it to avoid an expensive tree
035a61c3 1970 * traversal. If .parents does not exist then walk the tree.
b2476490 1971 */
d6968fca 1972static struct clk_core *__clk_init_parent(struct clk_core *core)
b2476490 1973{
035a61c3 1974 struct clk_core *ret = NULL;
b2476490
MT
1975 u8 index;
1976
1977 /* handle the trivial cases */
1978
d6968fca 1979 if (!core->num_parents)
b2476490
MT
1980 goto out;
1981
d6968fca
SB
1982 if (core->num_parents == 1) {
1983 if (IS_ERR_OR_NULL(core->parent))
1984 core->parent = clk_core_lookup(core->parent_names[0]);
1985 ret = core->parent;
b2476490
MT
1986 goto out;
1987 }
1988
d6968fca
SB
1989 if (!core->ops->get_parent) {
1990 WARN(!core->ops->get_parent,
b2476490
MT
1991 "%s: multi-parent clocks must implement .get_parent\n",
1992 __func__);
1993 goto out;
1994 };
1995
1996 /*
d6968fca
SB
1997 * Do our best to cache parent clocks in core->parents. This prevents
1998 * unnecessary and expensive lookups. We don't set core->parent here;
035a61c3 1999 * that is done by the calling function.
b2476490
MT
2000 */
2001
d6968fca 2002 index = core->ops->get_parent(core->hw);
b2476490 2003
d6968fca
SB
2004 if (!core->parents)
2005 core->parents =
2006 kcalloc(core->num_parents, sizeof(struct clk *),
b2476490
MT
2007 GFP_KERNEL);
2008
d6968fca 2009 ret = clk_core_get_parent_by_index(core, index);
b2476490
MT
2010
2011out:
2012 return ret;
2013}
2014
d6968fca 2015static void clk_core_reparent(struct clk_core *core,
035a61c3 2016 struct clk_core *new_parent)
b33d212f 2017{
d6968fca
SB
2018 clk_reparent(core, new_parent);
2019 __clk_recalc_accuracies(core);
2020 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
2021}
2022
b2476490 2023/**
4e88f3de
TR
2024 * clk_has_parent - check if a clock is a possible parent for another
2025 * @clk: clock source
2026 * @parent: parent clock source
b2476490 2027 *
4e88f3de
TR
2028 * This function can be used in drivers that need to check that a clock can be
2029 * the parent of another without actually changing the parent.
f8aa0bd5 2030 *
4e88f3de 2031 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 2032 */
4e88f3de
TR
2033bool clk_has_parent(struct clk *clk, struct clk *parent)
2034{
035a61c3 2035 struct clk_core *core, *parent_core;
4e88f3de
TR
2036 unsigned int i;
2037
2038 /* NULL clocks should be nops, so return success if either is NULL. */
2039 if (!clk || !parent)
2040 return true;
2041
035a61c3
TV
2042 core = clk->core;
2043 parent_core = parent->core;
2044
4e88f3de 2045 /* Optimize for the case where the parent is already the parent. */
035a61c3 2046 if (core->parent == parent_core)
4e88f3de
TR
2047 return true;
2048
035a61c3
TV
2049 for (i = 0; i < core->num_parents; i++)
2050 if (strcmp(core->parent_names[i], parent_core->name) == 0)
4e88f3de
TR
2051 return true;
2052
2053 return false;
2054}
2055EXPORT_SYMBOL_GPL(clk_has_parent);
2056
d6968fca 2057static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
b2476490
MT
2058{
2059 int ret = 0;
f1c8b2ed 2060 int p_index = 0;
031dcc9b 2061 unsigned long p_rate = 0;
b2476490 2062
d6968fca 2063 if (!core)
89ac8d7a
MT
2064 return 0;
2065
b2476490 2066 /* prevent racing with updates to the clock topology */
eab89f69 2067 clk_prepare_lock();
b2476490 2068
d6968fca 2069 if (core->parent == parent)
b2476490
MT
2070 goto out;
2071
b61c43c0 2072 /* verify ops for for multi-parent clks */
d6968fca 2073 if ((core->num_parents > 1) && (!core->ops->set_parent)) {
b61c43c0
SB
2074 ret = -ENOSYS;
2075 goto out;
2076 }
2077
031dcc9b 2078 /* check that we are allowed to re-parent if the clock is in use */
d6968fca 2079 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
031dcc9b
UH
2080 ret = -EBUSY;
2081 goto out;
2082 }
2083
2084 /* try finding the new parent index */
2085 if (parent) {
d6968fca 2086 p_index = clk_fetch_parent_index(core, parent);
031dcc9b 2087 p_rate = parent->rate;
f1c8b2ed 2088 if (p_index < 0) {
031dcc9b 2089 pr_debug("%s: clk %s can not be parent of clk %s\n",
d6968fca 2090 __func__, parent->name, core->name);
f1c8b2ed 2091 ret = p_index;
031dcc9b
UH
2092 goto out;
2093 }
2094 }
2095
b2476490 2096 /* propagate PRE_RATE_CHANGE notifications */
d6968fca 2097 ret = __clk_speculate_rates(core, p_rate);
b2476490
MT
2098
2099 /* abort if a driver objects */
fb72a059 2100 if (ret & NOTIFY_STOP_MASK)
b2476490
MT
2101 goto out;
2102
031dcc9b 2103 /* do the re-parent */
d6968fca 2104 ret = __clk_set_parent(core, parent, p_index);
b2476490 2105
5279fc40
BB
2106 /* propagate rate an accuracy recalculation accordingly */
2107 if (ret) {
d6968fca 2108 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
5279fc40 2109 } else {
d6968fca
SB
2110 __clk_recalc_rates(core, POST_RATE_CHANGE);
2111 __clk_recalc_accuracies(core);
5279fc40 2112 }
b2476490
MT
2113
2114out:
eab89f69 2115 clk_prepare_unlock();
b2476490
MT
2116
2117 return ret;
2118}
035a61c3
TV
2119
2120/**
2121 * clk_set_parent - switch the parent of a mux clk
2122 * @clk: the mux clk whose input we are switching
2123 * @parent: the new input to clk
2124 *
2125 * Re-parent clk to use parent as its new input source. If clk is in
2126 * prepared state, the clk will get enabled for the duration of this call. If
2127 * that's not acceptable for a specific clk (Eg: the consumer can't handle
2128 * that, the reparenting is glitchy in hardware, etc), use the
2129 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
2130 *
2131 * After successfully changing clk's parent clk_set_parent will update the
2132 * clk topology, sysfs topology and propagate rate recalculation via
2133 * __clk_recalc_rates.
2134 *
2135 * Returns 0 on success, -EERROR otherwise.
2136 */
2137int clk_set_parent(struct clk *clk, struct clk *parent)
2138{
2139 if (!clk)
2140 return 0;
2141
2142 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
2143}
b2476490
MT
2144EXPORT_SYMBOL_GPL(clk_set_parent);
2145
e59c5371
MT
2146/**
2147 * clk_set_phase - adjust the phase shift of a clock signal
2148 * @clk: clock signal source
2149 * @degrees: number of degrees the signal is shifted
2150 *
2151 * Shifts the phase of a clock signal by the specified
2152 * degrees. Returns 0 on success, -EERROR otherwise.
2153 *
2154 * This function makes no distinction about the input or reference
2155 * signal that we adjust the clock signal phase against. For example
2156 * phase locked-loop clock signal generators we may shift phase with
2157 * respect to feedback clock signal input, but for other cases the
2158 * clock phase may be shifted with respect to some other, unspecified
2159 * signal.
2160 *
2161 * Additionally the concept of phase shift does not propagate through
2162 * the clock tree hierarchy, which sets it apart from clock rates and
2163 * clock accuracy. A parent clock phase attribute does not have an
2164 * impact on the phase attribute of a child clock.
2165 */
2166int clk_set_phase(struct clk *clk, int degrees)
2167{
08b95756 2168 int ret = -EINVAL;
e59c5371
MT
2169
2170 if (!clk)
08b95756 2171 return 0;
e59c5371
MT
2172
2173 /* sanity check degrees */
2174 degrees %= 360;
2175 if (degrees < 0)
2176 degrees += 360;
2177
2178 clk_prepare_lock();
2179
dfc202ea
SB
2180 trace_clk_set_phase(clk->core, degrees);
2181
08b95756
SB
2182 if (clk->core->ops->set_phase)
2183 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
e59c5371 2184
dfc202ea
SB
2185 trace_clk_set_phase_complete(clk->core, degrees);
2186
e59c5371 2187 if (!ret)
035a61c3 2188 clk->core->phase = degrees;
e59c5371 2189
e59c5371
MT
2190 clk_prepare_unlock();
2191
e59c5371
MT
2192 return ret;
2193}
9767b04f 2194EXPORT_SYMBOL_GPL(clk_set_phase);
e59c5371 2195
d6968fca 2196static int clk_core_get_phase(struct clk_core *core)
e59c5371
MT
2197{
2198 int ret = 0;
2199
d6968fca 2200 if (!core)
e59c5371
MT
2201 goto out;
2202
2203 clk_prepare_lock();
d6968fca 2204 ret = core->phase;
e59c5371
MT
2205 clk_prepare_unlock();
2206
2207out:
2208 return ret;
2209}
9767b04f 2210EXPORT_SYMBOL_GPL(clk_get_phase);
e59c5371 2211
035a61c3
TV
2212/**
2213 * clk_get_phase - return the phase shift of a clock signal
2214 * @clk: clock signal source
2215 *
2216 * Returns the phase shift of a clock node in degrees, otherwise returns
2217 * -EERROR.
2218 */
2219int clk_get_phase(struct clk *clk)
2220{
2221 if (!clk)
2222 return 0;
2223
2224 return clk_core_get_phase(clk->core);
2225}
e59c5371 2226
3d3801ef
MT
2227/**
2228 * clk_is_match - check if two clk's point to the same hardware clock
2229 * @p: clk compared against q
2230 * @q: clk compared against p
2231 *
2232 * Returns true if the two struct clk pointers both point to the same hardware
2233 * clock node. Put differently, returns true if struct clk *p and struct clk *q
2234 * share the same struct clk_core object.
2235 *
2236 * Returns false otherwise. Note that two NULL clks are treated as matching.
2237 */
2238bool clk_is_match(const struct clk *p, const struct clk *q)
2239{
2240 /* trivial case: identical struct clk's or both NULL */
2241 if (p == q)
2242 return true;
2243
2244 /* true if clk->core pointers match. Avoid derefing garbage */
2245 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
2246 if (p->core == q->core)
2247 return true;
2248
2249 return false;
2250}
2251EXPORT_SYMBOL_GPL(clk_is_match);
2252
b2476490
MT
2253/**
2254 * __clk_init - initialize the data structures in a struct clk
2255 * @dev: device initializing this clk, placeholder for now
2256 * @clk: clk being initialized
2257 *
035a61c3 2258 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2259 * parent and rate and sets them both.
b2476490 2260 */
b09d6d99 2261static int __clk_init(struct device *dev, struct clk *clk_user)
b2476490 2262{
d1302a36 2263 int i, ret = 0;
035a61c3 2264 struct clk_core *orphan;
b67bfe0d 2265 struct hlist_node *tmp2;
d6968fca 2266 struct clk_core *core;
1c8e6004 2267 unsigned long rate;
b2476490 2268
035a61c3 2269 if (!clk_user)
d1302a36 2270 return -EINVAL;
b2476490 2271
d6968fca 2272 core = clk_user->core;
035a61c3 2273
eab89f69 2274 clk_prepare_lock();
b2476490
MT
2275
2276 /* check to see if a clock with this name is already registered */
d6968fca 2277 if (clk_core_lookup(core->name)) {
d1302a36 2278 pr_debug("%s: clk %s already initialized\n",
d6968fca 2279 __func__, core->name);
d1302a36 2280 ret = -EEXIST;
b2476490 2281 goto out;
d1302a36 2282 }
b2476490 2283
d4d7e3dd 2284 /* check that clk_ops are sane. See Documentation/clk.txt */
d6968fca
SB
2285 if (core->ops->set_rate &&
2286 !((core->ops->round_rate || core->ops->determine_rate) &&
2287 core->ops->recalc_rate)) {
71472c0c 2288 pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
d6968fca 2289 __func__, core->name);
d1302a36 2290 ret = -EINVAL;
d4d7e3dd
MT
2291 goto out;
2292 }
2293
d6968fca 2294 if (core->ops->set_parent && !core->ops->get_parent) {
d4d7e3dd 2295 pr_warning("%s: %s must implement .get_parent & .set_parent\n",
d6968fca 2296 __func__, core->name);
d1302a36 2297 ret = -EINVAL;
d4d7e3dd
MT
2298 goto out;
2299 }
2300
d6968fca
SB
2301 if (core->ops->set_rate_and_parent &&
2302 !(core->ops->set_parent && core->ops->set_rate)) {
3fa2252b 2303 pr_warn("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 2304 __func__, core->name);
3fa2252b
SB
2305 ret = -EINVAL;
2306 goto out;
2307 }
2308
b2476490 2309 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
2310 for (i = 0; i < core->num_parents; i++)
2311 WARN(!core->parent_names[i],
b2476490 2312 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 2313 __func__, core->name);
b2476490
MT
2314
2315 /*
2316 * Allocate an array of struct clk *'s to avoid unnecessary string
2317 * look-ups of clk's possible parents. This can fail for clocks passed
d6968fca 2318 * in to clk_init during early boot; thus any access to core->parents[]
b2476490
MT
2319 * must always check for a NULL pointer and try to populate it if
2320 * necessary.
2321 *
d6968fca
SB
2322 * If core->parents is not NULL we skip this entire block. This allows
2323 * for clock drivers to statically initialize core->parents.
b2476490 2324 */
d6968fca
SB
2325 if (core->num_parents > 1 && !core->parents) {
2326 core->parents = kcalloc(core->num_parents, sizeof(struct clk *),
96a7ed90 2327 GFP_KERNEL);
b2476490 2328 /*
035a61c3 2329 * clk_core_lookup returns NULL for parents that have not been
b2476490
MT
2330 * clk_init'd; thus any access to clk->parents[] must check
2331 * for a NULL pointer. We can always perform lazy lookups for
2332 * missing parents later on.
2333 */
d6968fca
SB
2334 if (core->parents)
2335 for (i = 0; i < core->num_parents; i++)
2336 core->parents[i] =
2337 clk_core_lookup(core->parent_names[i]);
b2476490
MT
2338 }
2339
d6968fca 2340 core->parent = __clk_init_parent(core);
b2476490
MT
2341
2342 /*
d6968fca 2343 * Populate core->parent if parent has already been __clk_init'd. If
b2476490
MT
2344 * parent has not yet been __clk_init'd then place clk in the orphan
2345 * list. If clk has set the CLK_IS_ROOT flag then place it in the root
2346 * clk list.
2347 *
2348 * Every time a new clk is clk_init'd then we walk the list of orphan
2349 * clocks and re-parent any that are children of the clock currently
2350 * being clk_init'd.
2351 */
d6968fca
SB
2352 if (core->parent)
2353 hlist_add_head(&core->child_node,
2354 &core->parent->children);
2355 else if (core->flags & CLK_IS_ROOT)
2356 hlist_add_head(&core->child_node, &clk_root_list);
b2476490 2357 else
d6968fca 2358 hlist_add_head(&core->child_node, &clk_orphan_list);
b2476490 2359
5279fc40
BB
2360 /*
2361 * Set clk's accuracy. The preferred method is to use
2362 * .recalc_accuracy. For simple clocks and lazy developers the default
2363 * fallback is to use the parent's accuracy. If a clock doesn't have a
2364 * parent (or is orphaned) then accuracy is set to zero (perfect
2365 * clock).
2366 */
d6968fca
SB
2367 if (core->ops->recalc_accuracy)
2368 core->accuracy = core->ops->recalc_accuracy(core->hw,
2369 __clk_get_accuracy(core->parent));
2370 else if (core->parent)
2371 core->accuracy = core->parent->accuracy;
5279fc40 2372 else
d6968fca 2373 core->accuracy = 0;
5279fc40 2374
9824cf73
MR
2375 /*
2376 * Set clk's phase.
2377 * Since a phase is by definition relative to its parent, just
2378 * query the current clock phase, or just assume it's in phase.
2379 */
d6968fca
SB
2380 if (core->ops->get_phase)
2381 core->phase = core->ops->get_phase(core->hw);
9824cf73 2382 else
d6968fca 2383 core->phase = 0;
9824cf73 2384
b2476490
MT
2385 /*
2386 * Set clk's rate. The preferred method is to use .recalc_rate. For
2387 * simple clocks and lazy developers the default fallback is to use the
2388 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2389 * then rate is set to zero.
2390 */
d6968fca
SB
2391 if (core->ops->recalc_rate)
2392 rate = core->ops->recalc_rate(core->hw,
2393 clk_core_get_rate_nolock(core->parent));
2394 else if (core->parent)
2395 rate = core->parent->rate;
b2476490 2396 else
1c8e6004 2397 rate = 0;
d6968fca 2398 core->rate = core->req_rate = rate;
b2476490
MT
2399
2400 /*
2401 * walk the list of orphan clocks and reparent any that are children of
2402 * this clock
2403 */
b67bfe0d 2404 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
12d29886 2405 if (orphan->num_parents && orphan->ops->get_parent) {
1f61e5f1 2406 i = orphan->ops->get_parent(orphan->hw);
d6968fca
SB
2407 if (!strcmp(core->name, orphan->parent_names[i]))
2408 clk_core_reparent(orphan, core);
1f61e5f1
MF
2409 continue;
2410 }
2411
b2476490 2412 for (i = 0; i < orphan->num_parents; i++)
d6968fca
SB
2413 if (!strcmp(core->name, orphan->parent_names[i])) {
2414 clk_core_reparent(orphan, core);
b2476490
MT
2415 break;
2416 }
1f61e5f1 2417 }
b2476490
MT
2418
2419 /*
2420 * optional platform-specific magic
2421 *
2422 * The .init callback is not used by any of the basic clock types, but
2423 * exists for weird hardware that must perform initialization magic.
2424 * Please consider other ways of solving initialization problems before
24ee1a08 2425 * using this callback, as its use is discouraged.
b2476490 2426 */
d6968fca
SB
2427 if (core->ops->init)
2428 core->ops->init(core->hw);
b2476490 2429
d6968fca 2430 kref_init(&core->ref);
b2476490 2431out:
eab89f69 2432 clk_prepare_unlock();
b2476490 2433
89f7e9de 2434 if (!ret)
d6968fca 2435 clk_debug_register(core);
89f7e9de 2436
d1302a36 2437 return ret;
b2476490
MT
2438}
2439
035a61c3
TV
2440struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2441 const char *con_id)
0197b3ea 2442{
0197b3ea
SK
2443 struct clk *clk;
2444
035a61c3
TV
2445 /* This is to allow this function to be chained to others */
2446 if (!hw || IS_ERR(hw))
2447 return (struct clk *) hw;
0197b3ea 2448
035a61c3
TV
2449 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2450 if (!clk)
2451 return ERR_PTR(-ENOMEM);
2452
2453 clk->core = hw->core;
2454 clk->dev_id = dev_id;
2455 clk->con_id = con_id;
1c8e6004
TV
2456 clk->max_rate = ULONG_MAX;
2457
2458 clk_prepare_lock();
50595f8b 2459 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2460 clk_prepare_unlock();
0197b3ea
SK
2461
2462 return clk;
2463}
035a61c3 2464
73e0e496 2465void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2466{
2467 clk_prepare_lock();
50595f8b 2468 hlist_del(&clk->clks_node);
1c8e6004
TV
2469 clk_prepare_unlock();
2470
2471 kfree(clk);
2472}
0197b3ea 2473
293ba3b4
SB
2474/**
2475 * clk_register - allocate a new clock, register it and return an opaque cookie
2476 * @dev: device that is registering this clock
2477 * @hw: link to hardware-specific clock data
2478 *
2479 * clk_register is the primary interface for populating the clock tree with new
2480 * clock nodes. It returns a pointer to the newly allocated struct clk which
2481 * cannot be dereferenced by driver code but may be used in conjuction with the
2482 * rest of the clock API. In the event of an error clk_register will return an
2483 * error code; drivers must test for an error code after calling clk_register.
2484 */
2485struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2486{
d1302a36 2487 int i, ret;
d6968fca 2488 struct clk_core *core;
293ba3b4 2489
d6968fca
SB
2490 core = kzalloc(sizeof(*core), GFP_KERNEL);
2491 if (!core) {
293ba3b4
SB
2492 pr_err("%s: could not allocate clk\n", __func__);
2493 ret = -ENOMEM;
2494 goto fail_out;
2495 }
b2476490 2496
d6968fca
SB
2497 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
2498 if (!core->name) {
0197b3ea
SK
2499 pr_err("%s: could not allocate clk->name\n", __func__);
2500 ret = -ENOMEM;
2501 goto fail_name;
2502 }
d6968fca 2503 core->ops = hw->init->ops;
ac2df527 2504 if (dev && dev->driver)
d6968fca
SB
2505 core->owner = dev->driver->owner;
2506 core->hw = hw;
2507 core->flags = hw->init->flags;
2508 core->num_parents = hw->init->num_parents;
2509 hw->core = core;
b2476490 2510
d1302a36 2511 /* allocate local copy in case parent_names is __initdata */
d6968fca 2512 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 2513 GFP_KERNEL);
d1302a36 2514
d6968fca 2515 if (!core->parent_names) {
d1302a36
MT
2516 pr_err("%s: could not allocate clk->parent_names\n", __func__);
2517 ret = -ENOMEM;
2518 goto fail_parent_names;
2519 }
2520
2521
2522 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
2523 for (i = 0; i < core->num_parents; i++) {
2524 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2525 GFP_KERNEL);
d6968fca 2526 if (!core->parent_names[i]) {
d1302a36
MT
2527 pr_err("%s: could not copy parent_names\n", __func__);
2528 ret = -ENOMEM;
2529 goto fail_parent_names_copy;
2530 }
2531 }
2532
d6968fca 2533 INIT_HLIST_HEAD(&core->clks);
1c8e6004 2534
035a61c3
TV
2535 hw->clk = __clk_create_clk(hw, NULL, NULL);
2536 if (IS_ERR(hw->clk)) {
2537 pr_err("%s: could not allocate per-user clk\n", __func__);
2538 ret = PTR_ERR(hw->clk);
2539 goto fail_parent_names_copy;
2540 }
2541
2542 ret = __clk_init(dev, hw->clk);
d1302a36 2543 if (!ret)
035a61c3 2544 return hw->clk;
b2476490 2545
1c8e6004 2546 __clk_free_clk(hw->clk);
035a61c3 2547 hw->clk = NULL;
b2476490 2548
d1302a36
MT
2549fail_parent_names_copy:
2550 while (--i >= 0)
d6968fca
SB
2551 kfree_const(core->parent_names[i]);
2552 kfree(core->parent_names);
d1302a36 2553fail_parent_names:
d6968fca 2554 kfree_const(core->name);
0197b3ea 2555fail_name:
d6968fca 2556 kfree(core);
d1302a36
MT
2557fail_out:
2558 return ERR_PTR(ret);
b2476490
MT
2559}
2560EXPORT_SYMBOL_GPL(clk_register);
2561
fcb0ee6a
SN
2562/*
2563 * Free memory allocated for a clock.
2564 * Caller must hold prepare_lock.
2565 */
2566static void __clk_release(struct kref *ref)
2567{
d6968fca
SB
2568 struct clk_core *core = container_of(ref, struct clk_core, ref);
2569 int i = core->num_parents;
fcb0ee6a 2570
496eadf8
KK
2571 lockdep_assert_held(&prepare_lock);
2572
d6968fca 2573 kfree(core->parents);
fcb0ee6a 2574 while (--i >= 0)
d6968fca 2575 kfree_const(core->parent_names[i]);
fcb0ee6a 2576
d6968fca
SB
2577 kfree(core->parent_names);
2578 kfree_const(core->name);
2579 kfree(core);
fcb0ee6a
SN
2580}
2581
2582/*
2583 * Empty clk_ops for unregistered clocks. These are used temporarily
2584 * after clk_unregister() was called on a clock and until last clock
2585 * consumer calls clk_put() and the struct clk object is freed.
2586 */
2587static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2588{
2589 return -ENXIO;
2590}
2591
2592static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2593{
2594 WARN_ON_ONCE(1);
2595}
2596
2597static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2598 unsigned long parent_rate)
2599{
2600 return -ENXIO;
2601}
2602
2603static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2604{
2605 return -ENXIO;
2606}
2607
2608static const struct clk_ops clk_nodrv_ops = {
2609 .enable = clk_nodrv_prepare_enable,
2610 .disable = clk_nodrv_disable_unprepare,
2611 .prepare = clk_nodrv_prepare_enable,
2612 .unprepare = clk_nodrv_disable_unprepare,
2613 .set_rate = clk_nodrv_set_rate,
2614 .set_parent = clk_nodrv_set_parent,
2615};
2616
1df5c939
MB
2617/**
2618 * clk_unregister - unregister a currently registered clock
2619 * @clk: clock to unregister
1df5c939 2620 */
fcb0ee6a
SN
2621void clk_unregister(struct clk *clk)
2622{
2623 unsigned long flags;
2624
6314b679
SB
2625 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2626 return;
2627
035a61c3 2628 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2629
2630 clk_prepare_lock();
2631
035a61c3
TV
2632 if (clk->core->ops == &clk_nodrv_ops) {
2633 pr_err("%s: unregistered clock: %s\n", __func__,
2634 clk->core->name);
6314b679 2635 return;
fcb0ee6a
SN
2636 }
2637 /*
2638 * Assign empty clock ops for consumers that might still hold
2639 * a reference to this clock.
2640 */
2641 flags = clk_enable_lock();
035a61c3 2642 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2643 clk_enable_unlock(flags);
2644
035a61c3
TV
2645 if (!hlist_empty(&clk->core->children)) {
2646 struct clk_core *child;
874f224c 2647 struct hlist_node *t;
fcb0ee6a
SN
2648
2649 /* Reparent all children to the orphan list. */
035a61c3
TV
2650 hlist_for_each_entry_safe(child, t, &clk->core->children,
2651 child_node)
2652 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2653 }
2654
035a61c3 2655 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2656
035a61c3 2657 if (clk->core->prepare_count)
fcb0ee6a 2658 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2659 __func__, clk->core->name);
2660 kref_put(&clk->core->ref, __clk_release);
6314b679 2661
fcb0ee6a
SN
2662 clk_prepare_unlock();
2663}
1df5c939
MB
2664EXPORT_SYMBOL_GPL(clk_unregister);
2665
46c8773a
SB
2666static void devm_clk_release(struct device *dev, void *res)
2667{
293ba3b4 2668 clk_unregister(*(struct clk **)res);
46c8773a
SB
2669}
2670
2671/**
2672 * devm_clk_register - resource managed clk_register()
2673 * @dev: device that is registering this clock
2674 * @hw: link to hardware-specific clock data
2675 *
2676 * Managed clk_register(). Clocks returned from this function are
2677 * automatically clk_unregister()ed on driver detach. See clk_register() for
2678 * more information.
2679 */
2680struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2681{
2682 struct clk *clk;
293ba3b4 2683 struct clk **clkp;
46c8773a 2684
293ba3b4
SB
2685 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2686 if (!clkp)
46c8773a
SB
2687 return ERR_PTR(-ENOMEM);
2688
293ba3b4
SB
2689 clk = clk_register(dev, hw);
2690 if (!IS_ERR(clk)) {
2691 *clkp = clk;
2692 devres_add(dev, clkp);
46c8773a 2693 } else {
293ba3b4 2694 devres_free(clkp);
46c8773a
SB
2695 }
2696
2697 return clk;
2698}
2699EXPORT_SYMBOL_GPL(devm_clk_register);
2700
2701static int devm_clk_match(struct device *dev, void *res, void *data)
2702{
2703 struct clk *c = res;
2704 if (WARN_ON(!c))
2705 return 0;
2706 return c == data;
2707}
2708
2709/**
2710 * devm_clk_unregister - resource managed clk_unregister()
2711 * @clk: clock to unregister
2712 *
2713 * Deallocate a clock allocated with devm_clk_register(). Normally
2714 * this function will not need to be called and the resource management
2715 * code will ensure that the resource is freed.
2716 */
2717void devm_clk_unregister(struct device *dev, struct clk *clk)
2718{
2719 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2720}
2721EXPORT_SYMBOL_GPL(devm_clk_unregister);
2722
ac2df527
SN
2723/*
2724 * clkdev helpers
2725 */
2726int __clk_get(struct clk *clk)
2727{
035a61c3
TV
2728 struct clk_core *core = !clk ? NULL : clk->core;
2729
2730 if (core) {
2731 if (!try_module_get(core->owner))
00efcb1c 2732 return 0;
ac2df527 2733
035a61c3 2734 kref_get(&core->ref);
00efcb1c 2735 }
ac2df527
SN
2736 return 1;
2737}
2738
2739void __clk_put(struct clk *clk)
2740{
10cdfe54
TV
2741 struct module *owner;
2742
00efcb1c 2743 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2744 return;
2745
fcb0ee6a 2746 clk_prepare_lock();
1c8e6004 2747
50595f8b 2748 hlist_del(&clk->clks_node);
ec02ace8
TV
2749 if (clk->min_rate > clk->core->req_rate ||
2750 clk->max_rate < clk->core->req_rate)
2751 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2752
1c8e6004
TV
2753 owner = clk->core->owner;
2754 kref_put(&clk->core->ref, __clk_release);
2755
fcb0ee6a
SN
2756 clk_prepare_unlock();
2757
10cdfe54 2758 module_put(owner);
035a61c3 2759
035a61c3 2760 kfree(clk);
ac2df527
SN
2761}
2762
b2476490
MT
2763/*** clk rate change notifiers ***/
2764
2765/**
2766 * clk_notifier_register - add a clk rate change notifier
2767 * @clk: struct clk * to watch
2768 * @nb: struct notifier_block * with callback info
2769 *
2770 * Request notification when clk's rate changes. This uses an SRCU
2771 * notifier because we want it to block and notifier unregistrations are
2772 * uncommon. The callbacks associated with the notifier must not
2773 * re-enter into the clk framework by calling any top-level clk APIs;
2774 * this will cause a nested prepare_lock mutex.
2775 *
5324fda7
SB
2776 * In all notification cases cases (pre, post and abort rate change) the
2777 * original clock rate is passed to the callback via struct
2778 * clk_notifier_data.old_rate and the new frequency is passed via struct
b2476490
MT
2779 * clk_notifier_data.new_rate.
2780 *
b2476490
MT
2781 * clk_notifier_register() must be called from non-atomic context.
2782 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2783 * allocation failure; otherwise, passes along the return value of
2784 * srcu_notifier_chain_register().
2785 */
2786int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2787{
2788 struct clk_notifier *cn;
2789 int ret = -ENOMEM;
2790
2791 if (!clk || !nb)
2792 return -EINVAL;
2793
eab89f69 2794 clk_prepare_lock();
b2476490
MT
2795
2796 /* search the list of notifiers for this clk */
2797 list_for_each_entry(cn, &clk_notifier_list, node)
2798 if (cn->clk == clk)
2799 break;
2800
2801 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2802 if (cn->clk != clk) {
2803 cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2804 if (!cn)
2805 goto out;
2806
2807 cn->clk = clk;
2808 srcu_init_notifier_head(&cn->notifier_head);
2809
2810 list_add(&cn->node, &clk_notifier_list);
2811 }
2812
2813 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2814
035a61c3 2815 clk->core->notifier_count++;
b2476490
MT
2816
2817out:
eab89f69 2818 clk_prepare_unlock();
b2476490
MT
2819
2820 return ret;
2821}
2822EXPORT_SYMBOL_GPL(clk_notifier_register);
2823
2824/**
2825 * clk_notifier_unregister - remove a clk rate change notifier
2826 * @clk: struct clk *
2827 * @nb: struct notifier_block * with callback info
2828 *
2829 * Request no further notification for changes to 'clk' and frees memory
2830 * allocated in clk_notifier_register.
2831 *
2832 * Returns -EINVAL if called with null arguments; otherwise, passes
2833 * along the return value of srcu_notifier_chain_unregister().
2834 */
2835int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2836{
2837 struct clk_notifier *cn = NULL;
2838 int ret = -EINVAL;
2839
2840 if (!clk || !nb)
2841 return -EINVAL;
2842
eab89f69 2843 clk_prepare_lock();
b2476490
MT
2844
2845 list_for_each_entry(cn, &clk_notifier_list, node)
2846 if (cn->clk == clk)
2847 break;
2848
2849 if (cn->clk == clk) {
2850 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2851
035a61c3 2852 clk->core->notifier_count--;
b2476490
MT
2853
2854 /* XXX the notifier code should handle this better */
2855 if (!cn->notifier_head.head) {
2856 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 2857 list_del(&cn->node);
b2476490
MT
2858 kfree(cn);
2859 }
2860
2861 } else {
2862 ret = -ENOENT;
2863 }
2864
eab89f69 2865 clk_prepare_unlock();
b2476490
MT
2866
2867 return ret;
2868}
2869EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
2870
2871#ifdef CONFIG_OF
2872/**
2873 * struct of_clk_provider - Clock provider registration structure
2874 * @link: Entry in global list of clock providers
2875 * @node: Pointer to device tree node of clock provider
2876 * @get: Get clock callback. Returns NULL or a struct clk for the
2877 * given clock specifier
2878 * @data: context pointer to be passed into @get callback
2879 */
2880struct of_clk_provider {
2881 struct list_head link;
2882
2883 struct device_node *node;
2884 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
2885 void *data;
2886};
2887
f2f6c255
PG
2888static const struct of_device_id __clk_of_table_sentinel
2889 __used __section(__clk_of_table_end);
2890
766e6a4e 2891static LIST_HEAD(of_clk_providers);
d6782c26
SN
2892static DEFINE_MUTEX(of_clk_mutex);
2893
766e6a4e
GL
2894struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2895 void *data)
2896{
2897 return data;
2898}
2899EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
2900
494bfec9
SG
2901struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
2902{
2903 struct clk_onecell_data *clk_data = data;
2904 unsigned int idx = clkspec->args[0];
2905
2906 if (idx >= clk_data->clk_num) {
2907 pr_err("%s: invalid clock index %d\n", __func__, idx);
2908 return ERR_PTR(-EINVAL);
2909 }
2910
2911 return clk_data->clks[idx];
2912}
2913EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
2914
766e6a4e
GL
2915/**
2916 * of_clk_add_provider() - Register a clock provider for a node
2917 * @np: Device node pointer associated with clock provider
2918 * @clk_src_get: callback for decoding clock
2919 * @data: context pointer for @clk_src_get callback.
2920 */
2921int of_clk_add_provider(struct device_node *np,
2922 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
2923 void *data),
2924 void *data)
2925{
2926 struct of_clk_provider *cp;
86be408b 2927 int ret;
766e6a4e
GL
2928
2929 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
2930 if (!cp)
2931 return -ENOMEM;
2932
2933 cp->node = of_node_get(np);
2934 cp->data = data;
2935 cp->get = clk_src_get;
2936
d6782c26 2937 mutex_lock(&of_clk_mutex);
766e6a4e 2938 list_add(&cp->link, &of_clk_providers);
d6782c26 2939 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2940 pr_debug("Added clock from %s\n", np->full_name);
2941
86be408b
SN
2942 ret = of_clk_set_defaults(np, true);
2943 if (ret < 0)
2944 of_clk_del_provider(np);
2945
2946 return ret;
766e6a4e
GL
2947}
2948EXPORT_SYMBOL_GPL(of_clk_add_provider);
2949
2950/**
2951 * of_clk_del_provider() - Remove a previously registered clock provider
2952 * @np: Device node pointer associated with clock provider
2953 */
2954void of_clk_del_provider(struct device_node *np)
2955{
2956 struct of_clk_provider *cp;
2957
d6782c26 2958 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2959 list_for_each_entry(cp, &of_clk_providers, link) {
2960 if (cp->node == np) {
2961 list_del(&cp->link);
2962 of_node_put(cp->node);
2963 kfree(cp);
2964 break;
2965 }
2966 }
d6782c26 2967 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2968}
2969EXPORT_SYMBOL_GPL(of_clk_del_provider);
2970
73e0e496
SB
2971struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
2972 const char *dev_id, const char *con_id)
766e6a4e
GL
2973{
2974 struct of_clk_provider *provider;
a34cd466 2975 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
766e6a4e 2976
306c342f
SB
2977 if (!clkspec)
2978 return ERR_PTR(-EINVAL);
2979
766e6a4e 2980 /* Check if we have such a provider in our array */
306c342f 2981 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2982 list_for_each_entry(provider, &of_clk_providers, link) {
2983 if (provider->node == clkspec->np)
2984 clk = provider->get(clkspec, provider->data);
73e0e496
SB
2985 if (!IS_ERR(clk)) {
2986 clk = __clk_create_clk(__clk_get_hw(clk), dev_id,
2987 con_id);
2988
2989 if (!IS_ERR(clk) && !__clk_get(clk)) {
2990 __clk_free_clk(clk);
2991 clk = ERR_PTR(-ENOENT);
2992 }
2993
766e6a4e 2994 break;
73e0e496 2995 }
766e6a4e 2996 }
306c342f 2997 mutex_unlock(&of_clk_mutex);
d6782c26
SN
2998
2999 return clk;
3000}
3001
306c342f
SB
3002/**
3003 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3004 * @clkspec: pointer to a clock specifier data structure
3005 *
3006 * This function looks up a struct clk from the registered list of clock
3007 * providers, an input is a clock specifier data structure as returned
3008 * from the of_parse_phandle_with_args() function call.
3009 */
d6782c26
SN
3010struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
3011{
306c342f 3012 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e
GL
3013}
3014
f6102742
MT
3015int of_clk_get_parent_count(struct device_node *np)
3016{
3017 return of_count_phandle_with_args(np, "clocks", "#clock-cells");
3018}
3019EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
3020
766e6a4e
GL
3021const char *of_clk_get_parent_name(struct device_node *np, int index)
3022{
3023 struct of_phandle_args clkspec;
7a0fc1a3 3024 struct property *prop;
766e6a4e 3025 const char *clk_name;
7a0fc1a3
BD
3026 const __be32 *vp;
3027 u32 pv;
766e6a4e 3028 int rc;
7a0fc1a3 3029 int count;
766e6a4e
GL
3030
3031 if (index < 0)
3032 return NULL;
3033
3034 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3035 &clkspec);
3036 if (rc)
3037 return NULL;
3038
7a0fc1a3
BD
3039 index = clkspec.args_count ? clkspec.args[0] : 0;
3040 count = 0;
3041
3042 /* if there is an indices property, use it to transfer the index
3043 * specified into an array offset for the clock-output-names property.
3044 */
3045 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3046 if (index == pv) {
3047 index = count;
3048 break;
3049 }
3050 count++;
3051 }
3052
766e6a4e 3053 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3054 index,
766e6a4e
GL
3055 &clk_name) < 0)
3056 clk_name = clkspec.np->name;
3057
3058 of_node_put(clkspec.np);
3059 return clk_name;
3060}
3061EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3062
1771b10d
GC
3063struct clock_provider {
3064 of_clk_init_cb_t clk_init_cb;
3065 struct device_node *np;
3066 struct list_head node;
3067};
3068
3069static LIST_HEAD(clk_provider_list);
3070
3071/*
3072 * This function looks for a parent clock. If there is one, then it
3073 * checks that the provider for this parent clock was initialized, in
3074 * this case the parent clock will be ready.
3075 */
3076static int parent_ready(struct device_node *np)
3077{
3078 int i = 0;
3079
3080 while (true) {
3081 struct clk *clk = of_clk_get(np, i);
3082
3083 /* this parent is ready we can check the next one */
3084 if (!IS_ERR(clk)) {
3085 clk_put(clk);
3086 i++;
3087 continue;
3088 }
3089
3090 /* at least one parent is not ready, we exit now */
3091 if (PTR_ERR(clk) == -EPROBE_DEFER)
3092 return 0;
3093
3094 /*
3095 * Here we make assumption that the device tree is
3096 * written correctly. So an error means that there is
3097 * no more parent. As we didn't exit yet, then the
3098 * previous parent are ready. If there is no clock
3099 * parent, no need to wait for them, then we can
3100 * consider their absence as being ready
3101 */
3102 return 1;
3103 }
3104}
3105
766e6a4e
GL
3106/**
3107 * of_clk_init() - Scan and init clock providers from the DT
3108 * @matches: array of compatible values and init functions for providers.
3109 *
1771b10d 3110 * This function scans the device tree for matching clock providers
e5ca8fb4 3111 * and calls their initialization functions. It also does it by trying
1771b10d 3112 * to follow the dependencies.
766e6a4e
GL
3113 */
3114void __init of_clk_init(const struct of_device_id *matches)
3115{
7f7ed584 3116 const struct of_device_id *match;
766e6a4e 3117 struct device_node *np;
1771b10d
GC
3118 struct clock_provider *clk_provider, *next;
3119 bool is_init_done;
3120 bool force = false;
766e6a4e 3121
f2f6c255 3122 if (!matches)
819b4861 3123 matches = &__clk_of_table;
f2f6c255 3124
1771b10d 3125 /* First prepare the list of the clocks providers */
7f7ed584 3126 for_each_matching_node_and_match(np, matches, &match) {
1771b10d
GC
3127 struct clock_provider *parent =
3128 kzalloc(sizeof(struct clock_provider), GFP_KERNEL);
3129
3130 parent->clk_init_cb = match->data;
3131 parent->np = np;
3f6d439f 3132 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3133 }
3134
3135 while (!list_empty(&clk_provider_list)) {
3136 is_init_done = false;
3137 list_for_each_entry_safe(clk_provider, next,
3138 &clk_provider_list, node) {
3139 if (force || parent_ready(clk_provider->np)) {
86be408b 3140
1771b10d 3141 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3142 of_clk_set_defaults(clk_provider->np, true);
3143
1771b10d
GC
3144 list_del(&clk_provider->node);
3145 kfree(clk_provider);
3146 is_init_done = true;
3147 }
3148 }
3149
3150 /*
e5ca8fb4 3151 * We didn't manage to initialize any of the
1771b10d
GC
3152 * remaining providers during the last loop, so now we
3153 * initialize all the remaining ones unconditionally
3154 * in case the clock parent was not mandatory
3155 */
3156 if (!is_init_done)
3157 force = true;
766e6a4e
GL
3158 }
3159}
3160#endif
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