[deliverable/linux.git] / drivers / clk / h8300 / clk-h8s2678.c

/*
 * H8S2678 clock driver
 *
 * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
 */

#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/slab.h>

static DEFINE_SPINLOCK(clklock);

#define MAX_FREQ 33333333
#define MIN_FREQ  8000000

struct pll_clock {
	struct clk_hw hw;
	void __iomem *sckcr;
	void __iomem *pllcr;
};

#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)

static unsigned long pll_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct pll_clock *pll_clock = to_pll_clock(hw);
	int mul = 1 << (readb(pll_clock->pllcr) & 3);

	return parent_rate * mul;
}

static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long *prate)
{
	int i, m = -1;
	long offset[3];

	if (rate > MAX_FREQ)
		rate = MAX_FREQ;
	if (rate < MIN_FREQ)
		rate = MIN_FREQ;

	for (i = 0; i < 3; i++)
		offset[i] = abs(rate - (*prate * (1 << i)));
	for (i = 0; i < 3; i++)
		if (m < 0)
			m = i;
		else
			m = (offset[i] < offset[m])?i:m;

	return *prate * (1 << m);
}

static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
			unsigned long parent_rate)
{
	int pll;
	unsigned char val;
	unsigned long flags;
	struct pll_clock *pll_clock = to_pll_clock(hw);

	pll = ((rate / parent_rate) / 2) & 0x03;
	spin_lock_irqsave(&clklock, flags);
	val = readb(pll_clock->sckcr);
	val |= 0x08;
	writeb(val, pll_clock->sckcr);
	val = readb(pll_clock->pllcr);
	val &= ~0x03;
	val |= pll;
	writeb(val, pll_clock->pllcr);
	spin_unlock_irqrestore(&clklock, flags);
	return 0;
}

static const struct clk_ops pll_ops = {
	.recalc_rate = pll_recalc_rate,
	.round_rate = pll_round_rate,
	.set_rate = pll_set_rate,
};

static void __init h8s2678_pll_clk_setup(struct device_node *node)
{
	unsigned int num_parents;
	const char *clk_name = node->name;
	const char *parent_name;
	struct pll_clock *pll_clock;
	struct clk_init_data init;
	int ret;

	num_parents = of_clk_get_parent_count(node);
	if (!num_parents) {
		pr_err("%s: no parent found", clk_name);
		return;
	}


	pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
	if (!pll_clock)
		return;

	pll_clock->sckcr = of_iomap(node, 0);
	if (pll_clock->sckcr == NULL) {
		pr_err("%s: failed to map divide register", clk_name);
		goto free_clock;
	}

	pll_clock->pllcr = of_iomap(node, 1);
	if (pll_clock->pllcr == NULL) {
		pr_err("%s: failed to map multiply register", clk_name);
		goto unmap_sckcr;
	}

	parent_name = of_clk_get_parent_name(node, 0);
	init.name = clk_name;
	init.ops = &pll_ops;
	init.flags = CLK_IS_BASIC;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	pll_clock->hw.init = &init;

	ret = clk_hw_register(NULL, &pll_clock->hw);
	if (ret) {
		pr_err("%s: failed to register %s div clock (%d)\n",
		       __func__, clk_name, ret);
		goto unmap_pllcr;
	}

	of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
	return;

unmap_pllcr:
	iounmap(pll_clock->pllcr);
unmap_sckcr:
	iounmap(pll_clock->sckcr);
free_clock:
	kfree(pll_clock);
}

CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
	       h8s2678_pll_clk_setup);
Commit	Line	Data
7b5bb891 YS	1	/*
	2	* H8S2678 clock driver
	3	*
	4	* Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
	5	*/
	6
7b5bb891 YS	7	#include <linux/clk-provider.h>
	8	#include <linux/err.h>
	9	#include <linux/device.h>
	10	#include <linux/of_address.h>
ac0e137a	11	#include <linux/slab.h>
7b5bb891 YS	12
	13	static DEFINE_SPINLOCK(clklock);
	14
	15	#define MAX_FREQ 33333333
	16	#define MIN_FREQ 8000000
	17
	18	struct pll_clock {
	19	struct clk_hw hw;
	20	void __iomem *sckcr;
	21	void __iomem *pllcr;
	22	};
	23
	24	#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
	25
	26	static unsigned long pll_recalc_rate(struct clk_hw *hw,
	27	unsigned long parent_rate)
	28	{
	29	struct pll_clock *pll_clock = to_pll_clock(hw);
006cb8b6	30	int mul = 1 << (readb(pll_clock->pllcr) & 3);
7b5bb891 YS	31
	32	return parent_rate * mul;
	33	}
	34
	35	static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
	36	unsigned long *prate)
	37	{
	38	int i, m = -1;
	39	long offset[3];
	40
	41	if (rate > MAX_FREQ)
	42	rate = MAX_FREQ;
	43	if (rate < MIN_FREQ)
	44	rate = MIN_FREQ;
	45
	46	for (i = 0; i < 3; i++)
	47	offset[i] = abs(rate - (prate (1 << i)));
	48	for (i = 0; i < 3; i++)
	49	if (m < 0)
	50	m = i;
	51	else
	52	m = (offset[i] < offset[m])?i:m;
	53
	54	return prate (1 << m);
	55	}
	56
	57	static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
	58	unsigned long parent_rate)
	59	{
	60	int pll;
	61	unsigned char val;
	62	unsigned long flags;
	63	struct pll_clock *pll_clock = to_pll_clock(hw);
	64
	65	pll = ((rate / parent_rate) / 2) & 0x03;
	66	spin_lock_irqsave(&clklock, flags);
006cb8b6	67	val = readb(pll_clock->sckcr);
7b5bb891	68	val \|= 0x08;
006cb8b6 SB	69	writeb(val, pll_clock->sckcr);
006cb8b6 SB	70	val = readb(pll_clock->pllcr);
7b5bb891 YS	71	val &= ~0x03;
7b5bb891 YS	72	val \|= pll;
006cb8b6	73	writeb(val, pll_clock->pllcr);
7b5bb891 YS	74	spin_unlock_irqrestore(&clklock, flags);
	75	return 0;
	76	}
	77
	78	static const struct clk_ops pll_ops = {
	79	.recalc_rate = pll_recalc_rate,
	80	.round_rate = pll_round_rate,
	81	.set_rate = pll_set_rate,
	82	};
	83
	84	static void __init h8s2678_pll_clk_setup(struct device_node *node)
	85	{
ebf3f9a9	86	unsigned int num_parents;
7b5bb891 YS	87	const char *clk_name = node->name;
	88	const char *parent_name;
	89	struct pll_clock *pll_clock;
	90	struct clk_init_data init;
8b2bdc76	91	int ret;
7b5bb891 YS	92
7b5bb891 YS	93	num_parents = of_clk_get_parent_count(node);
ebf3f9a9	94	if (!num_parents) {
7b5bb891 YS	95	pr_err("%s: no parent found", clk_name);
	96	return;
	97	}
	98
	99
9298f026 SB	100	pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
9298f026 SB	101	if (!pll_clock)
7b5bb891	102	return;
7b5bb891 YS	103
	104	pll_clock->sckcr = of_iomap(node, 0);
	105	if (pll_clock->sckcr == NULL) {
	106	pr_err("%s: failed to map divide register", clk_name);
ded515a4	107	goto free_clock;
7b5bb891 YS	108	}
	109
	110	pll_clock->pllcr = of_iomap(node, 1);
	111	if (pll_clock->pllcr == NULL) {
	112	pr_err("%s: failed to map multiply register", clk_name);
ded515a4	113	goto unmap_sckcr;
7b5bb891 YS	114	}
	115
	116	parent_name = of_clk_get_parent_name(node, 0);
	117	init.name = clk_name;
	118	init.ops = &pll_ops;
	119	init.flags = CLK_IS_BASIC;
	120	init.parent_names = &parent_name;
	121	init.num_parents = 1;
	122	pll_clock->hw.init = &init;
	123
8b2bdc76 SB	124	ret = clk_hw_register(NULL, &pll_clock->hw);
	125	if (ret) {
	126	pr_err("%s: failed to register %s div clock (%d)\n",
	127	__func__, clk_name, ret);
ded515a4	128	goto unmap_pllcr;
7b5bb891	129	}
ded515a4	130
8b2bdc76	131	of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
ded515a4 DC	132	return;
	133
	134	unmap_pllcr:
	135	iounmap(pll_clock->pllcr);
	136	unmap_sckcr:
	137	iounmap(pll_clock->sckcr);
	138	free_clock:
	139	kfree(pll_clock);
7b5bb891 YS	140	}
	141
	142	CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
	143	h8s2678_pll_clk_setup);