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45fe6810 | 1 | /* |
848db4a0 | 2 | * Copyright 2013-2014 Freescale Semiconductor, Inc. |
45fe6810 SG |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/clkdev.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_address.h> | |
15 | #include <linux/of_irq.h> | |
16 | #include <dt-bindings/clock/imx6sl-clock.h> | |
17 | ||
18 | #include "clk.h" | |
45fe6810 | 19 | |
6e6cdf66 AH |
20 | #define CCSR 0xc |
21 | #define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) | |
22 | #define CACRR 0x10 | |
23 | #define CDHIPR 0x48 | |
24 | #define BM_CDHIPR_ARM_PODF_BUSY (1 << 16) | |
25 | #define ARM_WAIT_DIV_396M 2 | |
26 | #define ARM_WAIT_DIV_792M 4 | |
27 | #define ARM_WAIT_DIV_996M 6 | |
28 | ||
29 | #define PLL_ARM 0x0 | |
30 | #define BM_PLL_ARM_DIV_SELECT (0x7f << 0) | |
31 | #define BM_PLL_ARM_POWERDOWN (1 << 12) | |
32 | #define BM_PLL_ARM_ENABLE (1 << 13) | |
33 | #define BM_PLL_ARM_LOCK (1 << 31) | |
34 | #define PLL_ARM_DIV_792M 66 | |
35 | ||
b21c22e3 LY |
36 | static const char *step_sels[] = { "osc", "pll2_pfd2", }; |
37 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; | |
38 | static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; | |
39 | static const char *ocram_sels[] = { "periph", "ocram_alt_sels", }; | |
40 | static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; | |
41 | static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; | |
42 | static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; | |
43 | static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; | |
44 | static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; | |
bad66c3e FE |
45 | static const char *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; |
46 | static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", }; | |
b21c22e3 LY |
47 | static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; |
48 | static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", }; | |
49 | static const char *perclk_sels[] = { "ipg", "osc", }; | |
e37c1ad0 FF |
50 | static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", }; |
51 | static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", }; | |
b21c22e3 LY |
52 | static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; |
53 | static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; | |
54 | static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; | |
55 | static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; | |
56 | static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; | |
57 | static const char *ecspi_sels[] = { "pll3_60m", "osc", }; | |
58 | static const char *uart_sels[] = { "pll3_80m", "osc", }; | |
e90f4199 SG |
59 | static const char *lvds_sels[] = { |
60 | "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video", | |
61 | "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1", | |
62 | "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy", | |
63 | "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", | |
64 | }; | |
65 | static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", }; | |
66 | static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; | |
67 | static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; | |
68 | static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; | |
69 | static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; | |
70 | static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; | |
71 | static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; | |
72 | static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; | |
45fe6810 SG |
73 | |
74 | static struct clk_div_table clk_enet_ref_table[] = { | |
75 | { .val = 0, .div = 20, }, | |
76 | { .val = 1, .div = 10, }, | |
77 | { .val = 2, .div = 5, }, | |
78 | { .val = 3, .div = 4, }, | |
79 | { } | |
80 | }; | |
81 | ||
82 | static struct clk_div_table post_div_table[] = { | |
83 | { .val = 2, .div = 1, }, | |
84 | { .val = 1, .div = 2, }, | |
85 | { .val = 0, .div = 4, }, | |
86 | { } | |
87 | }; | |
88 | ||
89 | static struct clk_div_table video_div_table[] = { | |
90 | { .val = 0, .div = 1, }, | |
91 | { .val = 1, .div = 2, }, | |
92 | { .val = 2, .div = 1, }, | |
93 | { .val = 3, .div = 4, }, | |
94 | { } | |
95 | }; | |
96 | ||
dbaf381f SW |
97 | static unsigned int share_count_ssi1; |
98 | static unsigned int share_count_ssi2; | |
99 | static unsigned int share_count_ssi3; | |
84a87250 | 100 | static unsigned int share_count_spdif; |
dbaf381f | 101 | |
4e5d0d61 | 102 | static struct clk *clks[IMX6SL_CLK_END]; |
45fe6810 | 103 | static struct clk_onecell_data clk_data; |
6e6cdf66 AH |
104 | static void __iomem *ccm_base; |
105 | static void __iomem *anatop_base; | |
45fe6810 | 106 | |
17626b7c AH |
107 | static const u32 clks_init_on[] __initconst = { |
108 | IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT, | |
109 | }; | |
110 | ||
751f7e99 AH |
111 | /* |
112 | * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken | |
113 | * during WAIT mode entry process could cause cache memory | |
114 | * corruption. | |
115 | * | |
116 | * Software workaround: | |
117 | * To prevent this issue from occurring, software should ensure that the | |
118 | * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before | |
119 | * entering WAIT mode. | |
120 | * | |
121 | * This function will set the ARM clk to max value within the 12:5 limit. | |
6e6cdf66 AH |
122 | * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz), |
123 | * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since | |
124 | * the clk APIs can NOT be called in idle thread(may cause kernel schedule | |
125 | * as there is sleep function in PLL wait function), so here we just slow | |
126 | * down ARM to below freq according to previous freq: | |
127 | * | |
128 | * run mode wait mode | |
129 | * 396MHz -> 132MHz; | |
130 | * 792MHz -> 158.4MHz; | |
131 | * 996MHz -> 142.3MHz; | |
751f7e99 | 132 | */ |
6e6cdf66 AH |
133 | static int imx6sl_get_arm_divider_for_wait(void) |
134 | { | |
135 | if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { | |
136 | return ARM_WAIT_DIV_396M; | |
137 | } else { | |
138 | if ((readl_relaxed(anatop_base + PLL_ARM) & | |
139 | BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M) | |
140 | return ARM_WAIT_DIV_792M; | |
141 | else | |
142 | return ARM_WAIT_DIV_996M; | |
143 | } | |
144 | } | |
145 | ||
146 | static void imx6sl_enable_pll_arm(bool enable) | |
147 | { | |
148 | static u32 saved_pll_arm; | |
149 | u32 val; | |
150 | ||
151 | if (enable) { | |
152 | saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); | |
153 | val |= BM_PLL_ARM_ENABLE; | |
154 | val &= ~BM_PLL_ARM_POWERDOWN; | |
155 | writel_relaxed(val, anatop_base + PLL_ARM); | |
156 | while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) | |
157 | ; | |
158 | } else { | |
159 | writel_relaxed(saved_pll_arm, anatop_base + PLL_ARM); | |
160 | } | |
161 | } | |
162 | ||
751f7e99 AH |
163 | void imx6sl_set_wait_clk(bool enter) |
164 | { | |
6e6cdf66 AH |
165 | static unsigned long saved_arm_div; |
166 | int arm_div_for_wait = imx6sl_get_arm_divider_for_wait(); | |
167 | ||
168 | /* | |
169 | * According to hardware design, arm podf change need | |
170 | * PLL1 clock enabled. | |
171 | */ | |
172 | if (arm_div_for_wait == ARM_WAIT_DIV_396M) | |
173 | imx6sl_enable_pll_arm(true); | |
751f7e99 AH |
174 | |
175 | if (enter) { | |
6e6cdf66 AH |
176 | saved_arm_div = readl_relaxed(ccm_base + CACRR); |
177 | writel_relaxed(arm_div_for_wait, ccm_base + CACRR); | |
751f7e99 | 178 | } else { |
6e6cdf66 | 179 | writel_relaxed(saved_arm_div, ccm_base + CACRR); |
751f7e99 | 180 | } |
6e6cdf66 AH |
181 | while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY) |
182 | ; | |
183 | ||
184 | if (arm_div_for_wait == ARM_WAIT_DIV_396M) | |
185 | imx6sl_enable_pll_arm(false); | |
751f7e99 AH |
186 | } |
187 | ||
0822f933 LS |
188 | static struct clk ** const uart_clks[] __initconst = { |
189 | &clks[IMX6SL_CLK_UART], | |
190 | &clks[IMX6SL_CLK_UART_SERIAL], | |
191 | NULL | |
192 | }; | |
193 | ||
53bb71da | 194 | static void __init imx6sl_clocks_init(struct device_node *ccm_node) |
45fe6810 SG |
195 | { |
196 | struct device_node *np; | |
197 | void __iomem *base; | |
45fe6810 | 198 | int i; |
848db4a0 | 199 | int ret; |
45fe6810 | 200 | |
45fe6810 SG |
201 | clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
202 | clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); | |
203 | clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); | |
e90f4199 SG |
204 | /* Clock source from external clock via CLK1 PAD */ |
205 | clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); | |
45fe6810 SG |
206 | |
207 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); | |
208 | base = of_iomap(np, 0); | |
209 | WARN_ON(!base); | |
6e6cdf66 | 210 | anatop_base = base; |
45fe6810 | 211 | |
e90f4199 SG |
212 | clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
213 | clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
214 | clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
215 | clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
216 | clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
217 | clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
218 | clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
219 | ||
220 | /* type name parent_name base div_mask */ | |
221 | clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); | |
222 | clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); | |
223 | clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); | |
224 | clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); | |
225 | clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); | |
226 | clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); | |
227 | clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); | |
228 | ||
229 | clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); | |
230 | clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); | |
231 | clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); | |
232 | clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); | |
233 | clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); | |
234 | clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); | |
235 | clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); | |
236 | ||
237 | /* Do not bypass PLLs initially */ | |
238 | clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]); | |
239 | clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]); | |
240 | clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]); | |
241 | clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]); | |
242 | clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]); | |
243 | clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]); | |
244 | clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]); | |
245 | ||
246 | clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); | |
247 | clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); | |
248 | clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); | |
249 | clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); | |
250 | clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); | |
251 | clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); | |
69d9a3fe | 252 | clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); |
e90f4199 SG |
253 | |
254 | clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | |
255 | clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12)); | |
256 | clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); | |
45fe6810 SG |
257 | |
258 | /* | |
259 | * usbphy1 and usbphy2 are implemented as dummy gates using reserve | |
260 | * bit 20. They are used by phy driver to keep the refcount of | |
261 | * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be | |
262 | * turned on during boot, and software will not need to control it | |
263 | * anymore after that. | |
264 | */ | |
265 | clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); | |
266 | clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); | |
267 | clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); | |
268 | clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); | |
269 | ||
270 | /* dev name parent_name flags reg shift width div: flags, div_table lock */ | |
271 | clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); | |
238fb182 | 272 | clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); |
45fe6810 SG |
273 | clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); |
274 | clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); | |
275 | clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); | |
276 | ||
277 | /* name parent_name reg idx */ | |
278 | clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0); | |
279 | clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1); | |
280 | clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2); | |
281 | clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0); | |
282 | clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1); | |
283 | clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2); | |
284 | clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3); | |
285 | ||
286 | /* name parent_name mult div */ | |
287 | clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2); | |
288 | clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); | |
289 | clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | |
290 | clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | |
291 | ||
53bb71da | 292 | np = ccm_node; |
45fe6810 SG |
293 | base = of_iomap(np, 0); |
294 | WARN_ON(!base); | |
6e6cdf66 | 295 | ccm_base = base; |
45fe6810 SG |
296 | |
297 | /* name reg shift width parent_names num_parents */ | |
298 | clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | |
299 | clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | |
300 | clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); | |
301 | clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); | |
302 | clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); | |
303 | clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); | |
304 | clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); | |
305 | clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | |
bad66c3e FE |
306 | clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); |
307 | clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels)); | |
dfd87144 LY |
308 | clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); |
309 | clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
310 | clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
311 | clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
312 | clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
313 | clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
314 | clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
315 | clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup); | |
e37c1ad0 FF |
316 | clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels)); |
317 | clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels)); | |
45fe6810 SG |
318 | clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); |
319 | clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); | |
320 | clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); | |
321 | clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); | |
322 | clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
323 | clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
324 | clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
325 | clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); | |
326 | clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); | |
327 | ||
328 | /* name reg shift width busy: reg, shift parent_names num_parents */ | |
329 | clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); | |
330 | clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); | |
331 | ||
332 | /* name parent_name reg shift width */ | |
333 | clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); | |
334 | clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); | |
335 | clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); | |
336 | clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); | |
337 | clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); | |
338 | clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3); | |
339 | clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); | |
340 | clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); | |
341 | clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); | |
342 | clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | |
343 | clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); | |
344 | clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); | |
345 | clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); | |
346 | clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | |
347 | clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | |
348 | clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | |
dfd87144 | 349 | clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup); |
45fe6810 SG |
350 | clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); |
351 | clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); | |
352 | clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); | |
353 | clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); | |
354 | clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); | |
355 | clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); | |
dfd87144 | 356 | clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup); |
45fe6810 SG |
357 | clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); |
358 | clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); | |
359 | clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); | |
360 | clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); | |
361 | clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); | |
362 | clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3); | |
363 | clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3); | |
364 | clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); | |
365 | clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6); | |
366 | ||
367 | /* name parent_name reg shift width busy: reg, shift */ | |
368 | clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | |
369 | clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2); | |
370 | clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); | |
371 | ||
372 | /* name parent_name reg shift */ | |
373 | clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); | |
374 | clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); | |
375 | clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); | |
376 | clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); | |
4ca2ad55 | 377 | clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); |
45fe6810 SG |
378 | clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); |
379 | clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); | |
380 | clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); | |
381 | clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20); | |
382 | clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); | |
383 | clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); | |
384 | clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); | |
385 | clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); | |
386 | clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); | |
387 | clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); | |
388 | clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0); | |
389 | clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2); | |
390 | clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4); | |
391 | clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); | |
392 | clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); | |
393 | clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); | |
394 | clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); | |
395 | clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); | |
396 | clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); | |
397 | clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); | |
398 | clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); | |
399 | clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); | |
8962a5db | 400 | clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); |
84a87250 SW |
401 | clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif); |
402 | clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); | |
dbaf381f SW |
403 | clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); |
404 | clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); | |
405 | clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); | |
406 | clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); | |
407 | clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); | |
408 | clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); | |
45fe6810 SG |
409 | clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); |
410 | clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); | |
411 | clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); | |
412 | clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); | |
413 | clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); | |
414 | clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | |
415 | clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | |
416 | ||
229be9c1 | 417 | imx_check_clocks(clks, ARRAY_SIZE(clks)); |
45fe6810 SG |
418 | |
419 | clk_data.clks = clks; | |
420 | clk_data.clk_num = ARRAY_SIZE(clks); | |
421 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
422 | ||
848db4a0 AH |
423 | /* Ensure the AHB clk is at 132MHz. */ |
424 | ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000); | |
425 | if (ret) | |
426 | pr_warn("%s: failed to set AHB clock rate %d!\n", | |
427 | __func__, ret); | |
428 | ||
17626b7c AH |
429 | /* |
430 | * Make sure those always on clocks are enabled to maintain the correct | |
431 | * usecount and enabling/disabling of parent PLLs. | |
432 | */ | |
433 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | |
434 | clk_prepare_enable(clks[clks_init_on[i]]); | |
435 | ||
45fe6810 SG |
436 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
437 | clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); | |
438 | clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); | |
439 | } | |
440 | ||
4390e622 NC |
441 | /* Audio-related clocks configuration */ |
442 | clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); | |
443 | ||
0783a560 FE |
444 | /* set PLL5 video as lcdif pix parent clock */ |
445 | clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], | |
446 | clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); | |
447 | ||
448 | clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], | |
449 | clks[IMX6SL_CLK_PLL2_PFD2]); | |
0822f933 LS |
450 | |
451 | imx_register_uart_clocks(uart_clks); | |
45fe6810 | 452 | } |
53bb71da | 453 | CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); |