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9741b1a6 JL |
1 | /* |
2 | * Copyright (c) 2014 MediaTek Inc. | |
3 | * Author: James Liao <jamesjj.liao@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/of.h> | |
16 | #include <linux/of_address.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/clkdev.h> | |
20 | #include <linux/delay.h> | |
21 | ||
22 | #include "clk-mtk.h" | |
23 | ||
24 | #define REG_CON0 0 | |
25 | #define REG_CON1 4 | |
26 | ||
27 | #define CON0_BASE_EN BIT(0) | |
28 | #define CON0_PWR_ON BIT(0) | |
29 | #define CON0_ISO_EN BIT(1) | |
30 | #define CON0_PCW_CHG BIT(31) | |
31 | ||
32 | #define AUDPLL_TUNER_EN BIT(31) | |
33 | ||
34 | #define POSTDIV_MASK 0x7 | |
35 | #define INTEGER_BITS 7 | |
36 | ||
37 | /* | |
38 | * MediaTek PLLs are configured through their pcw value. The pcw value describes | |
39 | * a divider in the PLL feedback loop which consists of 7 bits for the integer | |
40 | * part and the remaining bits (if present) for the fractional part. Also they | |
41 | * have a 3 bit power-of-two post divider. | |
42 | */ | |
43 | ||
44 | struct mtk_clk_pll { | |
45 | struct clk_hw hw; | |
46 | void __iomem *base_addr; | |
47 | void __iomem *pd_addr; | |
48 | void __iomem *pwr_addr; | |
49 | void __iomem *tuner_addr; | |
50 | void __iomem *pcw_addr; | |
51 | const struct mtk_pll_data *data; | |
52 | }; | |
53 | ||
54 | static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) | |
55 | { | |
56 | return container_of(hw, struct mtk_clk_pll, hw); | |
57 | } | |
58 | ||
59 | static int mtk_pll_is_prepared(struct clk_hw *hw) | |
60 | { | |
61 | struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); | |
62 | ||
63 | return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; | |
64 | } | |
65 | ||
66 | static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, | |
67 | u32 pcw, int postdiv) | |
68 | { | |
69 | int pcwbits = pll->data->pcwbits; | |
70 | int pcwfbits; | |
71 | u64 vco; | |
72 | u8 c = 0; | |
73 | ||
74 | /* The fractional part of the PLL divider. */ | |
75 | pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; | |
76 | ||
77 | vco = (u64)fin * pcw; | |
78 | ||
79 | if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) | |
80 | c = 1; | |
81 | ||
82 | vco >>= pcwfbits; | |
83 | ||
84 | if (c) | |
85 | vco++; | |
86 | ||
87 | return ((unsigned long)vco + postdiv - 1) / postdiv; | |
88 | } | |
89 | ||
90 | static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, | |
91 | int postdiv) | |
92 | { | |
b3be457e | 93 | u32 con1, val; |
9741b1a6 JL |
94 | int pll_en; |
95 | ||
9741b1a6 JL |
96 | pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; |
97 | ||
b3be457e JL |
98 | /* set postdiv */ |
99 | val = readl(pll->pd_addr); | |
100 | val &= ~(POSTDIV_MASK << pll->data->pd_shift); | |
101 | val |= (ffs(postdiv) - 1) << pll->data->pd_shift; | |
102 | ||
103 | /* postdiv and pcw need to set at the same time if on same register */ | |
104 | if (pll->pd_addr != pll->pcw_addr) { | |
105 | writel(val, pll->pd_addr); | |
106 | val = readl(pll->pcw_addr); | |
107 | } | |
9741b1a6 | 108 | |
b3be457e | 109 | /* set pcw */ |
9741b1a6 JL |
110 | val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1, |
111 | pll->data->pcw_shift); | |
112 | val |= pcw << pll->data->pcw_shift; | |
113 | writel(val, pll->pcw_addr); | |
114 | ||
115 | con1 = readl(pll->base_addr + REG_CON1); | |
116 | ||
117 | if (pll_en) | |
118 | con1 |= CON0_PCW_CHG; | |
119 | ||
120 | writel(con1, pll->base_addr + REG_CON1); | |
121 | if (pll->tuner_addr) | |
122 | writel(con1 + 1, pll->tuner_addr); | |
123 | ||
124 | if (pll_en) | |
125 | udelay(20); | |
126 | } | |
127 | ||
128 | /* | |
129 | * mtk_pll_calc_values - calculate good values for a given input frequency. | |
130 | * @pll: The pll | |
131 | * @pcw: The pcw value (output) | |
132 | * @postdiv: The post divider (output) | |
133 | * @freq: The desired target frequency | |
134 | * @fin: The input frequency | |
135 | * | |
136 | */ | |
137 | static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, | |
138 | u32 freq, u32 fin) | |
139 | { | |
140 | unsigned long fmin = 1000 * MHZ; | |
75ce0cdb | 141 | const struct mtk_pll_div_table *div_table = pll->data->div_table; |
9741b1a6 JL |
142 | u64 _pcw; |
143 | u32 val; | |
144 | ||
145 | if (freq > pll->data->fmax) | |
146 | freq = pll->data->fmax; | |
147 | ||
75ce0cdb JL |
148 | if (div_table) { |
149 | if (freq > div_table[0].freq) | |
150 | freq = div_table[0].freq; | |
151 | ||
152 | for (val = 0; div_table[val + 1].freq != 0; val++) { | |
153 | if (freq > div_table[val + 1].freq) | |
154 | break; | |
155 | } | |
9741b1a6 | 156 | *postdiv = 1 << val; |
75ce0cdb JL |
157 | } else { |
158 | for (val = 0; val < 5; val++) { | |
159 | *postdiv = 1 << val; | |
160 | if ((u64)freq * *postdiv >= fmin) | |
161 | break; | |
162 | } | |
9741b1a6 JL |
163 | } |
164 | ||
165 | /* _pcw = freq * postdiv / fin * 2^pcwfbits */ | |
166 | _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); | |
167 | do_div(_pcw, fin); | |
168 | ||
169 | *pcw = (u32)_pcw; | |
170 | } | |
171 | ||
172 | static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, | |
173 | unsigned long parent_rate) | |
174 | { | |
175 | struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); | |
176 | u32 pcw = 0; | |
177 | u32 postdiv; | |
178 | ||
179 | mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); | |
180 | mtk_pll_set_rate_regs(pll, pcw, postdiv); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, | |
186 | unsigned long parent_rate) | |
187 | { | |
188 | struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); | |
189 | u32 postdiv; | |
190 | u32 pcw; | |
191 | ||
192 | postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; | |
193 | postdiv = 1 << postdiv; | |
194 | ||
195 | pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; | |
196 | pcw &= GENMASK(pll->data->pcwbits - 1, 0); | |
197 | ||
198 | return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); | |
199 | } | |
200 | ||
201 | static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
202 | unsigned long *prate) | |
203 | { | |
204 | struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); | |
205 | u32 pcw = 0; | |
206 | int postdiv; | |
207 | ||
208 | mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate); | |
209 | ||
210 | return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); | |
211 | } | |
212 | ||
213 | static int mtk_pll_prepare(struct clk_hw *hw) | |
214 | { | |
215 | struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); | |
216 | u32 r; | |
217 | ||
218 | r = readl(pll->pwr_addr) | CON0_PWR_ON; | |
219 | writel(r, pll->pwr_addr); | |
220 | udelay(1); | |
221 | ||
222 | r = readl(pll->pwr_addr) & ~CON0_ISO_EN; | |
223 | writel(r, pll->pwr_addr); | |
224 | udelay(1); | |
225 | ||
226 | r = readl(pll->base_addr + REG_CON0); | |
227 | r |= pll->data->en_mask; | |
228 | writel(r, pll->base_addr + REG_CON0); | |
229 | ||
230 | if (pll->tuner_addr) { | |
231 | r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; | |
232 | writel(r, pll->tuner_addr); | |
233 | } | |
234 | ||
235 | udelay(20); | |
236 | ||
237 | if (pll->data->flags & HAVE_RST_BAR) { | |
238 | r = readl(pll->base_addr + REG_CON0); | |
239 | r |= pll->data->rst_bar_mask; | |
240 | writel(r, pll->base_addr + REG_CON0); | |
241 | } | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static void mtk_pll_unprepare(struct clk_hw *hw) | |
247 | { | |
248 | struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); | |
249 | u32 r; | |
250 | ||
251 | if (pll->data->flags & HAVE_RST_BAR) { | |
252 | r = readl(pll->base_addr + REG_CON0); | |
253 | r &= ~pll->data->rst_bar_mask; | |
254 | writel(r, pll->base_addr + REG_CON0); | |
255 | } | |
256 | ||
257 | if (pll->tuner_addr) { | |
258 | r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; | |
259 | writel(r, pll->tuner_addr); | |
260 | } | |
261 | ||
262 | r = readl(pll->base_addr + REG_CON0); | |
263 | r &= ~CON0_BASE_EN; | |
264 | writel(r, pll->base_addr + REG_CON0); | |
265 | ||
266 | r = readl(pll->pwr_addr) | CON0_ISO_EN; | |
267 | writel(r, pll->pwr_addr); | |
268 | ||
269 | r = readl(pll->pwr_addr) & ~CON0_PWR_ON; | |
270 | writel(r, pll->pwr_addr); | |
271 | } | |
272 | ||
273 | static const struct clk_ops mtk_pll_ops = { | |
274 | .is_prepared = mtk_pll_is_prepared, | |
275 | .prepare = mtk_pll_prepare, | |
276 | .unprepare = mtk_pll_unprepare, | |
277 | .recalc_rate = mtk_pll_recalc_rate, | |
278 | .round_rate = mtk_pll_round_rate, | |
279 | .set_rate = mtk_pll_set_rate, | |
280 | }; | |
281 | ||
282 | static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, | |
283 | void __iomem *base) | |
284 | { | |
285 | struct mtk_clk_pll *pll; | |
95f58981 | 286 | struct clk_init_data init = {}; |
9741b1a6 JL |
287 | struct clk *clk; |
288 | const char *parent_name = "clk26m"; | |
289 | ||
290 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | |
291 | if (!pll) | |
292 | return ERR_PTR(-ENOMEM); | |
293 | ||
294 | pll->base_addr = base + data->reg; | |
295 | pll->pwr_addr = base + data->pwr_reg; | |
296 | pll->pd_addr = base + data->pd_reg; | |
297 | pll->pcw_addr = base + data->pcw_reg; | |
298 | if (data->tuner_reg) | |
299 | pll->tuner_addr = base + data->tuner_reg; | |
300 | pll->hw.init = &init; | |
301 | pll->data = data; | |
302 | ||
303 | init.name = data->name; | |
304 | init.ops = &mtk_pll_ops; | |
305 | init.parent_names = &parent_name; | |
306 | init.num_parents = 1; | |
307 | ||
308 | clk = clk_register(NULL, &pll->hw); | |
309 | ||
310 | if (IS_ERR(clk)) | |
311 | kfree(pll); | |
312 | ||
313 | return clk; | |
314 | } | |
315 | ||
928f3bfb | 316 | void mtk_clk_register_plls(struct device_node *node, |
9741b1a6 JL |
317 | const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) |
318 | { | |
319 | void __iomem *base; | |
cdb2bab7 | 320 | int i; |
9741b1a6 JL |
321 | struct clk *clk; |
322 | ||
323 | base = of_iomap(node, 0); | |
324 | if (!base) { | |
325 | pr_err("%s(): ioremap failed\n", __func__); | |
326 | return; | |
327 | } | |
328 | ||
329 | for (i = 0; i < num_plls; i++) { | |
330 | const struct mtk_pll_data *pll = &plls[i]; | |
331 | ||
332 | clk = mtk_clk_register_pll(pll, base); | |
333 | ||
334 | if (IS_ERR(clk)) { | |
335 | pr_err("Failed to register clk %s: %ld\n", | |
336 | pll->name, PTR_ERR(clk)); | |
337 | continue; | |
338 | } | |
339 | ||
340 | clk_data->clks[pll->id] = clk; | |
341 | } | |
9741b1a6 | 342 | } |