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7a29a869 CC |
1 | /* |
2 | * Copyright (c) 2015 Endless Mobile, Inc. | |
3 | * Author: Carlo Caione <carlo@endlessm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | /* | |
19 | * CPU clock path: | |
20 | * | |
21 | * +-[/N]-----|3| | |
22 | * MUX2 +--[/3]-+----------|2| MUX1 | |
23 | * [sys_pll]---|1| |--[/2]------------|1|-|1| | |
24 | * | |---+------------------|0| | |----- [a5_clk] | |
25 | * +--|0| | | | |
26 | * [xtal]---+-------------------------------|0| | |
27 | * | |
28 | * | |
29 | * | |
30 | */ | |
31 | ||
32 | #include <linux/delay.h> | |
33 | #include <linux/err.h> | |
34 | #include <linux/io.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/of_address.h> | |
37 | #include <linux/slab.h> | |
c0eb1dff | 38 | #include <linux/clk.h> |
7a29a869 CC |
39 | #include <linux/clk-provider.h> |
40 | ||
41 | #define MESON_CPU_CLK_CNTL1 0x00 | |
42 | #define MESON_CPU_CLK_CNTL 0x40 | |
43 | ||
44 | #define MESON_CPU_CLK_MUX1 BIT(7) | |
45 | #define MESON_CPU_CLK_MUX2 BIT(0) | |
46 | ||
47 | #define MESON_N_WIDTH 9 | |
48 | #define MESON_N_SHIFT 20 | |
49 | #define MESON_SEL_WIDTH 2 | |
50 | #define MESON_SEL_SHIFT 2 | |
51 | ||
52 | #include "clkc.h" | |
53 | ||
7a29a869 CC |
54 | #define to_meson_clk_cpu_hw(_hw) container_of(_hw, struct meson_clk_cpu, hw) |
55 | #define to_meson_clk_cpu_nb(_nb) container_of(_nb, struct meson_clk_cpu, clk_nb) | |
56 | ||
57 | static long meson_clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate, | |
58 | unsigned long *prate) | |
59 | { | |
60 | struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw); | |
61 | ||
62 | return divider_round_rate(hw, rate, prate, clk_cpu->div_table, | |
63 | MESON_N_WIDTH, CLK_DIVIDER_ROUND_CLOSEST); | |
64 | } | |
65 | ||
66 | static int meson_clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate, | |
67 | unsigned long parent_rate) | |
68 | { | |
69 | struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw); | |
70 | unsigned int div, sel, N = 0; | |
71 | u32 reg; | |
72 | ||
73 | div = DIV_ROUND_UP(parent_rate, rate); | |
74 | ||
75 | if (div <= 3) { | |
76 | sel = div - 1; | |
77 | } else { | |
78 | sel = 3; | |
79 | N = div / 2; | |
80 | } | |
81 | ||
82 | reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); | |
83 | reg = PARM_SET(MESON_N_WIDTH, MESON_N_SHIFT, reg, N); | |
84 | writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); | |
85 | ||
86 | reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); | |
87 | reg = PARM_SET(MESON_SEL_WIDTH, MESON_SEL_SHIFT, reg, sel); | |
88 | writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
93 | static unsigned long meson_clk_cpu_recalc_rate(struct clk_hw *hw, | |
94 | unsigned long parent_rate) | |
95 | { | |
96 | struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw); | |
97 | unsigned int N, sel; | |
98 | unsigned int div = 1; | |
99 | u32 reg; | |
100 | ||
101 | reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); | |
102 | N = PARM_GET(MESON_N_WIDTH, MESON_N_SHIFT, reg); | |
103 | ||
104 | reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); | |
105 | sel = PARM_GET(MESON_SEL_WIDTH, MESON_SEL_SHIFT, reg); | |
106 | ||
107 | if (sel < 3) | |
108 | div = sel + 1; | |
109 | else | |
110 | div = 2 * N; | |
111 | ||
112 | return parent_rate / div; | |
113 | } | |
114 | ||
55d42c40 | 115 | /* FIXME MUX1 & MUX2 should be struct clk_hw objects */ |
7a29a869 CC |
116 | static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu, |
117 | struct clk_notifier_data *ndata) | |
118 | { | |
119 | u32 cpu_clk_cntl; | |
120 | ||
121 | /* switch MUX1 to xtal */ | |
122 | cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off | |
123 | + MESON_CPU_CLK_CNTL); | |
124 | cpu_clk_cntl &= ~MESON_CPU_CLK_MUX1; | |
125 | writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off | |
126 | + MESON_CPU_CLK_CNTL); | |
127 | udelay(100); | |
128 | ||
129 | /* switch MUX2 to sys-pll */ | |
130 | cpu_clk_cntl |= MESON_CPU_CLK_MUX2; | |
131 | writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off | |
132 | + MESON_CPU_CLK_CNTL); | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
55d42c40 | 137 | /* FIXME MUX1 & MUX2 should be struct clk_hw objects */ |
7a29a869 CC |
138 | static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu, |
139 | struct clk_notifier_data *ndata) | |
140 | { | |
141 | u32 cpu_clk_cntl; | |
142 | ||
143 | /* switch MUX1 to divisors' output */ | |
144 | cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off | |
145 | + MESON_CPU_CLK_CNTL); | |
146 | cpu_clk_cntl |= MESON_CPU_CLK_MUX1; | |
147 | writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off | |
148 | + MESON_CPU_CLK_CNTL); | |
149 | udelay(100); | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | /* | |
155 | * This clock notifier is called when the frequency of the of the parent | |
156 | * PLL clock is to be changed. We use the xtal input as temporary parent | |
157 | * while the PLL frequency is stabilized. | |
158 | */ | |
55d42c40 | 159 | int meson_clk_cpu_notifier_cb(struct notifier_block *nb, |
7a29a869 CC |
160 | unsigned long event, void *data) |
161 | { | |
162 | struct clk_notifier_data *ndata = data; | |
163 | struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_nb(nb); | |
164 | int ret = 0; | |
165 | ||
166 | if (event == PRE_RATE_CHANGE) | |
167 | ret = meson_clk_cpu_pre_rate_change(clk_cpu, ndata); | |
168 | else if (event == POST_RATE_CHANGE) | |
169 | ret = meson_clk_cpu_post_rate_change(clk_cpu, ndata); | |
170 | ||
171 | return notifier_from_errno(ret); | |
172 | } | |
173 | ||
55d42c40 | 174 | const struct clk_ops meson_clk_cpu_ops = { |
7a29a869 CC |
175 | .recalc_rate = meson_clk_cpu_recalc_rate, |
176 | .round_rate = meson_clk_cpu_round_rate, | |
177 | .set_rate = meson_clk_cpu_set_rate, | |
178 | }; |